2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
7 * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22 * The full GNU General Public License is included in this distribution in
23 * the file called "COPYING".
27 * Copyright(c) 2004-2009 Intel Corporation. All rights reserved.
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions are met:
32 * * Redistributions of source code must retain the above copyright
33 * notice, this list of conditions and the following disclaimer.
34 * * Redistributions in binary form must reproduce the above copyright
35 * notice, this list of conditions and the following disclaimer in
36 * the documentation and/or other materials provided with the
38 * * Neither the name of Intel Corporation nor the names of its
39 * contributors may be used to endorse or promote products derived
40 * from this software without specific prior written permission.
42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
46 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
47 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
48 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
49 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
50 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
51 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
52 * POSSIBILITY OF SUCH DAMAGE.
56 * Support routines for v3+ hardware
59 #include <linux/pci.h>
60 #include <linux/gfp.h>
61 #include <linux/dmaengine.h>
62 #include <linux/dma-mapping.h>
63 #include "registers.h"
68 /* ioat hardware assumes at least two sources for raid operations */
69 #define src_cnt_to_sw(x) ((x) + 2)
70 #define src_cnt_to_hw(x) ((x) - 2)
72 /* provide a lookup table for setting the source address in the base or
73 * extended descriptor of an xor or pq descriptor
75 static const u8 xor_idx_to_desc __read_mostly
= 0xd0;
76 static const u8 xor_idx_to_field
[] __read_mostly
= { 1, 4, 5, 6, 7, 0, 1, 2 };
77 static const u8 pq_idx_to_desc __read_mostly
= 0xf8;
78 static const u8 pq_idx_to_field
[] __read_mostly
= { 1, 4, 5, 0, 1, 2, 4, 5 };
80 static dma_addr_t
xor_get_src(struct ioat_raw_descriptor
*descs
[2], int idx
)
82 struct ioat_raw_descriptor
*raw
= descs
[xor_idx_to_desc
>> idx
& 1];
84 return raw
->field
[xor_idx_to_field
[idx
]];
87 static void xor_set_src(struct ioat_raw_descriptor
*descs
[2],
88 dma_addr_t addr
, u32 offset
, int idx
)
90 struct ioat_raw_descriptor
*raw
= descs
[xor_idx_to_desc
>> idx
& 1];
92 raw
->field
[xor_idx_to_field
[idx
]] = addr
+ offset
;
95 static dma_addr_t
pq_get_src(struct ioat_raw_descriptor
*descs
[2], int idx
)
97 struct ioat_raw_descriptor
*raw
= descs
[pq_idx_to_desc
>> idx
& 1];
99 return raw
->field
[pq_idx_to_field
[idx
]];
102 static void pq_set_src(struct ioat_raw_descriptor
*descs
[2],
103 dma_addr_t addr
, u32 offset
, u8 coef
, int idx
)
105 struct ioat_pq_descriptor
*pq
= (struct ioat_pq_descriptor
*) descs
[0];
106 struct ioat_raw_descriptor
*raw
= descs
[pq_idx_to_desc
>> idx
& 1];
108 raw
->field
[pq_idx_to_field
[idx
]] = addr
+ offset
;
109 pq
->coef
[idx
] = coef
;
112 static void ioat3_dma_unmap(struct ioat2_dma_chan
*ioat
,
113 struct ioat_ring_ent
*desc
, int idx
)
115 struct ioat_chan_common
*chan
= &ioat
->base
;
116 struct pci_dev
*pdev
= chan
->device
->pdev
;
117 size_t len
= desc
->len
;
118 size_t offset
= len
- desc
->hw
->size
;
119 struct dma_async_tx_descriptor
*tx
= &desc
->txd
;
120 enum dma_ctrl_flags flags
= tx
->flags
;
122 switch (desc
->hw
->ctl_f
.op
) {
124 if (!desc
->hw
->ctl_f
.null
) /* skip 'interrupt' ops */
125 ioat_dma_unmap(chan
, flags
, len
, desc
->hw
);
128 struct ioat_fill_descriptor
*hw
= desc
->fill
;
130 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
))
131 ioat_unmap(pdev
, hw
->dst_addr
- offset
, len
,
132 PCI_DMA_FROMDEVICE
, flags
, 1);
135 case IOAT_OP_XOR_VAL
:
137 struct ioat_xor_descriptor
*xor = desc
->xor;
138 struct ioat_ring_ent
*ext
;
139 struct ioat_xor_ext_descriptor
*xor_ex
= NULL
;
140 int src_cnt
= src_cnt_to_sw(xor->ctl_f
.src_cnt
);
141 struct ioat_raw_descriptor
*descs
[2];
145 ext
= ioat2_get_ring_ent(ioat
, idx
+ 1);
146 xor_ex
= ext
->xor_ex
;
149 if (!(flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
150 descs
[0] = (struct ioat_raw_descriptor
*) xor;
151 descs
[1] = (struct ioat_raw_descriptor
*) xor_ex
;
152 for (i
= 0; i
< src_cnt
; i
++) {
153 dma_addr_t src
= xor_get_src(descs
, i
);
155 ioat_unmap(pdev
, src
- offset
, len
,
156 PCI_DMA_TODEVICE
, flags
, 0);
159 /* dest is a source in xor validate operations */
160 if (xor->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
161 ioat_unmap(pdev
, xor->dst_addr
- offset
, len
,
162 PCI_DMA_TODEVICE
, flags
, 1);
167 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
))
168 ioat_unmap(pdev
, xor->dst_addr
- offset
, len
,
169 PCI_DMA_FROMDEVICE
, flags
, 1);
174 struct ioat_pq_descriptor
*pq
= desc
->pq
;
175 struct ioat_ring_ent
*ext
;
176 struct ioat_pq_ext_descriptor
*pq_ex
= NULL
;
177 int src_cnt
= src_cnt_to_sw(pq
->ctl_f
.src_cnt
);
178 struct ioat_raw_descriptor
*descs
[2];
182 ext
= ioat2_get_ring_ent(ioat
, idx
+ 1);
186 /* in the 'continue' case don't unmap the dests as sources */
187 if (dmaf_p_disabled_continue(flags
))
189 else if (dmaf_continue(flags
))
192 if (!(flags
& DMA_COMPL_SKIP_SRC_UNMAP
)) {
193 descs
[0] = (struct ioat_raw_descriptor
*) pq
;
194 descs
[1] = (struct ioat_raw_descriptor
*) pq_ex
;
195 for (i
= 0; i
< src_cnt
; i
++) {
196 dma_addr_t src
= pq_get_src(descs
, i
);
198 ioat_unmap(pdev
, src
- offset
, len
,
199 PCI_DMA_TODEVICE
, flags
, 0);
202 /* the dests are sources in pq validate operations */
203 if (pq
->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
204 if (!(flags
& DMA_PREP_PQ_DISABLE_P
))
205 ioat_unmap(pdev
, pq
->p_addr
- offset
,
206 len
, PCI_DMA_TODEVICE
, flags
, 0);
207 if (!(flags
& DMA_PREP_PQ_DISABLE_Q
))
208 ioat_unmap(pdev
, pq
->q_addr
- offset
,
209 len
, PCI_DMA_TODEVICE
, flags
, 0);
214 if (!(flags
& DMA_COMPL_SKIP_DEST_UNMAP
)) {
215 if (!(flags
& DMA_PREP_PQ_DISABLE_P
))
216 ioat_unmap(pdev
, pq
->p_addr
- offset
, len
,
217 PCI_DMA_BIDIRECTIONAL
, flags
, 1);
218 if (!(flags
& DMA_PREP_PQ_DISABLE_Q
))
219 ioat_unmap(pdev
, pq
->q_addr
- offset
, len
,
220 PCI_DMA_BIDIRECTIONAL
, flags
, 1);
225 dev_err(&pdev
->dev
, "%s: unknown op type: %#x\n",
226 __func__
, desc
->hw
->ctl_f
.op
);
230 static bool desc_has_ext(struct ioat_ring_ent
*desc
)
232 struct ioat_dma_descriptor
*hw
= desc
->hw
;
234 if (hw
->ctl_f
.op
== IOAT_OP_XOR
||
235 hw
->ctl_f
.op
== IOAT_OP_XOR_VAL
) {
236 struct ioat_xor_descriptor
*xor = desc
->xor;
238 if (src_cnt_to_sw(xor->ctl_f
.src_cnt
) > 5)
240 } else if (hw
->ctl_f
.op
== IOAT_OP_PQ
||
241 hw
->ctl_f
.op
== IOAT_OP_PQ_VAL
) {
242 struct ioat_pq_descriptor
*pq
= desc
->pq
;
244 if (src_cnt_to_sw(pq
->ctl_f
.src_cnt
) > 3)
252 * __cleanup - reclaim used descriptors
253 * @ioat: channel (ring) to clean
255 * The difference from the dma_v2.c __cleanup() is that this routine
256 * handles extended descriptors and dma-unmapping raid operations.
258 static void __cleanup(struct ioat2_dma_chan
*ioat
, unsigned long phys_complete
)
260 struct ioat_chan_common
*chan
= &ioat
->base
;
261 struct ioat_ring_ent
*desc
;
262 bool seen_current
= false;
263 int idx
= ioat
->tail
, i
;
266 dev_dbg(to_dev(chan
), "%s: head: %#x tail: %#x issued: %#x\n",
267 __func__
, ioat
->head
, ioat
->tail
, ioat
->issued
);
269 active
= ioat2_ring_active(ioat
);
270 for (i
= 0; i
< active
&& !seen_current
; i
++) {
271 struct dma_async_tx_descriptor
*tx
;
273 smp_read_barrier_depends();
274 prefetch(ioat2_get_ring_ent(ioat
, idx
+ i
+ 1));
275 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
276 dump_desc_dbg(ioat
, desc
);
279 chan
->completed_cookie
= tx
->cookie
;
280 ioat3_dma_unmap(ioat
, desc
, idx
+ i
);
283 tx
->callback(tx
->callback_param
);
288 if (tx
->phys
== phys_complete
)
291 /* skip extended descriptors */
292 if (desc_has_ext(desc
)) {
293 BUG_ON(i
+ 1 >= active
);
297 smp_mb(); /* finish all descriptor reads before incrementing tail */
298 ioat
->tail
= idx
+ i
;
299 BUG_ON(active
&& !seen_current
); /* no active descs have written a completion? */
300 chan
->last_completion
= phys_complete
;
302 if (active
- i
== 0) {
303 dev_dbg(to_dev(chan
), "%s: cancel completion timeout\n",
305 clear_bit(IOAT_COMPLETION_PENDING
, &chan
->state
);
306 mod_timer(&chan
->timer
, jiffies
+ IDLE_TIMEOUT
);
308 /* 5 microsecond delay per pending descriptor */
309 writew(min((5 * (active
- i
)), IOAT_INTRDELAY_MASK
),
310 chan
->device
->reg_base
+ IOAT_INTRDELAY_OFFSET
);
313 static void ioat3_cleanup(struct ioat2_dma_chan
*ioat
)
315 struct ioat_chan_common
*chan
= &ioat
->base
;
316 unsigned long phys_complete
;
318 spin_lock_bh(&chan
->cleanup_lock
);
319 if (ioat_cleanup_preamble(chan
, &phys_complete
))
320 __cleanup(ioat
, phys_complete
);
321 spin_unlock_bh(&chan
->cleanup_lock
);
324 static void ioat3_cleanup_event(unsigned long data
)
326 struct ioat2_dma_chan
*ioat
= to_ioat2_chan((void *) data
);
329 writew(IOAT_CHANCTRL_RUN
, ioat
->base
.reg_base
+ IOAT_CHANCTRL_OFFSET
);
332 static void ioat3_restart_channel(struct ioat2_dma_chan
*ioat
)
334 struct ioat_chan_common
*chan
= &ioat
->base
;
335 unsigned long phys_complete
;
337 ioat2_quiesce(chan
, 0);
338 if (ioat_cleanup_preamble(chan
, &phys_complete
))
339 __cleanup(ioat
, phys_complete
);
341 __ioat2_restart_chan(ioat
);
344 static void ioat3_timer_event(unsigned long data
)
346 struct ioat2_dma_chan
*ioat
= to_ioat2_chan((void *) data
);
347 struct ioat_chan_common
*chan
= &ioat
->base
;
349 if (test_bit(IOAT_COMPLETION_PENDING
, &chan
->state
)) {
350 unsigned long phys_complete
;
353 status
= ioat_chansts(chan
);
355 /* when halted due to errors check for channel
356 * programming errors before advancing the completion state
358 if (is_ioat_halted(status
)) {
361 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
362 dev_err(to_dev(chan
), "%s: Channel halted (%x)\n",
364 BUG_ON(is_ioat_bug(chanerr
));
367 /* if we haven't made progress and we have already
368 * acknowledged a pending completion once, then be more
369 * forceful with a restart
371 spin_lock_bh(&chan
->cleanup_lock
);
372 if (ioat_cleanup_preamble(chan
, &phys_complete
))
373 __cleanup(ioat
, phys_complete
);
374 else if (test_bit(IOAT_COMPLETION_ACK
, &chan
->state
)) {
375 spin_lock_bh(&ioat
->prep_lock
);
376 ioat3_restart_channel(ioat
);
377 spin_unlock_bh(&ioat
->prep_lock
);
379 set_bit(IOAT_COMPLETION_ACK
, &chan
->state
);
380 mod_timer(&chan
->timer
, jiffies
+ COMPLETION_TIMEOUT
);
382 spin_unlock_bh(&chan
->cleanup_lock
);
386 /* if the ring is idle, empty, and oversized try to step
389 spin_lock_bh(&chan
->cleanup_lock
);
390 spin_lock_bh(&ioat
->prep_lock
);
391 active
= ioat2_ring_active(ioat
);
392 if (active
== 0 && ioat
->alloc_order
> ioat_get_alloc_order())
393 reshape_ring(ioat
, ioat
->alloc_order
-1);
394 spin_unlock_bh(&ioat
->prep_lock
);
395 spin_unlock_bh(&chan
->cleanup_lock
);
397 /* keep shrinking until we get back to our minimum
400 if (ioat
->alloc_order
> ioat_get_alloc_order())
401 mod_timer(&chan
->timer
, jiffies
+ IDLE_TIMEOUT
);
405 static enum dma_status
406 ioat3_tx_status(struct dma_chan
*c
, dma_cookie_t cookie
,
407 struct dma_tx_state
*txstate
)
409 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
411 if (ioat_tx_status(c
, cookie
, txstate
) == DMA_SUCCESS
)
416 return ioat_tx_status(c
, cookie
, txstate
);
419 static struct dma_async_tx_descriptor
*
420 ioat3_prep_memset_lock(struct dma_chan
*c
, dma_addr_t dest
, int value
,
421 size_t len
, unsigned long flags
)
423 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
424 struct ioat_ring_ent
*desc
;
425 size_t total_len
= len
;
426 struct ioat_fill_descriptor
*fill
;
427 u64 src_data
= (0x0101010101010101ULL
) * (value
& 0xff);
428 int num_descs
, idx
, i
;
430 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
431 if (likely(num_descs
) && ioat2_check_space_lock(ioat
, num_descs
) == 0)
437 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
439 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
442 fill
->size
= xfer_size
;
443 fill
->src_data
= src_data
;
444 fill
->dst_addr
= dest
;
446 fill
->ctl_f
.op
= IOAT_OP_FILL
;
450 dump_desc_dbg(ioat
, desc
);
451 } while (++i
< num_descs
);
453 desc
->txd
.flags
= flags
;
454 desc
->len
= total_len
;
455 fill
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
456 fill
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
457 fill
->ctl_f
.compl_write
= 1;
458 dump_desc_dbg(ioat
, desc
);
460 /* we leave the channel locked to ensure in order submission */
464 static struct dma_async_tx_descriptor
*
465 __ioat3_prep_xor_lock(struct dma_chan
*c
, enum sum_check_flags
*result
,
466 dma_addr_t dest
, dma_addr_t
*src
, unsigned int src_cnt
,
467 size_t len
, unsigned long flags
)
469 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
470 struct ioat_ring_ent
*compl_desc
;
471 struct ioat_ring_ent
*desc
;
472 struct ioat_ring_ent
*ext
;
473 size_t total_len
= len
;
474 struct ioat_xor_descriptor
*xor;
475 struct ioat_xor_ext_descriptor
*xor_ex
= NULL
;
476 struct ioat_dma_descriptor
*hw
;
477 int num_descs
, with_ext
, idx
, i
;
479 u8 op
= result
? IOAT_OP_XOR_VAL
: IOAT_OP_XOR
;
483 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
484 /* we need 2x the number of descriptors to cover greater than 5
493 /* completion writes from the raid engine may pass completion
494 * writes from the legacy engine, so we need one extra null
495 * (legacy) descriptor to ensure all completion writes arrive in
498 if (likely(num_descs
) && ioat2_check_space_lock(ioat
, num_descs
+1) == 0)
504 struct ioat_raw_descriptor
*descs
[2];
505 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
508 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
511 /* save a branch by unconditionally retrieving the
512 * extended descriptor xor_set_src() knows to not write
513 * to it in the single descriptor case
515 ext
= ioat2_get_ring_ent(ioat
, idx
+ i
+ 1);
516 xor_ex
= ext
->xor_ex
;
518 descs
[0] = (struct ioat_raw_descriptor
*) xor;
519 descs
[1] = (struct ioat_raw_descriptor
*) xor_ex
;
520 for (s
= 0; s
< src_cnt
; s
++)
521 xor_set_src(descs
, src
[s
], offset
, s
);
522 xor->size
= xfer_size
;
523 xor->dst_addr
= dest
+ offset
;
526 xor->ctl_f
.src_cnt
= src_cnt_to_hw(src_cnt
);
530 dump_desc_dbg(ioat
, desc
);
531 } while ((i
+= 1 + with_ext
) < num_descs
);
533 /* last xor descriptor carries the unmap parameters and fence bit */
534 desc
->txd
.flags
= flags
;
535 desc
->len
= total_len
;
537 desc
->result
= result
;
538 xor->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
540 /* completion descriptor carries interrupt bit */
541 compl_desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
542 compl_desc
->txd
.flags
= flags
& DMA_PREP_INTERRUPT
;
546 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
547 hw
->ctl_f
.compl_write
= 1;
548 hw
->size
= NULL_DESC_BUFFER_SIZE
;
549 dump_desc_dbg(ioat
, compl_desc
);
551 /* we leave the channel locked to ensure in order submission */
552 return &compl_desc
->txd
;
555 static struct dma_async_tx_descriptor
*
556 ioat3_prep_xor(struct dma_chan
*chan
, dma_addr_t dest
, dma_addr_t
*src
,
557 unsigned int src_cnt
, size_t len
, unsigned long flags
)
559 return __ioat3_prep_xor_lock(chan
, NULL
, dest
, src
, src_cnt
, len
, flags
);
562 struct dma_async_tx_descriptor
*
563 ioat3_prep_xor_val(struct dma_chan
*chan
, dma_addr_t
*src
,
564 unsigned int src_cnt
, size_t len
,
565 enum sum_check_flags
*result
, unsigned long flags
)
567 /* the cleanup routine only sets bits on validate failure, it
568 * does not clear bits on validate success... so clear it here
572 return __ioat3_prep_xor_lock(chan
, result
, src
[0], &src
[1],
573 src_cnt
- 1, len
, flags
);
577 dump_pq_desc_dbg(struct ioat2_dma_chan
*ioat
, struct ioat_ring_ent
*desc
, struct ioat_ring_ent
*ext
)
579 struct device
*dev
= to_dev(&ioat
->base
);
580 struct ioat_pq_descriptor
*pq
= desc
->pq
;
581 struct ioat_pq_ext_descriptor
*pq_ex
= ext
? ext
->pq_ex
: NULL
;
582 struct ioat_raw_descriptor
*descs
[] = { (void *) pq
, (void *) pq_ex
};
583 int src_cnt
= src_cnt_to_sw(pq
->ctl_f
.src_cnt
);
586 dev_dbg(dev
, "desc[%d]: (%#llx->%#llx) flags: %#x"
587 " sz: %#x ctl: %#x (op: %d int: %d compl: %d pq: '%s%s' src_cnt: %d)\n",
588 desc_id(desc
), (unsigned long long) desc
->txd
.phys
,
589 (unsigned long long) (pq_ex
? pq_ex
->next
: pq
->next
),
590 desc
->txd
.flags
, pq
->size
, pq
->ctl
, pq
->ctl_f
.op
, pq
->ctl_f
.int_en
,
591 pq
->ctl_f
.compl_write
,
592 pq
->ctl_f
.p_disable
? "" : "p", pq
->ctl_f
.q_disable
? "" : "q",
594 for (i
= 0; i
< src_cnt
; i
++)
595 dev_dbg(dev
, "\tsrc[%d]: %#llx coef: %#x\n", i
,
596 (unsigned long long) pq_get_src(descs
, i
), pq
->coef
[i
]);
597 dev_dbg(dev
, "\tP: %#llx\n", pq
->p_addr
);
598 dev_dbg(dev
, "\tQ: %#llx\n", pq
->q_addr
);
601 static struct dma_async_tx_descriptor
*
602 __ioat3_prep_pq_lock(struct dma_chan
*c
, enum sum_check_flags
*result
,
603 const dma_addr_t
*dst
, const dma_addr_t
*src
,
604 unsigned int src_cnt
, const unsigned char *scf
,
605 size_t len
, unsigned long flags
)
607 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
608 struct ioat_chan_common
*chan
= &ioat
->base
;
609 struct ioat_ring_ent
*compl_desc
;
610 struct ioat_ring_ent
*desc
;
611 struct ioat_ring_ent
*ext
;
612 size_t total_len
= len
;
613 struct ioat_pq_descriptor
*pq
;
614 struct ioat_pq_ext_descriptor
*pq_ex
= NULL
;
615 struct ioat_dma_descriptor
*hw
;
617 u8 op
= result
? IOAT_OP_PQ_VAL
: IOAT_OP_PQ
;
618 int i
, s
, idx
, with_ext
, num_descs
;
620 dev_dbg(to_dev(chan
), "%s\n", __func__
);
621 /* the engine requires at least two sources (we provide
622 * at least 1 implied source in the DMA_PREP_CONTINUE case)
624 BUG_ON(src_cnt
+ dmaf_continue(flags
) < 2);
626 num_descs
= ioat2_xferlen_to_descs(ioat
, len
);
627 /* we need 2x the number of descriptors to cover greater than 3
628 * sources (we need 1 extra source in the q-only continuation
629 * case and 3 extra sources in the p+q continuation case.
631 if (src_cnt
+ dmaf_p_disabled_continue(flags
) > 3 ||
632 (dmaf_continue(flags
) && !dmaf_p_disabled_continue(flags
))) {
638 /* completion writes from the raid engine may pass completion
639 * writes from the legacy engine, so we need one extra null
640 * (legacy) descriptor to ensure all completion writes arrive in
643 if (likely(num_descs
) &&
644 ioat2_check_space_lock(ioat
, num_descs
+1) == 0)
650 struct ioat_raw_descriptor
*descs
[2];
651 size_t xfer_size
= min_t(size_t, len
, 1 << ioat
->xfercap_log
);
653 desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
656 /* save a branch by unconditionally retrieving the
657 * extended descriptor pq_set_src() knows to not write
658 * to it in the single descriptor case
660 ext
= ioat2_get_ring_ent(ioat
, idx
+ i
+ with_ext
);
663 descs
[0] = (struct ioat_raw_descriptor
*) pq
;
664 descs
[1] = (struct ioat_raw_descriptor
*) pq_ex
;
666 for (s
= 0; s
< src_cnt
; s
++)
667 pq_set_src(descs
, src
[s
], offset
, scf
[s
], s
);
669 /* see the comment for dma_maxpq in include/linux/dmaengine.h */
670 if (dmaf_p_disabled_continue(flags
))
671 pq_set_src(descs
, dst
[1], offset
, 1, s
++);
672 else if (dmaf_continue(flags
)) {
673 pq_set_src(descs
, dst
[0], offset
, 0, s
++);
674 pq_set_src(descs
, dst
[1], offset
, 1, s
++);
675 pq_set_src(descs
, dst
[1], offset
, 0, s
++);
677 pq
->size
= xfer_size
;
678 pq
->p_addr
= dst
[0] + offset
;
679 pq
->q_addr
= dst
[1] + offset
;
682 pq
->ctl_f
.src_cnt
= src_cnt_to_hw(s
);
683 pq
->ctl_f
.p_disable
= !!(flags
& DMA_PREP_PQ_DISABLE_P
);
684 pq
->ctl_f
.q_disable
= !!(flags
& DMA_PREP_PQ_DISABLE_Q
);
688 } while ((i
+= 1 + with_ext
) < num_descs
);
690 /* last pq descriptor carries the unmap parameters and fence bit */
691 desc
->txd
.flags
= flags
;
692 desc
->len
= total_len
;
694 desc
->result
= result
;
695 pq
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
696 dump_pq_desc_dbg(ioat
, desc
, ext
);
698 /* completion descriptor carries interrupt bit */
699 compl_desc
= ioat2_get_ring_ent(ioat
, idx
+ i
);
700 compl_desc
->txd
.flags
= flags
& DMA_PREP_INTERRUPT
;
704 hw
->ctl_f
.int_en
= !!(flags
& DMA_PREP_INTERRUPT
);
705 hw
->ctl_f
.compl_write
= 1;
706 hw
->size
= NULL_DESC_BUFFER_SIZE
;
707 dump_desc_dbg(ioat
, compl_desc
);
709 /* we leave the channel locked to ensure in order submission */
710 return &compl_desc
->txd
;
713 static struct dma_async_tx_descriptor
*
714 ioat3_prep_pq(struct dma_chan
*chan
, dma_addr_t
*dst
, dma_addr_t
*src
,
715 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
718 /* specify valid address for disabled result */
719 if (flags
& DMA_PREP_PQ_DISABLE_P
)
721 if (flags
& DMA_PREP_PQ_DISABLE_Q
)
724 /* handle the single source multiply case from the raid6
727 if ((flags
& DMA_PREP_PQ_DISABLE_P
) && src_cnt
== 1) {
728 dma_addr_t single_source
[2];
729 unsigned char single_source_coef
[2];
731 BUG_ON(flags
& DMA_PREP_PQ_DISABLE_Q
);
732 single_source
[0] = src
[0];
733 single_source
[1] = src
[0];
734 single_source_coef
[0] = scf
[0];
735 single_source_coef
[1] = 0;
737 return __ioat3_prep_pq_lock(chan
, NULL
, dst
, single_source
, 2,
738 single_source_coef
, len
, flags
);
740 return __ioat3_prep_pq_lock(chan
, NULL
, dst
, src
, src_cnt
, scf
,
744 struct dma_async_tx_descriptor
*
745 ioat3_prep_pq_val(struct dma_chan
*chan
, dma_addr_t
*pq
, dma_addr_t
*src
,
746 unsigned int src_cnt
, const unsigned char *scf
, size_t len
,
747 enum sum_check_flags
*pqres
, unsigned long flags
)
749 /* specify valid address for disabled result */
750 if (flags
& DMA_PREP_PQ_DISABLE_P
)
752 if (flags
& DMA_PREP_PQ_DISABLE_Q
)
755 /* the cleanup routine only sets bits on validate failure, it
756 * does not clear bits on validate success... so clear it here
760 return __ioat3_prep_pq_lock(chan
, pqres
, pq
, src
, src_cnt
, scf
, len
,
764 static struct dma_async_tx_descriptor
*
765 ioat3_prep_pqxor(struct dma_chan
*chan
, dma_addr_t dst
, dma_addr_t
*src
,
766 unsigned int src_cnt
, size_t len
, unsigned long flags
)
768 unsigned char scf
[src_cnt
];
771 memset(scf
, 0, src_cnt
);
773 flags
|= DMA_PREP_PQ_DISABLE_Q
;
774 pq
[1] = dst
; /* specify valid address for disabled result */
776 return __ioat3_prep_pq_lock(chan
, NULL
, pq
, src
, src_cnt
, scf
, len
,
780 struct dma_async_tx_descriptor
*
781 ioat3_prep_pqxor_val(struct dma_chan
*chan
, dma_addr_t
*src
,
782 unsigned int src_cnt
, size_t len
,
783 enum sum_check_flags
*result
, unsigned long flags
)
785 unsigned char scf
[src_cnt
];
788 /* the cleanup routine only sets bits on validate failure, it
789 * does not clear bits on validate success... so clear it here
793 memset(scf
, 0, src_cnt
);
795 flags
|= DMA_PREP_PQ_DISABLE_Q
;
796 pq
[1] = pq
[0]; /* specify valid address for disabled result */
798 return __ioat3_prep_pq_lock(chan
, result
, pq
, &src
[1], src_cnt
- 1, scf
,
802 static struct dma_async_tx_descriptor
*
803 ioat3_prep_interrupt_lock(struct dma_chan
*c
, unsigned long flags
)
805 struct ioat2_dma_chan
*ioat
= to_ioat2_chan(c
);
806 struct ioat_ring_ent
*desc
;
807 struct ioat_dma_descriptor
*hw
;
809 if (ioat2_check_space_lock(ioat
, 1) == 0)
810 desc
= ioat2_get_ring_ent(ioat
, ioat
->head
);
817 hw
->ctl_f
.int_en
= 1;
818 hw
->ctl_f
.fence
= !!(flags
& DMA_PREP_FENCE
);
819 hw
->ctl_f
.compl_write
= 1;
820 hw
->size
= NULL_DESC_BUFFER_SIZE
;
824 desc
->txd
.flags
= flags
;
827 dump_desc_dbg(ioat
, desc
);
829 /* we leave the channel locked to ensure in order submission */
833 static void __devinit
ioat3_dma_test_callback(void *dma_async_param
)
835 struct completion
*cmp
= dma_async_param
;
840 #define IOAT_NUM_SRC_TEST 6 /* must be <= 8 */
841 static int __devinit
ioat_xor_val_self_test(struct ioatdma_device
*device
)
845 struct page
*xor_srcs
[IOAT_NUM_SRC_TEST
];
846 struct page
*xor_val_srcs
[IOAT_NUM_SRC_TEST
+ 1];
847 dma_addr_t dma_srcs
[IOAT_NUM_SRC_TEST
+ 1];
848 dma_addr_t dma_addr
, dest_dma
;
849 struct dma_async_tx_descriptor
*tx
;
850 struct dma_chan
*dma_chan
;
856 struct completion cmp
;
858 struct device
*dev
= &device
->pdev
->dev
;
859 struct dma_device
*dma
= &device
->common
;
861 dev_dbg(dev
, "%s\n", __func__
);
863 if (!dma_has_cap(DMA_XOR
, dma
->cap_mask
))
866 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++) {
867 xor_srcs
[src_idx
] = alloc_page(GFP_KERNEL
);
868 if (!xor_srcs
[src_idx
]) {
870 __free_page(xor_srcs
[src_idx
]);
875 dest
= alloc_page(GFP_KERNEL
);
878 __free_page(xor_srcs
[src_idx
]);
882 /* Fill in src buffers */
883 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++) {
884 u8
*ptr
= page_address(xor_srcs
[src_idx
]);
885 for (i
= 0; i
< PAGE_SIZE
; i
++)
886 ptr
[i
] = (1 << src_idx
);
889 for (src_idx
= 0; src_idx
< IOAT_NUM_SRC_TEST
; src_idx
++)
890 cmp_byte
^= (u8
) (1 << src_idx
);
892 cmp_word
= (cmp_byte
<< 24) | (cmp_byte
<< 16) |
893 (cmp_byte
<< 8) | cmp_byte
;
895 memset(page_address(dest
), 0, PAGE_SIZE
);
897 dma_chan
= container_of(dma
->channels
.next
, struct dma_chan
,
899 if (dma
->device_alloc_chan_resources(dma_chan
) < 1) {
905 dest_dma
= dma_map_page(dev
, dest
, 0, PAGE_SIZE
, DMA_FROM_DEVICE
);
906 for (i
= 0; i
< IOAT_NUM_SRC_TEST
; i
++)
907 dma_srcs
[i
] = dma_map_page(dev
, xor_srcs
[i
], 0, PAGE_SIZE
,
909 tx
= dma
->device_prep_dma_xor(dma_chan
, dest_dma
, dma_srcs
,
910 IOAT_NUM_SRC_TEST
, PAGE_SIZE
,
914 dev_err(dev
, "Self-test xor prep failed\n");
920 init_completion(&cmp
);
921 tx
->callback
= ioat3_dma_test_callback
;
922 tx
->callback_param
= &cmp
;
923 cookie
= tx
->tx_submit(tx
);
925 dev_err(dev
, "Self-test xor setup failed\n");
929 dma
->device_issue_pending(dma_chan
);
931 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
933 if (dma
->device_tx_status(dma_chan
, cookie
, NULL
) != DMA_SUCCESS
) {
934 dev_err(dev
, "Self-test xor timed out\n");
939 dma_sync_single_for_cpu(dev
, dest_dma
, PAGE_SIZE
, DMA_FROM_DEVICE
);
940 for (i
= 0; i
< (PAGE_SIZE
/ sizeof(u32
)); i
++) {
941 u32
*ptr
= page_address(dest
);
942 if (ptr
[i
] != cmp_word
) {
943 dev_err(dev
, "Self-test xor failed compare\n");
948 dma_sync_single_for_device(dev
, dest_dma
, PAGE_SIZE
, DMA_TO_DEVICE
);
950 /* skip validate if the capability is not present */
951 if (!dma_has_cap(DMA_XOR_VAL
, dma_chan
->device
->cap_mask
))
954 /* validate the sources with the destintation page */
955 for (i
= 0; i
< IOAT_NUM_SRC_TEST
; i
++)
956 xor_val_srcs
[i
] = xor_srcs
[i
];
957 xor_val_srcs
[i
] = dest
;
961 for (i
= 0; i
< IOAT_NUM_SRC_TEST
+ 1; i
++)
962 dma_srcs
[i
] = dma_map_page(dev
, xor_val_srcs
[i
], 0, PAGE_SIZE
,
964 tx
= dma
->device_prep_dma_xor_val(dma_chan
, dma_srcs
,
965 IOAT_NUM_SRC_TEST
+ 1, PAGE_SIZE
,
966 &xor_val_result
, DMA_PREP_INTERRUPT
);
968 dev_err(dev
, "Self-test zero prep failed\n");
974 init_completion(&cmp
);
975 tx
->callback
= ioat3_dma_test_callback
;
976 tx
->callback_param
= &cmp
;
977 cookie
= tx
->tx_submit(tx
);
979 dev_err(dev
, "Self-test zero setup failed\n");
983 dma
->device_issue_pending(dma_chan
);
985 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
987 if (dma
->device_tx_status(dma_chan
, cookie
, NULL
) != DMA_SUCCESS
) {
988 dev_err(dev
, "Self-test validate timed out\n");
993 if (xor_val_result
!= 0) {
994 dev_err(dev
, "Self-test validate failed compare\n");
999 /* skip memset if the capability is not present */
1000 if (!dma_has_cap(DMA_MEMSET
, dma_chan
->device
->cap_mask
))
1001 goto free_resources
;
1004 dma_addr
= dma_map_page(dev
, dest
, 0,
1005 PAGE_SIZE
, DMA_FROM_DEVICE
);
1006 tx
= dma
->device_prep_dma_memset(dma_chan
, dma_addr
, 0, PAGE_SIZE
,
1007 DMA_PREP_INTERRUPT
);
1009 dev_err(dev
, "Self-test memset prep failed\n");
1011 goto free_resources
;
1015 init_completion(&cmp
);
1016 tx
->callback
= ioat3_dma_test_callback
;
1017 tx
->callback_param
= &cmp
;
1018 cookie
= tx
->tx_submit(tx
);
1020 dev_err(dev
, "Self-test memset setup failed\n");
1022 goto free_resources
;
1024 dma
->device_issue_pending(dma_chan
);
1026 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
1028 if (dma
->device_tx_status(dma_chan
, cookie
, NULL
) != DMA_SUCCESS
) {
1029 dev_err(dev
, "Self-test memset timed out\n");
1031 goto free_resources
;
1034 for (i
= 0; i
< PAGE_SIZE
/sizeof(u32
); i
++) {
1035 u32
*ptr
= page_address(dest
);
1037 dev_err(dev
, "Self-test memset failed compare\n");
1039 goto free_resources
;
1043 /* test for non-zero parity sum */
1045 for (i
= 0; i
< IOAT_NUM_SRC_TEST
+ 1; i
++)
1046 dma_srcs
[i
] = dma_map_page(dev
, xor_val_srcs
[i
], 0, PAGE_SIZE
,
1048 tx
= dma
->device_prep_dma_xor_val(dma_chan
, dma_srcs
,
1049 IOAT_NUM_SRC_TEST
+ 1, PAGE_SIZE
,
1050 &xor_val_result
, DMA_PREP_INTERRUPT
);
1052 dev_err(dev
, "Self-test 2nd zero prep failed\n");
1054 goto free_resources
;
1058 init_completion(&cmp
);
1059 tx
->callback
= ioat3_dma_test_callback
;
1060 tx
->callback_param
= &cmp
;
1061 cookie
= tx
->tx_submit(tx
);
1063 dev_err(dev
, "Self-test 2nd zero setup failed\n");
1065 goto free_resources
;
1067 dma
->device_issue_pending(dma_chan
);
1069 tmo
= wait_for_completion_timeout(&cmp
, msecs_to_jiffies(3000));
1071 if (dma
->device_tx_status(dma_chan
, cookie
, NULL
) != DMA_SUCCESS
) {
1072 dev_err(dev
, "Self-test 2nd validate timed out\n");
1074 goto free_resources
;
1077 if (xor_val_result
!= SUM_CHECK_P_RESULT
) {
1078 dev_err(dev
, "Self-test validate failed compare\n");
1080 goto free_resources
;
1084 dma
->device_free_chan_resources(dma_chan
);
1086 src_idx
= IOAT_NUM_SRC_TEST
;
1088 __free_page(xor_srcs
[src_idx
]);
1093 static int __devinit
ioat3_dma_self_test(struct ioatdma_device
*device
)
1095 int rc
= ioat_dma_self_test(device
);
1100 rc
= ioat_xor_val_self_test(device
);
1107 static int ioat3_reset_hw(struct ioat_chan_common
*chan
)
1109 /* throw away whatever the channel was doing and get it
1110 * initialized, with ioat3 specific workarounds
1112 struct ioatdma_device
*device
= chan
->device
;
1113 struct pci_dev
*pdev
= device
->pdev
;
1118 ioat2_quiesce(chan
, msecs_to_jiffies(100));
1120 chanerr
= readl(chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
1121 writel(chanerr
, chan
->reg_base
+ IOAT_CHANERR_OFFSET
);
1123 /* -= IOAT ver.3 workarounds =- */
1124 /* Write CHANERRMSK_INT with 3E07h to mask out the errors
1125 * that can cause stability issues for IOAT ver.3, and clear any
1128 pci_write_config_dword(pdev
, IOAT_PCI_CHANERRMASK_INT_OFFSET
, 0x3e07);
1129 err
= pci_read_config_dword(pdev
, IOAT_PCI_CHANERR_INT_OFFSET
, &chanerr
);
1131 dev_err(&pdev
->dev
, "channel error register unreachable\n");
1134 pci_write_config_dword(pdev
, IOAT_PCI_CHANERR_INT_OFFSET
, chanerr
);
1136 /* Clear DMAUNCERRSTS Cfg-Reg Parity Error status bit
1137 * (workaround for spurious config parity error after restart)
1139 pci_read_config_word(pdev
, IOAT_PCI_DEVICE_ID_OFFSET
, &dev_id
);
1140 if (dev_id
== PCI_DEVICE_ID_INTEL_IOAT_TBG0
)
1141 pci_write_config_dword(pdev
, IOAT_PCI_DMAUNCERRSTS_OFFSET
, 0x10);
1143 return ioat2_reset_sync(chan
, msecs_to_jiffies(200));
1146 int __devinit
ioat3_dma_probe(struct ioatdma_device
*device
, int dca
)
1148 struct pci_dev
*pdev
= device
->pdev
;
1149 int dca_en
= system_has_dca_enabled(pdev
);
1150 struct dma_device
*dma
;
1152 struct ioat_chan_common
*chan
;
1153 bool is_raid_device
= false;
1157 device
->enumerate_channels
= ioat2_enumerate_channels
;
1158 device
->reset_hw
= ioat3_reset_hw
;
1159 device
->self_test
= ioat3_dma_self_test
;
1160 dma
= &device
->common
;
1161 dma
->device_prep_dma_memcpy
= ioat2_dma_prep_memcpy_lock
;
1162 dma
->device_issue_pending
= ioat2_issue_pending
;
1163 dma
->device_alloc_chan_resources
= ioat2_alloc_chan_resources
;
1164 dma
->device_free_chan_resources
= ioat2_free_chan_resources
;
1166 dma_cap_set(DMA_INTERRUPT
, dma
->cap_mask
);
1167 dma
->device_prep_dma_interrupt
= ioat3_prep_interrupt_lock
;
1169 cap
= readl(device
->reg_base
+ IOAT_DMA_CAP_OFFSET
);
1171 /* dca is incompatible with raid operations */
1172 if (dca_en
&& (cap
& (IOAT_CAP_XOR
|IOAT_CAP_PQ
)))
1173 cap
&= ~(IOAT_CAP_XOR
|IOAT_CAP_PQ
);
1175 if (cap
& IOAT_CAP_XOR
) {
1176 is_raid_device
= true;
1180 dma_cap_set(DMA_XOR
, dma
->cap_mask
);
1181 dma
->device_prep_dma_xor
= ioat3_prep_xor
;
1183 dma_cap_set(DMA_XOR_VAL
, dma
->cap_mask
);
1184 dma
->device_prep_dma_xor_val
= ioat3_prep_xor_val
;
1186 if (cap
& IOAT_CAP_PQ
) {
1187 is_raid_device
= true;
1188 dma_set_maxpq(dma
, 8, 0);
1191 dma_cap_set(DMA_PQ
, dma
->cap_mask
);
1192 dma
->device_prep_dma_pq
= ioat3_prep_pq
;
1194 dma_cap_set(DMA_PQ_VAL
, dma
->cap_mask
);
1195 dma
->device_prep_dma_pq_val
= ioat3_prep_pq_val
;
1197 if (!(cap
& IOAT_CAP_XOR
)) {
1201 dma_cap_set(DMA_XOR
, dma
->cap_mask
);
1202 dma
->device_prep_dma_xor
= ioat3_prep_pqxor
;
1204 dma_cap_set(DMA_XOR_VAL
, dma
->cap_mask
);
1205 dma
->device_prep_dma_xor_val
= ioat3_prep_pqxor_val
;
1208 if (is_raid_device
&& (cap
& IOAT_CAP_FILL_BLOCK
)) {
1209 dma_cap_set(DMA_MEMSET
, dma
->cap_mask
);
1210 dma
->device_prep_dma_memset
= ioat3_prep_memset_lock
;
1214 if (is_raid_device
) {
1215 dma
->device_tx_status
= ioat3_tx_status
;
1216 device
->cleanup_fn
= ioat3_cleanup_event
;
1217 device
->timer_fn
= ioat3_timer_event
;
1219 dma
->device_tx_status
= ioat_dma_tx_status
;
1220 device
->cleanup_fn
= ioat2_cleanup_event
;
1221 device
->timer_fn
= ioat2_timer_event
;
1224 #ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA
1225 dma_cap_clear(DMA_PQ_VAL
, dma
->cap_mask
);
1226 dma
->device_prep_dma_pq_val
= NULL
;
1229 #ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA
1230 dma_cap_clear(DMA_XOR_VAL
, dma
->cap_mask
);
1231 dma
->device_prep_dma_xor_val
= NULL
;
1234 err
= ioat_probe(device
);
1237 ioat_set_tcp_copy_break(262144);
1239 list_for_each_entry(c
, &dma
->channels
, device_node
) {
1240 chan
= to_chan_common(c
);
1241 writel(IOAT_DMA_DCA_ANY_CPU
,
1242 chan
->reg_base
+ IOAT_DCACTRL_OFFSET
);
1245 err
= ioat_register(device
);
1249 ioat_kobject_add(device
, &ioat2_ktype
);
1252 device
->dca
= ioat3_dca_init(pdev
, device
->reg_base
);