2 * Copyright (C) 1994 Linus Torvalds
4 * Pentium III FXSR, SSE support
5 * General FPU state handling cleanups
6 * Gareth Hughes <gareth@valinux.com>, May 2000
7 * x86-64 work by Andi Kleen 2002
10 #ifndef _ASM_X86_I387_H
11 #define _ASM_X86_I387_H
15 #include <linux/sched.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/regset.h>
18 #include <linux/hardirq.h>
19 #include <linux/slab.h>
21 #include <asm/cpufeature.h>
22 #include <asm/processor.h>
23 #include <asm/sigcontext.h>
25 #include <asm/uaccess.h>
26 #include <asm/xsave.h>
28 extern unsigned int sig_xstate_size
;
29 extern void fpu_init(void);
30 extern void mxcsr_feature_mask_init(void);
31 extern int init_fpu(struct task_struct
*child
);
32 extern void math_state_restore(void);
33 extern int dump_fpu(struct pt_regs
*, struct user_i387_struct
*);
35 extern user_regset_active_fn fpregs_active
, xfpregs_active
;
36 extern user_regset_get_fn fpregs_get
, xfpregs_get
, fpregs_soft_get
,
38 extern user_regset_set_fn fpregs_set
, xfpregs_set
, fpregs_soft_set
,
42 * xstateregs_active == fpregs_active. Please refer to the comment
43 * at the definition of fpregs_active.
45 #define xstateregs_active fpregs_active
47 extern struct _fpx_sw_bytes fx_sw_reserved
;
48 #ifdef CONFIG_IA32_EMULATION
49 extern unsigned int sig_xstate_ia32_size
;
50 extern struct _fpx_sw_bytes fx_sw_reserved_ia32
;
53 extern int save_i387_xstate_ia32(void __user
*buf
);
54 extern int restore_i387_xstate_ia32(void __user
*buf
);
57 #ifdef CONFIG_MATH_EMULATION
58 extern void finit_soft_fpu(struct i387_soft_struct
*soft
);
60 static inline void finit_soft_fpu(struct i387_soft_struct
*soft
) {}
63 #define X87_FSW_ES (1 << 7) /* Exception Summary */
65 static __always_inline __pure
bool use_xsaveopt(void)
67 return static_cpu_has(X86_FEATURE_XSAVEOPT
);
70 static __always_inline __pure
bool use_xsave(void)
72 return static_cpu_has(X86_FEATURE_XSAVE
);
75 static __always_inline __pure
bool use_fxsr(void)
77 return static_cpu_has(X86_FEATURE_FXSR
);
80 extern void __sanitize_i387_state(struct task_struct
*);
82 static inline void sanitize_i387_state(struct task_struct
*tsk
)
86 __sanitize_i387_state(tsk
);
90 static inline int fxrstor_checking(struct i387_fxsave_struct
*fx
)
94 /* See comment in fxsave() below. */
95 #ifdef CONFIG_AS_FXSAVEQ
96 asm volatile("1: fxrstorq %[fx]\n\t"
98 ".section .fixup,\"ax\"\n"
99 "3: movl $-1,%[err]\n"
104 : [fx
] "m" (*fx
), "0" (0));
106 asm volatile("1: rex64/fxrstor (%[fx])\n\t"
108 ".section .fixup,\"ax\"\n"
109 "3: movl $-1,%[err]\n"
114 : [fx
] "R" (fx
), "m" (*fx
), "0" (0));
119 static inline int fxsave_user(struct i387_fxsave_struct __user
*fx
)
124 * Clear the bytes not touched by the fxsave and reserved
127 err
= __clear_user(&fx
->sw_reserved
,
128 sizeof(struct _fpx_sw_bytes
));
132 /* See comment in fxsave() below. */
133 #ifdef CONFIG_AS_FXSAVEQ
134 asm volatile("1: fxsaveq %[fx]\n\t"
136 ".section .fixup,\"ax\"\n"
137 "3: movl $-1,%[err]\n"
141 : [err
] "=r" (err
), [fx
] "=m" (*fx
)
144 asm volatile("1: rex64/fxsave (%[fx])\n\t"
146 ".section .fixup,\"ax\"\n"
147 "3: movl $-1,%[err]\n"
151 : [err
] "=r" (err
), "=m" (*fx
)
152 : [fx
] "R" (fx
), "0" (0));
155 __clear_user(fx
, sizeof(struct i387_fxsave_struct
)))
157 /* No need to clear here because the caller clears USED_MATH */
161 static inline void fpu_fxsave(struct fpu
*fpu
)
163 /* Using "rex64; fxsave %0" is broken because, if the memory operand
164 uses any extended registers for addressing, a second REX prefix
165 will be generated (to the assembler, rex64 followed by semicolon
166 is a separate instruction), and hence the 64-bitness is lost. */
168 #ifdef CONFIG_AS_FXSAVEQ
169 /* Using "fxsaveq %0" would be the ideal choice, but is only supported
170 starting with gas 2.16. */
171 __asm__
__volatile__("fxsaveq %0"
172 : "=m" (fpu
->state
->fxsave
));
174 /* Using, as a workaround, the properly prefixed form below isn't
175 accepted by any binutils version so far released, complaining that
176 the same type of prefix is used twice if an extended register is
177 needed for addressing (fix submitted to mainline 2005-11-21).
178 asm volatile("rex64/fxsave %0"
179 : "=m" (fpu->state->fxsave));
180 This, however, we can work around by forcing the compiler to select
181 an addressing mode that doesn't require extended registers. */
182 asm volatile("rex64/fxsave (%[fx])"
183 : "=m" (fpu
->state
->fxsave
)
184 : [fx
] "R" (&fpu
->state
->fxsave
));
188 #else /* CONFIG_X86_32 */
190 /* perform fxrstor iff the processor has extended states, otherwise frstor */
191 static inline int fxrstor_checking(struct i387_fxsave_struct
*fx
)
194 * The "nop" is needed to make the instructions the same
206 static inline void fpu_fxsave(struct fpu
*fpu
)
208 asm volatile("fxsave %[fx]"
209 : [fx
] "=m" (fpu
->state
->fxsave
));
212 #endif /* CONFIG_X86_64 */
215 * These must be called with preempt disabled
217 static inline void fpu_save_init(struct fpu
*fpu
)
223 * xsave header may indicate the init state of the FP.
225 if (!(fpu
->state
->xsave
.xsave_hdr
.xstate_bv
& XSTATE_FP
))
227 } else if (use_fxsr()) {
230 asm volatile("fnsave %[fx]; fwait"
231 : [fx
] "=m" (fpu
->state
->fsave
));
235 if (unlikely(fpu
->state
->fxsave
.swd
& X87_FSW_ES
))
236 asm volatile("fnclex");
239 static inline void __save_init_fpu(struct task_struct
*tsk
)
241 fpu_save_init(&tsk
->thread
.fpu
);
244 static inline int fpu_fxrstor_checking(struct fpu
*fpu
)
246 return fxrstor_checking(&fpu
->state
->fxsave
);
249 static inline int fpu_restore_checking(struct fpu
*fpu
)
252 return fpu_xrstor_checking(fpu
);
254 return fpu_fxrstor_checking(fpu
);
257 static inline int restore_fpu_checking(struct task_struct
*tsk
)
259 return fpu_restore_checking(&tsk
->thread
.fpu
);
263 * Software FPU state helpers. Careful: these need to
264 * be preemption protection *and* they need to be
265 * properly paired with the CR0.TS changes!
267 static inline int __thread_has_fpu(struct task_struct
*tsk
)
269 return tsk
->thread
.has_fpu
;
272 /* Must be paired with an 'stts' after! */
273 static inline void __thread_clear_has_fpu(struct task_struct
*tsk
)
275 tsk
->thread
.has_fpu
= 0;
278 /* Must be paired with a 'clts' before! */
279 static inline void __thread_set_has_fpu(struct task_struct
*tsk
)
281 tsk
->thread
.has_fpu
= 1;
285 * Encapsulate the CR0.TS handling together with the
288 * These generally need preemption protection to work,
289 * do try to avoid using these on their own.
291 static inline void __thread_fpu_end(struct task_struct
*tsk
)
293 __thread_clear_has_fpu(tsk
);
297 static inline void __thread_fpu_begin(struct task_struct
*tsk
)
300 __thread_set_has_fpu(tsk
);
304 * Signal frame handlers...
306 extern int save_i387_xstate(void __user
*buf
);
307 extern int restore_i387_xstate(void __user
*buf
);
309 static inline void __unlazy_fpu(struct task_struct
*tsk
)
311 if (__thread_has_fpu(tsk
)) {
312 __save_init_fpu(tsk
);
313 __thread_fpu_end(tsk
);
315 tsk
->fpu_counter
= 0;
318 static inline void __clear_fpu(struct task_struct
*tsk
)
320 if (__thread_has_fpu(tsk
)) {
321 /* Ignore delayed exceptions from user space */
322 asm volatile("1: fwait\n"
324 _ASM_EXTABLE(1b
, 2b
));
325 __thread_fpu_end(tsk
);
330 * Were we in an interrupt that interrupted kernel mode?
332 * We can do a kernel_fpu_begin/end() pair *ONLY* if that
333 * pair does nothing at all: the thread must not have fpu (so
334 * that we don't try to save the FPU state), and TS must
335 * be set (so that the clts/stts pair does nothing that is
336 * visible in the interrupted kernel thread).
338 static inline bool interrupted_kernel_fpu_idle(void)
340 return !__thread_has_fpu(current
) &&
341 (read_cr0() & X86_CR0_TS
);
345 * Were we in user mode (or vm86 mode) when we were
348 * Doing kernel_fpu_begin/end() is ok if we are running
349 * in an interrupt context from user mode - we'll just
350 * save the FPU state as required.
352 static inline bool interrupted_user_mode(void)
354 struct pt_regs
*regs
= get_irq_regs();
355 return regs
&& user_mode_vm(regs
);
359 * Can we use the FPU in kernel mode with the
360 * whole "kernel_fpu_begin/end()" sequence?
362 * It's always ok in process context (ie "not interrupt")
363 * but it is sometimes ok even from an irq.
365 static inline bool irq_fpu_usable(void)
367 return !in_interrupt() ||
368 interrupted_user_mode() ||
369 interrupted_kernel_fpu_idle();
372 static inline void kernel_fpu_begin(void)
374 struct task_struct
*me
= current
;
376 WARN_ON_ONCE(!irq_fpu_usable());
378 if (__thread_has_fpu(me
)) {
380 __thread_clear_has_fpu(me
);
381 /* We do 'stts()' in kernel_fpu_end() */
386 static inline void kernel_fpu_end(void)
393 * Some instructions like VIA's padlock instructions generate a spurious
394 * DNA fault but don't modify SSE registers. And these instructions
395 * get used from interrupt context as well. To prevent these kernel instructions
396 * in interrupt context interacting wrongly with other user/kernel fpu usage, we
397 * should use them only in the context of irq_ts_save/restore()
399 static inline int irq_ts_save(void)
402 * If in process context and not atomic, we can take a spurious DNA fault.
403 * Otherwise, doing clts() in process context requires disabling preemption
404 * or some heavy lifting like kernel_fpu_begin()
409 if (read_cr0() & X86_CR0_TS
) {
417 static inline void irq_ts_restore(int TS_state
)
424 * The question "does this thread have fpu access?"
425 * is slightly racy, since preemption could come in
426 * and revoke it immediately after the test.
428 * However, even in that very unlikely scenario,
429 * we can just assume we have FPU access - typically
430 * to save the FP state - we'll just take a #NM
431 * fault and get the FPU access back.
433 * The actual user_fpu_begin/end() functions
434 * need to be preemption-safe, though.
436 * NOTE! user_fpu_end() must be used only after you
437 * have saved the FP state, and user_fpu_begin() must
438 * be used only immediately before restoring it.
439 * These functions do not do any save/restore on
442 static inline int user_has_fpu(void)
444 return __thread_has_fpu(current
);
447 static inline void user_fpu_end(void)
450 __thread_fpu_end(current
);
454 static inline void user_fpu_begin(void)
458 __thread_fpu_begin(current
);
463 * These disable preemption on their own and are safe
465 static inline void save_init_fpu(struct task_struct
*tsk
)
467 WARN_ON_ONCE(!__thread_has_fpu(tsk
));
469 __save_init_fpu(tsk
);
470 __thread_fpu_end(tsk
);
474 static inline void unlazy_fpu(struct task_struct
*tsk
)
481 static inline void clear_fpu(struct task_struct
*tsk
)
489 * i387 state interaction
491 static inline unsigned short get_fpu_cwd(struct task_struct
*tsk
)
494 return tsk
->thread
.fpu
.state
->fxsave
.cwd
;
496 return (unsigned short)tsk
->thread
.fpu
.state
->fsave
.cwd
;
500 static inline unsigned short get_fpu_swd(struct task_struct
*tsk
)
503 return tsk
->thread
.fpu
.state
->fxsave
.swd
;
505 return (unsigned short)tsk
->thread
.fpu
.state
->fsave
.swd
;
509 static inline unsigned short get_fpu_mxcsr(struct task_struct
*tsk
)
512 return tsk
->thread
.fpu
.state
->fxsave
.mxcsr
;
514 return MXCSR_DEFAULT
;
518 static bool fpu_allocated(struct fpu
*fpu
)
520 return fpu
->state
!= NULL
;
523 static inline int fpu_alloc(struct fpu
*fpu
)
525 if (fpu_allocated(fpu
))
527 fpu
->state
= kmem_cache_alloc(task_xstate_cachep
, GFP_KERNEL
);
530 WARN_ON((unsigned long)fpu
->state
& 15);
534 static inline void fpu_free(struct fpu
*fpu
)
537 kmem_cache_free(task_xstate_cachep
, fpu
->state
);
542 static inline void fpu_copy(struct fpu
*dst
, struct fpu
*src
)
544 memcpy(dst
->state
, src
->state
, xstate_size
);
547 extern void fpu_finit(struct fpu
*fpu
);
549 #endif /* __ASSEMBLY__ */
551 #endif /* _ASM_X86_I387_H */