| blob | c00120d56f8f38cc61f2c5fd80014f740b395e60 |
1 /*
2 * PowerPC version
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
11 *
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
19 *
20 */
22 #include <linux/init.h>
23 #include <asm/processor.h>
24 #include <asm/page.h>
25 #include <asm/mmu.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
33 /* Macro to make the code more readable. */
34 #ifdef CONFIG_8xx_CPU6
35 #define DO_8xx_CPU6(val, reg) \
36 li reg, val; \
37 stw reg, 12(r0); \
38 lwz reg, 12(r0);
39 #else
40 #define DO_8xx_CPU6(val, reg)
41 #endif
42 __HEAD
43 _ENTRY(_stext);
44 _ENTRY(_start);
46 /* MPC8xx
47 * This port was done on an MBX board with an 860. Right now I only
48 * support an ELF compressed (zImage) boot from EPPC-Bug because the
49 * code there loads up some registers before calling us:
50 * r3: ptr to board info data
51 * r4: initrd_start or if no initrd then 0
52 * r5: initrd_end - unused if r4 is 0
53 * r6: Start of command line string
54 * r7: End of command line string
55 *
56 * I decided to use conditional compilation instead of checking PVR and
57 * adding more processor specific branches around code I don't need.
58 * Since this is an embedded processor, I also appreciate any memory
59 * savings I can get.
60 *
61 * The MPC8xx does not have any BATs, but it supports large page sizes.
62 * We first initialize the MMU to support 8M byte pages, then load one
63 * entry into each of the instruction and data TLBs to map the first
64 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
65 * the "internal" processor registers before MMU_init is called.
66 *
67 * The TLB code currently contains a major hack. Since I use the condition
68 * code register, I have to save and restore it. I am out of registers, so
69 * I just store it in memory location 0 (the TLB handlers are not reentrant).
70 * To avoid making any decisions, I need to use the "segment" valid bit
71 * in the first level table, but that would require many changes to the
72 * Linux page directory/table functions that I don't want to do right now.
73 *
74 * I used to use SPRG2 for a temporary register in the TLB handler, but it
75 * has since been put to other uses. I now use a hack to save a register
76 * and the CCR at memory location 0.....Someday I'll fix this.....
77 * -- Dan
78 */
79 .globl __start
80 __start:
81 mr r31,r3 /* save parameters */
82 mr r30,r4
83 mr r29,r5
84 mr r28,r6
85 mr r27,r7
87 /* We have to turn on the MMU right away so we get cache modes
88 * set correctly.
89 */
90 bl initial_mmu
92 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
93 * ready to work.
94 */
96 turn_on_mmu:
97 mfmsr r0
98 ori r0,r0,MSR_DR|MSR_IR
99 mtspr SPRN_SRR1,r0
100 lis r0,start_here@h
101 ori r0,r0,start_here@l
102 mtspr SPRN_SRR0,r0
103 SYNC
104 rfi /* enables MMU */
106 /*
107 * Exception entry code. This code runs with address translation
108 * turned off, i.e. using physical addresses.
109 * We assume sprg3 has the physical address of the current
110 * task's thread_struct.
111 */
112 #define EXCEPTION_PROLOG \
113 mtspr SPRN_SPRG_SCRATCH0,r10; \
114 mtspr SPRN_SPRG_SCRATCH1,r11; \
115 mfcr r10; \
116 EXCEPTION_PROLOG_1; \
117 EXCEPTION_PROLOG_2
119 #define EXCEPTION_PROLOG_1 \
120 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
121 andi. r11,r11,MSR_PR; \
122 tophys(r11,r1); /* use tophys(r1) if kernel */ \
123 beq 1f; \
124 mfspr r11,SPRN_SPRG_THREAD; \
125 lwz r11,THREAD_INFO-THREAD(r11); \
126 addi r11,r11,THREAD_SIZE; \
127 tophys(r11,r11); \
128 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
131 #define EXCEPTION_PROLOG_2 \
132 CLR_TOP32(r11); \
133 stw r10,_CCR(r11); /* save registers */ \
134 stw r12,GPR12(r11); \
135 stw r9,GPR9(r11); \
136 mfspr r10,SPRN_SPRG_SCRATCH0; \
137 stw r10,GPR10(r11); \
138 mfspr r12,SPRN_SPRG_SCRATCH1; \
139 stw r12,GPR11(r11); \
140 mflr r10; \
141 stw r10,_LINK(r11); \
142 mfspr r12,SPRN_SRR0; \
143 mfspr r9,SPRN_SRR1; \
144 stw r1,GPR1(r11); \
145 stw r1,0(r11); \
146 tovirt(r1,r11); /* set new kernel sp */ \
147 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
148 MTMSRD(r10); /* (except for mach check in rtas) */ \
149 stw r0,GPR0(r11); \
150 SAVE_4GPRS(3, r11); \
151 SAVE_2GPRS(7, r11)
153 /*
154 * Note: code which follows this uses cr0.eq (set if from kernel),
155 * r11, r12 (SRR0), and r9 (SRR1).
156 *
157 * Note2: once we have set r1 we are in a position to take exceptions
158 * again, and we could thus set MSR:RI at that point.
159 */
161 /*
162 * Exception vectors.
163 */
164 #define EXCEPTION(n, label, hdlr, xfer) \
165 . = n; \
166 label: \
167 EXCEPTION_PROLOG; \
168 addi r3,r1,STACK_FRAME_OVERHEAD; \
169 xfer(n, hdlr)
171 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
172 li r10,trap; \
173 stw r10,_TRAP(r11); \
174 li r10,MSR_KERNEL; \
175 copyee(r10, r9); \
176 bl tfer; \
177 i##n: \
178 .long hdlr; \
179 .long ret
181 #define COPY_EE(d, s) rlwimi d,s,0,16,16
182 #define NOCOPY(d, s)
184 #define EXC_XFER_STD(n, hdlr) \
185 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
186 ret_from_except_full)
188 #define EXC_XFER_LITE(n, hdlr) \
189 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
190 ret_from_except)
192 #define EXC_XFER_EE(n, hdlr) \
193 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
194 ret_from_except_full)
196 #define EXC_XFER_EE_LITE(n, hdlr) \
197 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
198 ret_from_except)
200 /* System reset */
201 EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
203 /* Machine check */
204 . = 0x200
205 MachineCheck:
206 EXCEPTION_PROLOG
207 mfspr r4,SPRN_DAR
208 stw r4,_DAR(r11)
209 li r5,0x00f0
210 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
211 mfspr r5,SPRN_DSISR
212 stw r5,_DSISR(r11)
213 addi r3,r1,STACK_FRAME_OVERHEAD
214 EXC_XFER_STD(0x200, machine_check_exception)
216 /* Data access exception.
217 * This is "never generated" by the MPC8xx. We jump to it for other
218 * translation errors.
219 */
220 . = 0x300
221 DataAccess:
222 EXCEPTION_PROLOG
223 mfspr r10,SPRN_DSISR
224 stw r10,_DSISR(r11)
225 mr r5,r10
226 mfspr r4,SPRN_DAR
227 li r10,0x00f0
228 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
229 EXC_XFER_EE_LITE(0x300, handle_page_fault)
231 /* Instruction access exception.
232 * This is "never generated" by the MPC8xx. We jump to it for other
233 * translation errors.
234 */
235 . = 0x400
236 InstructionAccess:
237 EXCEPTION_PROLOG
238 mr r4,r12
239 mr r5,r9
240 EXC_XFER_EE_LITE(0x400, handle_page_fault)
242 /* External interrupt */
243 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
245 /* Alignment exception */
246 . = 0x600
247 Alignment:
248 EXCEPTION_PROLOG
249 mfspr r4,SPRN_DAR
250 stw r4,_DAR(r11)
251 li r5,0x00f0
252 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
253 mfspr r5,SPRN_DSISR
254 stw r5,_DSISR(r11)
255 addi r3,r1,STACK_FRAME_OVERHEAD
256 EXC_XFER_EE(0x600, alignment_exception)
258 /* Program check exception */
259 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
261 /* No FPU on MPC8xx. This exception is not supposed to happen.
262 */
263 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
265 /* Decrementer */
266 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
268 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
269 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
271 /* System call */
272 . = 0xc00
273 SystemCall:
274 EXCEPTION_PROLOG
275 EXC_XFER_EE_LITE(0xc00, DoSyscall)
277 /* Single step - not used on 601 */
278 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
279 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
280 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
282 /* On the MPC8xx, this is a software emulation interrupt. It occurs
283 * for all unimplemented and illegal instructions.
284 */
285 EXCEPTION(0x1000, SoftEmu, SoftwareEmulation, EXC_XFER_STD)
287 . = 0x1100
288 /*
289 * For the MPC8xx, this is a software tablewalk to load the instruction
290 * TLB. It is modelled after the example in the Motorola manual. The task
291 * switch loads the M_TWB register with the pointer to the first level table.
292 * If we discover there is no second level table (value is zero) or if there
293 * is an invalid pte, we load that into the TLB, which causes another fault
294 * into the TLB Error interrupt where we can handle such problems.
295 * We have to use the MD_xxx registers for the tablewalk because the
296 * equivalent MI_xxx registers only perform the attribute functions.
297 */
298 InstructionTLBMiss:
299 #ifdef CONFIG_8xx_CPU6
300 stw r3, 8(r0)
301 #endif
302 DO_8xx_CPU6(0x3f80, r3)
303 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
304 mfcr r10
305 stw r10, 0(r0)
306 stw r11, 4(r0)
307 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
308 #ifdef CONFIG_8xx_CPU15
309 addi r11, r10, 0x1000
310 tlbie r11
311 addi r11, r10, -0x1000
312 tlbie r11
313 #endif
314 DO_8xx_CPU6(0x3780, r3)
315 mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */
316 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
318 /* If we are faulting a kernel address, we have to use the
319 * kernel page tables.
320 */
321 andi. r11, r10, 0x0800 /* Address >= 0x80000000 */
322 beq 3f
323 lis r11, swapper_pg_dir@h
324 ori r11, r11, swapper_pg_dir@l
325 rlwimi r10, r11, 0, 2, 19
326 3:
327 lwz r11, 0(r10) /* Get the level 1 entry */
328 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
329 beq 2f /* If zero, don't try to find a pte */
331 /* We have a pte table, so load the MI_TWC with the attributes
332 * for this "segment."
333 */
334 ori r11,r11,1 /* Set valid bit */
335 DO_8xx_CPU6(0x2b80, r3)
336 mtspr SPRN_MI_TWC, r11 /* Set segment attributes */
337 DO_8xx_CPU6(0x3b80, r3)
338 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
339 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
340 lwz r10, 0(r11) /* Get the pte */
342 andi. r11, r10, _PAGE_ACCESSED | _PAGE_PRESENT
343 cmpwi cr0, r11, _PAGE_ACCESSED | _PAGE_PRESENT
344 bne- cr0, 2f
346 /* Clear PP lsb, 0x400 */
347 rlwinm r10, r10, 0, 22, 20
349 /* The Linux PTE won't go exactly into the MMU TLB.
350 * Software indicator bits 22 and 28 must be clear.
351 * Software indicator bits 24, 25, 26, and 27 must be
352 * set. All other Linux PTE bits control the behavior
353 * of the MMU.
354 */
355 li r11, 0x00f0
356 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
357 DO_8xx_CPU6(0x2d80, r3)
358 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
360 mfspr r10, SPRN_M_TW /* Restore registers */
361 lwz r11, 0(r0)
362 mtcr r11
363 lwz r11, 4(r0)
364 #ifdef CONFIG_8xx_CPU6
365 lwz r3, 8(r0)
366 #endif
367 rfi
368 2:
369 mfspr r11, SPRN_SRR1
370 /* clear all error bits as TLB Miss
371 * sets a few unconditionally
372 */
373 rlwinm r11, r11, 0, 0xffff
374 mtspr SPRN_SRR1, r11
376 mfspr r10, SPRN_M_TW /* Restore registers */
377 lwz r11, 0(r0)
378 mtcr r11
379 lwz r11, 4(r0)
380 #ifdef CONFIG_8xx_CPU6
381 lwz r3, 8(r0)
382 #endif
383 b InstructionAccess
385 . = 0x1200
386 DataStoreTLBMiss:
387 #ifdef CONFIG_8xx_CPU6
388 stw r3, 8(r0)
389 #endif
390 DO_8xx_CPU6(0x3f80, r3)
391 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
392 mfcr r10
393 stw r10, 0(r0)
394 stw r11, 4(r0)
395 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
397 /* If we are faulting a kernel address, we have to use the
398 * kernel page tables.
399 */
400 andi. r11, r10, 0x0800
401 beq 3f
402 lis r11, swapper_pg_dir@h
403 ori r11, r11, swapper_pg_dir@l
404 rlwimi r10, r11, 0, 2, 19
405 3:
406 lwz r11, 0(r10) /* Get the level 1 entry */
407 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
408 beq 2f /* If zero, don't try to find a pte */
410 /* We have a pte table, so load fetch the pte from the table.
411 */
412 ori r11, r11, 1 /* Set valid bit in physical L2 page */
413 DO_8xx_CPU6(0x3b80, r3)
414 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
415 mfspr r10, SPRN_MD_TWC /* ....and get the pte address */
416 lwz r10, 0(r10) /* Get the pte */
418 /* Insert the Guarded flag into the TWC from the Linux PTE.
419 * It is bit 27 of both the Linux PTE and the TWC (at least
420 * I got that right :-). It will be better when we can put
421 * this into the Linux pgd/pmd and load it in the operation
422 * above.
423 */
424 rlwimi r11, r10, 0, 27, 27
425 DO_8xx_CPU6(0x3b80, r3)
426 mtspr SPRN_MD_TWC, r11
428 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
429 * We also need to know if the insn is a load/store, so:
430 * Clear _PAGE_PRESENT and load that which will
431 * trap into DTLB Error with store bit set accordinly.
432 */
433 /* PRESENT=0x1, ACCESSED=0x20
434 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
435 * r10 = (r10 & ~PRESENT) | r11;
436 */
437 rlwinm r11, r10, 32-5, 31, 31
438 and r11, r11, r10
439 rlwimi r10, r11, 0, 31, 31
441 /* Honour kernel RO, User NA */
442 andi. r11, r10, _PAGE_USER | _PAGE_RW
443 bne- cr0, 5f
444 ori r10,r10, 0x200 /* Extended encoding, bit 22 */
445 5: xori r10, r10, _PAGE_RW /* invert RW bit */
447 /* The Linux PTE won't go exactly into the MMU TLB.
448 * Software indicator bits 22 and 28 must be clear.
449 * Software indicator bits 24, 25, 26, and 27 must be
450 * set. All other Linux PTE bits control the behavior
451 * of the MMU.
452 */
453 2: li r11, 0x00f0
454 mtspr SPRN_DAR,r11 /* Tag DAR */
455 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
456 DO_8xx_CPU6(0x3d80, r3)
457 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
459 mfspr r10, SPRN_M_TW /* Restore registers */
460 lwz r11, 0(r0)
461 mtcr r11
462 lwz r11, 4(r0)
463 #ifdef CONFIG_8xx_CPU6
464 lwz r3, 8(r0)
465 #endif
466 rfi
468 /* This is an instruction TLB error on the MPC8xx. This could be due
469 * to many reasons, such as executing guarded memory or illegal instruction
470 * addresses. There is nothing to do but handle a big time error fault.
471 */
472 . = 0x1300
473 InstructionTLBError:
474 b InstructionAccess
476 /* This is the data TLB error on the MPC8xx. This could be due to
477 * many reasons, including a dirty update to a pte. We can catch that
478 * one here, but anything else is an error. First, we track down the
479 * Linux pte. If it is valid, write access is allowed, but the
480 * page dirty bit is not set, we will set it and reload the TLB. For
481 * any other case, we bail out to a higher level function that can
482 * handle it.
483 */
484 . = 0x1400
485 DataTLBError:
486 #ifdef CONFIG_8xx_CPU6
487 stw r3, 8(r0)
488 #endif
489 DO_8xx_CPU6(0x3f80, r3)
490 mtspr SPRN_M_TW, r10 /* Save a couple of working registers */
491 mfcr r10
492 stw r10, 0(r0)
493 stw r11, 4(r0)
495 mfspr r10, SPRN_DAR
496 cmpwi cr0, r10, 0x00f0
497 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
498 DARFixed:/* Return from dcbx instruction bug workaround, r10 holds value of DAR */
499 mfspr r11, SPRN_DSISR
500 /* As the DAR fixup may clear store we may have all 3 states zero.
501 * Make sure only 0x0200(store) falls down into DIRTY handling
502 */
503 andis. r11, r11, 0x4a00 /* !translation, protection or store */
504 srwi r11, r11, 16
505 cmpwi cr0, r11, 0x0200 /* just store ? */
506 bne 2f
507 /* Only Change bit left now, do it here as it is faster
508 * than trapping to the C fault handler.
509 */
511 /* The EA of a data TLB miss is automatically stored in the MD_EPN
512 * register. The EA of a data TLB error is automatically stored in
513 * the DAR, but not the MD_EPN register. We must copy the 20 most
514 * significant bits of the EA from the DAR to MD_EPN before we
515 * start walking the page tables. We also need to copy the CASID
516 * value from the M_CASID register.
517 * Addendum: The EA of a data TLB error is _supposed_ to be stored
518 * in DAR, but it seems that this doesn't happen in some cases, such
519 * as when the error is due to a dcbi instruction to a page with a
520 * TLB that doesn't have the changed bit set. In such cases, there
521 * does not appear to be any way to recover the EA of the error
522 * since it is neither in DAR nor MD_EPN. As a workaround, the
523 * _PAGE_HWWRITE bit is set for all kernel data pages when the PTEs
524 * are initialized in mapin_ram(). This will avoid the problem,
525 * assuming we only use the dcbi instruction on kernel addresses.
526 */
528 /* DAR is in r10 already */
529 rlwinm r11, r10, 0, 0, 19
530 ori r11, r11, MD_EVALID
531 mfspr r10, SPRN_M_CASID
532 rlwimi r11, r10, 0, 28, 31
533 DO_8xx_CPU6(0x3780, r3)
534 mtspr SPRN_MD_EPN, r11
536 mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */
538 /* If we are faulting a kernel address, we have to use the
539 * kernel page tables.
540 */
541 andi. r11, r10, 0x0800
542 beq 3f
543 lis r11, swapper_pg_dir@h
544 ori r11, r11, swapper_pg_dir@l
545 rlwimi r10, r11, 0, 2, 19
546 3:
547 lwz r11, 0(r10) /* Get the level 1 entry */
548 rlwinm. r10, r11,0,0,19 /* Extract page descriptor page address */
549 beq 2f /* If zero, bail */
551 /* We have a pte table, so fetch the pte from the table.
552 */
553 ori r11, r11, 1 /* Set valid bit in physical L2 page */
554 DO_8xx_CPU6(0x3b80, r3)
555 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
556 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
557 lwz r10, 0(r11) /* Get the pte */
559 ori r10, r10, _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HWWRITE
560 stw r10, 0(r11) /* and update pte in table */
561 xori r10, r10, _PAGE_RW /* RW bit is inverted */
563 /* The Linux PTE won't go exactly into the MMU TLB.
564 * Software indicator bits 22 and 28 must be clear.
565 * Software indicator bits 24, 25, 26, and 27 must be
566 * set. All other Linux PTE bits control the behavior
567 * of the MMU.
568 */
569 li r11, 0x00f0
570 mtspr SPRN_DAR,r11 /* Tag DAR */
571 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
572 DO_8xx_CPU6(0x3d80, r3)
573 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
575 mfspr r10, SPRN_M_TW /* Restore registers */
576 lwz r11, 0(r0)
577 mtcr r11
578 lwz r11, 4(r0)
579 #ifdef CONFIG_8xx_CPU6
580 lwz r3, 8(r0)
581 #endif
582 rfi
583 2:
584 mfspr r10, SPRN_M_TW /* Restore registers */
585 lwz r11, 0(r0)
586 mtcr r11
587 lwz r11, 4(r0)
588 #ifdef CONFIG_8xx_CPU6
589 lwz r3, 8(r0)
590 #endif
591 b DataAccess
593 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
594 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
595 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
596 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
597 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
598 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
599 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
601 /* On the MPC8xx, these next four traps are used for development
602 * support of breakpoints and such. Someday I will get around to
603 * using them.
604 */
605 EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
606 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
607 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
608 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
610 . = 0x2000
612 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
613 * by decoding the registers used by the dcbx instruction and adding them.
614 * DAR is set to the calculated address and r10 also holds the EA on exit.
615 */
616 /* define if you don't want to use self modifying code */
617 #define NO_SELF_MODIFYING_CODE
618 FixupDAR:/* Entry point for dcbx workaround. */
619 /* fetch instruction from memory. */
620 mfspr r10, SPRN_SRR0
621 DO_8xx_CPU6(0x3780, r3)
622 mtspr SPRN_MD_EPN, r10
623 mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
624 cmplwi cr0, r11, 0x0800
625 blt- 3f /* Branch if user space */
626 lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
627 ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
628 rlwimi r11, r10, 32-20, 0xffc /* r11 = r11&~0xffc|(r10>>20)&0xffc */
629 3: lwz r11, 0(r11) /* Get the level 1 entry */
630 DO_8xx_CPU6(0x3b80, r3)
631 mtspr SPRN_MD_TWC, r11 /* Load pte table base address */
632 mfspr r11, SPRN_MD_TWC /* ....and get the pte address */
633 lwz r11, 0(r11) /* Get the pte */
634 /* concat physical page address(r11) and page offset(r10) */
635 rlwimi r11, r10, 0, 20, 31
636 lwz r11,0(r11)
637 /* Check if it really is a dcbx instruction. */
638 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
639 * no need to include them here */
640 srwi r10, r11, 26 /* check if major OP code is 31 */
641 cmpwi cr0, r10, 31
642 bne- 141f
643 rlwinm r10, r11, 0, 21, 30
644 cmpwi cr0, r10, 2028 /* Is dcbz? */
645 beq+ 142f
646 cmpwi cr0, r10, 940 /* Is dcbi? */
647 beq+ 142f
648 cmpwi cr0, r10, 108 /* Is dcbst? */
649 beq+ 144f /* Fix up store bit! */
650 cmpwi cr0, r10, 172 /* Is dcbf? */
651 beq+ 142f
652 cmpwi cr0, r10, 1964 /* Is icbi? */
653 beq+ 142f
654 141: mfspr r10, SPRN_DAR /* r10 must hold DAR at exit */
655 b DARFixed /* Nope, go back to normal TLB processing */
657 144: mfspr r10, SPRN_DSISR
658 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
659 mtspr SPRN_DSISR, r10
660 142: /* continue, it was a dcbx, dcbi instruction. */
661 #ifdef CONFIG_8xx_CPU6
662 lwz r3, 8(r0) /* restore r3 from memory */
663 #endif
664 #ifndef NO_SELF_MODIFYING_CODE
665 andis. r10,r11,0x1f /* test if reg RA is r0 */
666 li r10,modified_instr@l
667 dcbtst r0,r10 /* touch for store */
668 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
669 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
670 ori r11,r11,532
671 stw r11,0(r10) /* store add/and instruction */
672 dcbf 0,r10 /* flush new instr. to memory. */
673 icbi 0,r10 /* invalidate instr. cache line */
674 lwz r11, 4(r0) /* restore r11 from memory */
675 mfspr r10, SPRN_M_TW /* restore r10 from M_TW */
676 isync /* Wait until new instr is loaded from memory */
677 modified_instr:
678 .space 4 /* this is where the add instr. is stored */
679 bne+ 143f
680 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
681 143: mtdar r10 /* store faulting EA in DAR */
682 b DARFixed /* Go back to normal TLB handling */
683 #else
684 mfctr r10
685 mtdar r10 /* save ctr reg in DAR */
686 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
687 addi r10, r10, 150f@l /* add start of table */
688 mtctr r10 /* load ctr with jump address */
689 xor r10, r10, r10 /* sum starts at zero */
690 bctr /* jump into table */
691 150:
692 add r10, r10, r0 ;b 151f
693 add r10, r10, r1 ;b 151f
694 add r10, r10, r2 ;b 151f
695 add r10, r10, r3 ;b 151f
696 add r10, r10, r4 ;b 151f
697 add r10, r10, r5 ;b 151f
698 add r10, r10, r6 ;b 151f
699 add r10, r10, r7 ;b 151f
700 add r10, r10, r8 ;b 151f
701 add r10, r10, r9 ;b 151f
702 mtctr r11 ;b 154f /* r10 needs special handling */
703 mtctr r11 ;b 153f /* r11 needs special handling */
704 add r10, r10, r12 ;b 151f
705 add r10, r10, r13 ;b 151f
706 add r10, r10, r14 ;b 151f
707 add r10, r10, r15 ;b 151f
708 add r10, r10, r16 ;b 151f
709 add r10, r10, r17 ;b 151f
710 add r10, r10, r18 ;b 151f
711 add r10, r10, r19 ;b 151f
712 add r10, r10, r20 ;b 151f
713 add r10, r10, r21 ;b 151f
714 add r10, r10, r22 ;b 151f
715 add r10, r10, r23 ;b 151f
716 add r10, r10, r24 ;b 151f
717 add r10, r10, r25 ;b 151f
718 add r10, r10, r26 ;b 151f
719 add r10, r10, r27 ;b 151f
720 add r10, r10, r28 ;b 151f
721 add r10, r10, r29 ;b 151f
722 add r10, r10, r30 ;b 151f
723 add r10, r10, r31
724 151:
725 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
726 beq 152f /* if reg RA is zero, don't add it */
727 addi r11, r11, 150b@l /* add start of table */
728 mtctr r11 /* load ctr with jump address */
729 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
730 bctr /* jump into table */
731 152:
732 mfdar r11
733 mtctr r11 /* restore ctr reg from DAR */
734 mtdar r10 /* save fault EA to DAR */
735 b DARFixed /* Go back to normal TLB handling */
737 /* special handling for r10,r11 since these are modified already */
738 153: lwz r11, 4(r0) /* load r11 from memory */
739 b 155f
740 154: mfspr r11, SPRN_M_TW /* load r10 from M_TW */
741 155: add r10, r10, r11 /* add it */
742 mfctr r11 /* restore r11 */
743 b 151b
744 #endif
746 .globl giveup_fpu
747 giveup_fpu:
748 blr
750 /*
751 * This is where the main kernel code starts.
752 */
753 start_here:
754 /* ptr to current */
755 lis r2,init_task@h
756 ori r2,r2,init_task@l
758 /* ptr to phys current thread */
759 tophys(r4,r2)
760 addi r4,r4,THREAD /* init task's THREAD */
761 mtspr SPRN_SPRG_THREAD,r4
762 li r3,0
763 /* XXX What is that for ? SPRG2 appears otherwise unused on 8xx */
764 mtspr SPRN_SPRG2,r3 /* 0 => r1 has kernel sp */
766 /* stack */
767 lis r1,init_thread_union@ha
768 addi r1,r1,init_thread_union@l
769 li r0,0
770 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
772 bl early_init /* We have to do this with MMU on */
774 /*
775 * Decide what sort of machine this is and initialize the MMU.
776 */
777 mr r3,r31
778 mr r4,r30
779 mr r5,r29
780 mr r6,r28
781 mr r7,r27
782 bl machine_init
783 bl MMU_init
785 /*
786 * Go back to running unmapped so we can load up new values
787 * and change to using our exception vectors.
788 * On the 8xx, all we have to do is invalidate the TLB to clear
789 * the old 8M byte TLB mappings and load the page table base register.
790 */
791 /* The right way to do this would be to track it down through
792 * init's THREAD like the context switch code does, but this is
793 * easier......until someone changes init's static structures.
794 */
795 lis r6, swapper_pg_dir@h
796 ori r6, r6, swapper_pg_dir@l
797 tophys(r6,r6)
798 #ifdef CONFIG_8xx_CPU6
799 lis r4, cpu6_errata_word@h
800 ori r4, r4, cpu6_errata_word@l
801 li r3, 0x3980
802 stw r3, 12(r4)
803 lwz r3, 12(r4)
804 #endif
805 mtspr SPRN_M_TWB, r6
806 lis r4,2f@h
807 ori r4,r4,2f@l
808 tophys(r4,r4)
809 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
810 mtspr SPRN_SRR0,r4
811 mtspr SPRN_SRR1,r3
812 rfi
813 /* Load up the kernel context */
814 2:
815 SYNC /* Force all PTE updates to finish */
816 tlbia /* Clear all TLB entries */
817 sync /* wait for tlbia/tlbie to finish */
818 TLBSYNC /* ... on all CPUs */
820 /* set up the PTE pointers for the Abatron bdiGDB.
821 */
822 tovirt(r6,r6)
823 lis r5, abatron_pteptrs@h
824 ori r5, r5, abatron_pteptrs@l
825 stw r5, 0xf0(r0) /* Must match your Abatron config file */
826 tophys(r5,r5)
827 stw r6, 0(r5)
829 /* Now turn on the MMU for real! */
830 li r4,MSR_KERNEL
831 lis r3,start_kernel@h
832 ori r3,r3,start_kernel@l
833 mtspr SPRN_SRR0,r3
834 mtspr SPRN_SRR1,r4
835 rfi /* enable MMU and jump to start_kernel */
837 /* Set up the initial MMU state so we can do the first level of
838 * kernel initialization. This maps the first 8 MBytes of memory 1:1
839 * virtual to physical. Also, set the cache mode since that is defined
840 * by TLB entries and perform any additional mapping (like of the IMMR).
841 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
842 * 24 Mbytes of data, and the 8M IMMR space. Anything not covered by
843 * these mappings is mapped by page tables.
844 */
845 initial_mmu:
846 tlbia /* Invalidate all TLB entries */
847 #ifdef CONFIG_PIN_TLB
848 lis r8, MI_RSV4I@h
849 ori r8, r8, 0x1c00
850 #else
851 li r8, 0
852 #endif
853 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
855 #ifdef CONFIG_PIN_TLB
856 lis r10, (MD_RSV4I | MD_RESETVAL)@h
857 ori r10, r10, 0x1c00
858 mr r8, r10
859 #else
860 lis r10, MD_RESETVAL@h
861 #endif
862 #ifndef CONFIG_8xx_COPYBACK
863 oris r10, r10, MD_WTDEF@h
864 #endif
865 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
867 /* Now map the lower 8 Meg into the TLBs. For this quick hack,
868 * we can load the instruction and data TLB registers with the
869 * same values.
870 */
871 lis r8, KERNELBASE@h /* Create vaddr for TLB */
872 ori r8, r8, MI_EVALID /* Mark it valid */
873 mtspr SPRN_MI_EPN, r8
874 mtspr SPRN_MD_EPN, r8
875 li r8, MI_PS8MEG /* Set 8M byte page */
876 ori r8, r8, MI_SVALID /* Make it valid */
877 mtspr SPRN_MI_TWC, r8
878 mtspr SPRN_MD_TWC, r8
879 li r8, MI_BOOTINIT /* Create RPN for address 0 */
880 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
881 mtspr SPRN_MD_RPN, r8
882 lis r8, MI_Kp@h /* Set the protection mode */
883 mtspr SPRN_MI_AP, r8
884 mtspr SPRN_MD_AP, r8
886 /* Map another 8 MByte at the IMMR to get the processor
887 * internal registers (among other things).
888 */
889 #ifdef CONFIG_PIN_TLB
890 addi r10, r10, 0x0100
891 mtspr SPRN_MD_CTR, r10
892 #endif
893 mfspr r9, 638 /* Get current IMMR */
894 andis. r9, r9, 0xff80 /* Get 8Mbyte boundary */
896 mr r8, r9 /* Create vaddr for TLB */
897 ori r8, r8, MD_EVALID /* Mark it valid */
898 mtspr SPRN_MD_EPN, r8
899 li r8, MD_PS8MEG /* Set 8M byte page */
900 ori r8, r8, MD_SVALID /* Make it valid */
901 mtspr SPRN_MD_TWC, r8
902 mr r8, r9 /* Create paddr for TLB */
903 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
904 mtspr SPRN_MD_RPN, r8
906 #ifdef CONFIG_PIN_TLB
907 /* Map two more 8M kernel data pages.
908 */
909 addi r10, r10, 0x0100
910 mtspr SPRN_MD_CTR, r10
912 lis r8, KERNELBASE@h /* Create vaddr for TLB */
913 addis r8, r8, 0x0080 /* Add 8M */
914 ori r8, r8, MI_EVALID /* Mark it valid */
915 mtspr SPRN_MD_EPN, r8
916 li r9, MI_PS8MEG /* Set 8M byte page */
917 ori r9, r9, MI_SVALID /* Make it valid */
918 mtspr SPRN_MD_TWC, r9
919 li r11, MI_BOOTINIT /* Create RPN for address 0 */
920 addis r11, r11, 0x0080 /* Add 8M */
921 mtspr SPRN_MD_RPN, r11
923 addis r8, r8, 0x0080 /* Add 8M */
924 mtspr SPRN_MD_EPN, r8
925 mtspr SPRN_MD_TWC, r9
926 addis r11, r11, 0x0080 /* Add 8M */
927 mtspr SPRN_MD_RPN, r11
928 #endif
930 /* Since the cache is enabled according to the information we
931 * just loaded into the TLB, invalidate and enable the caches here.
932 * We should probably check/set other modes....later.
933 */
934 lis r8, IDC_INVALL@h
935 mtspr SPRN_IC_CST, r8
936 mtspr SPRN_DC_CST, r8
937 lis r8, IDC_ENABLE@h
938 mtspr SPRN_IC_CST, r8
939 #ifdef CONFIG_8xx_COPYBACK
940 mtspr SPRN_DC_CST, r8
941 #else
942 /* For a debug option, I left this here to easily enable
943 * the write through cache mode
944 */
945 lis r8, DC_SFWT@h
946 mtspr SPRN_DC_CST, r8
947 lis r8, IDC_ENABLE@h
948 mtspr SPRN_DC_CST, r8
949 #endif
950 blr
953 /*
954 * Set up to use a given MMU context.
955 * r3 is context number, r4 is PGD pointer.
956 *
957 * We place the physical address of the new task page directory loaded
958 * into the MMU base register, and set the ASID compare register with
959 * the new "context."
960 */
961 _GLOBAL(set_context)
963 #ifdef CONFIG_BDI_SWITCH
964 /* Context switch the PTE pointer for the Abatron BDI2000.
965 * The PGDIR is passed as second argument.
966 */
967 lis r5, KERNELBASE@h
968 lwz r5, 0xf0(r5)
969 stw r4, 0x4(r5)
970 #endif
972 #ifdef CONFIG_8xx_CPU6
973 lis r6, cpu6_errata_word@h
974 ori r6, r6, cpu6_errata_word@l
975 tophys (r4, r4)
976 li r7, 0x3980
977 stw r7, 12(r6)
978 lwz r7, 12(r6)
979 mtspr SPRN_M_TWB, r4 /* Update MMU base address */
980 li r7, 0x3380
981 stw r7, 12(r6)
982 lwz r7, 12(r6)
983 mtspr SPRN_M_CASID, r3 /* Update context */
984 #else
985 mtspr SPRN_M_CASID,r3 /* Update context */
986 tophys (r4, r4)
987 mtspr SPRN_M_TWB, r4 /* and pgd */
988 #endif
989 SYNC
990 blr
992 #ifdef CONFIG_8xx_CPU6
993 /* It's here because it is unique to the 8xx.
994 * It is important we get called with interrupts disabled. I used to
995 * do that, but it appears that all code that calls this already had
996 * interrupt disabled.
997 */
998 .globl set_dec_cpu6
999 set_dec_cpu6:
1000 lis r7, cpu6_errata_word@h
1001 ori r7, r7, cpu6_errata_word@l
1002 li r4, 0x2c00
1003 stw r4, 8(r7)
1004 lwz r4, 8(r7)
1005 mtspr 22, r3 /* Update Decrementer */
1006 SYNC
1007 blr
1008 #endif
1010 /*
1011 * We put a few things here that have to be page-aligned.
1012 * This stuff goes at the beginning of the data segment,
1013 * which is page-aligned.
1014 */
1015 .data
1016 .globl sdata
1017 sdata:
1018 .globl empty_zero_page
1019 empty_zero_page:
1020 .space 4096
1022 .globl swapper_pg_dir
1023 swapper_pg_dir:
1024 .space 4096
1026 /* Room for two PTE table poiners, usually the kernel and current user
1027 * pointer to their respective root page table (pgdir).
1028 */
1029 abatron_pteptrs:
1030 .space 8
1032 #ifdef CONFIG_8xx_CPU6
1033 .globl cpu6_errata_word
1034 cpu6_errata_word:
1035 .space 16
1036 #endif