1 #include <linux/kernel.h>
2 #include <linux/module.h>
3 #include <linux/stddef.h>
4 #include <linux/init.h>
5 #include <linux/sched.h>
6 #include <linux/signal.h>
8 #include <linux/dma-mapping.h>
12 #include <asm/8xx_immap.h>
14 #include "mpc8xx_pic.h"
17 #define PIC_VEC_SPURRIOUS 15
19 extern int cpm_get_irq(struct pt_regs
*regs
);
21 static struct irq_host
*mpc8xx_pic_host
;
22 #define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
23 static unsigned long ppc_cached_irq_mask
[NR_MASK_WORDS
];
24 static sysconf8xx_t __iomem
*siu_reg
;
26 int cpm_get_irq(struct pt_regs
*regs
);
28 static void mpc8xx_unmask_irq(unsigned int virq
)
31 unsigned int irq_nr
= (unsigned int)irq_map
[virq
].hwirq
;
36 ppc_cached_irq_mask
[word
] |= (1 << (31-bit
));
37 out_be32(&siu_reg
->sc_simask
, ppc_cached_irq_mask
[word
]);
40 static void mpc8xx_mask_irq(unsigned int virq
)
43 unsigned int irq_nr
= (unsigned int)irq_map
[virq
].hwirq
;
48 ppc_cached_irq_mask
[word
] &= ~(1 << (31-bit
));
49 out_be32(&siu_reg
->sc_simask
, ppc_cached_irq_mask
[word
]);
52 static void mpc8xx_ack(unsigned int virq
)
55 unsigned int irq_nr
= (unsigned int)irq_map
[virq
].hwirq
;
58 out_be32(&siu_reg
->sc_sipend
, 1 << (31-bit
));
61 static void mpc8xx_end_irq(unsigned int virq
)
64 unsigned int irq_nr
= (unsigned int)irq_map
[virq
].hwirq
;
69 ppc_cached_irq_mask
[word
] |= (1 << (31-bit
));
70 out_be32(&siu_reg
->sc_simask
, ppc_cached_irq_mask
[word
]);
73 static int mpc8xx_set_irq_type(unsigned int virq
, unsigned int flow_type
)
75 struct irq_desc
*desc
= get_irq_desc(virq
);
77 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
78 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
79 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
80 desc
->status
|= IRQ_LEVEL
;
82 if (flow_type
& IRQ_TYPE_EDGE_FALLING
) {
83 irq_hw_number_t hw
= (unsigned int)irq_map
[virq
].hwirq
;
84 unsigned int siel
= in_be32(&siu_reg
->sc_siel
);
86 /* only external IRQ senses are programmable */
88 siel
|= (0x80000000 >> hw
);
89 out_be32(&siu_reg
->sc_siel
, siel
);
90 desc
->handle_irq
= handle_edge_irq
;
96 static struct irq_chip mpc8xx_pic
= {
97 .typename
= " MPC8XX SIU ",
98 .unmask
= mpc8xx_unmask_irq
,
99 .mask
= mpc8xx_mask_irq
,
101 .eoi
= mpc8xx_end_irq
,
102 .set_type
= mpc8xx_set_irq_type
,
105 unsigned int mpc8xx_get_irq(void)
109 /* For MPC8xx, read the SIVEC register and shift the bits down
110 * to get the irq number.
112 irq
= in_be32(&siu_reg
->sc_sivec
) >> 26;
114 if (irq
== PIC_VEC_SPURRIOUS
)
117 return irq_linear_revmap(mpc8xx_pic_host
, irq
);
121 static int mpc8xx_pic_host_map(struct irq_host
*h
, unsigned int virq
,
124 pr_debug("mpc8xx_pic_host_map(%d, 0x%lx)\n", virq
, hw
);
126 /* Set default irq handle */
127 set_irq_chip_and_handler(virq
, &mpc8xx_pic
, handle_level_irq
);
132 static int mpc8xx_pic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
133 u32
*intspec
, unsigned int intsize
,
134 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
136 static unsigned char map_pic_senses
[4] = {
137 IRQ_TYPE_EDGE_RISING
,
140 IRQ_TYPE_EDGE_FALLING
,
143 *out_hwirq
= intspec
[0];
144 if (intsize
> 1 && intspec
[1] < 4)
145 *out_flags
= map_pic_senses
[intspec
[1]];
147 *out_flags
= IRQ_TYPE_NONE
;
153 static struct irq_host_ops mpc8xx_pic_host_ops
= {
154 .map
= mpc8xx_pic_host_map
,
155 .xlate
= mpc8xx_pic_host_xlate
,
158 int mpc8xx_pic_init(void)
161 struct device_node
*np
;
164 np
= of_find_compatible_node(NULL
, NULL
, "fsl,pq1-pic");
166 np
= of_find_node_by_type(NULL
, "mpc8xx-pic");
168 printk(KERN_ERR
"Could not find fsl,pq1-pic node\n");
172 ret
= of_address_to_resource(np
, 0, &res
);
176 siu_reg
= ioremap(res
.start
, res
.end
- res
.start
+ 1);
177 if (siu_reg
== NULL
) {
182 mpc8xx_pic_host
= irq_alloc_host(np
, IRQ_HOST_MAP_LINEAR
,
183 64, &mpc8xx_pic_host_ops
, 64);
184 if (mpc8xx_pic_host
== NULL
) {
185 printk(KERN_ERR
"MPC8xx PIC: failed to allocate irq host!\n");