arch/powerpc/platforms/82xx/mpc82xx_ads.c

   1 /*
   2  * MPC82xx_ads setup and early boot code plus other random bits.
   3  *
   4  * Author: Vitaly Bordug <vbordug@ru.mvista.com>
   5  * m82xx_restart fix by Wade Farnsworth <wfarnsworth@mvista.com>
   6  *
   7  * Copyright (c) 2006 MontaVista Software, Inc.
   8  *
   9  * This program is free software; you can redistribute  it and/or modify it
  10  * under  the terms of  the GNU General  Public License as published by the
  11  * Free Software Foundation;  either version 2 of the  License, or (at your
  12  * option) any later version.
  13  */
  14
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/reboot.h>
  20 #include <linux/pci.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/major.h>
  24 #include <linux/console.h>
  25 #include <linux/delay.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/root_dev.h>
  28 #include <linux/initrd.h>
  29 #include <linux/module.h>
  30 #include <linux/fsl_devices.h>
  31 #include <linux/fs_uart_pd.h>
  32
  33 #include <asm/system.h>
  34 #include <asm/pgtable.h>
  35 #include <asm/page.h>
  36 #include <asm/atomic.h>
  37 #include <asm/time.h>
  38 #include <asm/io.h>
  39 #include <asm/machdep.h>
  40 #include <asm/bootinfo.h>
  41 #include <asm/pci-bridge.h>
  42 #include <asm/mpc8260.h>
  43 #include <asm/irq.h>
  44 #include <mm/mmu_decl.h>
  45 #include <asm/prom.h>
  46 #include <asm/cpm2.h>
  47 #include <asm/udbg.h>
  48 #include <asm/i8259.h>
  49 #include <linux/fs_enet_pd.h>
  50
  51 #include <sysdev/fsl_soc.h>
  52 #include <../sysdev/cpm2_pic.h>
  53
  54 #include "pq2ads.h"
  55
  56 #ifdef CONFIG_PCI
  57 static uint pci_clk_frq;
  58 static struct {
  59         unsigned long *pci_int_stat_reg;
  60         unsigned long *pci_int_mask_reg;
  61 } pci_regs;
  62
  63 static unsigned long pci_int_base;
  64 static struct irq_host *pci_pic_host;
  65 static struct device_node *pci_pic_node;
  66 #endif
  67
  68 static void __init mpc82xx_ads_pic_init(void)
  69 {
  70         struct device_node *np = of_find_compatible_node(NULL, "cpm-pic", "CPM2");
  71         struct resource r;
  72         cpm2_map_t *cpm_reg;
  73
  74         if (np == NULL) {
  75                 printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
  76                 return;
  77         }
  78         if (of_address_to_resource(np, 0, &r)) {
  79                 printk(KERN_ERR "PIC init: invalid resource\n");
  80                 of_node_put(np);
  81                 return;
  82         }
  83         cpm2_pic_init(np);
  84         of_node_put(np);
  85
  86         /* Initialize the default interrupt mapping priorities,
  87          * in case the boot rom changed something on us.
  88          */
  89         cpm_reg = (cpm2_map_t *) ioremap(get_immrbase(), sizeof(cpm2_map_t));
  90         cpm_reg->im_intctl.ic_siprr = 0x05309770;
  91         iounmap(cpm_reg);
  92 #ifdef CONFIG_PCI
  93         /* Initialize stuff for the 82xx CPLD IC and install demux  */
  94         m82xx_pci_init_irq();
  95 #endif
  96 }
  97
  98 static void init_fcc1_ioports(struct fs_platform_info *fpi)
  99 {
 100         struct io_port *io;
 101         u32 tempval;
 102         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 103         struct device_node *np;
 104         struct resource r;
 105         u32 *bcsr;
 106
 107         np = of_find_node_by_type(NULL, "memory");
 108         if (!np) {
 109                 printk(KERN_INFO "No memory node in device tree\n");
 110                 return;
 111         }
 112         if (of_address_to_resource(np, 1, &r)) {
 113                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 114                 return;
 115         }
 116         of_node_put(np);
 117         bcsr = ioremap(r.start + 4, sizeof(u32));
 118         io = &immap->im_ioport;
 119
 120         /* Enable the PHY */
 121         clrbits32(bcsr, BCSR1_FETHIEN);
 122         setbits32(bcsr, BCSR1_FETH_RST);
 123
 124         /* FCC1 pins are on port A/C. */
 125         /* Configure port A and C pins for FCC1 Ethernet. */
 126
 127         tempval = in_be32(&io->iop_pdira);
 128         tempval &= ~PA1_DIRA0;
 129         tempval |= PA1_DIRA1;
 130         out_be32(&io->iop_pdira, tempval);
 131
 132         tempval = in_be32(&io->iop_psora);
 133         tempval &= ~PA1_PSORA0;
 134         tempval |= PA1_PSORA1;
 135         out_be32(&io->iop_psora, tempval);
 136
 137         setbits32(&io->iop_ppara, PA1_DIRA0 | PA1_DIRA1);
 138
 139         /* Alter clocks */
 140         tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
 141
 142         clrbits32(&io->iop_psorc, tempval);
 143         clrbits32(&io->iop_pdirc, tempval);
 144         setbits32(&io->iop_pparc, tempval);
 145
 146         cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_rx, CPM_CLK_RX);
 147         cpm2_clk_setup(CPM_CLK_FCC1, fpi->clk_tx, CPM_CLK_TX);
 148
 149         iounmap(bcsr);
 150         iounmap(immap);
 151 }
 152
 153 static void init_fcc2_ioports(struct fs_platform_info *fpi)
 154 {
 155         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 156         struct device_node *np;
 157         struct resource r;
 158         u32 *bcsr;
 159
 160         struct io_port *io;
 161         u32 tempval;
 162
 163         np = of_find_node_by_type(NULL, "memory");
 164         if (!np) {
 165                 printk(KERN_INFO "No memory node in device tree\n");
 166                 return;
 167         }
 168         if (of_address_to_resource(np, 1, &r)) {
 169                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 170                 return;
 171         }
 172         of_node_put(np);
 173         io = &immap->im_ioport;
 174         bcsr = ioremap(r.start + 12, sizeof(u32));
 175
 176         /* Enable the PHY */
 177         clrbits32(bcsr, BCSR3_FETHIEN2);
 178         setbits32(bcsr, BCSR3_FETH2_RST);
 179
 180         /* FCC2 are port B/C. */
 181         /* Configure port A and C pins for FCC2 Ethernet. */
 182
 183         tempval = in_be32(&io->iop_pdirb);
 184         tempval &= ~PB2_DIRB0;
 185         tempval |= PB2_DIRB1;
 186         out_be32(&io->iop_pdirb, tempval);
 187
 188         tempval = in_be32(&io->iop_psorb);
 189         tempval &= ~PB2_PSORB0;
 190         tempval |= PB2_PSORB1;
 191         out_be32(&io->iop_psorb, tempval);
 192
 193         setbits32(&io->iop_pparb, PB2_DIRB0 | PB2_DIRB1);
 194
 195         tempval = PC_CLK(fpi->clk_tx - 8) | PC_CLK(fpi->clk_rx - 8);
 196
 197         /* Alter clocks */
 198         clrbits32(&io->iop_psorc, tempval);
 199         clrbits32(&io->iop_pdirc, tempval);
 200         setbits32(&io->iop_pparc, tempval);
 201
 202         cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_rx, CPM_CLK_RX);
 203         cpm2_clk_setup(CPM_CLK_FCC2, fpi->clk_tx, CPM_CLK_TX);
 204
 205         iounmap(bcsr);
 206         iounmap(immap);
 207 }
 208
 209 void init_fcc_ioports(struct fs_platform_info *fpi)
 210 {
 211         int fcc_no = fs_get_fcc_index(fpi->fs_no);
 212
 213         switch (fcc_no) {
 214         case 0:
 215                 init_fcc1_ioports(fpi);
 216                 break;
 217         case 1:
 218                 init_fcc2_ioports(fpi);
 219                 break;
 220         default:
 221                 printk(KERN_ERR "init_fcc_ioports: invalid FCC number\n");
 222                 return;
 223         }
 224 }
 225
 226 static void init_scc1_uart_ioports(struct fs_uart_platform_info *data)
 227 {
 228         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 229
 230         /* SCC1 is only on port D */
 231         setbits32(&immap->im_ioport.iop_ppard, 0x00000003);
 232         clrbits32(&immap->im_ioport.iop_psord, 0x00000001);
 233         setbits32(&immap->im_ioport.iop_psord, 0x00000002);
 234         clrbits32(&immap->im_ioport.iop_pdird, 0x00000001);
 235         setbits32(&immap->im_ioport.iop_pdird, 0x00000002);
 236
 237         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
 238         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
 239         setbits32(&immap->im_cpmux.cmx_scr,
 240                   ((data->clk_tx - 1) << (4 - data->clk_tx)));
 241         setbits32(&immap->im_cpmux.cmx_scr,
 242                   ((data->clk_rx - 1) << (4 - data->clk_rx)));
 243
 244         iounmap(immap);
 245 }
 246
 247 static void init_scc4_uart_ioports(struct fs_uart_platform_info *data)
 248 {
 249         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 250
 251         setbits32(&immap->im_ioport.iop_ppard, 0x00000600);
 252         clrbits32(&immap->im_ioport.iop_psord, 0x00000600);
 253         clrbits32(&immap->im_ioport.iop_pdird, 0x00000200);
 254         setbits32(&immap->im_ioport.iop_pdird, 0x00000400);
 255
 256         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000007 << (4 - data->clk_tx)));
 257         clrbits32(&immap->im_cpmux.cmx_scr, (0x00000038 << (4 - data->clk_rx)));
 258         setbits32(&immap->im_cpmux.cmx_scr,
 259                   ((data->clk_tx - 1) << (4 - data->clk_tx)));
 260         setbits32(&immap->im_cpmux.cmx_scr,
 261                   ((data->clk_rx - 1) << (4 - data->clk_rx)));
 262
 263         iounmap(immap);
 264 }
 265
 266 void init_scc_ioports(struct fs_uart_platform_info *data)
 267 {
 268         int scc_no = fs_get_scc_index(data->fs_no);
 269
 270         switch (scc_no) {
 271         case 0:
 272                 init_scc1_uart_ioports(data);
 273                 data->brg = data->clk_rx;
 274                 break;
 275         case 3:
 276                 init_scc4_uart_ioports(data);
 277                 data->brg = data->clk_rx;
 278                 break;
 279         default:
 280                 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
 281                 return;
 282         }
 283 }
 284
 285 void __init m82xx_board_setup(void)
 286 {
 287         cpm2_map_t *immap = ioremap(get_immrbase(), sizeof(cpm2_map_t));
 288         struct device_node *np;
 289         struct resource r;
 290         u32 *bcsr;
 291
 292         np = of_find_node_by_type(NULL, "memory");
 293         if (!np) {
 294                 printk(KERN_INFO "No memory node in device tree\n");
 295                 return;
 296         }
 297         if (of_address_to_resource(np, 1, &r)) {
 298                 printk(KERN_INFO "No memory reg property [1] in devicetree\n");
 299                 return;
 300         }
 301         of_node_put(np);
 302         bcsr = ioremap(r.start + 4, sizeof(u32));
 303         /* Enable the 2nd UART port */
 304         clrbits32(bcsr, BCSR1_RS232_EN2);
 305
 306 #ifdef CONFIG_SERIAL_CPM_SCC1
 307         clrbits32((u32 *) & immap->im_scc[0].scc_sccm,
 308                   UART_SCCM_TX | UART_SCCM_RX);
 309         clrbits32((u32 *) & immap->im_scc[0].scc_gsmrl,
 310                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 311 #endif
 312
 313 #ifdef CONFIG_SERIAL_CPM_SCC2
 314         clrbits32((u32 *) & immap->im_scc[1].scc_sccm,
 315                   UART_SCCM_TX | UART_SCCM_RX);
 316         clrbits32((u32 *) & immap->im_scc[1].scc_gsmrl,
 317                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 318 #endif
 319
 320 #ifdef CONFIG_SERIAL_CPM_SCC3
 321         clrbits32((u32 *) & immap->im_scc[2].scc_sccm,
 322                   UART_SCCM_TX | UART_SCCM_RX);
 323         clrbits32((u32 *) & immap->im_scc[2].scc_gsmrl,
 324                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 325 #endif
 326
 327 #ifdef CONFIG_SERIAL_CPM_SCC4
 328         clrbits32((u32 *) & immap->im_scc[3].scc_sccm,
 329                   UART_SCCM_TX | UART_SCCM_RX);
 330         clrbits32((u32 *) & immap->im_scc[3].scc_gsmrl,
 331                   SCC_GSMRL_ENR | SCC_GSMRL_ENT);
 332 #endif
 333
 334         iounmap(bcsr);
 335         iounmap(immap);
 336 }
 337
 338 #ifdef CONFIG_PCI
 339 static void m82xx_pci_mask_irq(unsigned int irq)
 340 {
 341         int bit = irq - pci_int_base;
 342
 343         *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
 344         return;
 345 }
 346
 347 static void m82xx_pci_unmask_irq(unsigned int irq)
 348 {
 349         int bit = irq - pci_int_base;
 350
 351         *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
 352         return;
 353 }
 354
 355 static void m82xx_pci_mask_and_ack(unsigned int irq)
 356 {
 357         int bit = irq - pci_int_base;
 358
 359         *pci_regs.pci_int_mask_reg |= (1 << (31 - bit));
 360         return;
 361 }
 362
 363 static void m82xx_pci_end_irq(unsigned int irq)
 364 {
 365         int bit = irq - pci_int_base;
 366
 367         *pci_regs.pci_int_mask_reg &= ~(1 << (31 - bit));
 368         return;
 369 }
 370
 371 struct hw_interrupt_type m82xx_pci_ic = {
 372         .typename = "MPC82xx ADS PCI",
 373         .name = "MPC82xx ADS PCI",
 374         .enable = m82xx_pci_unmask_irq,
 375         .disable = m82xx_pci_mask_irq,
 376         .ack = m82xx_pci_mask_and_ack,
 377         .end = m82xx_pci_end_irq,
 378         .mask = m82xx_pci_mask_irq,
 379         .mask_ack = m82xx_pci_mask_and_ack,
 380         .unmask = m82xx_pci_unmask_irq,
 381         .eoi = m82xx_pci_end_irq,
 382 };
 383
 384 static void
 385 m82xx_pci_irq_demux(unsigned int irq, struct irq_desc *desc)
 386 {
 387         unsigned long stat, mask, pend;
 388         int bit;
 389
 390         for (;;) {
 391                 stat = *pci_regs.pci_int_stat_reg;
 392                 mask = *pci_regs.pci_int_mask_reg;
 393                 pend = stat & ~mask & 0xf0000000;
 394                 if (!pend)
 395                         break;
 396                 for (bit = 0; pend != 0; ++bit, pend <<= 1) {
 397                         if (pend & 0x80000000)
 398                                 __do_IRQ(pci_int_base + bit);
 399                 }
 400         }
 401 }
 402
 403 static int pci_pic_host_match(struct irq_host *h, struct device_node *node)
 404 {
 405         return node == pci_pic_node;
 406 }
 407
 408 static int pci_pic_host_map(struct irq_host *h, unsigned int virq,
 409                             irq_hw_number_t hw)
 410 {
 411         get_irq_desc(virq)->status |= IRQ_LEVEL;
 412         set_irq_chip(virq, &m82xx_pci_ic);
 413         return 0;
 414 }
 415
 416 static void pci_host_unmap(struct irq_host *h, unsigned int virq)
 417 {
 418         /* remove chip and handler */
 419         set_irq_chip(virq, NULL);
 420 }
 421
 422 static struct irq_host_ops pci_pic_host_ops = {
 423         .match = pci_pic_host_match,
 424         .map = pci_pic_host_map,
 425         .unmap = pci_host_unmap,
 426 };
 427
 428 void m82xx_pci_init_irq(void)
 429 {
 430         int irq;
 431         cpm2_map_t *immap;
 432         struct device_node *np;
 433         struct resource r;
 434         const u32 *regs;
 435         unsigned int size;
 436         const u32 *irq_map;
 437         int i;
 438         unsigned int irq_max, irq_min;
 439
 440         if ((np = of_find_node_by_type(NULL, "soc")) == NULL) {
 441                 printk(KERN_INFO "No SOC node in device tree\n");
 442                 return;
 443         }
 444         memset(&r, 0, sizeof(r));
 445         if (of_address_to_resource(np, 0, &r)) {
 446                 printk(KERN_INFO "No SOC reg property in device tree\n");
 447                 return;
 448         }
 449         immap = ioremap(r.start, sizeof(*immap));
 450         of_node_put(np);
 451
 452         /* install the demultiplexer for the PCI cascade interrupt */
 453         np = of_find_node_by_type(NULL, "pci");
 454         if (!np) {
 455                 printk(KERN_INFO "No pci node on device tree\n");
 456                 iounmap(immap);
 457                 return;
 458         }
 459         irq_map = of_get_property(np, "interrupt-map", &size);
 460         if ((!irq_map) || (size <= 7)) {
 461                 printk(KERN_INFO "No interrupt-map property of pci node\n");
 462                 iounmap(immap);
 463                 return;
 464         }
 465         size /= sizeof(irq_map[0]);
 466         for (i = 0, irq_max = 0, irq_min = 512; i < size; i += 7, irq_map += 7) {
 467                 if (irq_map[5] < irq_min)
 468                         irq_min = irq_map[5];
 469                 if (irq_map[5] > irq_max)
 470                         irq_max = irq_map[5];
 471         }
 472         pci_int_base = irq_min;
 473         irq = irq_of_parse_and_map(np, 0);
 474         set_irq_chained_handler(irq, m82xx_pci_irq_demux);
 475         of_node_put(np);
 476         np = of_find_node_by_type(NULL, "pci-pic");
 477         if (!np) {
 478                 printk(KERN_INFO "No pci pic node on device tree\n");
 479                 iounmap(immap);
 480                 return;
 481         }
 482         pci_pic_node = of_node_get(np);
 483         /* PCI interrupt controller registers: status and mask */
 484         regs = of_get_property(np, "reg", &size);
 485         if ((!regs) || (size <= 2)) {
 486                 printk(KERN_INFO "No reg property in pci pic node\n");
 487                 iounmap(immap);
 488                 return;
 489         }
 490         pci_regs.pci_int_stat_reg =
 491             ioremap(regs[0], sizeof(*pci_regs.pci_int_stat_reg));
 492         pci_regs.pci_int_mask_reg =
 493             ioremap(regs[1], sizeof(*pci_regs.pci_int_mask_reg));
 494         of_node_put(np);
 495         /* configure chip select for PCI interrupt controller */
 496         immap->im_memctl.memc_br3 = regs[0] | 0x00001801;
 497         immap->im_memctl.memc_or3 = 0xffff8010;
 498         /* make PCI IRQ level sensitive */
 499         immap->im_intctl.ic_siexr &= ~(1 << (14 - (irq - SIU_INT_IRQ1)));
 500
 501         /* mask all PCI interrupts */
 502         *pci_regs.pci_int_mask_reg |= 0xfff00000;
 503         iounmap(immap);
 504         pci_pic_host =
 505             irq_alloc_host(IRQ_HOST_MAP_LINEAR, irq_max - irq_min + 1,
 506                            &pci_pic_host_ops, irq_max + 1);
 507         return;
 508 }
 509
 510 static int m82xx_pci_exclude_device(u_char bus, u_char devfn)
 511 {
 512         if (bus == 0 && PCI_SLOT(devfn) == 0)
 513                 return PCIBIOS_DEVICE_NOT_FOUND;
 514         else
 515                 return PCIBIOS_SUCCESSFUL;
 516 }
 517
 518 static void __init mpc82xx_add_bridge(struct device_node *np)
 519 {
 520         int len;
 521         struct pci_controller *hose;
 522         struct resource r;
 523         const int *bus_range;
 524         const uint *ptr;
 525
 526         memset(&r, 0, sizeof(r));
 527         if (of_address_to_resource(np, 0, &r)) {
 528                 printk(KERN_INFO "No PCI reg property in device tree\n");
 529                 return;
 530         }
 531         if (!(ptr = of_get_property(np, "clock-frequency", NULL))) {
 532                 printk(KERN_INFO "No clock-frequency property in PCI node");
 533                 return;
 534         }
 535         pci_clk_frq = *ptr;
 536         of_node_put(np);
 537         bus_range = of_get_property(np, "bus-range", &len);
 538         if (bus_range == NULL || len < 2 * sizeof(int)) {
 539                 printk(KERN_WARNING "Can't get bus-range for %s, assume"
 540                        " bus 0\n", np->full_name);
 541         }
 542
 543         pci_assign_all_buses = 1;
 544
 545         hose = pcibios_alloc_controller();
 546
 547         if (!hose)
 548                 return;
 549
 550         hose->arch_data = np;
 551         hose->set_cfg_type = 1;
 552
 553         hose->first_busno = bus_range ? bus_range[0] : 0;
 554         hose->last_busno = bus_range ? bus_range[1] : 0xff;
 555         hose->bus_offset = 0;
 556
 557         hose->set_cfg_type = 1;
 558
 559         setup_indirect_pci(hose,
 560                            r.start + offsetof(pci_cpm2_t, pci_cfg_addr),
 561                            r.start + offsetof(pci_cpm2_t, pci_cfg_data));
 562
 563         pci_process_bridge_OF_ranges(hose, np, 1);
 564 }
 565 #endif
 566
 567 /*
 568  * Setup the architecture
 569  */
 570 static void __init mpc82xx_ads_setup_arch(void)
 571 {
 572 #ifdef CONFIG_PCI
 573         struct device_node *np;
 574 #endif
 575
 576         if (ppc_md.progress)
 577                 ppc_md.progress("mpc82xx_ads_setup_arch()", 0);
 578         cpm2_reset();
 579
 580         /* Map I/O region to a 256MB BAT */
 581
 582         m82xx_board_setup();
 583
 584 #ifdef CONFIG_PCI
 585         ppc_md.pci_exclude_device = m82xx_pci_exclude_device;
 586         for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
 587                 mpc82xx_add_bridge(np);
 588
 589         of_node_put(np);
 590 #endif
 591
 592 #ifdef  CONFIG_ROOT_NFS
 593         ROOT_DEV = Root_NFS;
 594 #else
 595         ROOT_DEV = Root_HDA1;
 596 #endif
 597
 598         if (ppc_md.progress)
 599                 ppc_md.progress("mpc82xx_ads_setup_arch(), finish", 0);
 600 }
 601
 602 /*
 603  * Called very early, device-tree isn't unflattened
 604  */
 605 static int __init mpc82xx_ads_probe(void)
 606 {
 607         /* We always match for now, eventually we should look at
 608          * the flat dev tree to ensure this is the board we are
 609          * supposed to run on
 610          */
 611         return 1;
 612 }
 613
 614 #define RMR_CSRE 0x00000001
 615 static void m82xx_restart(char *cmd)
 616 {
 617         __volatile__ unsigned char dummy;
 618
 619         local_irq_disable();
 620         ((cpm2_map_t *) cpm2_immr)->im_clkrst.car_rmr |= RMR_CSRE;
 621
 622         /* Clear the ME,EE,IR & DR bits in MSR to cause checkstop */
 623         mtmsr(mfmsr() & ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR));
 624         dummy = ((cpm2_map_t *) cpm2_immr)->im_clkrst.res[0];
 625         printk("Restart failed\n");
 626         while (1) ;
 627 }
 628
 629 static void m82xx_halt(void)
 630 {
 631         local_irq_disable();
 632         while (1) ;
 633 }
 634
 635 define_machine(mpc82xx_ads)
 636 {
 637         .name = "MPC82xx ADS",
 638         .probe = mpc82xx_ads_probe,
 639         .setup_arch =    mpc82xx_ads_setup_arch,
 640         .init_IRQ =    mpc82xx_ads_pic_init,
 641         .show_cpuinfo =    mpc82xx_ads_show_cpuinfo,
 642         .get_irq =    cpm2_get_irq,
 643         .calibrate_decr =    m82xx_calibrate_decr,
 644         .restart = m82xx_restart,.halt = m82xx_halt,
 645 };