2 * drivers/mmc/host/omap_hsmmc.c
4 * Driver for OMAP2430/3430 MMC controller.
6 * Copyright (C) 2007 Texas Instruments.
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/debugfs.h>
21 #include <linux/seq_file.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/platform_device.h>
26 #include <linux/workqueue.h>
27 #include <linux/timer.h>
28 #include <linux/clk.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/core.h>
32 #include <linux/semaphore.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
36 #include <mach/hardware.h>
37 #include <plat/board.h>
41 /* OMAP HSMMC Host Controller Registers */
42 #define OMAP_HSMMC_SYSCONFIG 0x0010
43 #define OMAP_HSMMC_SYSSTATUS 0x0014
44 #define OMAP_HSMMC_CON 0x002C
45 #define OMAP_HSMMC_BLK 0x0104
46 #define OMAP_HSMMC_ARG 0x0108
47 #define OMAP_HSMMC_CMD 0x010C
48 #define OMAP_HSMMC_RSP10 0x0110
49 #define OMAP_HSMMC_RSP32 0x0114
50 #define OMAP_HSMMC_RSP54 0x0118
51 #define OMAP_HSMMC_RSP76 0x011C
52 #define OMAP_HSMMC_DATA 0x0120
53 #define OMAP_HSMMC_HCTL 0x0128
54 #define OMAP_HSMMC_SYSCTL 0x012C
55 #define OMAP_HSMMC_STAT 0x0130
56 #define OMAP_HSMMC_IE 0x0134
57 #define OMAP_HSMMC_ISE 0x0138
58 #define OMAP_HSMMC_CAPA 0x0140
60 #define VS18 (1 << 26)
61 #define VS30 (1 << 25)
62 #define SDVS18 (0x5 << 9)
63 #define SDVS30 (0x6 << 9)
64 #define SDVS33 (0x7 << 9)
65 #define SDVS_MASK 0x00000E00
66 #define SDVSCLR 0xFFFFF1FF
67 #define SDVSDET 0x00000400
74 #define CLKD_MASK 0x0000FFC0
76 #define DTO_MASK 0x000F0000
78 #define INT_EN_MASK 0x307F0033
79 #define BWR_ENABLE (1 << 4)
80 #define BRR_ENABLE (1 << 5)
81 #define INIT_STREAM (1 << 1)
82 #define DP_SELECT (1 << 21)
87 #define FOUR_BIT (1 << 1)
93 #define CMD_TIMEOUT (1 << 16)
94 #define DATA_TIMEOUT (1 << 20)
95 #define CMD_CRC (1 << 17)
96 #define DATA_CRC (1 << 21)
97 #define CARD_ERR (1 << 28)
98 #define STAT_CLEAR 0xFFFFFFFF
99 #define INIT_STREAM_CMD 0x00000000
100 #define DUAL_VOLT_OCR_BIT 7
101 #define SRC (1 << 25)
102 #define SRD (1 << 26)
103 #define SOFTRESET (1 << 1)
104 #define RESETDONE (1 << 0)
107 * FIXME: Most likely all the data using these _DEVID defines should come
108 * from the platform_data, or implemented in controller and slot specific
111 #define OMAP_MMC1_DEVID 0
112 #define OMAP_MMC2_DEVID 1
113 #define OMAP_MMC3_DEVID 2
114 #define OMAP_MMC4_DEVID 3
115 #define OMAP_MMC5_DEVID 4
117 #define MMC_TIMEOUT_MS 20
118 #define OMAP_MMC_MASTER_CLOCK 96000000
119 #define DRIVER_NAME "mmci-omap-hs"
121 /* Timeouts for entering power saving states on inactivity, msec */
122 #define OMAP_MMC_DISABLED_TIMEOUT 100
123 #define OMAP_MMC_SLEEP_TIMEOUT 1000
124 #define OMAP_MMC_OFF_TIMEOUT 8000
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
131 #define mmc_slot(host) (host->pdata->slots[host->slot_id])
134 * MMC Host controller read/write API's
136 #define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
139 #define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
142 struct omap_hsmmc_host
{
144 struct mmc_host
*mmc
;
145 struct mmc_request
*mrq
;
146 struct mmc_command
*cmd
;
147 struct mmc_data
*data
;
152 * vcc == configured supply
153 * vcc_aux == optional
154 * - MMC1, supply for DAT4..DAT7
155 * - MMC2/MMC2, external level shifter voltage supply, for
156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
158 struct regulator
*vcc
;
159 struct regulator
*vcc_aux
;
160 struct semaphore sem
;
161 struct work_struct mmc_carddetect_work
;
163 resource_size_t mapbase
;
164 spinlock_t irq_lock
; /* Prevent races with irq handler */
167 unsigned int dma_len
;
168 unsigned int dma_sg_idx
;
169 unsigned char bus_mode
;
170 unsigned char power_mode
;
176 int dma_line_tx
, dma_line_rx
;
187 struct omap_mmc_platform_data
*pdata
;
190 static int omap_hsmmc_card_detect(struct device
*dev
, int slot
)
192 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
194 /* NOTE: assumes card detect signal is active-low */
195 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
198 static int omap_hsmmc_get_wp(struct device
*dev
, int slot
)
200 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
202 /* NOTE: assumes write protect signal is active-high */
203 return gpio_get_value_cansleep(mmc
->slots
[0].gpio_wp
);
206 static int omap_hsmmc_get_cover_state(struct device
*dev
, int slot
)
208 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
210 /* NOTE: assumes card detect signal is active-low */
211 return !gpio_get_value_cansleep(mmc
->slots
[0].switch_pin
);
216 static int omap_hsmmc_suspend_cdirq(struct device
*dev
, int slot
)
218 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
220 disable_irq(mmc
->slots
[0].card_detect_irq
);
224 static int omap_hsmmc_resume_cdirq(struct device
*dev
, int slot
)
226 struct omap_mmc_platform_data
*mmc
= dev
->platform_data
;
228 enable_irq(mmc
->slots
[0].card_detect_irq
);
234 #define omap_hsmmc_suspend_cdirq NULL
235 #define omap_hsmmc_resume_cdirq NULL
239 #ifdef CONFIG_REGULATOR
241 static int omap_hsmmc_1_set_power(struct device
*dev
, int slot
, int power_on
,
244 struct omap_hsmmc_host
*host
=
245 platform_get_drvdata(to_platform_device(dev
));
248 if (mmc_slot(host
).before_set_reg
)
249 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
252 ret
= mmc_regulator_set_ocr(host
->vcc
, vdd
);
254 ret
= mmc_regulator_set_ocr(host
->vcc
, 0);
256 if (mmc_slot(host
).after_set_reg
)
257 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
262 static int omap_hsmmc_23_set_power(struct device
*dev
, int slot
, int power_on
,
265 struct omap_hsmmc_host
*host
=
266 platform_get_drvdata(to_platform_device(dev
));
270 * If we don't see a Vcc regulator, assume it's a fixed
271 * voltage always-on regulator.
276 if (mmc_slot(host
).before_set_reg
)
277 mmc_slot(host
).before_set_reg(dev
, slot
, power_on
, vdd
);
280 * Assume Vcc regulator is used only to power the card ... OMAP
281 * VDDS is used to power the pins, optionally with a transceiver to
282 * support cards using voltages other than VDDS (1.8V nominal). When a
283 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
285 * In some cases this regulator won't support enable/disable;
286 * e.g. it's a fixed rail for a WLAN chip.
288 * In other cases vcc_aux switches interface power. Example, for
289 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
290 * chips/cards need an interface voltage rail too.
293 ret
= mmc_regulator_set_ocr(host
->vcc
, vdd
);
294 /* Enable interface voltage rail, if needed */
295 if (ret
== 0 && host
->vcc_aux
) {
296 ret
= regulator_enable(host
->vcc_aux
);
298 ret
= mmc_regulator_set_ocr(host
->vcc
, 0);
302 ret
= regulator_disable(host
->vcc_aux
);
304 ret
= mmc_regulator_set_ocr(host
->vcc
, 0);
307 if (mmc_slot(host
).after_set_reg
)
308 mmc_slot(host
).after_set_reg(dev
, slot
, power_on
, vdd
);
313 static int omap_hsmmc_1_set_sleep(struct device
*dev
, int slot
, int sleep
,
314 int vdd
, int cardsleep
)
316 struct omap_hsmmc_host
*host
=
317 platform_get_drvdata(to_platform_device(dev
));
318 int mode
= sleep
? REGULATOR_MODE_STANDBY
: REGULATOR_MODE_NORMAL
;
320 return regulator_set_mode(host
->vcc
, mode
);
323 static int omap_hsmmc_23_set_sleep(struct device
*dev
, int slot
, int sleep
,
324 int vdd
, int cardsleep
)
326 struct omap_hsmmc_host
*host
=
327 platform_get_drvdata(to_platform_device(dev
));
331 * If we don't see a Vcc regulator, assume it's a fixed
332 * voltage always-on regulator.
337 mode
= sleep
? REGULATOR_MODE_STANDBY
: REGULATOR_MODE_NORMAL
;
340 return regulator_set_mode(host
->vcc
, mode
);
343 /* VCC can be turned off if card is asleep */
345 err
= mmc_regulator_set_ocr(host
->vcc
, 0);
347 err
= mmc_regulator_set_ocr(host
->vcc
, vdd
);
349 err
= regulator_set_mode(host
->vcc
, mode
);
353 if (!mmc_slot(host
).vcc_aux_disable_is_sleep
)
354 return regulator_set_mode(host
->vcc_aux
, mode
);
357 return regulator_disable(host
->vcc_aux
);
359 return regulator_enable(host
->vcc_aux
);
362 static int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
364 struct regulator
*reg
;
368 case OMAP_MMC1_DEVID
:
369 /* On-chip level shifting via PBIAS0/PBIAS1 */
370 mmc_slot(host
).set_power
= omap_hsmmc_1_set_power
;
371 mmc_slot(host
).set_sleep
= omap_hsmmc_1_set_sleep
;
373 case OMAP_MMC2_DEVID
:
374 case OMAP_MMC3_DEVID
:
375 /* Off-chip level shifting, or none */
376 mmc_slot(host
).set_power
= omap_hsmmc_23_set_power
;
377 mmc_slot(host
).set_sleep
= omap_hsmmc_23_set_sleep
;
380 pr_err("MMC%d configuration not supported!\n", host
->id
);
384 reg
= regulator_get(host
->dev
, "vmmc");
386 dev_dbg(host
->dev
, "vmmc regulator missing\n");
388 * HACK: until fixed.c regulator is usable,
389 * we don't require a main regulator
392 if (host
->id
== OMAP_MMC1_DEVID
) {
398 mmc_slot(host
).ocr_mask
= mmc_regulator_get_ocrmask(reg
);
400 /* Allow an aux regulator */
401 reg
= regulator_get(host
->dev
, "vmmc_aux");
402 host
->vcc_aux
= IS_ERR(reg
) ? NULL
: reg
;
405 * UGLY HACK: workaround regulator framework bugs.
406 * When the bootloader leaves a supply active, it's
407 * initialized with zero usecount ... and we can't
408 * disable it without first enabling it. Until the
409 * framework is fixed, we need a workaround like this
410 * (which is safe for MMC, but not in general).
412 if (regulator_is_enabled(host
->vcc
) > 0) {
413 regulator_enable(host
->vcc
);
414 regulator_disable(host
->vcc
);
417 if (regulator_is_enabled(reg
) > 0) {
418 regulator_enable(reg
);
419 regulator_disable(reg
);
427 mmc_slot(host
).set_power
= NULL
;
428 mmc_slot(host
).set_sleep
= NULL
;
432 static void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
434 regulator_put(host
->vcc
);
435 regulator_put(host
->vcc_aux
);
436 mmc_slot(host
).set_power
= NULL
;
437 mmc_slot(host
).set_sleep
= NULL
;
440 static inline int omap_hsmmc_have_reg(void)
447 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host
*host
)
452 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host
*host
)
456 static inline int omap_hsmmc_have_reg(void)
463 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data
*pdata
)
467 if (gpio_is_valid(pdata
->slots
[0].switch_pin
)) {
468 pdata
->suspend
= omap_hsmmc_suspend_cdirq
;
469 pdata
->resume
= omap_hsmmc_resume_cdirq
;
470 if (pdata
->slots
[0].cover
)
471 pdata
->slots
[0].get_cover_state
=
472 omap_hsmmc_get_cover_state
;
474 pdata
->slots
[0].card_detect
= omap_hsmmc_card_detect
;
475 pdata
->slots
[0].card_detect_irq
=
476 gpio_to_irq(pdata
->slots
[0].switch_pin
);
477 ret
= gpio_request(pdata
->slots
[0].switch_pin
, "mmc_cd");
480 ret
= gpio_direction_input(pdata
->slots
[0].switch_pin
);
484 pdata
->slots
[0].switch_pin
= -EINVAL
;
486 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
)) {
487 pdata
->slots
[0].get_ro
= omap_hsmmc_get_wp
;
488 ret
= gpio_request(pdata
->slots
[0].gpio_wp
, "mmc_wp");
491 ret
= gpio_direction_input(pdata
->slots
[0].gpio_wp
);
495 pdata
->slots
[0].gpio_wp
= -EINVAL
;
500 gpio_free(pdata
->slots
[0].gpio_wp
);
502 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
504 gpio_free(pdata
->slots
[0].switch_pin
);
508 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data
*pdata
)
510 if (gpio_is_valid(pdata
->slots
[0].gpio_wp
))
511 gpio_free(pdata
->slots
[0].gpio_wp
);
512 if (gpio_is_valid(pdata
->slots
[0].switch_pin
))
513 gpio_free(pdata
->slots
[0].switch_pin
);
517 * Stop clock to the card
519 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host
*host
)
521 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
522 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
523 if ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & CEN
) != 0x0)
524 dev_dbg(mmc_dev(host
->mmc
), "MMC Clock is not stoped\n");
530 * Restore the MMC host context, if it was lost as result of a
531 * power state change.
533 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
535 struct mmc_ios
*ios
= &host
->mmc
->ios
;
536 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
537 int context_loss
= 0;
540 unsigned long timeout
;
542 if (pdata
->get_context_loss_count
) {
543 context_loss
= pdata
->get_context_loss_count(host
->dev
);
544 if (context_loss
< 0)
548 dev_dbg(mmc_dev(host
->mmc
), "context was %slost\n",
549 context_loss
== host
->context_loss
? "not " : "");
550 if (host
->context_loss
== context_loss
)
553 /* Wait for hardware reset */
554 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
555 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
556 && time_before(jiffies
, timeout
))
559 /* Do software reset */
560 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, SOFTRESET
);
561 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
562 while ((OMAP_HSMMC_READ(host
->base
, SYSSTATUS
) & RESETDONE
) != RESETDONE
563 && time_before(jiffies
, timeout
))
566 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
,
567 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
) | AUTOIDLE
);
569 if (host
->id
== OMAP_MMC1_DEVID
) {
570 if (host
->power_mode
!= MMC_POWER_OFF
&&
571 (1 << ios
->vdd
) <= MMC_VDD_23_24
)
581 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
582 OMAP_HSMMC_READ(host
->base
, HCTL
) | hctl
);
584 OMAP_HSMMC_WRITE(host
->base
, CAPA
,
585 OMAP_HSMMC_READ(host
->base
, CAPA
) | capa
);
587 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
588 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
590 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
591 while ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
) != SDBP
592 && time_before(jiffies
, timeout
))
595 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
596 OMAP_HSMMC_WRITE(host
->base
, ISE
, INT_EN_MASK
);
597 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
599 /* Do not initialize card-specific things if the power is off */
600 if (host
->power_mode
== MMC_POWER_OFF
)
603 con
= OMAP_HSMMC_READ(host
->base
, CON
);
604 switch (ios
->bus_width
) {
605 case MMC_BUS_WIDTH_8
:
606 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
608 case MMC_BUS_WIDTH_4
:
609 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
610 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
611 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
613 case MMC_BUS_WIDTH_1
:
614 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
615 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
616 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
621 dsor
= OMAP_MMC_MASTER_CLOCK
/ ios
->clock
;
625 if (OMAP_MMC_MASTER_CLOCK
/ dsor
> ios
->clock
)
632 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
633 OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ~CEN
);
634 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, (dsor
<< 6) | (DTO
<< 16));
635 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
636 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
638 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
639 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
640 && time_before(jiffies
, timeout
))
643 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
644 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
646 con
= OMAP_HSMMC_READ(host
->base
, CON
);
647 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
648 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
650 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
652 host
->context_loss
= context_loss
;
654 dev_dbg(mmc_dev(host
->mmc
), "context is restored\n");
659 * Save the MMC host context (store the number of power state changes so far).
661 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
663 struct omap_mmc_platform_data
*pdata
= host
->pdata
;
666 if (pdata
->get_context_loss_count
) {
667 context_loss
= pdata
->get_context_loss_count(host
->dev
);
668 if (context_loss
< 0)
670 host
->context_loss
= context_loss
;
676 static int omap_hsmmc_context_restore(struct omap_hsmmc_host
*host
)
681 static void omap_hsmmc_context_save(struct omap_hsmmc_host
*host
)
688 * Send init stream sequence to card
689 * before sending IDLE command
691 static void send_init_stream(struct omap_hsmmc_host
*host
)
694 unsigned long timeout
;
696 if (host
->protect_card
)
699 disable_irq(host
->irq
);
700 OMAP_HSMMC_WRITE(host
->base
, CON
,
701 OMAP_HSMMC_READ(host
->base
, CON
) | INIT_STREAM
);
702 OMAP_HSMMC_WRITE(host
->base
, CMD
, INIT_STREAM_CMD
);
704 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
705 while ((reg
!= CC
) && time_before(jiffies
, timeout
))
706 reg
= OMAP_HSMMC_READ(host
->base
, STAT
) & CC
;
708 OMAP_HSMMC_WRITE(host
->base
, CON
,
709 OMAP_HSMMC_READ(host
->base
, CON
) & ~INIT_STREAM
);
711 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
712 OMAP_HSMMC_READ(host
->base
, STAT
);
714 enable_irq(host
->irq
);
718 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host
*host
)
722 if (mmc_slot(host
).get_cover_state
)
723 r
= mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
);
728 omap_hsmmc_show_cover_switch(struct device
*dev
, struct device_attribute
*attr
,
731 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
732 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
734 return sprintf(buf
, "%s\n",
735 omap_hsmmc_cover_is_closed(host
) ? "closed" : "open");
738 static DEVICE_ATTR(cover_switch
, S_IRUGO
, omap_hsmmc_show_cover_switch
, NULL
);
741 omap_hsmmc_show_slot_name(struct device
*dev
, struct device_attribute
*attr
,
744 struct mmc_host
*mmc
= container_of(dev
, struct mmc_host
, class_dev
);
745 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
747 return sprintf(buf
, "%s\n", mmc_slot(host
).name
);
750 static DEVICE_ATTR(slot_name
, S_IRUGO
, omap_hsmmc_show_slot_name
, NULL
);
753 * Configure the response type and send the cmd.
756 omap_hsmmc_start_command(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
,
757 struct mmc_data
*data
)
759 int cmdreg
= 0, resptype
= 0, cmdtype
= 0;
761 dev_dbg(mmc_dev(host
->mmc
), "%s: CMD%d, argument 0x%08x\n",
762 mmc_hostname(host
->mmc
), cmd
->opcode
, cmd
->arg
);
766 * Clear status bits and enable interrupts
768 OMAP_HSMMC_WRITE(host
->base
, STAT
, STAT_CLEAR
);
769 OMAP_HSMMC_WRITE(host
->base
, ISE
, INT_EN_MASK
);
772 OMAP_HSMMC_WRITE(host
->base
, IE
,
773 INT_EN_MASK
& ~(BRR_ENABLE
| BWR_ENABLE
));
775 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
777 host
->response_busy
= 0;
778 if (cmd
->flags
& MMC_RSP_PRESENT
) {
779 if (cmd
->flags
& MMC_RSP_136
)
781 else if (cmd
->flags
& MMC_RSP_BUSY
) {
783 host
->response_busy
= 1;
789 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
790 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
791 * a val of 0x3, rest 0x0.
793 if (cmd
== host
->mrq
->stop
)
796 cmdreg
= (cmd
->opcode
<< 24) | (resptype
<< 16) | (cmdtype
<< 22);
799 cmdreg
|= DP_SELECT
| MSBS
| BCE
;
800 if (data
->flags
& MMC_DATA_READ
)
810 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
811 * by the interrupt handler, otherwise (i.e. for a new request) it is
815 spin_unlock_irqrestore(&host
->irq_lock
, host
->flags
);
817 OMAP_HSMMC_WRITE(host
->base
, ARG
, cmd
->arg
);
818 OMAP_HSMMC_WRITE(host
->base
, CMD
, cmdreg
);
822 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
824 if (data
->flags
& MMC_DATA_WRITE
)
825 return DMA_TO_DEVICE
;
827 return DMA_FROM_DEVICE
;
831 * Notify the transfer complete to MMC core
834 omap_hsmmc_xfer_done(struct omap_hsmmc_host
*host
, struct mmc_data
*data
)
837 struct mmc_request
*mrq
= host
->mrq
;
839 /* TC before CC from CMD6 - don't know why, but it happens */
840 if (host
->cmd
&& host
->cmd
->opcode
== 6 &&
841 host
->response_busy
) {
842 host
->response_busy
= 0;
847 mmc_request_done(host
->mmc
, mrq
);
853 if (host
->use_dma
&& host
->dma_ch
!= -1)
854 dma_unmap_sg(mmc_dev(host
->mmc
), data
->sg
, host
->dma_len
,
855 omap_hsmmc_get_dma_dir(host
, data
));
858 data
->bytes_xfered
+= data
->blocks
* (data
->blksz
);
860 data
->bytes_xfered
= 0;
864 mmc_request_done(host
->mmc
, data
->mrq
);
867 omap_hsmmc_start_command(host
, data
->stop
, NULL
);
871 * Notify the core about command completion
874 omap_hsmmc_cmd_done(struct omap_hsmmc_host
*host
, struct mmc_command
*cmd
)
878 if (cmd
->flags
& MMC_RSP_PRESENT
) {
879 if (cmd
->flags
& MMC_RSP_136
) {
880 /* response type 2 */
881 cmd
->resp
[3] = OMAP_HSMMC_READ(host
->base
, RSP10
);
882 cmd
->resp
[2] = OMAP_HSMMC_READ(host
->base
, RSP32
);
883 cmd
->resp
[1] = OMAP_HSMMC_READ(host
->base
, RSP54
);
884 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP76
);
886 /* response types 1, 1b, 3, 4, 5, 6 */
887 cmd
->resp
[0] = OMAP_HSMMC_READ(host
->base
, RSP10
);
890 if ((host
->data
== NULL
&& !host
->response_busy
) || cmd
->error
) {
892 mmc_request_done(host
->mmc
, cmd
->mrq
);
897 * DMA clean up for command errors
899 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host
*host
, int errno
)
901 host
->data
->error
= errno
;
903 if (host
->use_dma
&& host
->dma_ch
!= -1) {
904 dma_unmap_sg(mmc_dev(host
->mmc
), host
->data
->sg
, host
->dma_len
,
905 omap_hsmmc_get_dma_dir(host
, host
->data
));
906 omap_free_dma(host
->dma_ch
);
914 * Readable error output
916 #ifdef CONFIG_MMC_DEBUG
917 static void omap_hsmmc_report_irq(struct omap_hsmmc_host
*host
, u32 status
)
919 /* --- means reserved bit without definition at documentation */
920 static const char *omap_hsmmc_status_bits
[] = {
921 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
922 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
923 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
924 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
930 len
= sprintf(buf
, "MMC IRQ 0x%x :", status
);
933 for (i
= 0; i
< ARRAY_SIZE(omap_hsmmc_status_bits
); i
++)
934 if (status
& (1 << i
)) {
935 len
= sprintf(buf
, " %s", omap_hsmmc_status_bits
[i
]);
939 dev_dbg(mmc_dev(host
->mmc
), "%s\n", res
);
941 #endif /* CONFIG_MMC_DEBUG */
944 * MMC controller internal state machines reset
946 * Used to reset command or data internal state machines, using respectively
947 * SRC or SRD bit of SYSCTL register
948 * Can be called from interrupt context
950 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host
*host
,
954 unsigned long limit
= (loops_per_jiffy
*
955 msecs_to_jiffies(MMC_TIMEOUT_MS
));
957 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
958 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | bit
);
960 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
) &&
964 if (OMAP_HSMMC_READ(host
->base
, SYSCTL
) & bit
)
965 dev_err(mmc_dev(host
->mmc
),
966 "Timeout waiting on controller reset in %s\n",
971 * MMC controller IRQ handler
973 static irqreturn_t
omap_hsmmc_irq(int irq
, void *dev_id
)
975 struct omap_hsmmc_host
*host
= dev_id
;
976 struct mmc_data
*data
;
977 int end_cmd
= 0, end_trans
= 0, status
;
979 spin_lock(&host
->irq_lock
);
981 if (host
->mrq
== NULL
) {
982 OMAP_HSMMC_WRITE(host
->base
, STAT
,
983 OMAP_HSMMC_READ(host
->base
, STAT
));
984 /* Flush posted write */
985 OMAP_HSMMC_READ(host
->base
, STAT
);
986 spin_unlock(&host
->irq_lock
);
991 status
= OMAP_HSMMC_READ(host
->base
, STAT
);
992 dev_dbg(mmc_dev(host
->mmc
), "IRQ Status is %x\n", status
);
995 #ifdef CONFIG_MMC_DEBUG
996 omap_hsmmc_report_irq(host
, status
);
998 if ((status
& CMD_TIMEOUT
) ||
999 (status
& CMD_CRC
)) {
1001 if (status
& CMD_TIMEOUT
) {
1002 omap_hsmmc_reset_controller_fsm(host
,
1004 host
->cmd
->error
= -ETIMEDOUT
;
1006 host
->cmd
->error
= -EILSEQ
;
1010 if (host
->data
|| host
->response_busy
) {
1012 omap_hsmmc_dma_cleanup(host
,
1014 host
->response_busy
= 0;
1015 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1018 if ((status
& DATA_TIMEOUT
) ||
1019 (status
& DATA_CRC
)) {
1020 if (host
->data
|| host
->response_busy
) {
1021 int err
= (status
& DATA_TIMEOUT
) ?
1022 -ETIMEDOUT
: -EILSEQ
;
1025 omap_hsmmc_dma_cleanup(host
, err
);
1027 host
->mrq
->cmd
->error
= err
;
1028 host
->response_busy
= 0;
1029 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1033 if (status
& CARD_ERR
) {
1034 dev_dbg(mmc_dev(host
->mmc
),
1035 "Ignoring card err CMD%d\n", host
->cmd
->opcode
);
1043 OMAP_HSMMC_WRITE(host
->base
, STAT
, status
);
1044 /* Flush posted write */
1045 OMAP_HSMMC_READ(host
->base
, STAT
);
1047 if (end_cmd
|| ((status
& CC
) && host
->cmd
))
1048 omap_hsmmc_cmd_done(host
, host
->cmd
);
1049 if ((end_trans
|| (status
& TC
)) && host
->mrq
)
1050 omap_hsmmc_xfer_done(host
, data
);
1052 spin_unlock(&host
->irq_lock
);
1057 static void set_sd_bus_power(struct omap_hsmmc_host
*host
)
1061 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1062 OMAP_HSMMC_READ(host
->base
, HCTL
) | SDBP
);
1063 for (i
= 0; i
< loops_per_jiffy
; i
++) {
1064 if (OMAP_HSMMC_READ(host
->base
, HCTL
) & SDBP
)
1071 * Switch MMC interface voltage ... only relevant for MMC1.
1073 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1074 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1075 * Some chips, like eMMC ones, use internal transceivers.
1077 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host
*host
, int vdd
)
1082 /* Disable the clocks */
1083 clk_disable(host
->fclk
);
1084 clk_disable(host
->iclk
);
1085 if (host
->got_dbclk
)
1086 clk_disable(host
->dbclk
);
1088 /* Turn the power off */
1089 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1091 /* Turn the power ON with given VDD 1.8 or 3.0v */
1093 ret
= mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 1,
1095 clk_enable(host
->iclk
);
1096 clk_enable(host
->fclk
);
1097 if (host
->got_dbclk
)
1098 clk_enable(host
->dbclk
);
1103 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1104 OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSCLR
);
1105 reg_val
= OMAP_HSMMC_READ(host
->base
, HCTL
);
1108 * If a MMC dual voltage card is detected, the set_ios fn calls
1109 * this fn with VDD bit set for 1.8V. Upon card removal from the
1110 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
1112 * Cope with a bit of slop in the range ... per data sheets:
1113 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1114 * but recommended values are 1.71V to 1.89V
1115 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1116 * but recommended values are 2.7V to 3.3V
1118 * Board setup code shouldn't permit anything very out-of-range.
1119 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1120 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
1122 if ((1 << vdd
) <= MMC_VDD_23_24
)
1127 OMAP_HSMMC_WRITE(host
->base
, HCTL
, reg_val
);
1128 set_sd_bus_power(host
);
1132 dev_dbg(mmc_dev(host
->mmc
), "Unable to switch operating voltage\n");
1136 /* Protect the card while the cover is open */
1137 static void omap_hsmmc_protect_card(struct omap_hsmmc_host
*host
)
1139 if (!mmc_slot(host
).get_cover_state
)
1142 host
->reqs_blocked
= 0;
1143 if (mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)) {
1144 if (host
->protect_card
) {
1145 printk(KERN_INFO
"%s: cover is closed, "
1146 "card is now accessible\n",
1147 mmc_hostname(host
->mmc
));
1148 host
->protect_card
= 0;
1151 if (!host
->protect_card
) {
1152 printk(KERN_INFO
"%s: cover is open, "
1153 "card is now inaccessible\n",
1154 mmc_hostname(host
->mmc
));
1155 host
->protect_card
= 1;
1161 * Work Item to notify the core about card insertion/removal
1163 static void omap_hsmmc_detect(struct work_struct
*work
)
1165 struct omap_hsmmc_host
*host
=
1166 container_of(work
, struct omap_hsmmc_host
, mmc_carddetect_work
);
1167 struct omap_mmc_slot_data
*slot
= &mmc_slot(host
);
1170 if (host
->suspended
)
1173 sysfs_notify(&host
->mmc
->class_dev
.kobj
, NULL
, "cover_switch");
1175 if (slot
->card_detect
)
1176 carddetect
= slot
->card_detect(host
->dev
, host
->slot_id
);
1178 omap_hsmmc_protect_card(host
);
1179 carddetect
= -ENOSYS
;
1183 mmc_detect_change(host
->mmc
, (HZ
* 200) / 1000);
1185 mmc_host_enable(host
->mmc
);
1186 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1187 mmc_host_lazy_disable(host
->mmc
);
1189 mmc_detect_change(host
->mmc
, (HZ
* 50) / 1000);
1194 * ISR for handling card insertion and removal
1196 static irqreturn_t
omap_hsmmc_cd_handler(int irq
, void *dev_id
)
1198 struct omap_hsmmc_host
*host
= (struct omap_hsmmc_host
*)dev_id
;
1200 if (host
->suspended
)
1202 schedule_work(&host
->mmc_carddetect_work
);
1207 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host
*host
,
1208 struct mmc_data
*data
)
1212 if (data
->flags
& MMC_DATA_WRITE
)
1213 sync_dev
= host
->dma_line_tx
;
1215 sync_dev
= host
->dma_line_rx
;
1219 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host
*host
,
1220 struct mmc_data
*data
,
1221 struct scatterlist
*sgl
)
1223 int blksz
, nblk
, dma_ch
;
1225 dma_ch
= host
->dma_ch
;
1226 if (data
->flags
& MMC_DATA_WRITE
) {
1227 omap_set_dma_dest_params(dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
1228 (host
->mapbase
+ OMAP_HSMMC_DATA
), 0, 0);
1229 omap_set_dma_src_params(dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
1230 sg_dma_address(sgl
), 0, 0);
1232 omap_set_dma_src_params(dma_ch
, 0, OMAP_DMA_AMODE_CONSTANT
,
1233 (host
->mapbase
+ OMAP_HSMMC_DATA
), 0, 0);
1234 omap_set_dma_dest_params(dma_ch
, 0, OMAP_DMA_AMODE_POST_INC
,
1235 sg_dma_address(sgl
), 0, 0);
1238 blksz
= host
->data
->blksz
;
1239 nblk
= sg_dma_len(sgl
) / blksz
;
1241 omap_set_dma_transfer_params(dma_ch
, OMAP_DMA_DATA_TYPE_S32
,
1242 blksz
/ 4, nblk
, OMAP_DMA_SYNC_FRAME
,
1243 omap_hsmmc_get_dma_sync_dev(host
, data
),
1244 !(data
->flags
& MMC_DATA_WRITE
));
1246 omap_start_dma(dma_ch
);
1250 * DMA call back function
1252 static void omap_hsmmc_dma_cb(int lch
, u16 ch_status
, void *data
)
1254 struct omap_hsmmc_host
*host
= data
;
1256 if (ch_status
& OMAP2_DMA_MISALIGNED_ERR_IRQ
)
1257 dev_dbg(mmc_dev(host
->mmc
), "MISALIGNED_ADRS_ERR\n");
1259 if (host
->dma_ch
< 0)
1263 if (host
->dma_sg_idx
< host
->dma_len
) {
1264 /* Fire up the next transfer. */
1265 omap_hsmmc_config_dma_params(host
, host
->data
,
1266 host
->data
->sg
+ host
->dma_sg_idx
);
1270 omap_free_dma(host
->dma_ch
);
1273 * DMA Callback: run in interrupt context.
1274 * mutex_unlock will throw a kernel warning if used.
1280 * Routine to configure and start DMA for the MMC card
1282 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host
*host
,
1283 struct mmc_request
*req
)
1285 int dma_ch
= 0, ret
= 0, err
= 1, i
;
1286 struct mmc_data
*data
= req
->data
;
1288 /* Sanity check: all the SG entries must be aligned by block size. */
1289 for (i
= 0; i
< data
->sg_len
; i
++) {
1290 struct scatterlist
*sgl
;
1293 if (sgl
->length
% data
->blksz
)
1296 if ((data
->blksz
% 4) != 0)
1297 /* REVISIT: The MMC buffer increments only when MSB is written.
1298 * Return error for blksz which is non multiple of four.
1303 * If for some reason the DMA transfer is still active,
1304 * we wait for timeout period and free the dma
1306 if (host
->dma_ch
!= -1) {
1307 set_current_state(TASK_UNINTERRUPTIBLE
);
1308 schedule_timeout(100);
1309 if (down_trylock(&host
->sem
)) {
1310 omap_free_dma(host
->dma_ch
);
1316 if (down_trylock(&host
->sem
))
1320 ret
= omap_request_dma(omap_hsmmc_get_dma_sync_dev(host
, data
),
1321 "MMC/SD", omap_hsmmc_dma_cb
, host
, &dma_ch
);
1323 dev_err(mmc_dev(host
->mmc
),
1324 "%s: omap_request_dma() failed with %d\n",
1325 mmc_hostname(host
->mmc
), ret
);
1329 host
->dma_len
= dma_map_sg(mmc_dev(host
->mmc
), data
->sg
,
1330 data
->sg_len
, omap_hsmmc_get_dma_dir(host
, data
));
1331 host
->dma_ch
= dma_ch
;
1332 host
->dma_sg_idx
= 0;
1334 omap_hsmmc_config_dma_params(host
, data
, data
->sg
);
1339 static void set_data_timeout(struct omap_hsmmc_host
*host
,
1340 unsigned int timeout_ns
,
1341 unsigned int timeout_clks
)
1343 unsigned int timeout
, cycle_ns
;
1344 uint32_t reg
, clkd
, dto
= 0;
1346 reg
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1347 clkd
= (reg
& CLKD_MASK
) >> CLKD_SHIFT
;
1351 cycle_ns
= 1000000000 / (clk_get_rate(host
->fclk
) / clkd
);
1352 timeout
= timeout_ns
/ cycle_ns
;
1353 timeout
+= timeout_clks
;
1355 while ((timeout
& 0x80000000) == 0) {
1372 reg
|= dto
<< DTO_SHIFT
;
1373 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, reg
);
1377 * Configure block length for MMC/SD cards and initiate the transfer.
1380 omap_hsmmc_prepare_data(struct omap_hsmmc_host
*host
, struct mmc_request
*req
)
1383 host
->data
= req
->data
;
1385 if (req
->data
== NULL
) {
1386 OMAP_HSMMC_WRITE(host
->base
, BLK
, 0);
1388 * Set an arbitrary 100ms data timeout for commands with
1391 if (req
->cmd
->flags
& MMC_RSP_BUSY
)
1392 set_data_timeout(host
, 100000000U, 0);
1396 OMAP_HSMMC_WRITE(host
->base
, BLK
, (req
->data
->blksz
)
1397 | (req
->data
->blocks
<< 16));
1398 set_data_timeout(host
, req
->data
->timeout_ns
, req
->data
->timeout_clks
);
1400 if (host
->use_dma
) {
1401 ret
= omap_hsmmc_start_dma_transfer(host
, req
);
1403 dev_dbg(mmc_dev(host
->mmc
), "MMC start dma failure\n");
1411 * Request function. for read/write operation
1413 static void omap_hsmmc_request(struct mmc_host
*mmc
, struct mmc_request
*req
)
1415 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1419 * Prevent races with the interrupt handler because of unexpected
1420 * interrupts, but not if we are already in interrupt context i.e.
1423 if (!in_interrupt()) {
1424 spin_lock_irqsave(&host
->irq_lock
, host
->flags
);
1426 * Protect the card from I/O if there is a possibility
1427 * it can be removed.
1429 if (host
->protect_card
) {
1430 if (host
->reqs_blocked
< 3) {
1432 * Ensure the controller is left in a consistent
1433 * state by resetting the command and data state
1436 omap_hsmmc_reset_controller_fsm(host
, SRD
);
1437 omap_hsmmc_reset_controller_fsm(host
, SRC
);
1438 host
->reqs_blocked
+= 1;
1440 req
->cmd
->error
= -EBADF
;
1442 req
->data
->error
= -EBADF
;
1443 spin_unlock_irqrestore(&host
->irq_lock
, host
->flags
);
1444 mmc_request_done(mmc
, req
);
1446 } else if (host
->reqs_blocked
)
1447 host
->reqs_blocked
= 0;
1449 WARN_ON(host
->mrq
!= NULL
);
1451 err
= omap_hsmmc_prepare_data(host
, req
);
1453 req
->cmd
->error
= err
;
1455 req
->data
->error
= err
;
1457 if (!in_interrupt())
1458 spin_unlock_irqrestore(&host
->irq_lock
, host
->flags
);
1459 mmc_request_done(mmc
, req
);
1463 omap_hsmmc_start_command(host
, req
->cmd
, req
->data
);
1466 /* Routine to configure clock values. Exposed API to core */
1467 static void omap_hsmmc_set_ios(struct mmc_host
*mmc
, struct mmc_ios
*ios
)
1469 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1471 unsigned long regval
;
1472 unsigned long timeout
;
1474 int do_send_init_stream
= 0;
1476 mmc_host_enable(host
->mmc
);
1478 if (ios
->power_mode
!= host
->power_mode
) {
1479 switch (ios
->power_mode
) {
1481 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1486 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
,
1488 host
->vdd
= ios
->vdd
;
1491 do_send_init_stream
= 1;
1494 host
->power_mode
= ios
->power_mode
;
1497 /* FIXME: set registers based only on changes to ios */
1499 con
= OMAP_HSMMC_READ(host
->base
, CON
);
1500 switch (mmc
->ios
.bus_width
) {
1501 case MMC_BUS_WIDTH_8
:
1502 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| DW8
);
1504 case MMC_BUS_WIDTH_4
:
1505 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
1506 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1507 OMAP_HSMMC_READ(host
->base
, HCTL
) | FOUR_BIT
);
1509 case MMC_BUS_WIDTH_1
:
1510 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~DW8
);
1511 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
1512 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~FOUR_BIT
);
1516 if (host
->id
== OMAP_MMC1_DEVID
) {
1517 /* Only MMC1 can interface at 3V without some flavor
1518 * of external transceiver; but they all handle 1.8V.
1520 if ((OMAP_HSMMC_READ(host
->base
, HCTL
) & SDVSDET
) &&
1521 (ios
->vdd
== DUAL_VOLT_OCR_BIT
)) {
1523 * The mmc_select_voltage fn of the core does
1524 * not seem to set the power_mode to
1525 * MMC_POWER_UP upon recalculating the voltage.
1528 if (omap_hsmmc_switch_opcond(host
, ios
->vdd
) != 0)
1529 dev_dbg(mmc_dev(host
->mmc
),
1530 "Switch operation failed\n");
1535 dsor
= OMAP_MMC_MASTER_CLOCK
/ ios
->clock
;
1539 if (OMAP_MMC_MASTER_CLOCK
/ dsor
> ios
->clock
)
1545 omap_hsmmc_stop_clock(host
);
1546 regval
= OMAP_HSMMC_READ(host
->base
, SYSCTL
);
1547 regval
= regval
& ~(CLKD_MASK
);
1548 regval
= regval
| (dsor
<< 6) | (DTO
<< 16);
1549 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
, regval
);
1550 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
1551 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | ICE
);
1553 /* Wait till the ICS bit is set */
1554 timeout
= jiffies
+ msecs_to_jiffies(MMC_TIMEOUT_MS
);
1555 while ((OMAP_HSMMC_READ(host
->base
, SYSCTL
) & ICS
) != ICS
1556 && time_before(jiffies
, timeout
))
1559 OMAP_HSMMC_WRITE(host
->base
, SYSCTL
,
1560 OMAP_HSMMC_READ(host
->base
, SYSCTL
) | CEN
);
1562 if (do_send_init_stream
)
1563 send_init_stream(host
);
1565 con
= OMAP_HSMMC_READ(host
->base
, CON
);
1566 if (ios
->bus_mode
== MMC_BUSMODE_OPENDRAIN
)
1567 OMAP_HSMMC_WRITE(host
->base
, CON
, con
| OD
);
1569 OMAP_HSMMC_WRITE(host
->base
, CON
, con
& ~OD
);
1571 if (host
->power_mode
== MMC_POWER_OFF
)
1572 mmc_host_disable(host
->mmc
);
1574 mmc_host_lazy_disable(host
->mmc
);
1577 static int omap_hsmmc_get_cd(struct mmc_host
*mmc
)
1579 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1581 if (!mmc_slot(host
).card_detect
)
1583 return mmc_slot(host
).card_detect(host
->dev
, host
->slot_id
);
1586 static int omap_hsmmc_get_ro(struct mmc_host
*mmc
)
1588 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1590 if (!mmc_slot(host
).get_ro
)
1592 return mmc_slot(host
).get_ro(host
->dev
, 0);
1595 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host
*host
)
1597 u32 hctl
, capa
, value
;
1599 /* Only MMC1 supports 3.0V */
1600 if (host
->id
== OMAP_MMC1_DEVID
) {
1608 value
= OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDVS_MASK
;
1609 OMAP_HSMMC_WRITE(host
->base
, HCTL
, value
| hctl
);
1611 value
= OMAP_HSMMC_READ(host
->base
, CAPA
);
1612 OMAP_HSMMC_WRITE(host
->base
, CAPA
, value
| capa
);
1614 /* Set the controller to AUTO IDLE mode */
1615 value
= OMAP_HSMMC_READ(host
->base
, SYSCONFIG
);
1616 OMAP_HSMMC_WRITE(host
->base
, SYSCONFIG
, value
| AUTOIDLE
);
1618 /* Set SD bus power bit */
1619 set_sd_bus_power(host
);
1623 * Dynamic power saving handling, FSM:
1624 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1626 * |______________________|______________________|
1628 * ENABLED: mmc host is fully functional
1629 * DISABLED: fclk is off
1630 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1631 * REGSLEEP: fclk is off, voltage regulator is asleep
1632 * OFF: fclk is off, voltage regulator is off
1634 * Transition handlers return the timeout for the next state transition
1635 * or negative error.
1638 enum {ENABLED
= 0, DISABLED
, CARDSLEEP
, REGSLEEP
, OFF
};
1640 /* Handler for [ENABLED -> DISABLED] transition */
1641 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host
*host
)
1643 omap_hsmmc_context_save(host
);
1644 clk_disable(host
->fclk
);
1645 host
->dpm_state
= DISABLED
;
1647 dev_dbg(mmc_dev(host
->mmc
), "ENABLED -> DISABLED\n");
1649 if (host
->power_mode
== MMC_POWER_OFF
)
1652 return OMAP_MMC_SLEEP_TIMEOUT
;
1655 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
1656 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host
*host
)
1660 if (!mmc_try_claim_host(host
->mmc
))
1663 clk_enable(host
->fclk
);
1664 omap_hsmmc_context_restore(host
);
1665 if (mmc_card_can_sleep(host
->mmc
)) {
1666 err
= mmc_card_sleep(host
->mmc
);
1668 clk_disable(host
->fclk
);
1669 mmc_release_host(host
->mmc
);
1672 new_state
= CARDSLEEP
;
1674 new_state
= REGSLEEP
;
1676 if (mmc_slot(host
).set_sleep
)
1677 mmc_slot(host
).set_sleep(host
->dev
, host
->slot_id
, 1, 0,
1678 new_state
== CARDSLEEP
);
1679 /* FIXME: turn off bus power and perhaps interrupts too */
1680 clk_disable(host
->fclk
);
1681 host
->dpm_state
= new_state
;
1683 mmc_release_host(host
->mmc
);
1685 dev_dbg(mmc_dev(host
->mmc
), "DISABLED -> %s\n",
1686 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1688 if (mmc_slot(host
).no_off
)
1691 if ((host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
) ||
1692 mmc_slot(host
).card_detect
||
1693 (mmc_slot(host
).get_cover_state
&&
1694 mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)))
1695 return OMAP_MMC_OFF_TIMEOUT
;
1700 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
1701 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host
*host
)
1703 if (!mmc_try_claim_host(host
->mmc
))
1706 if (mmc_slot(host
).no_off
)
1709 if (!((host
->mmc
->caps
& MMC_CAP_NONREMOVABLE
) ||
1710 mmc_slot(host
).card_detect
||
1711 (mmc_slot(host
).get_cover_state
&&
1712 mmc_slot(host
).get_cover_state(host
->dev
, host
->slot_id
)))) {
1713 mmc_release_host(host
->mmc
);
1717 mmc_slot(host
).set_power(host
->dev
, host
->slot_id
, 0, 0);
1719 host
->power_mode
= MMC_POWER_OFF
;
1721 dev_dbg(mmc_dev(host
->mmc
), "%s -> OFF\n",
1722 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1724 host
->dpm_state
= OFF
;
1726 mmc_release_host(host
->mmc
);
1731 /* Handler for [DISABLED -> ENABLED] transition */
1732 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host
*host
)
1736 err
= clk_enable(host
->fclk
);
1740 omap_hsmmc_context_restore(host
);
1741 host
->dpm_state
= ENABLED
;
1743 dev_dbg(mmc_dev(host
->mmc
), "DISABLED -> ENABLED\n");
1748 /* Handler for [SLEEP -> ENABLED] transition */
1749 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host
*host
)
1751 if (!mmc_try_claim_host(host
->mmc
))
1754 clk_enable(host
->fclk
);
1755 omap_hsmmc_context_restore(host
);
1756 if (mmc_slot(host
).set_sleep
)
1757 mmc_slot(host
).set_sleep(host
->dev
, host
->slot_id
, 0,
1758 host
->vdd
, host
->dpm_state
== CARDSLEEP
);
1759 if (mmc_card_can_sleep(host
->mmc
))
1760 mmc_card_awake(host
->mmc
);
1762 dev_dbg(mmc_dev(host
->mmc
), "%s -> ENABLED\n",
1763 host
->dpm_state
== CARDSLEEP
? "CARDSLEEP" : "REGSLEEP");
1765 host
->dpm_state
= ENABLED
;
1767 mmc_release_host(host
->mmc
);
1772 /* Handler for [OFF -> ENABLED] transition */
1773 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host
*host
)
1775 clk_enable(host
->fclk
);
1777 omap_hsmmc_context_restore(host
);
1778 omap_hsmmc_conf_bus_power(host
);
1779 mmc_power_restore_host(host
->mmc
);
1781 host
->dpm_state
= ENABLED
;
1783 dev_dbg(mmc_dev(host
->mmc
), "OFF -> ENABLED\n");
1789 * Bring MMC host to ENABLED from any other PM state.
1791 static int omap_hsmmc_enable(struct mmc_host
*mmc
)
1793 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1795 switch (host
->dpm_state
) {
1797 return omap_hsmmc_disabled_to_enabled(host
);
1800 return omap_hsmmc_sleep_to_enabled(host
);
1802 return omap_hsmmc_off_to_enabled(host
);
1804 dev_dbg(mmc_dev(host
->mmc
), "UNKNOWN state\n");
1810 * Bring MMC host in PM state (one level deeper).
1812 static int omap_hsmmc_disable(struct mmc_host
*mmc
, int lazy
)
1814 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1816 switch (host
->dpm_state
) {
1820 delay
= omap_hsmmc_enabled_to_disabled(host
);
1821 if (lazy
|| delay
< 0)
1826 return omap_hsmmc_disabled_to_sleep(host
);
1829 return omap_hsmmc_sleep_to_off(host
);
1831 dev_dbg(mmc_dev(host
->mmc
), "UNKNOWN state\n");
1836 static int omap_hsmmc_enable_fclk(struct mmc_host
*mmc
)
1838 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1841 err
= clk_enable(host
->fclk
);
1844 dev_dbg(mmc_dev(host
->mmc
), "mmc_fclk: enabled\n");
1845 omap_hsmmc_context_restore(host
);
1849 static int omap_hsmmc_disable_fclk(struct mmc_host
*mmc
, int lazy
)
1851 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1853 omap_hsmmc_context_save(host
);
1854 clk_disable(host
->fclk
);
1855 dev_dbg(mmc_dev(host
->mmc
), "mmc_fclk: disabled\n");
1859 static const struct mmc_host_ops omap_hsmmc_ops
= {
1860 .enable
= omap_hsmmc_enable_fclk
,
1861 .disable
= omap_hsmmc_disable_fclk
,
1862 .request
= omap_hsmmc_request
,
1863 .set_ios
= omap_hsmmc_set_ios
,
1864 .get_cd
= omap_hsmmc_get_cd
,
1865 .get_ro
= omap_hsmmc_get_ro
,
1866 /* NYET -- enable_sdio_irq */
1869 static const struct mmc_host_ops omap_hsmmc_ps_ops
= {
1870 .enable
= omap_hsmmc_enable
,
1871 .disable
= omap_hsmmc_disable
,
1872 .request
= omap_hsmmc_request
,
1873 .set_ios
= omap_hsmmc_set_ios
,
1874 .get_cd
= omap_hsmmc_get_cd
,
1875 .get_ro
= omap_hsmmc_get_ro
,
1876 /* NYET -- enable_sdio_irq */
1879 #ifdef CONFIG_DEBUG_FS
1881 static int omap_hsmmc_regs_show(struct seq_file
*s
, void *data
)
1883 struct mmc_host
*mmc
= s
->private;
1884 struct omap_hsmmc_host
*host
= mmc_priv(mmc
);
1885 int context_loss
= 0;
1887 if (host
->pdata
->get_context_loss_count
)
1888 context_loss
= host
->pdata
->get_context_loss_count(host
->dev
);
1890 seq_printf(s
, "mmc%d:\n"
1893 " nesting_cnt:\t%d\n"
1894 " ctx_loss:\t%d:%d\n"
1896 mmc
->index
, mmc
->enabled
? 1 : 0,
1897 host
->dpm_state
, mmc
->nesting_cnt
,
1898 host
->context_loss
, context_loss
);
1900 if (host
->suspended
|| host
->dpm_state
== OFF
) {
1901 seq_printf(s
, "host suspended, can't read registers\n");
1905 if (clk_enable(host
->fclk
) != 0) {
1906 seq_printf(s
, "can't read the regs\n");
1910 seq_printf(s
, "SYSCONFIG:\t0x%08x\n",
1911 OMAP_HSMMC_READ(host
->base
, SYSCONFIG
));
1912 seq_printf(s
, "CON:\t\t0x%08x\n",
1913 OMAP_HSMMC_READ(host
->base
, CON
));
1914 seq_printf(s
, "HCTL:\t\t0x%08x\n",
1915 OMAP_HSMMC_READ(host
->base
, HCTL
));
1916 seq_printf(s
, "SYSCTL:\t\t0x%08x\n",
1917 OMAP_HSMMC_READ(host
->base
, SYSCTL
));
1918 seq_printf(s
, "IE:\t\t0x%08x\n",
1919 OMAP_HSMMC_READ(host
->base
, IE
));
1920 seq_printf(s
, "ISE:\t\t0x%08x\n",
1921 OMAP_HSMMC_READ(host
->base
, ISE
));
1922 seq_printf(s
, "CAPA:\t\t0x%08x\n",
1923 OMAP_HSMMC_READ(host
->base
, CAPA
));
1925 clk_disable(host
->fclk
);
1930 static int omap_hsmmc_regs_open(struct inode
*inode
, struct file
*file
)
1932 return single_open(file
, omap_hsmmc_regs_show
, inode
->i_private
);
1935 static const struct file_operations mmc_regs_fops
= {
1936 .open
= omap_hsmmc_regs_open
,
1938 .llseek
= seq_lseek
,
1939 .release
= single_release
,
1942 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1944 if (mmc
->debugfs_root
)
1945 debugfs_create_file("regs", S_IRUSR
, mmc
->debugfs_root
,
1946 mmc
, &mmc_regs_fops
);
1951 static void omap_hsmmc_debugfs(struct mmc_host
*mmc
)
1957 static int __init
omap_hsmmc_probe(struct platform_device
*pdev
)
1959 struct omap_mmc_platform_data
*pdata
= pdev
->dev
.platform_data
;
1960 struct mmc_host
*mmc
;
1961 struct omap_hsmmc_host
*host
= NULL
;
1962 struct resource
*res
;
1965 if (pdata
== NULL
) {
1966 dev_err(&pdev
->dev
, "Platform Data is missing\n");
1970 if (pdata
->nr_slots
== 0) {
1971 dev_err(&pdev
->dev
, "No Slots\n");
1975 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1976 irq
= platform_get_irq(pdev
, 0);
1977 if (res
== NULL
|| irq
< 0)
1980 res
= request_mem_region(res
->start
, res
->end
- res
->start
+ 1,
1985 ret
= omap_hsmmc_gpio_init(pdata
);
1989 mmc
= mmc_alloc_host(sizeof(struct omap_hsmmc_host
), &pdev
->dev
);
1995 host
= mmc_priv(mmc
);
1997 host
->pdata
= pdata
;
1998 host
->dev
= &pdev
->dev
;
2000 host
->dev
->dma_mask
= &pdata
->dma_mask
;
2003 host
->id
= pdev
->id
;
2005 host
->mapbase
= res
->start
;
2006 host
->base
= ioremap(host
->mapbase
, SZ_4K
);
2007 host
->power_mode
= MMC_POWER_OFF
;
2009 platform_set_drvdata(pdev
, host
);
2010 INIT_WORK(&host
->mmc_carddetect_work
, omap_hsmmc_detect
);
2012 if (mmc_slot(host
).power_saving
)
2013 mmc
->ops
= &omap_hsmmc_ps_ops
;
2015 mmc
->ops
= &omap_hsmmc_ops
;
2018 * If regulator_disable can only put vcc_aux to sleep then there is
2021 if (mmc_slot(host
).vcc_aux_disable_is_sleep
)
2022 mmc_slot(host
).no_off
= 1;
2024 mmc
->f_min
= 400000;
2025 mmc
->f_max
= 52000000;
2027 sema_init(&host
->sem
, 1);
2028 spin_lock_init(&host
->irq_lock
);
2030 host
->iclk
= clk_get(&pdev
->dev
, "ick");
2031 if (IS_ERR(host
->iclk
)) {
2032 ret
= PTR_ERR(host
->iclk
);
2036 host
->fclk
= clk_get(&pdev
->dev
, "fck");
2037 if (IS_ERR(host
->fclk
)) {
2038 ret
= PTR_ERR(host
->fclk
);
2040 clk_put(host
->iclk
);
2044 omap_hsmmc_context_save(host
);
2046 mmc
->caps
|= MMC_CAP_DISABLE
;
2047 mmc_set_disable_delay(mmc
, OMAP_MMC_DISABLED_TIMEOUT
);
2048 /* we start off in DISABLED state */
2049 host
->dpm_state
= DISABLED
;
2051 if (mmc_host_enable(host
->mmc
) != 0) {
2052 clk_put(host
->iclk
);
2053 clk_put(host
->fclk
);
2057 if (clk_enable(host
->iclk
) != 0) {
2058 mmc_host_disable(host
->mmc
);
2059 clk_put(host
->iclk
);
2060 clk_put(host
->fclk
);
2064 if (cpu_is_omap2430()) {
2065 host
->dbclk
= clk_get(&pdev
->dev
, "mmchsdb_fck");
2067 * MMC can still work without debounce clock.
2069 if (IS_ERR(host
->dbclk
))
2070 dev_warn(mmc_dev(host
->mmc
),
2071 "Failed to get debounce clock\n");
2073 host
->got_dbclk
= 1;
2075 if (host
->got_dbclk
)
2076 if (clk_enable(host
->dbclk
) != 0)
2077 dev_dbg(mmc_dev(host
->mmc
), "Enabling debounce"
2081 /* Since we do only SG emulation, we can have as many segs
2083 mmc
->max_phys_segs
= 1024;
2084 mmc
->max_hw_segs
= 1024;
2086 mmc
->max_blk_size
= 512; /* Block Length at max can be 1024 */
2087 mmc
->max_blk_count
= 0xFFFF; /* No. of Blocks is 16 bits */
2088 mmc
->max_req_size
= mmc
->max_blk_size
* mmc
->max_blk_count
;
2089 mmc
->max_seg_size
= mmc
->max_req_size
;
2091 mmc
->caps
|= MMC_CAP_MMC_HIGHSPEED
| MMC_CAP_SD_HIGHSPEED
|
2092 MMC_CAP_WAIT_WHILE_BUSY
;
2094 if (mmc_slot(host
).wires
>= 8)
2095 mmc
->caps
|= MMC_CAP_8_BIT_DATA
;
2096 else if (mmc_slot(host
).wires
>= 4)
2097 mmc
->caps
|= MMC_CAP_4_BIT_DATA
;
2099 if (mmc_slot(host
).nonremovable
)
2100 mmc
->caps
|= MMC_CAP_NONREMOVABLE
;
2102 omap_hsmmc_conf_bus_power(host
);
2104 /* Select DMA lines */
2106 case OMAP_MMC1_DEVID
:
2107 host
->dma_line_tx
= OMAP24XX_DMA_MMC1_TX
;
2108 host
->dma_line_rx
= OMAP24XX_DMA_MMC1_RX
;
2110 case OMAP_MMC2_DEVID
:
2111 host
->dma_line_tx
= OMAP24XX_DMA_MMC2_TX
;
2112 host
->dma_line_rx
= OMAP24XX_DMA_MMC2_RX
;
2114 case OMAP_MMC3_DEVID
:
2115 host
->dma_line_tx
= OMAP34XX_DMA_MMC3_TX
;
2116 host
->dma_line_rx
= OMAP34XX_DMA_MMC3_RX
;
2118 case OMAP_MMC4_DEVID
:
2119 host
->dma_line_tx
= OMAP44XX_DMA_MMC4_TX
;
2120 host
->dma_line_rx
= OMAP44XX_DMA_MMC4_RX
;
2122 case OMAP_MMC5_DEVID
:
2123 host
->dma_line_tx
= OMAP44XX_DMA_MMC5_TX
;
2124 host
->dma_line_rx
= OMAP44XX_DMA_MMC5_RX
;
2127 dev_err(mmc_dev(host
->mmc
), "Invalid MMC id\n");
2131 /* Request IRQ for MMC operations */
2132 ret
= request_irq(host
->irq
, omap_hsmmc_irq
, IRQF_DISABLED
,
2133 mmc_hostname(mmc
), host
);
2135 dev_dbg(mmc_dev(host
->mmc
), "Unable to grab HSMMC IRQ\n");
2139 if (pdata
->init
!= NULL
) {
2140 if (pdata
->init(&pdev
->dev
) != 0) {
2141 dev_dbg(mmc_dev(host
->mmc
),
2142 "Unable to configure MMC IRQs\n");
2143 goto err_irq_cd_init
;
2147 if (omap_hsmmc_have_reg() && !mmc_slot(host
).set_power
) {
2148 ret
= omap_hsmmc_reg_get(host
);
2154 mmc
->ocr_avail
= mmc_slot(host
).ocr_mask
;
2156 /* Request IRQ for card detect */
2157 if ((mmc_slot(host
).card_detect_irq
)) {
2158 ret
= request_irq(mmc_slot(host
).card_detect_irq
,
2159 omap_hsmmc_cd_handler
,
2160 IRQF_TRIGGER_RISING
| IRQF_TRIGGER_FALLING
2162 mmc_hostname(mmc
), host
);
2164 dev_dbg(mmc_dev(host
->mmc
),
2165 "Unable to grab MMC CD IRQ\n");
2170 OMAP_HSMMC_WRITE(host
->base
, ISE
, INT_EN_MASK
);
2171 OMAP_HSMMC_WRITE(host
->base
, IE
, INT_EN_MASK
);
2173 mmc_host_lazy_disable(host
->mmc
);
2175 omap_hsmmc_protect_card(host
);
2179 if (mmc_slot(host
).name
!= NULL
) {
2180 ret
= device_create_file(&mmc
->class_dev
, &dev_attr_slot_name
);
2184 if (mmc_slot(host
).card_detect_irq
&& mmc_slot(host
).get_cover_state
) {
2185 ret
= device_create_file(&mmc
->class_dev
,
2186 &dev_attr_cover_switch
);
2191 omap_hsmmc_debugfs(mmc
);
2196 mmc_remove_host(mmc
);
2197 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2200 omap_hsmmc_reg_put(host
);
2202 if (host
->pdata
->cleanup
)
2203 host
->pdata
->cleanup(&pdev
->dev
);
2205 free_irq(host
->irq
, host
);
2207 mmc_host_disable(host
->mmc
);
2208 clk_disable(host
->iclk
);
2209 clk_put(host
->fclk
);
2210 clk_put(host
->iclk
);
2211 if (host
->got_dbclk
) {
2212 clk_disable(host
->dbclk
);
2213 clk_put(host
->dbclk
);
2216 iounmap(host
->base
);
2217 platform_set_drvdata(pdev
, NULL
);
2220 omap_hsmmc_gpio_free(pdata
);
2222 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
2226 static int omap_hsmmc_remove(struct platform_device
*pdev
)
2228 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2229 struct resource
*res
;
2232 mmc_host_enable(host
->mmc
);
2233 mmc_remove_host(host
->mmc
);
2235 omap_hsmmc_reg_put(host
);
2236 if (host
->pdata
->cleanup
)
2237 host
->pdata
->cleanup(&pdev
->dev
);
2238 free_irq(host
->irq
, host
);
2239 if (mmc_slot(host
).card_detect_irq
)
2240 free_irq(mmc_slot(host
).card_detect_irq
, host
);
2241 flush_scheduled_work();
2243 mmc_host_disable(host
->mmc
);
2244 clk_disable(host
->iclk
);
2245 clk_put(host
->fclk
);
2246 clk_put(host
->iclk
);
2247 if (host
->got_dbclk
) {
2248 clk_disable(host
->dbclk
);
2249 clk_put(host
->dbclk
);
2252 mmc_free_host(host
->mmc
);
2253 iounmap(host
->base
);
2254 omap_hsmmc_gpio_free(pdev
->dev
.platform_data
);
2257 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2259 release_mem_region(res
->start
, res
->end
- res
->start
+ 1);
2260 platform_set_drvdata(pdev
, NULL
);
2266 static int omap_hsmmc_suspend(struct platform_device
*pdev
, pm_message_t state
)
2269 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2271 if (host
&& host
->suspended
)
2275 host
->suspended
= 1;
2276 if (host
->pdata
->suspend
) {
2277 ret
= host
->pdata
->suspend(&pdev
->dev
,
2280 dev_dbg(mmc_dev(host
->mmc
),
2281 "Unable to handle MMC board"
2282 " level suspend\n");
2283 host
->suspended
= 0;
2287 cancel_work_sync(&host
->mmc_carddetect_work
);
2288 mmc_host_enable(host
->mmc
);
2289 ret
= mmc_suspend_host(host
->mmc
, state
);
2291 OMAP_HSMMC_WRITE(host
->base
, ISE
, 0);
2292 OMAP_HSMMC_WRITE(host
->base
, IE
, 0);
2295 OMAP_HSMMC_WRITE(host
->base
, HCTL
,
2296 OMAP_HSMMC_READ(host
->base
, HCTL
) & ~SDBP
);
2297 mmc_host_disable(host
->mmc
);
2298 clk_disable(host
->iclk
);
2299 if (host
->got_dbclk
)
2300 clk_disable(host
->dbclk
);
2302 host
->suspended
= 0;
2303 if (host
->pdata
->resume
) {
2304 ret
= host
->pdata
->resume(&pdev
->dev
,
2307 dev_dbg(mmc_dev(host
->mmc
),
2308 "Unmask interrupt failed\n");
2310 mmc_host_disable(host
->mmc
);
2317 /* Routine to resume the MMC device */
2318 static int omap_hsmmc_resume(struct platform_device
*pdev
)
2321 struct omap_hsmmc_host
*host
= platform_get_drvdata(pdev
);
2323 if (host
&& !host
->suspended
)
2327 ret
= clk_enable(host
->iclk
);
2331 if (mmc_host_enable(host
->mmc
) != 0) {
2332 clk_disable(host
->iclk
);
2336 if (host
->got_dbclk
)
2337 clk_enable(host
->dbclk
);
2339 omap_hsmmc_conf_bus_power(host
);
2341 if (host
->pdata
->resume
) {
2342 ret
= host
->pdata
->resume(&pdev
->dev
, host
->slot_id
);
2344 dev_dbg(mmc_dev(host
->mmc
),
2345 "Unmask interrupt failed\n");
2348 omap_hsmmc_protect_card(host
);
2350 /* Notify the core to resume the host */
2351 ret
= mmc_resume_host(host
->mmc
);
2353 host
->suspended
= 0;
2355 mmc_host_lazy_disable(host
->mmc
);
2361 dev_dbg(mmc_dev(host
->mmc
),
2362 "Failed to enable MMC clocks during resume\n");
2367 #define omap_hsmmc_suspend NULL
2368 #define omap_hsmmc_resume NULL
2371 static struct platform_driver omap_hsmmc_driver
= {
2372 .remove
= omap_hsmmc_remove
,
2373 .suspend
= omap_hsmmc_suspend
,
2374 .resume
= omap_hsmmc_resume
,
2376 .name
= DRIVER_NAME
,
2377 .owner
= THIS_MODULE
,
2381 static int __init
omap_hsmmc_init(void)
2383 /* Register the MMC driver */
2384 return platform_driver_probe(&omap_hsmmc_driver
, omap_hsmmc_probe
);
2387 static void __exit
omap_hsmmc_cleanup(void)
2389 /* Unregister MMC driver */
2390 platform_driver_unregister(&omap_hsmmc_driver
);
2393 module_init(omap_hsmmc_init
);
2394 module_exit(omap_hsmmc_cleanup
);
2396 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2397 MODULE_LICENSE("GPL");
2398 MODULE_ALIAS("platform:" DRIVER_NAME
);
2399 MODULE_AUTHOR("Texas Instruments Inc");