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mmc: Atmel host kconfig cleanup for everyone else
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / mmc / host / davinci_mmc.c
blob3bd0ba294e9de667a56c2abf3915f77d43ad8b1b
1 /*
2 * davinci_mmc.c - TI DaVinci MMC/SD/SDIO driver
3 *
4 * Copyright (C) 2006 Texas Instruments.
5 * Original author: Purushotam Kumar
6 * Copyright (C) 2009 David Brownell
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23 #include <linux/module.h>
24 #include <linux/ioport.h>
25 #include <linux/platform_device.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
28 #include <linux/cpufreq.h>
29 #include <linux/mmc/host.h>
30 #include <linux/io.h>
31 #include <linux/irq.h>
32 #include <linux/delay.h>
33 #include <linux/dma-mapping.h>
34 #include <linux/mmc/mmc.h>
35
36 #include <mach/mmc.h>
37 #include <mach/edma.h>
38
39 /*
40 * Register Definitions
41 */
42 #define DAVINCI_MMCCTL 0x00 /* Control Register */
43 #define DAVINCI_MMCCLK 0x04 /* Memory Clock Control Register */
44 #define DAVINCI_MMCST0 0x08 /* Status Register 0 */
45 #define DAVINCI_MMCST1 0x0C /* Status Register 1 */
46 #define DAVINCI_MMCIM 0x10 /* Interrupt Mask Register */
47 #define DAVINCI_MMCTOR 0x14 /* Response Time-Out Register */
48 #define DAVINCI_MMCTOD 0x18 /* Data Read Time-Out Register */
49 #define DAVINCI_MMCBLEN 0x1C /* Block Length Register */
50 #define DAVINCI_MMCNBLK 0x20 /* Number of Blocks Register */
51 #define DAVINCI_MMCNBLC 0x24 /* Number of Blocks Counter Register */
52 #define DAVINCI_MMCDRR 0x28 /* Data Receive Register */
53 #define DAVINCI_MMCDXR 0x2C /* Data Transmit Register */
54 #define DAVINCI_MMCCMD 0x30 /* Command Register */
55 #define DAVINCI_MMCARGHL 0x34 /* Argument Register */
56 #define DAVINCI_MMCRSP01 0x38 /* Response Register 0 and 1 */
57 #define DAVINCI_MMCRSP23 0x3C /* Response Register 0 and 1 */
58 #define DAVINCI_MMCRSP45 0x40 /* Response Register 0 and 1 */
59 #define DAVINCI_MMCRSP67 0x44 /* Response Register 0 and 1 */
60 #define DAVINCI_MMCDRSP 0x48 /* Data Response Register */
61 #define DAVINCI_MMCETOK 0x4C
62 #define DAVINCI_MMCCIDX 0x50 /* Command Index Register */
63 #define DAVINCI_MMCCKC 0x54
64 #define DAVINCI_MMCTORC 0x58
65 #define DAVINCI_MMCTODC 0x5C
66 #define DAVINCI_MMCBLNC 0x60
67 #define DAVINCI_SDIOCTL 0x64
68 #define DAVINCI_SDIOST0 0x68
69 #define DAVINCI_SDIOEN 0x6C
70 #define DAVINCI_SDIOST 0x70
71 #define DAVINCI_MMCFIFOCTL 0x74 /* FIFO Control Register */
72
73 /* DAVINCI_MMCCTL definitions */
74 #define MMCCTL_DATRST (1 << 0)
75 #define MMCCTL_CMDRST (1 << 1)
76 #define MMCCTL_WIDTH_8_BIT (1 << 8)
77 #define MMCCTL_WIDTH_4_BIT (1 << 2)
78 #define MMCCTL_DATEG_DISABLED (0 << 6)
79 #define MMCCTL_DATEG_RISING (1 << 6)
80 #define MMCCTL_DATEG_FALLING (2 << 6)
81 #define MMCCTL_DATEG_BOTH (3 << 6)
82 #define MMCCTL_PERMDR_LE (0 << 9)
83 #define MMCCTL_PERMDR_BE (1 << 9)
84 #define MMCCTL_PERMDX_LE (0 << 10)
85 #define MMCCTL_PERMDX_BE (1 << 10)
86
87 /* DAVINCI_MMCCLK definitions */
88 #define MMCCLK_CLKEN (1 << 8)
89 #define MMCCLK_CLKRT_MASK (0xFF << 0)
90
91 /* IRQ bit definitions, for DAVINCI_MMCST0 and DAVINCI_MMCIM */
92 #define MMCST0_DATDNE BIT(0) /* data done */
93 #define MMCST0_BSYDNE BIT(1) /* busy done */
94 #define MMCST0_RSPDNE BIT(2) /* command done */
95 #define MMCST0_TOUTRD BIT(3) /* data read timeout */
96 #define MMCST0_TOUTRS BIT(4) /* command response timeout */
97 #define MMCST0_CRCWR BIT(5) /* data write CRC error */
98 #define MMCST0_CRCRD BIT(6) /* data read CRC error */
99 #define MMCST0_CRCRS BIT(7) /* command response CRC error */
100 #define MMCST0_DXRDY BIT(9) /* data transmit ready (fifo empty) */
101 #define MMCST0_DRRDY BIT(10) /* data receive ready (data in fifo)*/
102 #define MMCST0_DATED BIT(11) /* DAT3 edge detect */
103 #define MMCST0_TRNDNE BIT(12) /* transfer done */
104
105 /* DAVINCI_MMCST1 definitions */
106 #define MMCST1_BUSY (1 << 0)
107
108 /* DAVINCI_MMCCMD definitions */
109 #define MMCCMD_CMD_MASK (0x3F << 0)
110 #define MMCCMD_PPLEN (1 << 7)
111 #define MMCCMD_BSYEXP (1 << 8)
112 #define MMCCMD_RSPFMT_MASK (3 << 9)
113 #define MMCCMD_RSPFMT_NONE (0 << 9)
114 #define MMCCMD_RSPFMT_R1456 (1 << 9)
115 #define MMCCMD_RSPFMT_R2 (2 << 9)
116 #define MMCCMD_RSPFMT_R3 (3 << 9)
117 #define MMCCMD_DTRW (1 << 11)
118 #define MMCCMD_STRMTP (1 << 12)
119 #define MMCCMD_WDATX (1 << 13)
120 #define MMCCMD_INITCK (1 << 14)
121 #define MMCCMD_DCLR (1 << 15)
122 #define MMCCMD_DMATRIG (1 << 16)
123
124 /* DAVINCI_MMCFIFOCTL definitions */
125 #define MMCFIFOCTL_FIFORST (1 << 0)
126 #define MMCFIFOCTL_FIFODIR_WR (1 << 1)
127 #define MMCFIFOCTL_FIFODIR_RD (0 << 1)
128 #define MMCFIFOCTL_FIFOLEV (1 << 2) /* 0 = 128 bits, 1 = 256 bits */
129 #define MMCFIFOCTL_ACCWD_4 (0 << 3) /* access width of 4 bytes */
130 #define MMCFIFOCTL_ACCWD_3 (1 << 3) /* access width of 3 bytes */
131 #define MMCFIFOCTL_ACCWD_2 (2 << 3) /* access width of 2 bytes */
132 #define MMCFIFOCTL_ACCWD_1 (3 << 3) /* access width of 1 byte */
133
134
135 /* MMCSD Init clock in Hz in opendrain mode */
136 #define MMCSD_INIT_CLOCK 200000
137
138 /*
139 * One scatterlist dma "segment" is at most MAX_CCNT rw_threshold units,
140 * and we handle up to NR_SG segments. MMC_BLOCK_BOUNCE kicks in only
141 * for drivers with max_hw_segs == 1, making the segments bigger (64KB)
142 * than the page or two that's otherwise typical. NR_SG == 16 gives at
143 * least the same throughput boost, using EDMA transfer linkage instead
144 * of spending CPU time copying pages.
145 */
146 #define MAX_CCNT ((1 << 16) - 1)
147
148 #define NR_SG 16
149
150 static unsigned rw_threshold = 32;
151 module_param(rw_threshold, uint, S_IRUGO);
152 MODULE_PARM_DESC(rw_threshold,
153 "Read/Write threshold. Default = 32");
154
155 static unsigned __initdata use_dma = 1;
156 module_param(use_dma, uint, 0);
157 MODULE_PARM_DESC(use_dma, "Whether to use DMA or not. Default = 1");
158
159 struct mmc_davinci_host {
160 struct mmc_command *cmd;
161 struct mmc_data *data;
162 struct mmc_host *mmc;
163 struct clk *clk;
164 unsigned int mmc_input_clk;
165 void __iomem *base;
166 struct resource *mem_res;
167 int irq;
168 unsigned char bus_mode;
169
170 #define DAVINCI_MMC_DATADIR_NONE 0
171 #define DAVINCI_MMC_DATADIR_READ 1
172 #define DAVINCI_MMC_DATADIR_WRITE 2
173 unsigned char data_dir;
174
175 /* buffer is used during PIO of one scatterlist segment, and
176 * is updated along with buffer_bytes_left. bytes_left applies
177 * to all N blocks of the PIO transfer.
178 */
179 u8 *buffer;
180 u32 buffer_bytes_left;
181 u32 bytes_left;
182
183 u32 rxdma, txdma;
184 bool use_dma;
185 bool do_dma;
186
187 /* Scatterlist DMA uses one or more parameter RAM entries:
188 * the main one (associated with rxdma or txdma) plus zero or
189 * more links. The entries for a given transfer differ only
190 * by memory buffer (address, length) and link field.
191 */
192 struct edmacc_param tx_template;
193 struct edmacc_param rx_template;
194 unsigned n_link;
195 u32 links[NR_SG - 1];
196
197 /* For PIO we walk scatterlists one segment at a time. */
198 unsigned int sg_len;
199 struct scatterlist *sg;
200
201 /* Version of the MMC/SD controller */
202 u8 version;
203 /* for ns in one cycle calculation */
204 unsigned ns_in_one_cycle;
205 #ifdef CONFIG_CPU_FREQ
206 struct notifier_block freq_transition;
207 #endif
208 };
209
210
211 /* PIO only */
212 static void mmc_davinci_sg_to_buf(struct mmc_davinci_host *host)
213 {
214 host->buffer_bytes_left = sg_dma_len(host->sg);
215 host->buffer = sg_virt(host->sg);
216 if (host->buffer_bytes_left > host->bytes_left)
217 host->buffer_bytes_left = host->bytes_left;
218 }
219
220 static void davinci_fifo_data_trans(struct mmc_davinci_host *host,
221 unsigned int n)
222 {
223 u8 *p;
224 unsigned int i;
225
226 if (host->buffer_bytes_left == 0) {
227 host->sg = sg_next(host->data->sg);
228 mmc_davinci_sg_to_buf(host);
229 }
230
231 p = host->buffer;
232 if (n > host->buffer_bytes_left)
233 n = host->buffer_bytes_left;
234 host->buffer_bytes_left -= n;
235 host->bytes_left -= n;
236
237 /* NOTE: we never transfer more than rw_threshold bytes
238 * to/from the fifo here; there's no I/O overlap.
239 * This also assumes that access width( i.e. ACCWD) is 4 bytes
240 */
241 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
242 for (i = 0; i < (n >> 2); i++) {
243 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR);
244 p = p + 4;
245 }
246 if (n & 3) {
247 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3));
248 p = p + (n & 3);
249 }
250 } else {
251 for (i = 0; i < (n >> 2); i++) {
252 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR);
253 p = p + 4;
254 }
255 if (n & 3) {
256 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3));
257 p = p + (n & 3);
258 }
259 }
260 host->buffer = p;
261 }
262
263 static void mmc_davinci_start_command(struct mmc_davinci_host *host,
264 struct mmc_command *cmd)
265 {
266 u32 cmd_reg = 0;
267 u32 im_val;
268
269 dev_dbg(mmc_dev(host->mmc), "CMD%d, arg 0x%08x%s\n",
270 cmd->opcode, cmd->arg,
271 ({ char *s;
272 switch (mmc_resp_type(cmd)) {
273 case MMC_RSP_R1:
274 s = ", R1/R5/R6/R7 response";
275 break;
276 case MMC_RSP_R1B:
277 s = ", R1b response";
278 break;
279 case MMC_RSP_R2:
280 s = ", R2 response";
281 break;
282 case MMC_RSP_R3:
283 s = ", R3/R4 response";
284 break;
285 default:
286 s = ", (R? response)";
287 break;
288 }; s; }));
289 host->cmd = cmd;
290
291 switch (mmc_resp_type(cmd)) {
292 case MMC_RSP_R1B:
293 /* There's some spec confusion about when R1B is
294 * allowed, but if the card doesn't issue a BUSY
295 * then it's harmless for us to allow it.
296 */
297 cmd_reg |= MMCCMD_BSYEXP;
298 /* FALLTHROUGH */
299 case MMC_RSP_R1: /* 48 bits, CRC */
300 cmd_reg |= MMCCMD_RSPFMT_R1456;
301 break;
302 case MMC_RSP_R2: /* 136 bits, CRC */
303 cmd_reg |= MMCCMD_RSPFMT_R2;
304 break;
305 case MMC_RSP_R3: /* 48 bits, no CRC */
306 cmd_reg |= MMCCMD_RSPFMT_R3;
307 break;
308 default:
309 cmd_reg |= MMCCMD_RSPFMT_NONE;
310 dev_dbg(mmc_dev(host->mmc), "unknown resp_type %04x\n",
311 mmc_resp_type(cmd));
312 break;
313 }
314
315 /* Set command index */
316 cmd_reg |= cmd->opcode;
317
318 /* Enable EDMA transfer triggers */
319 if (host->do_dma)
320 cmd_reg |= MMCCMD_DMATRIG;
321
322 if (host->version == MMC_CTLR_VERSION_2 && host->data != NULL &&
323 host->data_dir == DAVINCI_MMC_DATADIR_READ)
324 cmd_reg |= MMCCMD_DMATRIG;
325
326 /* Setting whether command involves data transfer or not */
327 if (cmd->data)
328 cmd_reg |= MMCCMD_WDATX;
329
330 /* Setting whether stream or block transfer */
331 if (cmd->flags & MMC_DATA_STREAM)
332 cmd_reg |= MMCCMD_STRMTP;
333
334 /* Setting whether data read or write */
335 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
336 cmd_reg |= MMCCMD_DTRW;
337
338 if (host->bus_mode == MMC_BUSMODE_PUSHPULL)
339 cmd_reg |= MMCCMD_PPLEN;
340
341 /* set Command timeout */
342 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
343
344 /* Enable interrupt (calculate here, defer until FIFO is stuffed). */
345 im_val = MMCST0_RSPDNE | MMCST0_CRCRS | MMCST0_TOUTRS;
346 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
347 im_val |= MMCST0_DATDNE | MMCST0_CRCWR;
348
349 if (!host->do_dma)
350 im_val |= MMCST0_DXRDY;
351 } else if (host->data_dir == DAVINCI_MMC_DATADIR_READ) {
352 im_val |= MMCST0_DATDNE | MMCST0_CRCRD | MMCST0_TOUTRD;
353
354 if (!host->do_dma)
355 im_val |= MMCST0_DRRDY;
356 }
357
358 /*
359 * Before non-DMA WRITE commands the controller needs priming:
360 * FIFO should be populated with 32 bytes i.e. whatever is the FIFO size
361 */
362 if (!host->do_dma && (host->data_dir == DAVINCI_MMC_DATADIR_WRITE))
363 davinci_fifo_data_trans(host, rw_threshold);
364
365 writel(cmd->arg, host->base + DAVINCI_MMCARGHL);
366 writel(cmd_reg, host->base + DAVINCI_MMCCMD);
367 writel(im_val, host->base + DAVINCI_MMCIM);
368 }
369
370 /*----------------------------------------------------------------------*/
371
372 /* DMA infrastructure */
373
374 static void davinci_abort_dma(struct mmc_davinci_host *host)
375 {
376 int sync_dev;
377
378 if (host->data_dir == DAVINCI_MMC_DATADIR_READ)
379 sync_dev = host->rxdma;
380 else
381 sync_dev = host->txdma;
382
383 edma_stop(sync_dev);
384 edma_clean_channel(sync_dev);
385 }
386
387 static void
388 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data);
389
390 static void mmc_davinci_dma_cb(unsigned channel, u16 ch_status, void *data)
391 {
392 if (DMA_COMPLETE != ch_status) {
393 struct mmc_davinci_host *host = data;
394
395 /* Currently means: DMA Event Missed, or "null" transfer
396 * request was seen. In the future, TC errors (like bad
397 * addresses) might be presented too.
398 */
399 dev_warn(mmc_dev(host->mmc), "DMA %s error\n",
400 (host->data->flags & MMC_DATA_WRITE)
401 ? "write" : "read");
402 host->data->error = -EIO;
403 mmc_davinci_xfer_done(host, host->data);
404 }
405 }
406
407 /* Set up tx or rx template, to be modified and updated later */
408 static void __init mmc_davinci_dma_setup(struct mmc_davinci_host *host,
409 bool tx, struct edmacc_param *template)
410 {
411 unsigned sync_dev;
412 const u16 acnt = 4;
413 const u16 bcnt = rw_threshold >> 2;
414 const u16 ccnt = 0;
415 u32 src_port = 0;
416 u32 dst_port = 0;
417 s16 src_bidx, dst_bidx;
418 s16 src_cidx, dst_cidx;
419
420 /*
421 * A-B Sync transfer: each DMA request is for one "frame" of
422 * rw_threshold bytes, broken into "acnt"-size chunks repeated
423 * "bcnt" times. Each segment needs "ccnt" such frames; since
424 * we tell the block layer our mmc->max_seg_size limit, we can
425 * trust (later) that it's within bounds.
426 *
427 * The FIFOs are read/written in 4-byte chunks (acnt == 4) and
428 * EDMA will optimize memory operations to use larger bursts.
429 */
430 if (tx) {
431 sync_dev = host->txdma;
432
433 /* src_prt, ccnt, and link to be set up later */
434 src_bidx = acnt;
435 src_cidx = acnt * bcnt;
436
437 dst_port = host->mem_res->start + DAVINCI_MMCDXR;
438 dst_bidx = 0;
439 dst_cidx = 0;
440 } else {
441 sync_dev = host->rxdma;
442
443 src_port = host->mem_res->start + DAVINCI_MMCDRR;
444 src_bidx = 0;
445 src_cidx = 0;
446
447 /* dst_prt, ccnt, and link to be set up later */
448 dst_bidx = acnt;
449 dst_cidx = acnt * bcnt;
450 }
451
452 /*
453 * We can't use FIFO mode for the FIFOs because MMC FIFO addresses
454 * are not 256-bit (32-byte) aligned. So we use INCR, and the W8BIT
455 * parameter is ignored.
456 */
457 edma_set_src(sync_dev, src_port, INCR, W8BIT);
458 edma_set_dest(sync_dev, dst_port, INCR, W8BIT);
459
460 edma_set_src_index(sync_dev, src_bidx, src_cidx);
461 edma_set_dest_index(sync_dev, dst_bidx, dst_cidx);
462
463 edma_set_transfer_params(sync_dev, acnt, bcnt, ccnt, 8, ABSYNC);
464
465 edma_read_slot(sync_dev, template);
466
467 /* don't bother with irqs or chaining */
468 template->opt |= EDMA_CHAN_SLOT(sync_dev) << 12;
469 }
470
471 static void mmc_davinci_send_dma_request(struct mmc_davinci_host *host,
472 struct mmc_data *data)
473 {
474 struct edmacc_param *template;
475 int channel, slot;
476 unsigned link;
477 struct scatterlist *sg;
478 unsigned sg_len;
479 unsigned bytes_left = host->bytes_left;
480 const unsigned shift = ffs(rw_threshold) - 1;;
481
482 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE) {
483 template = &host->tx_template;
484 channel = host->txdma;
485 } else {
486 template = &host->rx_template;
487 channel = host->rxdma;
488 }
489
490 /* We know sg_len and ccnt will never be out of range because
491 * we told the mmc layer which in turn tells the block layer
492 * to ensure that it only hands us one scatterlist segment
493 * per EDMA PARAM entry. Update the PARAM
494 * entries needed for each segment of this scatterlist.
495 */
496 for (slot = channel, link = 0, sg = data->sg, sg_len = host->sg_len;
497 sg_len-- != 0 && bytes_left;
498 sg = sg_next(sg), slot = host->links[link++]) {
499 u32 buf = sg_dma_address(sg);
500 unsigned count = sg_dma_len(sg);
501
502 template->link_bcntrld = sg_len
503 ? (EDMA_CHAN_SLOT(host->links[link]) << 5)
504 : 0xffff;
505
506 if (count > bytes_left)
507 count = bytes_left;
508 bytes_left -= count;
509
510 if (host->data_dir == DAVINCI_MMC_DATADIR_WRITE)
511 template->src = buf;
512 else
513 template->dst = buf;
514 template->ccnt = count >> shift;
515
516 edma_write_slot(slot, template);
517 }
518
519 if (host->version == MMC_CTLR_VERSION_2)
520 edma_clear_event(channel);
521
522 edma_start(channel);
523 }
524
525 static int mmc_davinci_start_dma_transfer(struct mmc_davinci_host *host,
526 struct mmc_data *data)
527 {
528 int i;
529 int mask = rw_threshold - 1;
530
531 host->sg_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
532 ((data->flags & MMC_DATA_WRITE)
533 ? DMA_TO_DEVICE
534 : DMA_FROM_DEVICE));
535
536 /* no individual DMA segment should need a partial FIFO */
537 for (i = 0; i < host->sg_len; i++) {
538 if (sg_dma_len(data->sg + i) & mask) {
539 dma_unmap_sg(mmc_dev(host->mmc),
540 data->sg, data->sg_len,
541 (data->flags & MMC_DATA_WRITE)
542 ? DMA_TO_DEVICE
543 : DMA_FROM_DEVICE);
544 return -1;
545 }
546 }
547
548 host->do_dma = 1;
549 mmc_davinci_send_dma_request(host, data);
550
551 return 0;
552 }
553
554 static void __init_or_module
555 davinci_release_dma_channels(struct mmc_davinci_host *host)
556 {
557 unsigned i;
558
559 if (!host->use_dma)
560 return;
561
562 for (i = 0; i < host->n_link; i++)
563 edma_free_slot(host->links[i]);
564
565 edma_free_channel(host->txdma);
566 edma_free_channel(host->rxdma);
567 }
568
569 static int __init davinci_acquire_dma_channels(struct mmc_davinci_host *host)
570 {
571 int r, i;
572
573 /* Acquire master DMA write channel */
574 r = edma_alloc_channel(host->txdma, mmc_davinci_dma_cb, host,
575 EVENTQ_DEFAULT);
576 if (r < 0) {
577 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
578 "tx", r);
579 return r;
580 }
581 mmc_davinci_dma_setup(host, true, &host->tx_template);
582
583 /* Acquire master DMA read channel */
584 r = edma_alloc_channel(host->rxdma, mmc_davinci_dma_cb, host,
585 EVENTQ_DEFAULT);
586 if (r < 0) {
587 dev_warn(mmc_dev(host->mmc), "alloc %s channel err %d\n",
588 "rx", r);
589 goto free_master_write;
590 }
591 mmc_davinci_dma_setup(host, false, &host->rx_template);
592
593 /* Allocate parameter RAM slots, which will later be bound to a
594 * channel as needed to handle a scatterlist.
595 */
596 for (i = 0; i < ARRAY_SIZE(host->links); i++) {
597 r = edma_alloc_slot(EDMA_CTLR(host->txdma), EDMA_SLOT_ANY);
598 if (r < 0) {
599 dev_dbg(mmc_dev(host->mmc), "dma PaRAM alloc --> %d\n",
600 r);
601 break;
602 }
603 host->links[i] = r;
604 }
605 host->n_link = i;
606
607 return 0;
608
609 free_master_write:
610 edma_free_channel(host->txdma);
611
612 return r;
613 }
614
615 /*----------------------------------------------------------------------*/
616
617 static void
618 mmc_davinci_prepare_data(struct mmc_davinci_host *host, struct mmc_request *req)
619 {
620 int fifo_lev = (rw_threshold == 32) ? MMCFIFOCTL_FIFOLEV : 0;
621 int timeout;
622 struct mmc_data *data = req->data;
623
624 if (host->version == MMC_CTLR_VERSION_2)
625 fifo_lev = (rw_threshold == 64) ? MMCFIFOCTL_FIFOLEV : 0;
626
627 host->data = data;
628 if (data == NULL) {
629 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
630 writel(0, host->base + DAVINCI_MMCBLEN);
631 writel(0, host->base + DAVINCI_MMCNBLK);
632 return;
633 }
634
635 dev_dbg(mmc_dev(host->mmc), "%s %s, %d blocks of %d bytes\n",
636 (data->flags & MMC_DATA_STREAM) ? "stream" : "block",
637 (data->flags & MMC_DATA_WRITE) ? "write" : "read",
638 data->blocks, data->blksz);
639 dev_dbg(mmc_dev(host->mmc), " DTO %d cycles + %d ns\n",
640 data->timeout_clks, data->timeout_ns);
641 timeout = data->timeout_clks +
642 (data->timeout_ns / host->ns_in_one_cycle);
643 if (timeout > 0xffff)
644 timeout = 0xffff;
645
646 writel(timeout, host->base + DAVINCI_MMCTOD);
647 writel(data->blocks, host->base + DAVINCI_MMCNBLK);
648 writel(data->blksz, host->base + DAVINCI_MMCBLEN);
649
650 /* Configure the FIFO */
651 switch (data->flags & MMC_DATA_WRITE) {
652 case MMC_DATA_WRITE:
653 host->data_dir = DAVINCI_MMC_DATADIR_WRITE;
654 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR | MMCFIFOCTL_FIFORST,
655 host->base + DAVINCI_MMCFIFOCTL);
656 writel(fifo_lev | MMCFIFOCTL_FIFODIR_WR,
657 host->base + DAVINCI_MMCFIFOCTL);
658 break;
659
660 default:
661 host->data_dir = DAVINCI_MMC_DATADIR_READ;
662 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD | MMCFIFOCTL_FIFORST,
663 host->base + DAVINCI_MMCFIFOCTL);
664 writel(fifo_lev | MMCFIFOCTL_FIFODIR_RD,
665 host->base + DAVINCI_MMCFIFOCTL);
666 break;
667 }
668
669 host->buffer = NULL;
670 host->bytes_left = data->blocks * data->blksz;
671
672 /* For now we try to use DMA whenever we won't need partial FIFO
673 * reads or writes, either for the whole transfer (as tested here)
674 * or for any individual scatterlist segment (tested when we call
675 * start_dma_transfer).
676 *
677 * While we *could* change that, unusual block sizes are rarely
678 * used. The occasional fallback to PIO should't hurt.
679 */
680 if (host->use_dma && (host->bytes_left & (rw_threshold - 1)) == 0
681 && mmc_davinci_start_dma_transfer(host, data) == 0) {
682 /* zero this to ensure we take no PIO paths */
683 host->bytes_left = 0;
684 } else {
685 /* Revert to CPU Copy */
686 host->sg_len = data->sg_len;
687 host->sg = host->data->sg;
688 mmc_davinci_sg_to_buf(host);
689 }
690 }
691
692 static void mmc_davinci_request(struct mmc_host *mmc, struct mmc_request *req)
693 {
694 struct mmc_davinci_host *host = mmc_priv(mmc);
695 unsigned long timeout = jiffies + msecs_to_jiffies(900);
696 u32 mmcst1 = 0;
697
698 /* Card may still be sending BUSY after a previous operation,
699 * typically some kind of write. If so, we can't proceed yet.
700 */
701 while (time_before(jiffies, timeout)) {
702 mmcst1 = readl(host->base + DAVINCI_MMCST1);
703 if (!(mmcst1 & MMCST1_BUSY))
704 break;
705 cpu_relax();
706 }
707 if (mmcst1 & MMCST1_BUSY) {
708 dev_err(mmc_dev(host->mmc), "still BUSY? bad ... \n");
709 req->cmd->error = -ETIMEDOUT;
710 mmc_request_done(mmc, req);
711 return;
712 }
713
714 host->do_dma = 0;
715 mmc_davinci_prepare_data(host, req);
716 mmc_davinci_start_command(host, req->cmd);
717 }
718
719 static unsigned int calculate_freq_for_card(struct mmc_davinci_host *host,
720 unsigned int mmc_req_freq)
721 {
722 unsigned int mmc_freq = 0, mmc_pclk = 0, mmc_push_pull_divisor = 0;
723
724 mmc_pclk = host->mmc_input_clk;
725 if (mmc_req_freq && mmc_pclk > (2 * mmc_req_freq))
726 mmc_push_pull_divisor = ((unsigned int)mmc_pclk
727 / (2 * mmc_req_freq)) - 1;
728 else
729 mmc_push_pull_divisor = 0;
730
731 mmc_freq = (unsigned int)mmc_pclk
732 / (2 * (mmc_push_pull_divisor + 1));
733
734 if (mmc_freq > mmc_req_freq)
735 mmc_push_pull_divisor = mmc_push_pull_divisor + 1;
736 /* Convert ns to clock cycles */
737 if (mmc_req_freq <= 400000)
738 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
739 / (2 * (mmc_push_pull_divisor + 1)))/1000));
740 else
741 host->ns_in_one_cycle = (1000000) / (((mmc_pclk
742 / (2 * (mmc_push_pull_divisor + 1)))/1000000));
743
744 return mmc_push_pull_divisor;
745 }
746
747 static void calculate_clk_divider(struct mmc_host *mmc, struct mmc_ios *ios)
748 {
749 unsigned int open_drain_freq = 0, mmc_pclk = 0;
750 unsigned int mmc_push_pull_freq = 0;
751 struct mmc_davinci_host *host = mmc_priv(mmc);
752
753 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
754 u32 temp;
755
756 /* Ignoring the init clock value passed for fixing the inter
757 * operability with different cards.
758 */
759 open_drain_freq = ((unsigned int)mmc_pclk
760 / (2 * MMCSD_INIT_CLOCK)) - 1;
761
762 if (open_drain_freq > 0xFF)
763 open_drain_freq = 0xFF;
764
765 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
766 temp |= open_drain_freq;
767 writel(temp, host->base + DAVINCI_MMCCLK);
768
769 /* Convert ns to clock cycles */
770 host->ns_in_one_cycle = (1000000) / (MMCSD_INIT_CLOCK/1000);
771 } else {
772 u32 temp;
773 mmc_push_pull_freq = calculate_freq_for_card(host, ios->clock);
774
775 if (mmc_push_pull_freq > 0xFF)
776 mmc_push_pull_freq = 0xFF;
777
778 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKEN;
779 writel(temp, host->base + DAVINCI_MMCCLK);
780
781 udelay(10);
782
783 temp = readl(host->base + DAVINCI_MMCCLK) & ~MMCCLK_CLKRT_MASK;
784 temp |= mmc_push_pull_freq;
785 writel(temp, host->base + DAVINCI_MMCCLK);
786
787 writel(temp | MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
788
789 udelay(10);
790 }
791 }
792
793 static void mmc_davinci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
794 {
795 struct mmc_davinci_host *host = mmc_priv(mmc);
796
797 dev_dbg(mmc_dev(host->mmc),
798 "clock %dHz busmode %d powermode %d Vdd %04x\n",
799 ios->clock, ios->bus_mode, ios->power_mode,
800 ios->vdd);
801
802 switch (ios->bus_width) {
803 case MMC_BUS_WIDTH_8:
804 dev_dbg(mmc_dev(host->mmc), "Enabling 8 bit mode\n");
805 writel((readl(host->base + DAVINCI_MMCCTL) &
806 ~MMCCTL_WIDTH_4_BIT) | MMCCTL_WIDTH_8_BIT,
807 host->base + DAVINCI_MMCCTL);
808 break;
809 case MMC_BUS_WIDTH_4:
810 dev_dbg(mmc_dev(host->mmc), "Enabling 4 bit mode\n");
811 if (host->version == MMC_CTLR_VERSION_2)
812 writel((readl(host->base + DAVINCI_MMCCTL) &
813 ~MMCCTL_WIDTH_8_BIT) | MMCCTL_WIDTH_4_BIT,
814 host->base + DAVINCI_MMCCTL);
815 else
816 writel(readl(host->base + DAVINCI_MMCCTL) |
817 MMCCTL_WIDTH_4_BIT,
818 host->base + DAVINCI_MMCCTL);
819 break;
820 case MMC_BUS_WIDTH_1:
821 dev_dbg(mmc_dev(host->mmc), "Enabling 1 bit mode\n");
822 if (host->version == MMC_CTLR_VERSION_2)
823 writel(readl(host->base + DAVINCI_MMCCTL) &
824 ~(MMCCTL_WIDTH_8_BIT | MMCCTL_WIDTH_4_BIT),
825 host->base + DAVINCI_MMCCTL);
826 else
827 writel(readl(host->base + DAVINCI_MMCCTL) &
828 ~MMCCTL_WIDTH_4_BIT,
829 host->base + DAVINCI_MMCCTL);
830 break;
831 }
832
833 calculate_clk_divider(mmc, ios);
834
835 host->bus_mode = ios->bus_mode;
836 if (ios->power_mode == MMC_POWER_UP) {
837 unsigned long timeout = jiffies + msecs_to_jiffies(50);
838 bool lose = true;
839
840 /* Send clock cycles, poll completion */
841 writel(0, host->base + DAVINCI_MMCARGHL);
842 writel(MMCCMD_INITCK, host->base + DAVINCI_MMCCMD);
843 while (time_before(jiffies, timeout)) {
844 u32 tmp = readl(host->base + DAVINCI_MMCST0);
845
846 if (tmp & MMCST0_RSPDNE) {
847 lose = false;
848 break;
849 }
850 cpu_relax();
851 }
852 if (lose)
853 dev_warn(mmc_dev(host->mmc), "powerup timeout\n");
854 }
855
856 /* FIXME on power OFF, reset things ... */
857 }
858
859 static void
860 mmc_davinci_xfer_done(struct mmc_davinci_host *host, struct mmc_data *data)
861 {
862 host->data = NULL;
863
864 if (host->do_dma) {
865 davinci_abort_dma(host);
866
867 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
868 (data->flags & MMC_DATA_WRITE)
869 ? DMA_TO_DEVICE
870 : DMA_FROM_DEVICE);
871 host->do_dma = false;
872 }
873 host->data_dir = DAVINCI_MMC_DATADIR_NONE;
874
875 if (!data->stop || (host->cmd && host->cmd->error)) {
876 mmc_request_done(host->mmc, data->mrq);
877 writel(0, host->base + DAVINCI_MMCIM);
878 } else
879 mmc_davinci_start_command(host, data->stop);
880 }
881
882 static void mmc_davinci_cmd_done(struct mmc_davinci_host *host,
883 struct mmc_command *cmd)
884 {
885 host->cmd = NULL;
886
887 if (cmd->flags & MMC_RSP_PRESENT) {
888 if (cmd->flags & MMC_RSP_136) {
889 /* response type 2 */
890 cmd->resp[3] = readl(host->base + DAVINCI_MMCRSP01);
891 cmd->resp[2] = readl(host->base + DAVINCI_MMCRSP23);
892 cmd->resp[1] = readl(host->base + DAVINCI_MMCRSP45);
893 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
894 } else {
895 /* response types 1, 1b, 3, 4, 5, 6 */
896 cmd->resp[0] = readl(host->base + DAVINCI_MMCRSP67);
897 }
898 }
899
900 if (host->data == NULL || cmd->error) {
901 if (cmd->error == -ETIMEDOUT)
902 cmd->mrq->cmd->retries = 0;
903 mmc_request_done(host->mmc, cmd->mrq);
904 writel(0, host->base + DAVINCI_MMCIM);
905 }
906 }
907
908 static void
909 davinci_abort_data(struct mmc_davinci_host *host, struct mmc_data *data)
910 {
911 u32 temp;
912
913 /* reset command and data state machines */
914 temp = readl(host->base + DAVINCI_MMCCTL);
915 writel(temp | MMCCTL_CMDRST | MMCCTL_DATRST,
916 host->base + DAVINCI_MMCCTL);
917
918 temp &= ~(MMCCTL_CMDRST | MMCCTL_DATRST);
919 udelay(10);
920 writel(temp, host->base + DAVINCI_MMCCTL);
921 }
922
923 static irqreturn_t mmc_davinci_irq(int irq, void *dev_id)
924 {
925 struct mmc_davinci_host *host = (struct mmc_davinci_host *)dev_id;
926 unsigned int status, qstatus;
927 int end_command = 0;
928 int end_transfer = 0;
929 struct mmc_data *data = host->data;
930
931 if (host->cmd == NULL && host->data == NULL) {
932 status = readl(host->base + DAVINCI_MMCST0);
933 dev_dbg(mmc_dev(host->mmc),
934 "Spurious interrupt 0x%04x\n", status);
935 /* Disable the interrupt from mmcsd */
936 writel(0, host->base + DAVINCI_MMCIM);
937 return IRQ_NONE;
938 }
939
940 status = readl(host->base + DAVINCI_MMCST0);
941 qstatus = status;
942
943 /* handle FIFO first when using PIO for data.
944 * bytes_left will decrease to zero as I/O progress and status will
945 * read zero over iteration because this controller status
946 * register(MMCST0) reports any status only once and it is cleared
947 * by read. So, it is not unbouned loop even in the case of
948 * non-dma.
949 */
950 while (host->bytes_left && (status & (MMCST0_DXRDY | MMCST0_DRRDY))) {
951 davinci_fifo_data_trans(host, rw_threshold);
952 status = readl(host->base + DAVINCI_MMCST0);
953 if (!status)
954 break;
955 qstatus |= status;
956 }
957
958 if (qstatus & MMCST0_DATDNE) {
959 /* All blocks sent/received, and CRC checks passed */
960 if (data != NULL) {
961 if ((host->do_dma == 0) && (host->bytes_left > 0)) {
962 /* if datasize < rw_threshold
963 * no RX ints are generated
964 */
965 davinci_fifo_data_trans(host, host->bytes_left);
966 }
967 end_transfer = 1;
968 data->bytes_xfered = data->blocks * data->blksz;
969 } else {
970 dev_err(mmc_dev(host->mmc),
971 "DATDNE with no host->data\n");
972 }
973 }
974
975 if (qstatus & MMCST0_TOUTRD) {
976 /* Read data timeout */
977 data->error = -ETIMEDOUT;
978 end_transfer = 1;
979
980 dev_dbg(mmc_dev(host->mmc),
981 "read data timeout, status %x\n",
982 qstatus);
983
984 davinci_abort_data(host, data);
985 }
986
987 if (qstatus & (MMCST0_CRCWR | MMCST0_CRCRD)) {
988 /* Data CRC error */
989 data->error = -EILSEQ;
990 end_transfer = 1;
991
992 /* NOTE: this controller uses CRCWR to report both CRC
993 * errors and timeouts (on writes). MMCDRSP values are
994 * only weakly documented, but 0x9f was clearly a timeout
995 * case and the two three-bit patterns in various SD specs
996 * (101, 010) aren't part of it ...
997 */
998 if (qstatus & MMCST0_CRCWR) {
999 u32 temp = readb(host->base + DAVINCI_MMCDRSP);
1000
1001 if (temp == 0x9f)
1002 data->error = -ETIMEDOUT;
1003 }
1004 dev_dbg(mmc_dev(host->mmc), "data %s %s error\n",
1005 (qstatus & MMCST0_CRCWR) ? "write" : "read",
1006 (data->error == -ETIMEDOUT) ? "timeout" : "CRC");
1007
1008 davinci_abort_data(host, data);
1009 }
1010
1011 if (qstatus & MMCST0_TOUTRS) {
1012 /* Command timeout */
1013 if (host->cmd) {
1014 dev_dbg(mmc_dev(host->mmc),
1015 "CMD%d timeout, status %x\n",
1016 host->cmd->opcode, qstatus);
1017 host->cmd->error = -ETIMEDOUT;
1018 if (data) {
1019 end_transfer = 1;
1020 davinci_abort_data(host, data);
1021 } else
1022 end_command = 1;
1023 }
1024 }
1025
1026 if (qstatus & MMCST0_CRCRS) {
1027 /* Command CRC error */
1028 dev_dbg(mmc_dev(host->mmc), "Command CRC error\n");
1029 if (host->cmd) {
1030 host->cmd->error = -EILSEQ;
1031 end_command = 1;
1032 }
1033 }
1034
1035 if (qstatus & MMCST0_RSPDNE) {
1036 /* End of command phase */
1037 end_command = (int) host->cmd;
1038 }
1039
1040 if (end_command)
1041 mmc_davinci_cmd_done(host, host->cmd);
1042 if (end_transfer)
1043 mmc_davinci_xfer_done(host, data);
1044 return IRQ_HANDLED;
1045 }
1046
1047 static int mmc_davinci_get_cd(struct mmc_host *mmc)
1048 {
1049 struct platform_device *pdev = to_platform_device(mmc->parent);
1050 struct davinci_mmc_config *config = pdev->dev.platform_data;
1051
1052 if (!config || !config->get_cd)
1053 return -ENOSYS;
1054 return config->get_cd(pdev->id);
1055 }
1056
1057 static int mmc_davinci_get_ro(struct mmc_host *mmc)
1058 {
1059 struct platform_device *pdev = to_platform_device(mmc->parent);
1060 struct davinci_mmc_config *config = pdev->dev.platform_data;
1061
1062 if (!config || !config->get_ro)
1063 return -ENOSYS;
1064 return config->get_ro(pdev->id);
1065 }
1066
1067 static struct mmc_host_ops mmc_davinci_ops = {
1068 .request = mmc_davinci_request,
1069 .set_ios = mmc_davinci_set_ios,
1070 .get_cd = mmc_davinci_get_cd,
1071 .get_ro = mmc_davinci_get_ro,
1072 };
1073
1074 /*----------------------------------------------------------------------*/
1075
1076 #ifdef CONFIG_CPU_FREQ
1077 static int mmc_davinci_cpufreq_transition(struct notifier_block *nb,
1078 unsigned long val, void *data)
1079 {
1080 struct mmc_davinci_host *host;
1081 unsigned int mmc_pclk;
1082 struct mmc_host *mmc;
1083 unsigned long flags;
1084
1085 host = container_of(nb, struct mmc_davinci_host, freq_transition);
1086 mmc = host->mmc;
1087 mmc_pclk = clk_get_rate(host->clk);
1088
1089 if (val == CPUFREQ_POSTCHANGE) {
1090 spin_lock_irqsave(&mmc->lock, flags);
1091 host->mmc_input_clk = mmc_pclk;
1092 calculate_clk_divider(mmc, &mmc->ios);
1093 spin_unlock_irqrestore(&mmc->lock, flags);
1094 }
1095
1096 return 0;
1097 }
1098
1099 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1100 {
1101 host->freq_transition.notifier_call = mmc_davinci_cpufreq_transition;
1102
1103 return cpufreq_register_notifier(&host->freq_transition,
1104 CPUFREQ_TRANSITION_NOTIFIER);
1105 }
1106
1107 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1108 {
1109 cpufreq_unregister_notifier(&host->freq_transition,
1110 CPUFREQ_TRANSITION_NOTIFIER);
1111 }
1112 #else
1113 static inline int mmc_davinci_cpufreq_register(struct mmc_davinci_host *host)
1114 {
1115 return 0;
1116 }
1117
1118 static inline void mmc_davinci_cpufreq_deregister(struct mmc_davinci_host *host)
1119 {
1120 }
1121 #endif
1122 static void __init init_mmcsd_host(struct mmc_davinci_host *host)
1123 {
1124 /* DAT line portion is diabled and in reset state */
1125 writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_DATRST,
1126 host->base + DAVINCI_MMCCTL);
1127
1128 /* CMD line portion is diabled and in reset state */
1129 writel(readl(host->base + DAVINCI_MMCCTL) | MMCCTL_CMDRST,
1130 host->base + DAVINCI_MMCCTL);
1131
1132 udelay(10);
1133
1134 writel(0, host->base + DAVINCI_MMCCLK);
1135 writel(MMCCLK_CLKEN, host->base + DAVINCI_MMCCLK);
1136
1137 writel(0x1FFF, host->base + DAVINCI_MMCTOR);
1138 writel(0xFFFF, host->base + DAVINCI_MMCTOD);
1139
1140 writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_DATRST,
1141 host->base + DAVINCI_MMCCTL);
1142 writel(readl(host->base + DAVINCI_MMCCTL) & ~MMCCTL_CMDRST,
1143 host->base + DAVINCI_MMCCTL);
1144
1145 udelay(10);
1146 }
1147
1148 static int __init davinci_mmcsd_probe(struct platform_device *pdev)
1149 {
1150 struct davinci_mmc_config *pdata = pdev->dev.platform_data;
1151 struct mmc_davinci_host *host = NULL;
1152 struct mmc_host *mmc = NULL;
1153 struct resource *r, *mem = NULL;
1154 int ret = 0, irq = 0;
1155 size_t mem_size;
1156
1157 /* REVISIT: when we're fully converted, fail if pdata is NULL */
1158
1159 ret = -ENODEV;
1160 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1161 irq = platform_get_irq(pdev, 0);
1162 if (!r || irq == NO_IRQ)
1163 goto out;
1164
1165 ret = -EBUSY;
1166 mem_size = resource_size(r);
1167 mem = request_mem_region(r->start, mem_size, pdev->name);
1168 if (!mem)
1169 goto out;
1170
1171 ret = -ENOMEM;
1172 mmc = mmc_alloc_host(sizeof(struct mmc_davinci_host), &pdev->dev);
1173 if (!mmc)
1174 goto out;
1175
1176 host = mmc_priv(mmc);
1177 host->mmc = mmc; /* Important */
1178
1179 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1180 if (!r)
1181 goto out;
1182 host->rxdma = r->start;
1183
1184 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
1185 if (!r)
1186 goto out;
1187 host->txdma = r->start;
1188
1189 host->mem_res = mem;
1190 host->base = ioremap(mem->start, mem_size);
1191 if (!host->base)
1192 goto out;
1193
1194 ret = -ENXIO;
1195 host->clk = clk_get(&pdev->dev, "MMCSDCLK");
1196 if (IS_ERR(host->clk)) {
1197 ret = PTR_ERR(host->clk);
1198 goto out;
1199 }
1200 clk_enable(host->clk);
1201 host->mmc_input_clk = clk_get_rate(host->clk);
1202
1203 init_mmcsd_host(host);
1204
1205 host->use_dma = use_dma;
1206 host->irq = irq;
1207
1208 if (host->use_dma && davinci_acquire_dma_channels(host) != 0)
1209 host->use_dma = 0;
1210
1211 /* REVISIT: someday, support IRQ-driven card detection. */
1212 mmc->caps |= MMC_CAP_NEEDS_POLL;
1213 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1214
1215 if (pdata && (pdata->wires == 4 || pdata->wires == 0))
1216 mmc->caps |= MMC_CAP_4_BIT_DATA;
1217
1218 if (pdata && (pdata->wires == 8))
1219 mmc->caps |= (MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA);
1220
1221 host->version = pdata->version;
1222
1223 mmc->ops = &mmc_davinci_ops;
1224 mmc->f_min = 312500;
1225 mmc->f_max = 25000000;
1226 if (pdata && pdata->max_freq)
1227 mmc->f_max = pdata->max_freq;
1228 if (pdata && pdata->caps)
1229 mmc->caps |= pdata->caps;
1230 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1231
1232 /* With no iommu coalescing pages, each phys_seg is a hw_seg.
1233 * Each hw_seg uses one EDMA parameter RAM slot, always one
1234 * channel and then usually some linked slots.
1235 */
1236 mmc->max_hw_segs = 1 + host->n_link;
1237 mmc->max_phys_segs = mmc->max_hw_segs;
1238
1239 /* EDMA limit per hw segment (one or two MBytes) */
1240 mmc->max_seg_size = MAX_CCNT * rw_threshold;
1241
1242 /* MMC/SD controller limits for multiblock requests */
1243 mmc->max_blk_size = 4095; /* BLEN is 12 bits */
1244 mmc->max_blk_count = 65535; /* NBLK is 16 bits */
1245 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1246
1247 dev_dbg(mmc_dev(host->mmc), "max_phys_segs=%d\n", mmc->max_phys_segs);
1248 dev_dbg(mmc_dev(host->mmc), "max_hw_segs=%d\n", mmc->max_hw_segs);
1249 dev_dbg(mmc_dev(host->mmc), "max_blk_size=%d\n", mmc->max_blk_size);
1250 dev_dbg(mmc_dev(host->mmc), "max_req_size=%d\n", mmc->max_req_size);
1251 dev_dbg(mmc_dev(host->mmc), "max_seg_size=%d\n", mmc->max_seg_size);
1252
1253 platform_set_drvdata(pdev, host);
1254
1255 ret = mmc_davinci_cpufreq_register(host);
1256 if (ret) {
1257 dev_err(&pdev->dev, "failed to register cpufreq\n");
1258 goto cpu_freq_fail;
1259 }
1260
1261 ret = mmc_add_host(mmc);
1262 if (ret < 0)
1263 goto out;
1264
1265 ret = request_irq(irq, mmc_davinci_irq, 0, mmc_hostname(mmc), host);
1266 if (ret)
1267 goto out;
1268
1269 rename_region(mem, mmc_hostname(mmc));
1270
1271 dev_info(mmc_dev(host->mmc), "Using %s, %d-bit mode\n",
1272 host->use_dma ? "DMA" : "PIO",
1273 (mmc->caps & MMC_CAP_4_BIT_DATA) ? 4 : 1);
1274
1275 return 0;
1276
1277 out:
1278 mmc_davinci_cpufreq_deregister(host);
1279 cpu_freq_fail:
1280 if (host) {
1281 davinci_release_dma_channels(host);
1282
1283 if (host->clk) {
1284 clk_disable(host->clk);
1285 clk_put(host->clk);
1286 }
1287
1288 if (host->base)
1289 iounmap(host->base);
1290 }
1291
1292 if (mmc)
1293 mmc_free_host(mmc);
1294
1295 if (mem)
1296 release_resource(mem);
1297
1298 dev_dbg(&pdev->dev, "probe err %d\n", ret);
1299
1300 return ret;
1301 }
1302
1303 static int __exit davinci_mmcsd_remove(struct platform_device *pdev)
1304 {
1305 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1306
1307 platform_set_drvdata(pdev, NULL);
1308 if (host) {
1309 mmc_davinci_cpufreq_deregister(host);
1310
1311 mmc_remove_host(host->mmc);
1312 free_irq(host->irq, host);
1313
1314 davinci_release_dma_channels(host);
1315
1316 clk_disable(host->clk);
1317 clk_put(host->clk);
1318
1319 iounmap(host->base);
1320
1321 release_resource(host->mem_res);
1322
1323 mmc_free_host(host->mmc);
1324 }
1325
1326 return 0;
1327 }
1328
1329 #ifdef CONFIG_PM
1330 static int davinci_mmcsd_suspend(struct platform_device *pdev, pm_message_t msg)
1331 {
1332 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1333
1334 return mmc_suspend_host(host->mmc, msg);
1335 }
1336
1337 static int davinci_mmcsd_resume(struct platform_device *pdev)
1338 {
1339 struct mmc_davinci_host *host = platform_get_drvdata(pdev);
1340
1341 return mmc_resume_host(host->mmc);
1342 }
1343 #else
1344 #define davinci_mmcsd_suspend NULL
1345 #define davinci_mmcsd_resume NULL
1346 #endif
1347
1348 static struct platform_driver davinci_mmcsd_driver = {
1349 .driver = {
1350 .name = "davinci_mmc",
1351 .owner = THIS_MODULE,
1352 },
1353 .remove = __exit_p(davinci_mmcsd_remove),
1354 .suspend = davinci_mmcsd_suspend,
1355 .resume = davinci_mmcsd_resume,
1356 };
1357
1358 static int __init davinci_mmcsd_init(void)
1359 {
1360 return platform_driver_probe(&davinci_mmcsd_driver,
1361 davinci_mmcsd_probe);
1362 }
1363 module_init(davinci_mmcsd_init);
1364
1365 static void __exit davinci_mmcsd_exit(void)
1366 {
1367 platform_driver_unregister(&davinci_mmcsd_driver);
1368 }
1369 module_exit(davinci_mmcsd_exit);
1370
1371 MODULE_AUTHOR("Texas Instruments India");
1372 MODULE_LICENSE("GPL");
1373 MODULE_DESCRIPTION("MMC/SD driver for Davinci MMC controller");
1374
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree