arch/arm/mach-omap2/clock3xxx.c

   1 /*
   2  * OMAP3-specific clock framework functions
   3  *
   4  * Copyright (C) 2007-2008 Texas Instruments, Inc.
   5  * Copyright (C) 2007-2010 Nokia Corporation
   6  *
   7  * Paul Walmsley
   8  * Jouni Högander
   9  *
  10  * Parts of this code are based on code written by
  11  * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of the GNU General Public License version 2 as
  15  * published by the Free Software Foundation.
  16  */
  17 #undef DEBUG
  18
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/clk.h>
  22 #include <linux/io.h>
  23
  24 #include <plat/clock.h>
  25
  26 #include "clock.h"
  27 #include "clock3xxx.h"
  28 #include "prm.h"
  29 #include "prm-regbits-34xx.h"
  30 #include "cm.h"
  31 #include "cm-regbits-34xx.h"
  32
  33 /*
  34  * DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
  35  * that are sourced by DPLL5, and both of these require this clock
  36  * to be at 120 MHz for proper operation.
  37  */
  38 #define DPLL5_FREQ_FOR_USBHOST          120000000
  39
  40 /* needed by omap3_core_dpll_m2_set_rate() */
  41 struct clk *sdrc_ick_p, *arm_fck_p;
  42
  43 int omap3_dpll4_set_rate(struct clk *clk, unsigned long rate)
  44 {
  45         /*
  46          * According to the 12-5 CDP code from TI, "Limitation 2.5"
  47          * on 3430ES1 prevents us from changing DPLL multipliers or dividers
  48          * on DPLL4.
  49          */
  50         if (omap_rev() == OMAP3430_REV_ES1_0) {
  51                 pr_err("clock: DPLL4 cannot change rate due to "
  52                        "silicon 'Limitation 2.5' on 3430ES1.\n");
  53                 return -EINVAL;
  54         }
  55
  56         return omap3_noncore_dpll_set_rate(clk, rate);
  57 }
  58
  59 void __init omap3_clk_lock_dpll5(void)
  60 {
  61         struct clk *dpll5_clk;
  62         struct clk *dpll5_m2_clk;
  63
  64         dpll5_clk = clk_get(NULL, "dpll5_ck");
  65         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
  66         clk_enable(dpll5_clk);
  67
  68         /* Enable autoidle to allow it to enter low power bypass */
  69         omap3_dpll_allow_idle(dpll5_clk);
  70
  71         /* Program dpll5_m2_clk divider for no division */
  72         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
  73         clk_enable(dpll5_m2_clk);
  74         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
  75
  76         clk_disable(dpll5_m2_clk);
  77         clk_disable(dpll5_clk);
  78         return;
  79 }
  80
  81 /* Common clock code */
  82
  83 /*
  84  * Switch the MPU rate if specified on cmdline.  We cannot do this
  85  * early until cmdline is parsed.  XXX This should be removed from the
  86  * clock code and handled by the OPP layer code in the near future.
  87  */
  88 static int __init omap3xxx_clk_arch_init(void)
  89 {
  90         int ret;
  91
  92         if (!cpu_is_omap34xx())
  93                 return 0;
  94
  95         ret = omap2_clk_switch_mpurate_at_boot("dpll1_ck");
  96         if (!ret)
  97                 omap2_clk_print_new_rates("osc_sys_ck", "arm_fck", "core_ck");
  98
  99         return ret;
 100 }
 101
 102 arch_initcall(omap3xxx_clk_arch_init);
 103
 104