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ixgbe: add structure for containing RX/TX rings to q_vector
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ixgbe / ixgbe_main.c
blobbd1fd8f422dc0e9cd5cc49a049a014039b962baf
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/types.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/netdevice.h>
32 #include <linux/vmalloc.h>
33 #include <linux/string.h>
34 #include <linux/in.h>
35 #include <linux/interrupt.h>
36 #include <linux/ip.h>
37 #include <linux/tcp.h>
38 #include <linux/sctp.h>
39 #include <linux/pkt_sched.h>
40 #include <linux/ipv6.h>
41 #include <linux/slab.h>
42 #include <net/checksum.h>
43 #include <net/ip6_checksum.h>
44 #include <linux/ethtool.h>
45 #include <linux/if_vlan.h>
46 #include <linux/prefetch.h>
47 #include <scsi/fc/fc_fcoe.h>
48
49 #include "ixgbe.h"
50 #include "ixgbe_common.h"
51 #include "ixgbe_dcb_82599.h"
52 #include "ixgbe_sriov.h"
53
54 char ixgbe_driver_name[] = "ixgbe";
55 static const char ixgbe_driver_string[] =
56 "Intel(R) 10 Gigabit PCI Express Network Driver";
57 #define MAJ 3
58 #define MIN 4
59 #define BUILD 8
60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
61 __stringify(BUILD) "-k"
62 const char ixgbe_driver_version[] = DRV_VERSION;
63 static const char ixgbe_copyright[] =
64 "Copyright (c) 1999-2011 Intel Corporation.";
65
66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
67 [board_82598] = &ixgbe_82598_info,
68 [board_82599] = &ixgbe_82599_info,
69 [board_X540] = &ixgbe_X540_info,
70 };
71
72 /* ixgbe_pci_tbl - PCI Device ID Table
73 *
74 * Wildcard entries (PCI_ANY_ID) should come last
75 * Last entry must be all 0s
76 *
77 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
78 * Class, Class Mask, private data (not used) }
79 */
80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
81 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
82 board_82598 },
83 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
84 board_82598 },
85 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
86 board_82598 },
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
88 board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
90 board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
92 board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
94 board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
96 board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
98 board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
100 board_82598 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
102 board_82598 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
104 board_82598 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
106 board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
108 board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
110 board_82599 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
112 board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
114 board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
116 board_82599 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
118 board_82599 },
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
120 board_82599 },
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
122 board_82599 },
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
124 board_82599 },
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
126 board_82599 },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
128 board_X540 },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
130 board_82599 },
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
132 board_82599 },
133
134 /* required last entry */
135 {0, }
136 };
137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
141 void *p);
142 static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146 };
147 #endif
148
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs;
151 module_param(max_vfs, uint, 0);
152 MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function");
154 #endif /* CONFIG_PCI_IOV */
155
156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
158 MODULE_LICENSE("GPL");
159 MODULE_VERSION(DRV_VERSION);
160
161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
162
163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
164 {
165 struct ixgbe_hw *hw = &adapter->hw;
166 u32 gcr;
167 u32 gpie;
168 u32 vmdctl;
169
170 #ifdef CONFIG_PCI_IOV
171 /* disable iov and allow time for transactions to clear */
172 pci_disable_sriov(adapter->pdev);
173 #endif
174
175 /* turn off device IOV mode */
176 gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
177 gcr &= ~(IXGBE_GCR_EXT_SRIOV);
178 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
179 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
180 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
181 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
182
183 /* set default pool back to 0 */
184 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
185 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
186 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
187
188 /* take a breather then clean up driver data */
189 msleep(100);
190
191 kfree(adapter->vfinfo);
192 adapter->vfinfo = NULL;
193
194 adapter->num_vfs = 0;
195 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
196 }
197
198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
199 {
200 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
201 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
202 schedule_work(&adapter->service_task);
203 }
204
205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
206 {
207 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
208
209 /* flush memory to make sure state is correct before next watchog */
210 smp_mb__before_clear_bit();
211 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
212 }
213
214 struct ixgbe_reg_info {
215 u32 ofs;
216 char *name;
217 };
218
219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
220
221 /* General Registers */
222 {IXGBE_CTRL, "CTRL"},
223 {IXGBE_STATUS, "STATUS"},
224 {IXGBE_CTRL_EXT, "CTRL_EXT"},
225
226 /* Interrupt Registers */
227 {IXGBE_EICR, "EICR"},
228
229 /* RX Registers */
230 {IXGBE_SRRCTL(0), "SRRCTL"},
231 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
232 {IXGBE_RDLEN(0), "RDLEN"},
233 {IXGBE_RDH(0), "RDH"},
234 {IXGBE_RDT(0), "RDT"},
235 {IXGBE_RXDCTL(0), "RXDCTL"},
236 {IXGBE_RDBAL(0), "RDBAL"},
237 {IXGBE_RDBAH(0), "RDBAH"},
238
239 /* TX Registers */
240 {IXGBE_TDBAL(0), "TDBAL"},
241 {IXGBE_TDBAH(0), "TDBAH"},
242 {IXGBE_TDLEN(0), "TDLEN"},
243 {IXGBE_TDH(0), "TDH"},
244 {IXGBE_TDT(0), "TDT"},
245 {IXGBE_TXDCTL(0), "TXDCTL"},
246
247 /* List Terminator */
248 {}
249 };
250
251
252 /*
253 * ixgbe_regdump - register printout routine
254 */
255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
256 {
257 int i = 0, j = 0;
258 char rname[16];
259 u32 regs[64];
260
261 switch (reginfo->ofs) {
262 case IXGBE_SRRCTL(0):
263 for (i = 0; i < 64; i++)
264 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
265 break;
266 case IXGBE_DCA_RXCTRL(0):
267 for (i = 0; i < 64; i++)
268 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
269 break;
270 case IXGBE_RDLEN(0):
271 for (i = 0; i < 64; i++)
272 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
273 break;
274 case IXGBE_RDH(0):
275 for (i = 0; i < 64; i++)
276 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
277 break;
278 case IXGBE_RDT(0):
279 for (i = 0; i < 64; i++)
280 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
281 break;
282 case IXGBE_RXDCTL(0):
283 for (i = 0; i < 64; i++)
284 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
285 break;
286 case IXGBE_RDBAL(0):
287 for (i = 0; i < 64; i++)
288 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
289 break;
290 case IXGBE_RDBAH(0):
291 for (i = 0; i < 64; i++)
292 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
293 break;
294 case IXGBE_TDBAL(0):
295 for (i = 0; i < 64; i++)
296 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
297 break;
298 case IXGBE_TDBAH(0):
299 for (i = 0; i < 64; i++)
300 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
301 break;
302 case IXGBE_TDLEN(0):
303 for (i = 0; i < 64; i++)
304 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
305 break;
306 case IXGBE_TDH(0):
307 for (i = 0; i < 64; i++)
308 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
309 break;
310 case IXGBE_TDT(0):
311 for (i = 0; i < 64; i++)
312 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
313 break;
314 case IXGBE_TXDCTL(0):
315 for (i = 0; i < 64; i++)
316 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
317 break;
318 default:
319 pr_info("%-15s %08x\n", reginfo->name,
320 IXGBE_READ_REG(hw, reginfo->ofs));
321 return;
322 }
323
324 for (i = 0; i < 8; i++) {
325 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
326 pr_err("%-15s", rname);
327 for (j = 0; j < 8; j++)
328 pr_cont(" %08x", regs[i*8+j]);
329 pr_cont("\n");
330 }
331
332 }
333
334 /*
335 * ixgbe_dump - Print registers, tx-rings and rx-rings
336 */
337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
338 {
339 struct net_device *netdev = adapter->netdev;
340 struct ixgbe_hw *hw = &adapter->hw;
341 struct ixgbe_reg_info *reginfo;
342 int n = 0;
343 struct ixgbe_ring *tx_ring;
344 struct ixgbe_tx_buffer *tx_buffer_info;
345 union ixgbe_adv_tx_desc *tx_desc;
346 struct my_u0 { u64 a; u64 b; } *u0;
347 struct ixgbe_ring *rx_ring;
348 union ixgbe_adv_rx_desc *rx_desc;
349 struct ixgbe_rx_buffer *rx_buffer_info;
350 u32 staterr;
351 int i = 0;
352
353 if (!netif_msg_hw(adapter))
354 return;
355
356 /* Print netdevice Info */
357 if (netdev) {
358 dev_info(&adapter->pdev->dev, "Net device Info\n");
359 pr_info("Device Name state "
360 "trans_start last_rx\n");
361 pr_info("%-15s %016lX %016lX %016lX\n",
362 netdev->name,
363 netdev->state,
364 netdev->trans_start,
365 netdev->last_rx);
366 }
367
368 /* Print Registers */
369 dev_info(&adapter->pdev->dev, "Register Dump\n");
370 pr_info(" Register Name Value\n");
371 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
372 reginfo->name; reginfo++) {
373 ixgbe_regdump(hw, reginfo);
374 }
375
376 /* Print TX Ring Summary */
377 if (!netdev || !netif_running(netdev))
378 goto exit;
379
380 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
381 pr_info("Queue [NTU] [NTC] [bi(ntc)->dma ] leng ntw timestamp\n");
382 for (n = 0; n < adapter->num_tx_queues; n++) {
383 tx_ring = adapter->tx_ring[n];
384 tx_buffer_info =
385 &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
386 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
387 n, tx_ring->next_to_use, tx_ring->next_to_clean,
388 (u64)tx_buffer_info->dma,
389 tx_buffer_info->length,
390 tx_buffer_info->next_to_watch,
391 (u64)tx_buffer_info->time_stamp);
392 }
393
394 /* Print TX Rings */
395 if (!netif_msg_tx_done(adapter))
396 goto rx_ring_summary;
397
398 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
399
400 /* Transmit Descriptor Formats
401 *
402 * Advanced Transmit Descriptor
403 * +--------------------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +--------------------------------------------------------------+
406 * 8 | PAYLEN | PORTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
407 * +--------------------------------------------------------------+
408 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
409 */
410
411 for (n = 0; n < adapter->num_tx_queues; n++) {
412 tx_ring = adapter->tx_ring[n];
413 pr_info("------------------------------------\n");
414 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
415 pr_info("------------------------------------\n");
416 pr_info("T [desc] [address 63:0 ] "
417 "[PlPOIdStDDt Ln] [bi->dma ] "
418 "leng ntw timestamp bi->skb\n");
419
420 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
421 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
422 tx_buffer_info = &tx_ring->tx_buffer_info[i];
423 u0 = (struct my_u0 *)tx_desc;
424 pr_info("T [0x%03X] %016llX %016llX %016llX"
425 " %04X %3X %016llX %p", i,
426 le64_to_cpu(u0->a),
427 le64_to_cpu(u0->b),
428 (u64)tx_buffer_info->dma,
429 tx_buffer_info->length,
430 tx_buffer_info->next_to_watch,
431 (u64)tx_buffer_info->time_stamp,
432 tx_buffer_info->skb);
433 if (i == tx_ring->next_to_use &&
434 i == tx_ring->next_to_clean)
435 pr_cont(" NTC/U\n");
436 else if (i == tx_ring->next_to_use)
437 pr_cont(" NTU\n");
438 else if (i == tx_ring->next_to_clean)
439 pr_cont(" NTC\n");
440 else
441 pr_cont("\n");
442
443 if (netif_msg_pktdata(adapter) &&
444 tx_buffer_info->dma != 0)
445 print_hex_dump(KERN_INFO, "",
446 DUMP_PREFIX_ADDRESS, 16, 1,
447 phys_to_virt(tx_buffer_info->dma),
448 tx_buffer_info->length, true);
449 }
450 }
451
452 /* Print RX Rings Summary */
453 rx_ring_summary:
454 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
455 pr_info("Queue [NTU] [NTC]\n");
456 for (n = 0; n < adapter->num_rx_queues; n++) {
457 rx_ring = adapter->rx_ring[n];
458 pr_info("%5d %5X %5X\n",
459 n, rx_ring->next_to_use, rx_ring->next_to_clean);
460 }
461
462 /* Print RX Rings */
463 if (!netif_msg_rx_status(adapter))
464 goto exit;
465
466 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
467
468 /* Advanced Receive Descriptor (Read) Format
469 * 63 1 0
470 * +-----------------------------------------------------+
471 * 0 | Packet Buffer Address [63:1] |A0/NSE|
472 * +----------------------------------------------+------+
473 * 8 | Header Buffer Address [63:1] | DD |
474 * +-----------------------------------------------------+
475 *
476 *
477 * Advanced Receive Descriptor (Write-Back) Format
478 *
479 * 63 48 47 32 31 30 21 20 16 15 4 3 0
480 * +------------------------------------------------------+
481 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
482 * | Checksum Ident | | | | Type | Type |
483 * +------------------------------------------------------+
484 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
485 * +------------------------------------------------------+
486 * 63 48 47 32 31 20 19 0
487 */
488 for (n = 0; n < adapter->num_rx_queues; n++) {
489 rx_ring = adapter->rx_ring[n];
490 pr_info("------------------------------------\n");
491 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
492 pr_info("------------------------------------\n");
493 pr_info("R [desc] [ PktBuf A0] "
494 "[ HeadBuf DD] [bi->dma ] [bi->skb] "
495 "<-- Adv Rx Read format\n");
496 pr_info("RWB[desc] [PcsmIpSHl PtRs] "
497 "[vl er S cks ln] ---------------- [bi->skb] "
498 "<-- Adv Rx Write-Back format\n");
499
500 for (i = 0; i < rx_ring->count; i++) {
501 rx_buffer_info = &rx_ring->rx_buffer_info[i];
502 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
503 u0 = (struct my_u0 *)rx_desc;
504 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
505 if (staterr & IXGBE_RXD_STAT_DD) {
506 /* Descriptor Done */
507 pr_info("RWB[0x%03X] %016llX "
508 "%016llX ---------------- %p", i,
509 le64_to_cpu(u0->a),
510 le64_to_cpu(u0->b),
511 rx_buffer_info->skb);
512 } else {
513 pr_info("R [0x%03X] %016llX "
514 "%016llX %016llX %p", i,
515 le64_to_cpu(u0->a),
516 le64_to_cpu(u0->b),
517 (u64)rx_buffer_info->dma,
518 rx_buffer_info->skb);
519
520 if (netif_msg_pktdata(adapter)) {
521 print_hex_dump(KERN_INFO, "",
522 DUMP_PREFIX_ADDRESS, 16, 1,
523 phys_to_virt(rx_buffer_info->dma),
524 rx_ring->rx_buf_len, true);
525
526 if (rx_ring->rx_buf_len
527 < IXGBE_RXBUFFER_2048)
528 print_hex_dump(KERN_INFO, "",
529 DUMP_PREFIX_ADDRESS, 16, 1,
530 phys_to_virt(
531 rx_buffer_info->page_dma +
532 rx_buffer_info->page_offset
533 ),
534 PAGE_SIZE/2, true);
535 }
536 }
537
538 if (i == rx_ring->next_to_use)
539 pr_cont(" NTU\n");
540 else if (i == rx_ring->next_to_clean)
541 pr_cont(" NTC\n");
542 else
543 pr_cont("\n");
544
545 }
546 }
547
548 exit:
549 return;
550 }
551
552 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
553 {
554 u32 ctrl_ext;
555
556 /* Let firmware take over control of h/w */
557 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
558 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
559 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
560 }
561
562 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
563 {
564 u32 ctrl_ext;
565
566 /* Let firmware know the driver has taken over */
567 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
568 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
569 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
570 }
571
572 /*
573 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
574 * @adapter: pointer to adapter struct
575 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
576 * @queue: queue to map the corresponding interrupt to
577 * @msix_vector: the vector to map to the corresponding queue
578 *
579 */
580 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
581 u8 queue, u8 msix_vector)
582 {
583 u32 ivar, index;
584 struct ixgbe_hw *hw = &adapter->hw;
585 switch (hw->mac.type) {
586 case ixgbe_mac_82598EB:
587 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
588 if (direction == -1)
589 direction = 0;
590 index = (((direction * 64) + queue) >> 2) & 0x1F;
591 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
592 ivar &= ~(0xFF << (8 * (queue & 0x3)));
593 ivar |= (msix_vector << (8 * (queue & 0x3)));
594 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
595 break;
596 case ixgbe_mac_82599EB:
597 case ixgbe_mac_X540:
598 if (direction == -1) {
599 /* other causes */
600 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
601 index = ((queue & 1) * 8);
602 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
603 ivar &= ~(0xFF << index);
604 ivar |= (msix_vector << index);
605 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
606 break;
607 } else {
608 /* tx or rx causes */
609 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
610 index = ((16 * (queue & 1)) + (8 * direction));
611 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
612 ivar &= ~(0xFF << index);
613 ivar |= (msix_vector << index);
614 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
615 break;
616 }
617 default:
618 break;
619 }
620 }
621
622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
623 u64 qmask)
624 {
625 u32 mask;
626
627 switch (adapter->hw.mac.type) {
628 case ixgbe_mac_82598EB:
629 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
631 break;
632 case ixgbe_mac_82599EB:
633 case ixgbe_mac_X540:
634 mask = (qmask & 0xFFFFFFFF);
635 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
636 mask = (qmask >> 32);
637 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
638 break;
639 default:
640 break;
641 }
642 }
643
644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
645 struct ixgbe_tx_buffer *tx_buffer_info)
646 {
647 if (tx_buffer_info->dma) {
648 if (tx_buffer_info->mapped_as_page)
649 dma_unmap_page(tx_ring->dev,
650 tx_buffer_info->dma,
651 tx_buffer_info->length,
652 DMA_TO_DEVICE);
653 else
654 dma_unmap_single(tx_ring->dev,
655 tx_buffer_info->dma,
656 tx_buffer_info->length,
657 DMA_TO_DEVICE);
658 tx_buffer_info->dma = 0;
659 }
660 if (tx_buffer_info->skb) {
661 dev_kfree_skb_any(tx_buffer_info->skb);
662 tx_buffer_info->skb = NULL;
663 }
664 tx_buffer_info->time_stamp = 0;
665 /* tx_buffer_info must be completely set up in the transmit path */
666 }
667
668 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
669 {
670 struct ixgbe_hw *hw = &adapter->hw;
671 struct ixgbe_hw_stats *hwstats = &adapter->stats;
672 u32 data = 0;
673 u32 xoff[8] = {0};
674 int i;
675
676 if ((hw->fc.current_mode == ixgbe_fc_full) ||
677 (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
678 switch (hw->mac.type) {
679 case ixgbe_mac_82598EB:
680 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
681 break;
682 default:
683 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
684 }
685 hwstats->lxoffrxc += data;
686
687 /* refill credits (no tx hang) if we received xoff */
688 if (!data)
689 return;
690
691 for (i = 0; i < adapter->num_tx_queues; i++)
692 clear_bit(__IXGBE_HANG_CHECK_ARMED,
693 &adapter->tx_ring[i]->state);
694 return;
695 } else if (!(adapter->dcb_cfg.pfc_mode_enable))
696 return;
697
698 /* update stats for each tc, only valid with PFC enabled */
699 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
700 switch (hw->mac.type) {
701 case ixgbe_mac_82598EB:
702 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
703 break;
704 default:
705 xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
706 }
707 hwstats->pxoffrxc[i] += xoff[i];
708 }
709
710 /* disarm tx queues that have received xoff frames */
711 for (i = 0; i < adapter->num_tx_queues; i++) {
712 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
713 u8 tc = tx_ring->dcb_tc;
714
715 if (xoff[tc])
716 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
717 }
718 }
719
720 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
721 {
722 return ring->tx_stats.completed;
723 }
724
725 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
726 {
727 struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
728 struct ixgbe_hw *hw = &adapter->hw;
729
730 u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
731 u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
732
733 if (head != tail)
734 return (head < tail) ?
735 tail - head : (tail + ring->count - head);
736
737 return 0;
738 }
739
740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
741 {
742 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
743 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
744 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
745 bool ret = false;
746
747 clear_check_for_tx_hang(tx_ring);
748
749 /*
750 * Check for a hung queue, but be thorough. This verifies
751 * that a transmit has been completed since the previous
752 * check AND there is at least one packet pending. The
753 * ARMED bit is set to indicate a potential hang. The
754 * bit is cleared if a pause frame is received to remove
755 * false hang detection due to PFC or 802.3x frames. By
756 * requiring this to fail twice we avoid races with
757 * pfc clearing the ARMED bit and conditions where we
758 * run the check_tx_hang logic with a transmit completion
759 * pending but without time to complete it yet.
760 */
761 if ((tx_done_old == tx_done) && tx_pending) {
762 /* make sure it is true for two checks in a row */
763 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
764 &tx_ring->state);
765 } else {
766 /* update completed stats and continue */
767 tx_ring->tx_stats.tx_done_old = tx_done;
768 /* reset the countdown */
769 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
770 }
771
772 return ret;
773 }
774
775 /**
776 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
777 * @adapter: driver private struct
778 **/
779 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
780 {
781
782 /* Do the reset outside of interrupt context */
783 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
784 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
785 ixgbe_service_event_schedule(adapter);
786 }
787 }
788
789 /**
790 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
791 * @q_vector: structure containing interrupt and ring information
792 * @tx_ring: tx ring to clean
793 **/
794 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
795 struct ixgbe_ring *tx_ring)
796 {
797 struct ixgbe_adapter *adapter = q_vector->adapter;
798 union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
799 struct ixgbe_tx_buffer *tx_buffer_info;
800 unsigned int total_bytes = 0, total_packets = 0;
801 u16 i, eop, count = 0;
802
803 i = tx_ring->next_to_clean;
804 eop = tx_ring->tx_buffer_info[i].next_to_watch;
805 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
806
807 while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
808 (count < tx_ring->work_limit)) {
809 bool cleaned = false;
810 rmb(); /* read buffer_info after eop_desc */
811 for ( ; !cleaned; count++) {
812 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
813 tx_buffer_info = &tx_ring->tx_buffer_info[i];
814
815 tx_desc->wb.status = 0;
816 cleaned = (i == eop);
817
818 i++;
819 if (i == tx_ring->count)
820 i = 0;
821
822 if (cleaned && tx_buffer_info->skb) {
823 total_bytes += tx_buffer_info->bytecount;
824 total_packets += tx_buffer_info->gso_segs;
825 }
826
827 ixgbe_unmap_and_free_tx_resource(tx_ring,
828 tx_buffer_info);
829 }
830
831 tx_ring->tx_stats.completed++;
832 eop = tx_ring->tx_buffer_info[i].next_to_watch;
833 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
834 }
835
836 tx_ring->next_to_clean = i;
837 tx_ring->total_bytes += total_bytes;
838 tx_ring->total_packets += total_packets;
839 u64_stats_update_begin(&tx_ring->syncp);
840 tx_ring->stats.packets += total_packets;
841 tx_ring->stats.bytes += total_bytes;
842 u64_stats_update_end(&tx_ring->syncp);
843
844 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
845 /* schedule immediate reset if we believe we hung */
846 struct ixgbe_hw *hw = &adapter->hw;
847 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
848 e_err(drv, "Detected Tx Unit Hang\n"
849 " Tx Queue <%d>\n"
850 " TDH, TDT <%x>, <%x>\n"
851 " next_to_use <%x>\n"
852 " next_to_clean <%x>\n"
853 "tx_buffer_info[next_to_clean]\n"
854 " time_stamp <%lx>\n"
855 " jiffies <%lx>\n",
856 tx_ring->queue_index,
857 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
858 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
859 tx_ring->next_to_use, eop,
860 tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
861
862 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
863
864 e_info(probe,
865 "tx hang %d detected on queue %d, resetting adapter\n",
866 adapter->tx_timeout_count + 1, tx_ring->queue_index);
867
868 /* schedule immediate reset if we believe we hung */
869 ixgbe_tx_timeout_reset(adapter);
870
871 /* the adapter is about to reset, no point in enabling stuff */
872 return true;
873 }
874
875 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
876 if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
877 (ixgbe_desc_unused(tx_ring) >= TX_WAKE_THRESHOLD))) {
878 /* Make sure that anybody stopping the queue after this
879 * sees the new next_to_clean.
880 */
881 smp_mb();
882 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
883 !test_bit(__IXGBE_DOWN, &adapter->state)) {
884 netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
885 ++tx_ring->tx_stats.restart_queue;
886 }
887 }
888
889 return count < tx_ring->work_limit;
890 }
891
892 #ifdef CONFIG_IXGBE_DCA
893 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
894 struct ixgbe_ring *rx_ring,
895 int cpu)
896 {
897 struct ixgbe_hw *hw = &adapter->hw;
898 u32 rxctrl;
899 u8 reg_idx = rx_ring->reg_idx;
900
901 rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
902 switch (hw->mac.type) {
903 case ixgbe_mac_82598EB:
904 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
905 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
906 break;
907 case ixgbe_mac_82599EB:
908 case ixgbe_mac_X540:
909 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
910 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
911 IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
912 break;
913 default:
914 break;
915 }
916 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
917 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
918 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
919 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
920 }
921
922 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
923 struct ixgbe_ring *tx_ring,
924 int cpu)
925 {
926 struct ixgbe_hw *hw = &adapter->hw;
927 u32 txctrl;
928 u8 reg_idx = tx_ring->reg_idx;
929
930 switch (hw->mac.type) {
931 case ixgbe_mac_82598EB:
932 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
933 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
934 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
935 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
936 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
937 break;
938 case ixgbe_mac_82599EB:
939 case ixgbe_mac_X540:
940 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
941 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
942 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
943 IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
944 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
945 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
946 break;
947 default:
948 break;
949 }
950 }
951
952 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
953 {
954 struct ixgbe_adapter *adapter = q_vector->adapter;
955 int cpu = get_cpu();
956 long r_idx;
957 int i;
958
959 if (q_vector->cpu == cpu)
960 goto out_no_update;
961
962 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
963 for (i = 0; i < q_vector->tx.count; i++) {
964 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
965 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
966 r_idx + 1);
967 }
968
969 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
970 for (i = 0; i < q_vector->rx.count; i++) {
971 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
972 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
973 r_idx + 1);
974 }
975
976 q_vector->cpu = cpu;
977 out_no_update:
978 put_cpu();
979 }
980
981 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
982 {
983 int num_q_vectors;
984 int i;
985
986 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
987 return;
988
989 /* always use CB2 mode, difference is masked in the CB driver */
990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
991
992 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
993 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
994 else
995 num_q_vectors = 1;
996
997 for (i = 0; i < num_q_vectors; i++) {
998 adapter->q_vector[i]->cpu = -1;
999 ixgbe_update_dca(adapter->q_vector[i]);
1000 }
1001 }
1002
1003 static int __ixgbe_notify_dca(struct device *dev, void *data)
1004 {
1005 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1006 unsigned long event = *(unsigned long *)data;
1007
1008 if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1009 return 0;
1010
1011 switch (event) {
1012 case DCA_PROVIDER_ADD:
1013 /* if we're already enabled, don't do it again */
1014 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1015 break;
1016 if (dca_add_requester(dev) == 0) {
1017 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1018 ixgbe_setup_dca(adapter);
1019 break;
1020 }
1021 /* Fall Through since DCA is disabled. */
1022 case DCA_PROVIDER_REMOVE:
1023 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1024 dca_remove_requester(dev);
1025 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1026 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1027 }
1028 break;
1029 }
1030
1031 return 0;
1032 }
1033 #endif /* CONFIG_IXGBE_DCA */
1034
1035 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1036 struct sk_buff *skb)
1037 {
1038 skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1039 }
1040
1041 /**
1042 * ixgbe_receive_skb - Send a completed packet up the stack
1043 * @adapter: board private structure
1044 * @skb: packet to send up
1045 * @status: hardware indication of status of receive
1046 * @rx_ring: rx descriptor ring (for a specific queue) to setup
1047 * @rx_desc: rx descriptor
1048 **/
1049 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1050 struct sk_buff *skb, u8 status,
1051 struct ixgbe_ring *ring,
1052 union ixgbe_adv_rx_desc *rx_desc)
1053 {
1054 struct ixgbe_adapter *adapter = q_vector->adapter;
1055 struct napi_struct *napi = &q_vector->napi;
1056 bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1057 u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1058
1059 if (is_vlan && (tag & VLAN_VID_MASK))
1060 __vlan_hwaccel_put_tag(skb, tag);
1061
1062 if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1063 napi_gro_receive(napi, skb);
1064 else
1065 netif_rx(skb);
1066 }
1067
1068 /**
1069 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1070 * @adapter: address of board private structure
1071 * @status_err: hardware indication of status of receive
1072 * @skb: skb currently being received and modified
1073 **/
1074 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1075 union ixgbe_adv_rx_desc *rx_desc,
1076 struct sk_buff *skb)
1077 {
1078 u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1079
1080 skb_checksum_none_assert(skb);
1081
1082 /* Rx csum disabled */
1083 if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1084 return;
1085
1086 /* if IP and error */
1087 if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1088 (status_err & IXGBE_RXDADV_ERR_IPE)) {
1089 adapter->hw_csum_rx_error++;
1090 return;
1091 }
1092
1093 if (!(status_err & IXGBE_RXD_STAT_L4CS))
1094 return;
1095
1096 if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1097 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1098
1099 /*
1100 * 82599 errata, UDP frames with a 0 checksum can be marked as
1101 * checksum errors.
1102 */
1103 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1104 (adapter->hw.mac.type == ixgbe_mac_82599EB))
1105 return;
1106
1107 adapter->hw_csum_rx_error++;
1108 return;
1109 }
1110
1111 /* It must be a TCP or UDP packet with a valid checksum */
1112 skb->ip_summed = CHECKSUM_UNNECESSARY;
1113 }
1114
1115 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1116 {
1117 /*
1118 * Force memory writes to complete before letting h/w
1119 * know there are new descriptors to fetch. (Only
1120 * applicable for weak-ordered memory model archs,
1121 * such as IA-64).
1122 */
1123 wmb();
1124 writel(val, rx_ring->tail);
1125 }
1126
1127 /**
1128 * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1129 * @rx_ring: ring to place buffers on
1130 * @cleaned_count: number of buffers to replace
1131 **/
1132 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1133 {
1134 union ixgbe_adv_rx_desc *rx_desc;
1135 struct ixgbe_rx_buffer *bi;
1136 struct sk_buff *skb;
1137 u16 i = rx_ring->next_to_use;
1138
1139 /* do nothing if no valid netdev defined */
1140 if (!rx_ring->netdev)
1141 return;
1142
1143 while (cleaned_count--) {
1144 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1145 bi = &rx_ring->rx_buffer_info[i];
1146 skb = bi->skb;
1147
1148 if (!skb) {
1149 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1150 rx_ring->rx_buf_len);
1151 if (!skb) {
1152 rx_ring->rx_stats.alloc_rx_buff_failed++;
1153 goto no_buffers;
1154 }
1155 /* initialize queue mapping */
1156 skb_record_rx_queue(skb, rx_ring->queue_index);
1157 bi->skb = skb;
1158 }
1159
1160 if (!bi->dma) {
1161 bi->dma = dma_map_single(rx_ring->dev,
1162 skb->data,
1163 rx_ring->rx_buf_len,
1164 DMA_FROM_DEVICE);
1165 if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1166 rx_ring->rx_stats.alloc_rx_buff_failed++;
1167 bi->dma = 0;
1168 goto no_buffers;
1169 }
1170 }
1171
1172 if (ring_is_ps_enabled(rx_ring)) {
1173 if (!bi->page) {
1174 bi->page = netdev_alloc_page(rx_ring->netdev);
1175 if (!bi->page) {
1176 rx_ring->rx_stats.alloc_rx_page_failed++;
1177 goto no_buffers;
1178 }
1179 }
1180
1181 if (!bi->page_dma) {
1182 /* use a half page if we're re-using */
1183 bi->page_offset ^= PAGE_SIZE / 2;
1184 bi->page_dma = dma_map_page(rx_ring->dev,
1185 bi->page,
1186 bi->page_offset,
1187 PAGE_SIZE / 2,
1188 DMA_FROM_DEVICE);
1189 if (dma_mapping_error(rx_ring->dev,
1190 bi->page_dma)) {
1191 rx_ring->rx_stats.alloc_rx_page_failed++;
1192 bi->page_dma = 0;
1193 goto no_buffers;
1194 }
1195 }
1196
1197 /* Refresh the desc even if buffer_addrs didn't change
1198 * because each write-back erases this info. */
1199 rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1200 rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1201 } else {
1202 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1203 rx_desc->read.hdr_addr = 0;
1204 }
1205
1206 i++;
1207 if (i == rx_ring->count)
1208 i = 0;
1209 }
1210
1211 no_buffers:
1212 if (rx_ring->next_to_use != i) {
1213 rx_ring->next_to_use = i;
1214 ixgbe_release_rx_desc(rx_ring, i);
1215 }
1216 }
1217
1218 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1219 {
1220 /* HW will not DMA in data larger than the given buffer, even if it
1221 * parses the (NFS, of course) header to be larger. In that case, it
1222 * fills the header buffer and spills the rest into the page.
1223 */
1224 u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1225 u16 hlen = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1226 IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1227 if (hlen > IXGBE_RX_HDR_SIZE)
1228 hlen = IXGBE_RX_HDR_SIZE;
1229 return hlen;
1230 }
1231
1232 /**
1233 * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1234 * @skb: pointer to the last skb in the rsc queue
1235 *
1236 * This function changes a queue full of hw rsc buffers into a completed
1237 * packet. It uses the ->prev pointers to find the first packet and then
1238 * turns it into the frag list owner.
1239 **/
1240 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1241 {
1242 unsigned int frag_list_size = 0;
1243 unsigned int skb_cnt = 1;
1244
1245 while (skb->prev) {
1246 struct sk_buff *prev = skb->prev;
1247 frag_list_size += skb->len;
1248 skb->prev = NULL;
1249 skb = prev;
1250 skb_cnt++;
1251 }
1252
1253 skb_shinfo(skb)->frag_list = skb->next;
1254 skb->next = NULL;
1255 skb->len += frag_list_size;
1256 skb->data_len += frag_list_size;
1257 skb->truesize += frag_list_size;
1258 IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1259
1260 return skb;
1261 }
1262
1263 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1264 {
1265 return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1266 IXGBE_RXDADV_RSCCNT_MASK);
1267 }
1268
1269 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1270 struct ixgbe_ring *rx_ring,
1271 int *work_done, int work_to_do)
1272 {
1273 struct ixgbe_adapter *adapter = q_vector->adapter;
1274 union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1275 struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1276 struct sk_buff *skb;
1277 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1278 const int current_node = numa_node_id();
1279 #ifdef IXGBE_FCOE
1280 int ddp_bytes = 0;
1281 #endif /* IXGBE_FCOE */
1282 u32 staterr;
1283 u16 i;
1284 u16 cleaned_count = 0;
1285 bool pkt_is_rsc = false;
1286
1287 i = rx_ring->next_to_clean;
1288 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1289 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1290
1291 while (staterr & IXGBE_RXD_STAT_DD) {
1292 u32 upper_len = 0;
1293
1294 rmb(); /* read descriptor and rx_buffer_info after status DD */
1295
1296 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1297
1298 skb = rx_buffer_info->skb;
1299 rx_buffer_info->skb = NULL;
1300 prefetch(skb->data);
1301
1302 if (ring_is_rsc_enabled(rx_ring))
1303 pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1304
1305 /* if this is a skb from previous receive DMA will be 0 */
1306 if (rx_buffer_info->dma) {
1307 u16 hlen;
1308 if (pkt_is_rsc &&
1309 !(staterr & IXGBE_RXD_STAT_EOP) &&
1310 !skb->prev) {
1311 /*
1312 * When HWRSC is enabled, delay unmapping
1313 * of the first packet. It carries the
1314 * header information, HW may still
1315 * access the header after the writeback.
1316 * Only unmap it when EOP is reached
1317 */
1318 IXGBE_RSC_CB(skb)->delay_unmap = true;
1319 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1320 } else {
1321 dma_unmap_single(rx_ring->dev,
1322 rx_buffer_info->dma,
1323 rx_ring->rx_buf_len,
1324 DMA_FROM_DEVICE);
1325 }
1326 rx_buffer_info->dma = 0;
1327
1328 if (ring_is_ps_enabled(rx_ring)) {
1329 hlen = ixgbe_get_hlen(rx_desc);
1330 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1331 } else {
1332 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1333 }
1334
1335 skb_put(skb, hlen);
1336 } else {
1337 /* assume packet split since header is unmapped */
1338 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1339 }
1340
1341 if (upper_len) {
1342 dma_unmap_page(rx_ring->dev,
1343 rx_buffer_info->page_dma,
1344 PAGE_SIZE / 2,
1345 DMA_FROM_DEVICE);
1346 rx_buffer_info->page_dma = 0;
1347 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1348 rx_buffer_info->page,
1349 rx_buffer_info->page_offset,
1350 upper_len);
1351
1352 if ((page_count(rx_buffer_info->page) == 1) &&
1353 (page_to_nid(rx_buffer_info->page) == current_node))
1354 get_page(rx_buffer_info->page);
1355 else
1356 rx_buffer_info->page = NULL;
1357
1358 skb->len += upper_len;
1359 skb->data_len += upper_len;
1360 skb->truesize += upper_len;
1361 }
1362
1363 i++;
1364 if (i == rx_ring->count)
1365 i = 0;
1366
1367 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1368 prefetch(next_rxd);
1369 cleaned_count++;
1370
1371 if (pkt_is_rsc) {
1372 u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1373 IXGBE_RXDADV_NEXTP_SHIFT;
1374 next_buffer = &rx_ring->rx_buffer_info[nextp];
1375 } else {
1376 next_buffer = &rx_ring->rx_buffer_info[i];
1377 }
1378
1379 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1380 if (ring_is_ps_enabled(rx_ring)) {
1381 rx_buffer_info->skb = next_buffer->skb;
1382 rx_buffer_info->dma = next_buffer->dma;
1383 next_buffer->skb = skb;
1384 next_buffer->dma = 0;
1385 } else {
1386 skb->next = next_buffer->skb;
1387 skb->next->prev = skb;
1388 }
1389 rx_ring->rx_stats.non_eop_descs++;
1390 goto next_desc;
1391 }
1392
1393 if (skb->prev) {
1394 skb = ixgbe_transform_rsc_queue(skb);
1395 /* if we got here without RSC the packet is invalid */
1396 if (!pkt_is_rsc) {
1397 __pskb_trim(skb, 0);
1398 rx_buffer_info->skb = skb;
1399 goto next_desc;
1400 }
1401 }
1402
1403 if (ring_is_rsc_enabled(rx_ring)) {
1404 if (IXGBE_RSC_CB(skb)->delay_unmap) {
1405 dma_unmap_single(rx_ring->dev,
1406 IXGBE_RSC_CB(skb)->dma,
1407 rx_ring->rx_buf_len,
1408 DMA_FROM_DEVICE);
1409 IXGBE_RSC_CB(skb)->dma = 0;
1410 IXGBE_RSC_CB(skb)->delay_unmap = false;
1411 }
1412 }
1413 if (pkt_is_rsc) {
1414 if (ring_is_ps_enabled(rx_ring))
1415 rx_ring->rx_stats.rsc_count +=
1416 skb_shinfo(skb)->nr_frags;
1417 else
1418 rx_ring->rx_stats.rsc_count +=
1419 IXGBE_RSC_CB(skb)->skb_cnt;
1420 rx_ring->rx_stats.rsc_flush++;
1421 }
1422
1423 /* ERR_MASK will only have valid bits if EOP set */
1424 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1425 /* trim packet back to size 0 and recycle it */
1426 __pskb_trim(skb, 0);
1427 rx_buffer_info->skb = skb;
1428 goto next_desc;
1429 }
1430
1431 ixgbe_rx_checksum(adapter, rx_desc, skb);
1432 if (adapter->netdev->features & NETIF_F_RXHASH)
1433 ixgbe_rx_hash(rx_desc, skb);
1434
1435 /* probably a little skewed due to removing CRC */
1436 total_rx_bytes += skb->len;
1437 total_rx_packets++;
1438
1439 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1440 #ifdef IXGBE_FCOE
1441 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1442 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1443 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1444 if (!ddp_bytes)
1445 goto next_desc;
1446 }
1447 #endif /* IXGBE_FCOE */
1448 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1449
1450 next_desc:
1451 rx_desc->wb.upper.status_error = 0;
1452
1453 (*work_done)++;
1454 if (*work_done >= work_to_do)
1455 break;
1456
1457 /* return some buffers to hardware, one at a time is too slow */
1458 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1459 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1460 cleaned_count = 0;
1461 }
1462
1463 /* use prefetched values */
1464 rx_desc = next_rxd;
1465 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1466 }
1467
1468 rx_ring->next_to_clean = i;
1469 cleaned_count = ixgbe_desc_unused(rx_ring);
1470
1471 if (cleaned_count)
1472 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1473
1474 #ifdef IXGBE_FCOE
1475 /* include DDPed FCoE data */
1476 if (ddp_bytes > 0) {
1477 unsigned int mss;
1478
1479 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1480 sizeof(struct fc_frame_header) -
1481 sizeof(struct fcoe_crc_eof);
1482 if (mss > 512)
1483 mss &= ~511;
1484 total_rx_bytes += ddp_bytes;
1485 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1486 }
1487 #endif /* IXGBE_FCOE */
1488
1489 rx_ring->total_packets += total_rx_packets;
1490 rx_ring->total_bytes += total_rx_bytes;
1491 u64_stats_update_begin(&rx_ring->syncp);
1492 rx_ring->stats.packets += total_rx_packets;
1493 rx_ring->stats.bytes += total_rx_bytes;
1494 u64_stats_update_end(&rx_ring->syncp);
1495 }
1496
1497 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1498 /**
1499 * ixgbe_configure_msix - Configure MSI-X hardware
1500 * @adapter: board private structure
1501 *
1502 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1503 * interrupts.
1504 **/
1505 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1506 {
1507 struct ixgbe_q_vector *q_vector;
1508 int i, q_vectors, v_idx, r_idx;
1509 u32 mask;
1510
1511 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1512
1513 /*
1514 * Populate the IVAR table and set the ITR values to the
1515 * corresponding register.
1516 */
1517 for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1518 q_vector = adapter->q_vector[v_idx];
1519 /* XXX for_each_set_bit(...) */
1520 r_idx = find_first_bit(q_vector->rx.idx,
1521 adapter->num_rx_queues);
1522
1523 for (i = 0; i < q_vector->rx.count; i++) {
1524 u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1525 ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1526 r_idx = find_next_bit(q_vector->rx.idx,
1527 adapter->num_rx_queues,
1528 r_idx + 1);
1529 }
1530 r_idx = find_first_bit(q_vector->tx.idx,
1531 adapter->num_tx_queues);
1532
1533 for (i = 0; i < q_vector->tx.count; i++) {
1534 u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1535 ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1536 r_idx = find_next_bit(q_vector->tx.idx,
1537 adapter->num_tx_queues,
1538 r_idx + 1);
1539 }
1540
1541 if (q_vector->tx.count && !q_vector->rx.count)
1542 /* tx only */
1543 q_vector->eitr = adapter->tx_eitr_param;
1544 else if (q_vector->rx.count)
1545 /* rx or mixed */
1546 q_vector->eitr = adapter->rx_eitr_param;
1547
1548 ixgbe_write_eitr(q_vector);
1549 /* If ATR is enabled, set interrupt affinity */
1550 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1551 /*
1552 * Allocate the affinity_hint cpumask, assign the mask
1553 * for this vector, and set our affinity_hint for
1554 * this irq.
1555 */
1556 if (!alloc_cpumask_var(&q_vector->affinity_mask,
1557 GFP_KERNEL))
1558 return;
1559 cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1560 irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1561 q_vector->affinity_mask);
1562 }
1563 }
1564
1565 switch (adapter->hw.mac.type) {
1566 case ixgbe_mac_82598EB:
1567 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1568 v_idx);
1569 break;
1570 case ixgbe_mac_82599EB:
1571 case ixgbe_mac_X540:
1572 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1573 break;
1574
1575 default:
1576 break;
1577 }
1578 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1579
1580 /* set up to autoclear timer, and the vectors */
1581 mask = IXGBE_EIMS_ENABLE_MASK;
1582 if (adapter->num_vfs)
1583 mask &= ~(IXGBE_EIMS_OTHER |
1584 IXGBE_EIMS_MAILBOX |
1585 IXGBE_EIMS_LSC);
1586 else
1587 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1588 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1589 }
1590
1591 enum latency_range {
1592 lowest_latency = 0,
1593 low_latency = 1,
1594 bulk_latency = 2,
1595 latency_invalid = 255
1596 };
1597
1598 /**
1599 * ixgbe_update_itr - update the dynamic ITR value based on statistics
1600 * @adapter: pointer to adapter
1601 * @eitr: eitr setting (ints per sec) to give last timeslice
1602 * @itr_setting: current throttle rate in ints/second
1603 * @packets: the number of packets during this measurement interval
1604 * @bytes: the number of bytes during this measurement interval
1605 *
1606 * Stores a new ITR value based on packets and byte
1607 * counts during the last interrupt. The advantage of per interrupt
1608 * computation is faster updates and more accurate ITR for the current
1609 * traffic pattern. Constants in this function were computed
1610 * based on theoretical maximum wire speed and thresholds were set based
1611 * on testing data as well as attempting to minimize response time
1612 * while increasing bulk throughput.
1613 * this functionality is controlled by the InterruptThrottleRate module
1614 * parameter (see ixgbe_param.c)
1615 **/
1616 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1617 u32 eitr, u8 itr_setting,
1618 int packets, int bytes)
1619 {
1620 unsigned int retval = itr_setting;
1621 u32 timepassed_us;
1622 u64 bytes_perint;
1623
1624 if (packets == 0)
1625 goto update_itr_done;
1626
1627
1628 /* simple throttlerate management
1629 * 0-20MB/s lowest (100000 ints/s)
1630 * 20-100MB/s low (20000 ints/s)
1631 * 100-1249MB/s bulk (8000 ints/s)
1632 */
1633 /* what was last interrupt timeslice? */
1634 timepassed_us = 1000000/eitr;
1635 bytes_perint = bytes / timepassed_us; /* bytes/usec */
1636
1637 switch (itr_setting) {
1638 case lowest_latency:
1639 if (bytes_perint > adapter->eitr_low)
1640 retval = low_latency;
1641 break;
1642 case low_latency:
1643 if (bytes_perint > adapter->eitr_high)
1644 retval = bulk_latency;
1645 else if (bytes_perint <= adapter->eitr_low)
1646 retval = lowest_latency;
1647 break;
1648 case bulk_latency:
1649 if (bytes_perint <= adapter->eitr_high)
1650 retval = low_latency;
1651 break;
1652 }
1653
1654 update_itr_done:
1655 return retval;
1656 }
1657
1658 /**
1659 * ixgbe_write_eitr - write EITR register in hardware specific way
1660 * @q_vector: structure containing interrupt and ring information
1661 *
1662 * This function is made to be called by ethtool and by the driver
1663 * when it needs to update EITR registers at runtime. Hardware
1664 * specific quirks/differences are taken care of here.
1665 */
1666 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1667 {
1668 struct ixgbe_adapter *adapter = q_vector->adapter;
1669 struct ixgbe_hw *hw = &adapter->hw;
1670 int v_idx = q_vector->v_idx;
1671 u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1672
1673 switch (adapter->hw.mac.type) {
1674 case ixgbe_mac_82598EB:
1675 /* must write high and low 16 bits to reset counter */
1676 itr_reg |= (itr_reg << 16);
1677 break;
1678 case ixgbe_mac_82599EB:
1679 case ixgbe_mac_X540:
1680 /*
1681 * 82599 and X540 can support a value of zero, so allow it for
1682 * max interrupt rate, but there is an errata where it can
1683 * not be zero with RSC
1684 */
1685 if (itr_reg == 8 &&
1686 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1687 itr_reg = 0;
1688
1689 /*
1690 * set the WDIS bit to not clear the timer bits and cause an
1691 * immediate assertion of the interrupt
1692 */
1693 itr_reg |= IXGBE_EITR_CNT_WDIS;
1694 break;
1695 default:
1696 break;
1697 }
1698 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1699 }
1700
1701 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1702 {
1703 struct ixgbe_adapter *adapter = q_vector->adapter;
1704 int i, r_idx;
1705 u32 new_itr;
1706 u8 current_itr, ret_itr;
1707
1708 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
1709 for (i = 0; i < q_vector->tx.count; i++) {
1710 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1711 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1712 q_vector->tx.itr,
1713 tx_ring->total_packets,
1714 tx_ring->total_bytes);
1715 /* if the result for this queue would decrease interrupt
1716 * rate for this vector then use that result */
1717 q_vector->tx.itr = ((q_vector->tx.itr > ret_itr) ?
1718 q_vector->tx.itr - 1 : ret_itr);
1719 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
1720 r_idx + 1);
1721 }
1722
1723 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
1724 for (i = 0; i < q_vector->rx.count; i++) {
1725 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1726 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1727 q_vector->rx.itr,
1728 rx_ring->total_packets,
1729 rx_ring->total_bytes);
1730 /* if the result for this queue would decrease interrupt
1731 * rate for this vector then use that result */
1732 q_vector->rx.itr = ((q_vector->rx.itr > ret_itr) ?
1733 q_vector->rx.itr - 1 : ret_itr);
1734 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
1735 r_idx + 1);
1736 }
1737
1738 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
1739
1740 switch (current_itr) {
1741 /* counts and packets in update_itr are dependent on these numbers */
1742 case lowest_latency:
1743 new_itr = 100000;
1744 break;
1745 case low_latency:
1746 new_itr = 20000; /* aka hwitr = ~200 */
1747 break;
1748 case bulk_latency:
1749 default:
1750 new_itr = 8000;
1751 break;
1752 }
1753
1754 if (new_itr != q_vector->eitr) {
1755 /* do an exponential smoothing */
1756 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1757
1758 /* save the algorithm value here, not the smoothed one */
1759 q_vector->eitr = new_itr;
1760
1761 ixgbe_write_eitr(q_vector);
1762 }
1763 }
1764
1765 /**
1766 * ixgbe_check_overtemp_subtask - check for over tempurature
1767 * @adapter: pointer to adapter
1768 **/
1769 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1770 {
1771 struct ixgbe_hw *hw = &adapter->hw;
1772 u32 eicr = adapter->interrupt_event;
1773
1774 if (test_bit(__IXGBE_DOWN, &adapter->state))
1775 return;
1776
1777 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1778 !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1779 return;
1780
1781 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1782
1783 switch (hw->device_id) {
1784 case IXGBE_DEV_ID_82599_T3_LOM:
1785 /*
1786 * Since the warning interrupt is for both ports
1787 * we don't have to check if:
1788 * - This interrupt wasn't for our port.
1789 * - We may have missed the interrupt so always have to
1790 * check if we got a LSC
1791 */
1792 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1793 !(eicr & IXGBE_EICR_LSC))
1794 return;
1795
1796 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1797 u32 autoneg;
1798 bool link_up = false;
1799
1800 hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1801
1802 if (link_up)
1803 return;
1804 }
1805
1806 /* Check if this is not due to overtemp */
1807 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1808 return;
1809
1810 break;
1811 default:
1812 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1813 return;
1814 break;
1815 }
1816 e_crit(drv,
1817 "Network adapter has been stopped because it has over heated. "
1818 "Restart the computer. If the problem persists, "
1819 "power off the system and replace the adapter\n");
1820
1821 adapter->interrupt_event = 0;
1822 }
1823
1824 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1825 {
1826 struct ixgbe_hw *hw = &adapter->hw;
1827
1828 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1829 (eicr & IXGBE_EICR_GPI_SDP1)) {
1830 e_crit(probe, "Fan has stopped, replace the adapter\n");
1831 /* write to clear the interrupt */
1832 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1833 }
1834 }
1835
1836 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1837 {
1838 struct ixgbe_hw *hw = &adapter->hw;
1839
1840 if (eicr & IXGBE_EICR_GPI_SDP2) {
1841 /* Clear the interrupt */
1842 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1843 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1844 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1845 ixgbe_service_event_schedule(adapter);
1846 }
1847 }
1848
1849 if (eicr & IXGBE_EICR_GPI_SDP1) {
1850 /* Clear the interrupt */
1851 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1852 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1853 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1854 ixgbe_service_event_schedule(adapter);
1855 }
1856 }
1857 }
1858
1859 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1860 {
1861 struct ixgbe_hw *hw = &adapter->hw;
1862
1863 adapter->lsc_int++;
1864 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1865 adapter->link_check_timeout = jiffies;
1866 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1867 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1868 IXGBE_WRITE_FLUSH(hw);
1869 ixgbe_service_event_schedule(adapter);
1870 }
1871 }
1872
1873 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1874 {
1875 struct ixgbe_adapter *adapter = data;
1876 struct ixgbe_hw *hw = &adapter->hw;
1877 u32 eicr;
1878
1879 /*
1880 * Workaround for Silicon errata. Use clear-by-write instead
1881 * of clear-by-read. Reading with EICS will return the
1882 * interrupt causes without clearing, which later be done
1883 * with the write to EICR.
1884 */
1885 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1886 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1887
1888 if (eicr & IXGBE_EICR_LSC)
1889 ixgbe_check_lsc(adapter);
1890
1891 if (eicr & IXGBE_EICR_MAILBOX)
1892 ixgbe_msg_task(adapter);
1893
1894 switch (hw->mac.type) {
1895 case ixgbe_mac_82599EB:
1896 case ixgbe_mac_X540:
1897 /* Handle Flow Director Full threshold interrupt */
1898 if (eicr & IXGBE_EICR_FLOW_DIR) {
1899 int reinit_count = 0;
1900 int i;
1901 for (i = 0; i < adapter->num_tx_queues; i++) {
1902 struct ixgbe_ring *ring = adapter->tx_ring[i];
1903 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1904 &ring->state))
1905 reinit_count++;
1906 }
1907 if (reinit_count) {
1908 /* no more flow director interrupts until after init */
1909 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1910 eicr &= ~IXGBE_EICR_FLOW_DIR;
1911 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1912 ixgbe_service_event_schedule(adapter);
1913 }
1914 }
1915 ixgbe_check_sfp_event(adapter, eicr);
1916 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1917 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1918 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1919 adapter->interrupt_event = eicr;
1920 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1921 ixgbe_service_event_schedule(adapter);
1922 }
1923 }
1924 break;
1925 default:
1926 break;
1927 }
1928
1929 ixgbe_check_fan_failure(adapter, eicr);
1930
1931 /* re-enable the original interrupt state, no lsc, no queues */
1932 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1933 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1934 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1935
1936 return IRQ_HANDLED;
1937 }
1938
1939 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1940 u64 qmask)
1941 {
1942 u32 mask;
1943 struct ixgbe_hw *hw = &adapter->hw;
1944
1945 switch (hw->mac.type) {
1946 case ixgbe_mac_82598EB:
1947 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1948 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1949 break;
1950 case ixgbe_mac_82599EB:
1951 case ixgbe_mac_X540:
1952 mask = (qmask & 0xFFFFFFFF);
1953 if (mask)
1954 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1955 mask = (qmask >> 32);
1956 if (mask)
1957 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1958 break;
1959 default:
1960 break;
1961 }
1962 /* skip the flush */
1963 }
1964
1965 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1966 u64 qmask)
1967 {
1968 u32 mask;
1969 struct ixgbe_hw *hw = &adapter->hw;
1970
1971 switch (hw->mac.type) {
1972 case ixgbe_mac_82598EB:
1973 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1974 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1975 break;
1976 case ixgbe_mac_82599EB:
1977 case ixgbe_mac_X540:
1978 mask = (qmask & 0xFFFFFFFF);
1979 if (mask)
1980 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1981 mask = (qmask >> 32);
1982 if (mask)
1983 IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1984 break;
1985 default:
1986 break;
1987 }
1988 /* skip the flush */
1989 }
1990
1991 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1992 {
1993 struct ixgbe_q_vector *q_vector = data;
1994 struct ixgbe_adapter *adapter = q_vector->adapter;
1995 struct ixgbe_ring *tx_ring;
1996 int i, r_idx;
1997
1998 if (!q_vector->tx.count)
1999 return IRQ_HANDLED;
2000
2001 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2002 for (i = 0; i < q_vector->tx.count; i++) {
2003 tx_ring = adapter->tx_ring[r_idx];
2004 tx_ring->total_bytes = 0;
2005 tx_ring->total_packets = 0;
2006 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2007 r_idx + 1);
2008 }
2009
2010 /* EIAM disabled interrupts (on this vector) for us */
2011 napi_schedule(&q_vector->napi);
2012
2013 return IRQ_HANDLED;
2014 }
2015
2016 /**
2017 * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2018 * @irq: unused
2019 * @data: pointer to our q_vector struct for this interrupt vector
2020 **/
2021 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2022 {
2023 struct ixgbe_q_vector *q_vector = data;
2024 struct ixgbe_adapter *adapter = q_vector->adapter;
2025 struct ixgbe_ring *rx_ring;
2026 int r_idx;
2027 int i;
2028
2029 #ifdef CONFIG_IXGBE_DCA
2030 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2031 ixgbe_update_dca(q_vector);
2032 #endif
2033
2034 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2035 for (i = 0; i < q_vector->rx.count; i++) {
2036 rx_ring = adapter->rx_ring[r_idx];
2037 rx_ring->total_bytes = 0;
2038 rx_ring->total_packets = 0;
2039 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2040 r_idx + 1);
2041 }
2042
2043 if (!q_vector->rx.count)
2044 return IRQ_HANDLED;
2045
2046 /* EIAM disabled interrupts (on this vector) for us */
2047 napi_schedule(&q_vector->napi);
2048
2049 return IRQ_HANDLED;
2050 }
2051
2052 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2053 {
2054 struct ixgbe_q_vector *q_vector = data;
2055 struct ixgbe_adapter *adapter = q_vector->adapter;
2056 struct ixgbe_ring *ring;
2057 int r_idx;
2058 int i;
2059
2060 if (!q_vector->tx.count && !q_vector->rx.count)
2061 return IRQ_HANDLED;
2062
2063 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2064 for (i = 0; i < q_vector->tx.count; i++) {
2065 ring = adapter->tx_ring[r_idx];
2066 ring->total_bytes = 0;
2067 ring->total_packets = 0;
2068 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2069 r_idx + 1);
2070 }
2071
2072 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2073 for (i = 0; i < q_vector->rx.count; i++) {
2074 ring = adapter->rx_ring[r_idx];
2075 ring->total_bytes = 0;
2076 ring->total_packets = 0;
2077 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2078 r_idx + 1);
2079 }
2080
2081 /* EIAM disabled interrupts (on this vector) for us */
2082 napi_schedule(&q_vector->napi);
2083
2084 return IRQ_HANDLED;
2085 }
2086
2087 /**
2088 * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2089 * @napi: napi struct with our devices info in it
2090 * @budget: amount of work driver is allowed to do this pass, in packets
2091 *
2092 * This function is optimized for cleaning one queue only on a single
2093 * q_vector!!!
2094 **/
2095 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2096 {
2097 struct ixgbe_q_vector *q_vector =
2098 container_of(napi, struct ixgbe_q_vector, napi);
2099 struct ixgbe_adapter *adapter = q_vector->adapter;
2100 struct ixgbe_ring *rx_ring = NULL;
2101 int work_done = 0;
2102 long r_idx;
2103
2104 #ifdef CONFIG_IXGBE_DCA
2105 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2106 ixgbe_update_dca(q_vector);
2107 #endif
2108
2109 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2110 rx_ring = adapter->rx_ring[r_idx];
2111
2112 ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2113
2114 /* If all Rx work done, exit the polling mode */
2115 if (work_done < budget) {
2116 napi_complete(napi);
2117 if (adapter->rx_itr_setting & 1)
2118 ixgbe_set_itr_msix(q_vector);
2119 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2120 ixgbe_irq_enable_queues(adapter,
2121 ((u64)1 << q_vector->v_idx));
2122 }
2123
2124 return work_done;
2125 }
2126
2127 /**
2128 * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2129 * @napi: napi struct with our devices info in it
2130 * @budget: amount of work driver is allowed to do this pass, in packets
2131 *
2132 * This function will clean more than one rx queue associated with a
2133 * q_vector.
2134 **/
2135 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2136 {
2137 struct ixgbe_q_vector *q_vector =
2138 container_of(napi, struct ixgbe_q_vector, napi);
2139 struct ixgbe_adapter *adapter = q_vector->adapter;
2140 struct ixgbe_ring *ring = NULL;
2141 int work_done = 0, i;
2142 long r_idx;
2143 bool tx_clean_complete = true;
2144
2145 #ifdef CONFIG_IXGBE_DCA
2146 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2147 ixgbe_update_dca(q_vector);
2148 #endif
2149
2150 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2151 for (i = 0; i < q_vector->tx.count; i++) {
2152 ring = adapter->tx_ring[r_idx];
2153 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2154 r_idx = find_next_bit(q_vector->tx.idx, adapter->num_tx_queues,
2155 r_idx + 1);
2156 }
2157
2158 /* attempt to distribute budget to each queue fairly, but don't allow
2159 * the budget to go below 1 because we'll exit polling */
2160 budget /= (q_vector->rx.count ?: 1);
2161 budget = max(budget, 1);
2162 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2163 for (i = 0; i < q_vector->rx.count; i++) {
2164 ring = adapter->rx_ring[r_idx];
2165 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2166 r_idx = find_next_bit(q_vector->rx.idx, adapter->num_rx_queues,
2167 r_idx + 1);
2168 }
2169
2170 r_idx = find_first_bit(q_vector->rx.idx, adapter->num_rx_queues);
2171 ring = adapter->rx_ring[r_idx];
2172 /* If all Rx work done, exit the polling mode */
2173 if (work_done < budget) {
2174 napi_complete(napi);
2175 if (adapter->rx_itr_setting & 1)
2176 ixgbe_set_itr_msix(q_vector);
2177 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2178 ixgbe_irq_enable_queues(adapter,
2179 ((u64)1 << q_vector->v_idx));
2180 return 0;
2181 }
2182
2183 return work_done;
2184 }
2185
2186 /**
2187 * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2188 * @napi: napi struct with our devices info in it
2189 * @budget: amount of work driver is allowed to do this pass, in packets
2190 *
2191 * This function is optimized for cleaning one queue only on a single
2192 * q_vector!!!
2193 **/
2194 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2195 {
2196 struct ixgbe_q_vector *q_vector =
2197 container_of(napi, struct ixgbe_q_vector, napi);
2198 struct ixgbe_adapter *adapter = q_vector->adapter;
2199 struct ixgbe_ring *tx_ring = NULL;
2200 int work_done = 0;
2201 long r_idx;
2202
2203 #ifdef CONFIG_IXGBE_DCA
2204 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2205 ixgbe_update_dca(q_vector);
2206 #endif
2207
2208 r_idx = find_first_bit(q_vector->tx.idx, adapter->num_tx_queues);
2209 tx_ring = adapter->tx_ring[r_idx];
2210
2211 if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2212 work_done = budget;
2213
2214 /* If all Tx work done, exit the polling mode */
2215 if (work_done < budget) {
2216 napi_complete(napi);
2217 if (adapter->tx_itr_setting & 1)
2218 ixgbe_set_itr_msix(q_vector);
2219 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2220 ixgbe_irq_enable_queues(adapter,
2221 ((u64)1 << q_vector->v_idx));
2222 }
2223
2224 return work_done;
2225 }
2226
2227 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2228 int r_idx)
2229 {
2230 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2231 struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2232
2233 set_bit(r_idx, q_vector->rx.idx);
2234 q_vector->rx.count++;
2235 rx_ring->q_vector = q_vector;
2236 }
2237
2238 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2239 int t_idx)
2240 {
2241 struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2242 struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2243
2244 set_bit(t_idx, q_vector->tx.idx);
2245 q_vector->tx.count++;
2246 tx_ring->q_vector = q_vector;
2247 }
2248
2249 /**
2250 * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2251 * @adapter: board private structure to initialize
2252 *
2253 * This function maps descriptor rings to the queue-specific vectors
2254 * we were allotted through the MSI-X enabling code. Ideally, we'd have
2255 * one vector per ring/queue, but on a constrained vector budget, we
2256 * group the rings as "efficiently" as possible. You would add new
2257 * mapping configurations in here.
2258 **/
2259 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2260 {
2261 int q_vectors;
2262 int v_start = 0;
2263 int rxr_idx = 0, txr_idx = 0;
2264 int rxr_remaining = adapter->num_rx_queues;
2265 int txr_remaining = adapter->num_tx_queues;
2266 int i, j;
2267 int rqpv, tqpv;
2268 int err = 0;
2269
2270 /* No mapping required if MSI-X is disabled. */
2271 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2272 goto out;
2273
2274 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2275
2276 /*
2277 * The ideal configuration...
2278 * We have enough vectors to map one per queue.
2279 */
2280 if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2281 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2282 map_vector_to_rxq(adapter, v_start, rxr_idx);
2283
2284 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2285 map_vector_to_txq(adapter, v_start, txr_idx);
2286
2287 goto out;
2288 }
2289
2290 /*
2291 * If we don't have enough vectors for a 1-to-1
2292 * mapping, we'll have to group them so there are
2293 * multiple queues per vector.
2294 */
2295 /* Re-adjusting *qpv takes care of the remainder. */
2296 for (i = v_start; i < q_vectors; i++) {
2297 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2298 for (j = 0; j < rqpv; j++) {
2299 map_vector_to_rxq(adapter, i, rxr_idx);
2300 rxr_idx++;
2301 rxr_remaining--;
2302 }
2303 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2304 for (j = 0; j < tqpv; j++) {
2305 map_vector_to_txq(adapter, i, txr_idx);
2306 txr_idx++;
2307 txr_remaining--;
2308 }
2309 }
2310 out:
2311 return err;
2312 }
2313
2314 /**
2315 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2316 * @adapter: board private structure
2317 *
2318 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2319 * interrupts from the kernel.
2320 **/
2321 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2322 {
2323 struct net_device *netdev = adapter->netdev;
2324 irqreturn_t (*handler)(int, void *);
2325 int i, vector, q_vectors, err;
2326 int ri = 0, ti = 0;
2327
2328 /* Decrement for Other and TCP Timer vectors */
2329 q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2330
2331 err = ixgbe_map_rings_to_vectors(adapter);
2332 if (err)
2333 return err;
2334
2335 #define SET_HANDLER(_v) (((_v)->rx.count && (_v)->tx.count) \
2336 ? &ixgbe_msix_clean_many : \
2337 (_v)->rx.count ? &ixgbe_msix_clean_rx : \
2338 (_v)->tx.count ? &ixgbe_msix_clean_tx : \
2339 NULL)
2340 for (vector = 0; vector < q_vectors; vector++) {
2341 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2342 handler = SET_HANDLER(q_vector);
2343
2344 if (handler == &ixgbe_msix_clean_rx) {
2345 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2346 "%s-%s-%d", netdev->name, "rx", ri++);
2347 } else if (handler == &ixgbe_msix_clean_tx) {
2348 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2349 "%s-%s-%d", netdev->name, "tx", ti++);
2350 } else if (handler == &ixgbe_msix_clean_many) {
2351 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2352 "%s-%s-%d", netdev->name, "TxRx", ri++);
2353 ti++;
2354 } else {
2355 /* skip this unused q_vector */
2356 continue;
2357 }
2358 err = request_irq(adapter->msix_entries[vector].vector,
2359 handler, 0, q_vector->name,
2360 q_vector);
2361 if (err) {
2362 e_err(probe, "request_irq failed for MSIX interrupt "
2363 "Error: %d\n", err);
2364 goto free_queue_irqs;
2365 }
2366 }
2367
2368 sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2369 err = request_irq(adapter->msix_entries[vector].vector,
2370 ixgbe_msix_lsc, 0, adapter->lsc_int_name, adapter);
2371 if (err) {
2372 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2373 goto free_queue_irqs;
2374 }
2375
2376 return 0;
2377
2378 free_queue_irqs:
2379 for (i = vector - 1; i >= 0; i--)
2380 free_irq(adapter->msix_entries[--vector].vector,
2381 adapter->q_vector[i]);
2382 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2383 pci_disable_msix(adapter->pdev);
2384 kfree(adapter->msix_entries);
2385 adapter->msix_entries = NULL;
2386 return err;
2387 }
2388
2389 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2390 {
2391 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2392 struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2393 struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2394 u32 new_itr = q_vector->eitr;
2395 u8 current_itr;
2396
2397 q_vector->tx.itr = ixgbe_update_itr(adapter, new_itr,
2398 q_vector->tx.itr,
2399 tx_ring->total_packets,
2400 tx_ring->total_bytes);
2401 q_vector->rx.itr = ixgbe_update_itr(adapter, new_itr,
2402 q_vector->rx.itr,
2403 rx_ring->total_packets,
2404 rx_ring->total_bytes);
2405
2406 current_itr = max(q_vector->rx.itr, q_vector->tx.itr);
2407
2408 switch (current_itr) {
2409 /* counts and packets in update_itr are dependent on these numbers */
2410 case lowest_latency:
2411 new_itr = 100000;
2412 break;
2413 case low_latency:
2414 new_itr = 20000; /* aka hwitr = ~200 */
2415 break;
2416 case bulk_latency:
2417 new_itr = 8000;
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 if (new_itr != q_vector->eitr) {
2424 /* do an exponential smoothing */
2425 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2426
2427 /* save the algorithm value here */
2428 q_vector->eitr = new_itr;
2429
2430 ixgbe_write_eitr(q_vector);
2431 }
2432 }
2433
2434 /**
2435 * ixgbe_irq_enable - Enable default interrupt generation settings
2436 * @adapter: board private structure
2437 **/
2438 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2439 bool flush)
2440 {
2441 u32 mask;
2442
2443 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2444 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2445 mask |= IXGBE_EIMS_GPI_SDP0;
2446 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2447 mask |= IXGBE_EIMS_GPI_SDP1;
2448 switch (adapter->hw.mac.type) {
2449 case ixgbe_mac_82599EB:
2450 case ixgbe_mac_X540:
2451 mask |= IXGBE_EIMS_ECC;
2452 mask |= IXGBE_EIMS_GPI_SDP1;
2453 mask |= IXGBE_EIMS_GPI_SDP2;
2454 if (adapter->num_vfs)
2455 mask |= IXGBE_EIMS_MAILBOX;
2456 break;
2457 default:
2458 break;
2459 }
2460 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2461 mask |= IXGBE_EIMS_FLOW_DIR;
2462
2463 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2464 if (queues)
2465 ixgbe_irq_enable_queues(adapter, ~0);
2466 if (flush)
2467 IXGBE_WRITE_FLUSH(&adapter->hw);
2468
2469 if (adapter->num_vfs > 32) {
2470 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2471 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2472 }
2473 }
2474
2475 /**
2476 * ixgbe_intr - legacy mode Interrupt Handler
2477 * @irq: interrupt number
2478 * @data: pointer to a network interface device structure
2479 **/
2480 static irqreturn_t ixgbe_intr(int irq, void *data)
2481 {
2482 struct ixgbe_adapter *adapter = data;
2483 struct ixgbe_hw *hw = &adapter->hw;
2484 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2485 u32 eicr;
2486
2487 /*
2488 * Workaround for silicon errata on 82598. Mask the interrupts
2489 * before the read of EICR.
2490 */
2491 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2492
2493 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2494 * therefore no explict interrupt disable is necessary */
2495 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2496 if (!eicr) {
2497 /*
2498 * shared interrupt alert!
2499 * make sure interrupts are enabled because the read will
2500 * have disabled interrupts due to EIAM
2501 * finish the workaround of silicon errata on 82598. Unmask
2502 * the interrupt that we masked before the EICR read.
2503 */
2504 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2505 ixgbe_irq_enable(adapter, true, true);
2506 return IRQ_NONE; /* Not our interrupt */
2507 }
2508
2509 if (eicr & IXGBE_EICR_LSC)
2510 ixgbe_check_lsc(adapter);
2511
2512 switch (hw->mac.type) {
2513 case ixgbe_mac_82599EB:
2514 ixgbe_check_sfp_event(adapter, eicr);
2515 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2516 ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2517 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2518 adapter->interrupt_event = eicr;
2519 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2520 ixgbe_service_event_schedule(adapter);
2521 }
2522 }
2523 break;
2524 default:
2525 break;
2526 }
2527
2528 ixgbe_check_fan_failure(adapter, eicr);
2529
2530 if (napi_schedule_prep(&(q_vector->napi))) {
2531 adapter->tx_ring[0]->total_packets = 0;
2532 adapter->tx_ring[0]->total_bytes = 0;
2533 adapter->rx_ring[0]->total_packets = 0;
2534 adapter->rx_ring[0]->total_bytes = 0;
2535 /* would disable interrupts here but EIAM disabled it */
2536 __napi_schedule(&(q_vector->napi));
2537 }
2538
2539 /*
2540 * re-enable link(maybe) and non-queue interrupts, no flush.
2541 * ixgbe_poll will re-enable the queue interrupts
2542 */
2543
2544 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2545 ixgbe_irq_enable(adapter, false, false);
2546
2547 return IRQ_HANDLED;
2548 }
2549
2550 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2551 {
2552 int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2553
2554 for (i = 0; i < q_vectors; i++) {
2555 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2556 bitmap_zero(q_vector->rx.idx, MAX_RX_QUEUES);
2557 bitmap_zero(q_vector->tx.idx, MAX_TX_QUEUES);
2558 q_vector->rx.count = 0;
2559 q_vector->tx.count = 0;
2560 }
2561 }
2562
2563 /**
2564 * ixgbe_request_irq - initialize interrupts
2565 * @adapter: board private structure
2566 *
2567 * Attempts to configure interrupts using the best available
2568 * capabilities of the hardware and kernel.
2569 **/
2570 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2571 {
2572 struct net_device *netdev = adapter->netdev;
2573 int err;
2574
2575 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2576 err = ixgbe_request_msix_irqs(adapter);
2577 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2578 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2579 netdev->name, adapter);
2580 } else {
2581 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2582 netdev->name, adapter);
2583 }
2584
2585 if (err)
2586 e_err(probe, "request_irq failed, Error %d\n", err);
2587
2588 return err;
2589 }
2590
2591 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2592 {
2593 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2594 int i, q_vectors;
2595
2596 q_vectors = adapter->num_msix_vectors;
2597
2598 i = q_vectors - 1;
2599 free_irq(adapter->msix_entries[i].vector, adapter);
2600
2601 i--;
2602 for (; i >= 0; i--) {
2603 /* free only the irqs that were actually requested */
2604 if (!adapter->q_vector[i]->rx.count &&
2605 !adapter->q_vector[i]->tx.count)
2606 continue;
2607
2608 free_irq(adapter->msix_entries[i].vector,
2609 adapter->q_vector[i]);
2610 }
2611
2612 ixgbe_reset_q_vectors(adapter);
2613 } else {
2614 free_irq(adapter->pdev->irq, adapter);
2615 }
2616 }
2617
2618 /**
2619 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2620 * @adapter: board private structure
2621 **/
2622 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2623 {
2624 switch (adapter->hw.mac.type) {
2625 case ixgbe_mac_82598EB:
2626 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2627 break;
2628 case ixgbe_mac_82599EB:
2629 case ixgbe_mac_X540:
2630 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2631 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2632 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2633 if (adapter->num_vfs > 32)
2634 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2635 break;
2636 default:
2637 break;
2638 }
2639 IXGBE_WRITE_FLUSH(&adapter->hw);
2640 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2641 int i;
2642 for (i = 0; i < adapter->num_msix_vectors; i++)
2643 synchronize_irq(adapter->msix_entries[i].vector);
2644 } else {
2645 synchronize_irq(adapter->pdev->irq);
2646 }
2647 }
2648
2649 /**
2650 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2651 *
2652 **/
2653 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2654 {
2655 struct ixgbe_hw *hw = &adapter->hw;
2656
2657 IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2658 EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2659
2660 ixgbe_set_ivar(adapter, 0, 0, 0);
2661 ixgbe_set_ivar(adapter, 1, 0, 0);
2662
2663 map_vector_to_rxq(adapter, 0, 0);
2664 map_vector_to_txq(adapter, 0, 0);
2665
2666 e_info(hw, "Legacy interrupt IVAR setup done\n");
2667 }
2668
2669 /**
2670 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2671 * @adapter: board private structure
2672 * @ring: structure containing ring specific data
2673 *
2674 * Configure the Tx descriptor ring after a reset.
2675 **/
2676 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2677 struct ixgbe_ring *ring)
2678 {
2679 struct ixgbe_hw *hw = &adapter->hw;
2680 u64 tdba = ring->dma;
2681 int wait_loop = 10;
2682 u32 txdctl;
2683 u8 reg_idx = ring->reg_idx;
2684
2685 /* disable queue to avoid issues while updating state */
2686 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2687 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2688 txdctl & ~IXGBE_TXDCTL_ENABLE);
2689 IXGBE_WRITE_FLUSH(hw);
2690
2691 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2692 (tdba & DMA_BIT_MASK(32)));
2693 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2694 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2695 ring->count * sizeof(union ixgbe_adv_tx_desc));
2696 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2697 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2698 ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2699
2700 /* configure fetching thresholds */
2701 if (adapter->rx_itr_setting == 0) {
2702 /* cannot set wthresh when itr==0 */
2703 txdctl &= ~0x007F0000;
2704 } else {
2705 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2706 txdctl |= (8 << 16);
2707 }
2708 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2709 /* PThresh workaround for Tx hang with DFP enabled. */
2710 txdctl |= 32;
2711 }
2712
2713 /* reinitialize flowdirector state */
2714 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2715 adapter->atr_sample_rate) {
2716 ring->atr_sample_rate = adapter->atr_sample_rate;
2717 ring->atr_count = 0;
2718 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2719 } else {
2720 ring->atr_sample_rate = 0;
2721 }
2722
2723 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2724
2725 /* enable queue */
2726 txdctl |= IXGBE_TXDCTL_ENABLE;
2727 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2728
2729 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2730 if (hw->mac.type == ixgbe_mac_82598EB &&
2731 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2732 return;
2733
2734 /* poll to verify queue is enabled */
2735 do {
2736 usleep_range(1000, 2000);
2737 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2738 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2739 if (!wait_loop)
2740 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2741 }
2742
2743 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2744 {
2745 struct ixgbe_hw *hw = &adapter->hw;
2746 u32 rttdcs;
2747 u32 reg;
2748 u8 tcs = netdev_get_num_tc(adapter->netdev);
2749
2750 if (hw->mac.type == ixgbe_mac_82598EB)
2751 return;
2752
2753 /* disable the arbiter while setting MTQC */
2754 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2755 rttdcs |= IXGBE_RTTDCS_ARBDIS;
2756 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2757
2758 /* set transmit pool layout */
2759 switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2760 case (IXGBE_FLAG_SRIOV_ENABLED):
2761 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2762 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2763 break;
2764 default:
2765 if (!tcs)
2766 reg = IXGBE_MTQC_64Q_1PB;
2767 else if (tcs <= 4)
2768 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2769 else
2770 reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2771
2772 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2773
2774 /* Enable Security TX Buffer IFG for multiple pb */
2775 if (tcs) {
2776 reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2777 reg |= IXGBE_SECTX_DCB;
2778 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2779 }
2780 break;
2781 }
2782
2783 /* re-enable the arbiter */
2784 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2785 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2786 }
2787
2788 /**
2789 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2790 * @adapter: board private structure
2791 *
2792 * Configure the Tx unit of the MAC after a reset.
2793 **/
2794 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2795 {
2796 struct ixgbe_hw *hw = &adapter->hw;
2797 u32 dmatxctl;
2798 u32 i;
2799
2800 ixgbe_setup_mtqc(adapter);
2801
2802 if (hw->mac.type != ixgbe_mac_82598EB) {
2803 /* DMATXCTL.EN must be before Tx queues are enabled */
2804 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2805 dmatxctl |= IXGBE_DMATXCTL_TE;
2806 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2807 }
2808
2809 /* Setup the HW Tx Head and Tail descriptor pointers */
2810 for (i = 0; i < adapter->num_tx_queues; i++)
2811 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2812 }
2813
2814 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2815
2816 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2817 struct ixgbe_ring *rx_ring)
2818 {
2819 u32 srrctl;
2820 u8 reg_idx = rx_ring->reg_idx;
2821
2822 switch (adapter->hw.mac.type) {
2823 case ixgbe_mac_82598EB: {
2824 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2825 const int mask = feature[RING_F_RSS].mask;
2826 reg_idx = reg_idx & mask;
2827 }
2828 break;
2829 case ixgbe_mac_82599EB:
2830 case ixgbe_mac_X540:
2831 default:
2832 break;
2833 }
2834
2835 srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2836
2837 srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2838 srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2839 if (adapter->num_vfs)
2840 srrctl |= IXGBE_SRRCTL_DROP_EN;
2841
2842 srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2843 IXGBE_SRRCTL_BSIZEHDR_MASK;
2844
2845 if (ring_is_ps_enabled(rx_ring)) {
2846 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2847 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2848 #else
2849 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2850 #endif
2851 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2852 } else {
2853 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2854 IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2855 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2856 }
2857
2858 IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2859 }
2860
2861 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2862 {
2863 struct ixgbe_hw *hw = &adapter->hw;
2864 static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2865 0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2866 0x6A3E67EA, 0x14364D17, 0x3BED200D};
2867 u32 mrqc = 0, reta = 0;
2868 u32 rxcsum;
2869 int i, j;
2870 u8 tcs = netdev_get_num_tc(adapter->netdev);
2871 int maxq = adapter->ring_feature[RING_F_RSS].indices;
2872
2873 if (tcs)
2874 maxq = min(maxq, adapter->num_tx_queues / tcs);
2875
2876 /* Fill out hash function seeds */
2877 for (i = 0; i < 10; i++)
2878 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2879
2880 /* Fill out redirection table */
2881 for (i = 0, j = 0; i < 128; i++, j++) {
2882 if (j == maxq)
2883 j = 0;
2884 /* reta = 4-byte sliding window of
2885 * 0x00..(indices-1)(indices-1)00..etc. */
2886 reta = (reta << 8) | (j * 0x11);
2887 if ((i & 3) == 3)
2888 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2889 }
2890
2891 /* Disable indicating checksum in descriptor, enables RSS hash */
2892 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2893 rxcsum |= IXGBE_RXCSUM_PCSD;
2894 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2895
2896 if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2897 (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2898 mrqc = IXGBE_MRQC_RSSEN;
2899 } else {
2900 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2901 | IXGBE_FLAG_SRIOV_ENABLED);
2902
2903 switch (mask) {
2904 case (IXGBE_FLAG_RSS_ENABLED):
2905 if (!tcs)
2906 mrqc = IXGBE_MRQC_RSSEN;
2907 else if (tcs <= 4)
2908 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2909 else
2910 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2911 break;
2912 case (IXGBE_FLAG_SRIOV_ENABLED):
2913 mrqc = IXGBE_MRQC_VMDQEN;
2914 break;
2915 default:
2916 break;
2917 }
2918 }
2919
2920 /* Perform hash on these packet types */
2921 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2922 | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2923 | IXGBE_MRQC_RSS_FIELD_IPV6
2924 | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2925
2926 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2927 }
2928
2929 /**
2930 * ixgbe_clear_rscctl - disable RSC for the indicated ring
2931 * @adapter: address of board private structure
2932 * @ring: structure containing ring specific data
2933 **/
2934 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2935 struct ixgbe_ring *ring)
2936 {
2937 struct ixgbe_hw *hw = &adapter->hw;
2938 u32 rscctrl;
2939 u8 reg_idx = ring->reg_idx;
2940
2941 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2942 rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2943 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2944 }
2945
2946 /**
2947 * ixgbe_configure_rscctl - enable RSC for the indicated ring
2948 * @adapter: address of board private structure
2949 * @index: index of ring to set
2950 **/
2951 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2952 struct ixgbe_ring *ring)
2953 {
2954 struct ixgbe_hw *hw = &adapter->hw;
2955 u32 rscctrl;
2956 int rx_buf_len;
2957 u8 reg_idx = ring->reg_idx;
2958
2959 if (!ring_is_rsc_enabled(ring))
2960 return;
2961
2962 rx_buf_len = ring->rx_buf_len;
2963 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2964 rscctrl |= IXGBE_RSCCTL_RSCEN;
2965 /*
2966 * we must limit the number of descriptors so that the
2967 * total size of max desc * buf_len is not greater
2968 * than 65535
2969 */
2970 if (ring_is_ps_enabled(ring)) {
2971 #if (MAX_SKB_FRAGS > 16)
2972 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2973 #elif (MAX_SKB_FRAGS > 8)
2974 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2975 #elif (MAX_SKB_FRAGS > 4)
2976 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2977 #else
2978 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2979 #endif
2980 } else {
2981 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2982 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2983 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2984 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2985 else
2986 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2987 }
2988 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2989 }
2990
2991 /**
2992 * ixgbe_set_uta - Set unicast filter table address
2993 * @adapter: board private structure
2994 *
2995 * The unicast table address is a register array of 32-bit registers.
2996 * The table is meant to be used in a way similar to how the MTA is used
2997 * however due to certain limitations in the hardware it is necessary to
2998 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
2999 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
3000 **/
3001 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3002 {
3003 struct ixgbe_hw *hw = &adapter->hw;
3004 int i;
3005
3006 /* The UTA table only exists on 82599 hardware and newer */
3007 if (hw->mac.type < ixgbe_mac_82599EB)
3008 return;
3009
3010 /* we only need to do this if VMDq is enabled */
3011 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3012 return;
3013
3014 for (i = 0; i < 128; i++)
3015 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3016 }
3017
3018 #define IXGBE_MAX_RX_DESC_POLL 10
3019 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3020 struct ixgbe_ring *ring)
3021 {
3022 struct ixgbe_hw *hw = &adapter->hw;
3023 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3024 u32 rxdctl;
3025 u8 reg_idx = ring->reg_idx;
3026
3027 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3028 if (hw->mac.type == ixgbe_mac_82598EB &&
3029 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3030 return;
3031
3032 do {
3033 usleep_range(1000, 2000);
3034 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3035 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3036
3037 if (!wait_loop) {
3038 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3039 "the polling period\n", reg_idx);
3040 }
3041 }
3042
3043 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3044 struct ixgbe_ring *ring)
3045 {
3046 struct ixgbe_hw *hw = &adapter->hw;
3047 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3048 u32 rxdctl;
3049 u8 reg_idx = ring->reg_idx;
3050
3051 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3052 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3053
3054 /* write value back with RXDCTL.ENABLE bit cleared */
3055 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3056
3057 if (hw->mac.type == ixgbe_mac_82598EB &&
3058 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3059 return;
3060
3061 /* the hardware may take up to 100us to really disable the rx queue */
3062 do {
3063 udelay(10);
3064 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3065 } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3066
3067 if (!wait_loop) {
3068 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3069 "the polling period\n", reg_idx);
3070 }
3071 }
3072
3073 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3074 struct ixgbe_ring *ring)
3075 {
3076 struct ixgbe_hw *hw = &adapter->hw;
3077 u64 rdba = ring->dma;
3078 u32 rxdctl;
3079 u8 reg_idx = ring->reg_idx;
3080
3081 /* disable queue to avoid issues while updating state */
3082 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3083 ixgbe_disable_rx_queue(adapter, ring);
3084
3085 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3086 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3087 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3088 ring->count * sizeof(union ixgbe_adv_rx_desc));
3089 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3090 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3091 ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3092
3093 ixgbe_configure_srrctl(adapter, ring);
3094 ixgbe_configure_rscctl(adapter, ring);
3095
3096 /* If operating in IOV mode set RLPML for X540 */
3097 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3098 hw->mac.type == ixgbe_mac_X540) {
3099 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3100 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3101 ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3102 }
3103
3104 if (hw->mac.type == ixgbe_mac_82598EB) {
3105 /*
3106 * enable cache line friendly hardware writes:
3107 * PTHRESH=32 descriptors (half the internal cache),
3108 * this also removes ugly rx_no_buffer_count increment
3109 * HTHRESH=4 descriptors (to minimize latency on fetch)
3110 * WTHRESH=8 burst writeback up to two cache lines
3111 */
3112 rxdctl &= ~0x3FFFFF;
3113 rxdctl |= 0x080420;
3114 }
3115
3116 /* enable receive descriptor ring */
3117 rxdctl |= IXGBE_RXDCTL_ENABLE;
3118 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3119
3120 ixgbe_rx_desc_queue_enable(adapter, ring);
3121 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
3122 }
3123
3124 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3125 {
3126 struct ixgbe_hw *hw = &adapter->hw;
3127 int p;
3128
3129 /* PSRTYPE must be initialized in non 82598 adapters */
3130 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3131 IXGBE_PSRTYPE_UDPHDR |
3132 IXGBE_PSRTYPE_IPV4HDR |
3133 IXGBE_PSRTYPE_L2HDR |
3134 IXGBE_PSRTYPE_IPV6HDR;
3135
3136 if (hw->mac.type == ixgbe_mac_82598EB)
3137 return;
3138
3139 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3140 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3141
3142 for (p = 0; p < adapter->num_rx_pools; p++)
3143 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3144 psrtype);
3145 }
3146
3147 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3148 {
3149 struct ixgbe_hw *hw = &adapter->hw;
3150 u32 gcr_ext;
3151 u32 vt_reg_bits;
3152 u32 reg_offset, vf_shift;
3153 u32 vmdctl;
3154
3155 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3156 return;
3157
3158 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3159 vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3160 vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3161 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3162
3163 vf_shift = adapter->num_vfs % 32;
3164 reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3165
3166 /* Enable only the PF's pool for Tx/Rx */
3167 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3168 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3169 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3170 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3171 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3172
3173 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3174 hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3175
3176 /*
3177 * Set up VF register offsets for selected VT Mode,
3178 * i.e. 32 or 64 VFs for SR-IOV
3179 */
3180 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3181 gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3182 gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3183 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3184
3185 /* enable Tx loopback for VF/PF communication */
3186 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3187 /* Enable MAC Anti-Spoofing */
3188 hw->mac.ops.set_mac_anti_spoofing(hw,
3189 (adapter->antispoofing_enabled =
3190 (adapter->num_vfs != 0)),
3191 adapter->num_vfs);
3192 }
3193
3194 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3195 {
3196 struct ixgbe_hw *hw = &adapter->hw;
3197 struct net_device *netdev = adapter->netdev;
3198 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3199 int rx_buf_len;
3200 struct ixgbe_ring *rx_ring;
3201 int i;
3202 u32 mhadd, hlreg0;
3203
3204 /* Decide whether to use packet split mode or not */
3205 /* On by default */
3206 adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3207
3208 /* Do not use packet split if we're in SR-IOV Mode */
3209 if (adapter->num_vfs)
3210 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3211
3212 /* Disable packet split due to 82599 erratum #45 */
3213 if (hw->mac.type == ixgbe_mac_82599EB)
3214 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3215
3216 /* Set the RX buffer length according to the mode */
3217 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3218 rx_buf_len = IXGBE_RX_HDR_SIZE;
3219 } else {
3220 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3221 (netdev->mtu <= ETH_DATA_LEN))
3222 rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3223 else
3224 rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3225 }
3226
3227 #ifdef IXGBE_FCOE
3228 /* adjust max frame to be able to do baby jumbo for FCoE */
3229 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3230 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3231 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3232
3233 #endif /* IXGBE_FCOE */
3234 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3235 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3236 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3237 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3238
3239 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3240 }
3241
3242 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3243 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3244 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3245 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3246
3247 /*
3248 * Setup the HW Rx Head and Tail Descriptor Pointers and
3249 * the Base and Length of the Rx Descriptor Ring
3250 */
3251 for (i = 0; i < adapter->num_rx_queues; i++) {
3252 rx_ring = adapter->rx_ring[i];
3253 rx_ring->rx_buf_len = rx_buf_len;
3254
3255 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3256 set_ring_ps_enabled(rx_ring);
3257 else
3258 clear_ring_ps_enabled(rx_ring);
3259
3260 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3261 set_ring_rsc_enabled(rx_ring);
3262 else
3263 clear_ring_rsc_enabled(rx_ring);
3264
3265 #ifdef IXGBE_FCOE
3266 if (netdev->features & NETIF_F_FCOE_MTU) {
3267 struct ixgbe_ring_feature *f;
3268 f = &adapter->ring_feature[RING_F_FCOE];
3269 if ((i >= f->mask) && (i < f->mask + f->indices)) {
3270 clear_ring_ps_enabled(rx_ring);
3271 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3272 rx_ring->rx_buf_len =
3273 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3274 } else if (!ring_is_rsc_enabled(rx_ring) &&
3275 !ring_is_ps_enabled(rx_ring)) {
3276 rx_ring->rx_buf_len =
3277 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3278 }
3279 }
3280 #endif /* IXGBE_FCOE */
3281 }
3282 }
3283
3284 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3285 {
3286 struct ixgbe_hw *hw = &adapter->hw;
3287 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3288
3289 switch (hw->mac.type) {
3290 case ixgbe_mac_82598EB:
3291 /*
3292 * For VMDq support of different descriptor types or
3293 * buffer sizes through the use of multiple SRRCTL
3294 * registers, RDRXCTL.MVMEN must be set to 1
3295 *
3296 * also, the manual doesn't mention it clearly but DCA hints
3297 * will only use queue 0's tags unless this bit is set. Side
3298 * effects of setting this bit are only that SRRCTL must be
3299 * fully programmed [0..15]
3300 */
3301 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3302 break;
3303 case ixgbe_mac_82599EB:
3304 case ixgbe_mac_X540:
3305 /* Disable RSC for ACK packets */
3306 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3307 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3308 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3309 /* hardware requires some bits to be set by default */
3310 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3311 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3312 break;
3313 default:
3314 /* We should do nothing since we don't know this hardware */
3315 return;
3316 }
3317
3318 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3319 }
3320
3321 /**
3322 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3323 * @adapter: board private structure
3324 *
3325 * Configure the Rx unit of the MAC after a reset.
3326 **/
3327 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3328 {
3329 struct ixgbe_hw *hw = &adapter->hw;
3330 int i;
3331 u32 rxctrl;
3332
3333 /* disable receives while setting up the descriptors */
3334 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3335 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3336
3337 ixgbe_setup_psrtype(adapter);
3338 ixgbe_setup_rdrxctl(adapter);
3339
3340 /* Program registers for the distribution of queues */
3341 ixgbe_setup_mrqc(adapter);
3342
3343 ixgbe_set_uta(adapter);
3344
3345 /* set_rx_buffer_len must be called before ring initialization */
3346 ixgbe_set_rx_buffer_len(adapter);
3347
3348 /*
3349 * Setup the HW Rx Head and Tail Descriptor Pointers and
3350 * the Base and Length of the Rx Descriptor Ring
3351 */
3352 for (i = 0; i < adapter->num_rx_queues; i++)
3353 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3354
3355 /* disable drop enable for 82598 parts */
3356 if (hw->mac.type == ixgbe_mac_82598EB)
3357 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3358
3359 /* enable all receives */
3360 rxctrl |= IXGBE_RXCTRL_RXEN;
3361 hw->mac.ops.enable_rx_dma(hw, rxctrl);
3362 }
3363
3364 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3365 {
3366 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3367 struct ixgbe_hw *hw = &adapter->hw;
3368 int pool_ndx = adapter->num_vfs;
3369
3370 /* add VID to filter table */
3371 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3372 set_bit(vid, adapter->active_vlans);
3373 }
3374
3375 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3376 {
3377 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3378 struct ixgbe_hw *hw = &adapter->hw;
3379 int pool_ndx = adapter->num_vfs;
3380
3381 /* remove VID from filter table */
3382 hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3383 clear_bit(vid, adapter->active_vlans);
3384 }
3385
3386 /**
3387 * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3388 * @adapter: driver data
3389 */
3390 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3391 {
3392 struct ixgbe_hw *hw = &adapter->hw;
3393 u32 vlnctrl;
3394
3395 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3396 vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3397 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3398 }
3399
3400 /**
3401 * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3402 * @adapter: driver data
3403 */
3404 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3405 {
3406 struct ixgbe_hw *hw = &adapter->hw;
3407 u32 vlnctrl;
3408
3409 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3410 vlnctrl |= IXGBE_VLNCTRL_VFE;
3411 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3412 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3413 }
3414
3415 /**
3416 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3417 * @adapter: driver data
3418 */
3419 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3420 {
3421 struct ixgbe_hw *hw = &adapter->hw;
3422 u32 vlnctrl;
3423 int i, j;
3424
3425 switch (hw->mac.type) {
3426 case ixgbe_mac_82598EB:
3427 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3428 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3429 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3430 break;
3431 case ixgbe_mac_82599EB:
3432 case ixgbe_mac_X540:
3433 for (i = 0; i < adapter->num_rx_queues; i++) {
3434 j = adapter->rx_ring[i]->reg_idx;
3435 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3436 vlnctrl &= ~IXGBE_RXDCTL_VME;
3437 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3438 }
3439 break;
3440 default:
3441 break;
3442 }
3443 }
3444
3445 /**
3446 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3447 * @adapter: driver data
3448 */
3449 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3450 {
3451 struct ixgbe_hw *hw = &adapter->hw;
3452 u32 vlnctrl;
3453 int i, j;
3454
3455 switch (hw->mac.type) {
3456 case ixgbe_mac_82598EB:
3457 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3458 vlnctrl |= IXGBE_VLNCTRL_VME;
3459 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3460 break;
3461 case ixgbe_mac_82599EB:
3462 case ixgbe_mac_X540:
3463 for (i = 0; i < adapter->num_rx_queues; i++) {
3464 j = adapter->rx_ring[i]->reg_idx;
3465 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3466 vlnctrl |= IXGBE_RXDCTL_VME;
3467 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3468 }
3469 break;
3470 default:
3471 break;
3472 }
3473 }
3474
3475 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3476 {
3477 u16 vid;
3478
3479 ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3480
3481 for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3482 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3483 }
3484
3485 /**
3486 * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3487 * @netdev: network interface device structure
3488 *
3489 * Writes unicast address list to the RAR table.
3490 * Returns: -ENOMEM on failure/insufficient address space
3491 * 0 on no addresses written
3492 * X on writing X addresses to the RAR table
3493 **/
3494 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3495 {
3496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3497 struct ixgbe_hw *hw = &adapter->hw;
3498 unsigned int vfn = adapter->num_vfs;
3499 unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3500 int count = 0;
3501
3502 /* return ENOMEM indicating insufficient memory for addresses */
3503 if (netdev_uc_count(netdev) > rar_entries)
3504 return -ENOMEM;
3505
3506 if (!netdev_uc_empty(netdev) && rar_entries) {
3507 struct netdev_hw_addr *ha;
3508 /* return error if we do not support writing to RAR table */
3509 if (!hw->mac.ops.set_rar)
3510 return -ENOMEM;
3511
3512 netdev_for_each_uc_addr(ha, netdev) {
3513 if (!rar_entries)
3514 break;
3515 hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3516 vfn, IXGBE_RAH_AV);
3517 count++;
3518 }
3519 }
3520 /* write the addresses in reverse order to avoid write combining */
3521 for (; rar_entries > 0 ; rar_entries--)
3522 hw->mac.ops.clear_rar(hw, rar_entries);
3523
3524 return count;
3525 }
3526
3527 /**
3528 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3529 * @netdev: network interface device structure
3530 *
3531 * The set_rx_method entry point is called whenever the unicast/multicast
3532 * address list or the network interface flags are updated. This routine is
3533 * responsible for configuring the hardware for proper unicast, multicast and
3534 * promiscuous mode.
3535 **/
3536 void ixgbe_set_rx_mode(struct net_device *netdev)
3537 {
3538 struct ixgbe_adapter *adapter = netdev_priv(netdev);
3539 struct ixgbe_hw *hw = &adapter->hw;
3540 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3541 int count;
3542
3543 /* Check for Promiscuous and All Multicast modes */
3544
3545 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3546
3547 /* set all bits that we expect to always be set */
3548 fctrl |= IXGBE_FCTRL_BAM;
3549 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3550 fctrl |= IXGBE_FCTRL_PMCF;
3551
3552 /* clear the bits we are changing the status of */
3553 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3554
3555 if (netdev->flags & IFF_PROMISC) {
3556 hw->addr_ctrl.user_set_promisc = true;
3557 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3558 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3559 /* don't hardware filter vlans in promisc mode */
3560 ixgbe_vlan_filter_disable(adapter);
3561 } else {
3562 if (netdev->flags & IFF_ALLMULTI) {
3563 fctrl |= IXGBE_FCTRL_MPE;
3564 vmolr |= IXGBE_VMOLR_MPE;
3565 } else {
3566 /*
3567 * Write addresses to the MTA, if the attempt fails
3568 * then we should just turn on promiscuous mode so
3569 * that we can at least receive multicast traffic
3570 */
3571 hw->mac.ops.update_mc_addr_list(hw, netdev);
3572 vmolr |= IXGBE_VMOLR_ROMPE;
3573 }
3574 ixgbe_vlan_filter_enable(adapter);
3575 hw->addr_ctrl.user_set_promisc = false;
3576 /*
3577 * Write addresses to available RAR registers, if there is not
3578 * sufficient space to store all the addresses then enable
3579 * unicast promiscuous mode
3580 */
3581 count = ixgbe_write_uc_addr_list(netdev);
3582 if (count < 0) {
3583 fctrl |= IXGBE_FCTRL_UPE;
3584 vmolr |= IXGBE_VMOLR_ROPE;
3585 }
3586 }
3587
3588 if (adapter->num_vfs) {
3589 ixgbe_restore_vf_multicasts(adapter);
3590 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3591 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3592 IXGBE_VMOLR_ROPE);
3593 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3594 }
3595
3596 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3597
3598 if (netdev->features & NETIF_F_HW_VLAN_RX)
3599 ixgbe_vlan_strip_enable(adapter);
3600 else
3601 ixgbe_vlan_strip_disable(adapter);
3602 }
3603
3604 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3605 {
3606 int q_idx;
3607 struct ixgbe_q_vector *q_vector;
3608 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3609
3610 /* legacy and MSI only use one vector */
3611 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3612 q_vectors = 1;
3613
3614 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3615 struct napi_struct *napi;
3616 q_vector = adapter->q_vector[q_idx];
3617 napi = &q_vector->napi;
3618 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3619 if (!q_vector->rx.count || !q_vector->tx.count) {
3620 if (q_vector->tx.count == 1)
3621 napi->poll = &ixgbe_clean_txonly;
3622 else if (q_vector->rx.count == 1)
3623 napi->poll = &ixgbe_clean_rxonly;
3624 }
3625 }
3626
3627 napi_enable(napi);
3628 }
3629 }
3630
3631 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3632 {
3633 int q_idx;
3634 struct ixgbe_q_vector *q_vector;
3635 int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3636
3637 /* legacy and MSI only use one vector */
3638 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3639 q_vectors = 1;
3640
3641 for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3642 q_vector = adapter->q_vector[q_idx];
3643 napi_disable(&q_vector->napi);
3644 }
3645 }
3646
3647 #ifdef CONFIG_IXGBE_DCB
3648 /*
3649 * ixgbe_configure_dcb - Configure DCB hardware
3650 * @adapter: ixgbe adapter struct
3651 *
3652 * This is called by the driver on open to configure the DCB hardware.
3653 * This is also called by the gennetlink interface when reconfiguring
3654 * the DCB state.
3655 */
3656 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3657 {
3658 struct ixgbe_hw *hw = &adapter->hw;
3659 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3660
3661 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3662 if (hw->mac.type == ixgbe_mac_82598EB)
3663 netif_set_gso_max_size(adapter->netdev, 65536);
3664 return;
3665 }
3666
3667 if (hw->mac.type == ixgbe_mac_82598EB)
3668 netif_set_gso_max_size(adapter->netdev, 32768);
3669
3670
3671 /* Enable VLAN tag insert/strip */
3672 adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3673
3674 hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3675
3676 /* reconfigure the hardware */
3677 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3678 #ifdef CONFIG_FCOE
3679 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3680 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3681 #endif
3682 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3683 DCB_TX_CONFIG);
3684 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3685 DCB_RX_CONFIG);
3686 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3687 } else {
3688 struct net_device *dev = adapter->netdev;
3689
3690 if (adapter->ixgbe_ieee_ets)
3691 dev->dcbnl_ops->ieee_setets(dev,
3692 adapter->ixgbe_ieee_ets);
3693 if (adapter->ixgbe_ieee_pfc)
3694 dev->dcbnl_ops->ieee_setpfc(dev,
3695 adapter->ixgbe_ieee_pfc);
3696 }
3697
3698 /* Enable RSS Hash per TC */
3699 if (hw->mac.type != ixgbe_mac_82598EB) {
3700 int i;
3701 u32 reg = 0;
3702
3703 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3704 u8 msb = 0;
3705 u8 cnt = adapter->netdev->tc_to_txq[i].count;
3706
3707 while (cnt >>= 1)
3708 msb++;
3709
3710 reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3711 }
3712 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3713 }
3714 }
3715
3716 #endif
3717
3718 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3719 {
3720 int hdrm = 0;
3721 int num_tc = netdev_get_num_tc(adapter->netdev);
3722 struct ixgbe_hw *hw = &adapter->hw;
3723
3724 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3725 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3726 hdrm = 64 << adapter->fdir_pballoc;
3727
3728 hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3729 }
3730
3731 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
3732 {
3733 struct ixgbe_hw *hw = &adapter->hw;
3734 struct hlist_node *node, *node2;
3735 struct ixgbe_fdir_filter *filter;
3736
3737 spin_lock(&adapter->fdir_perfect_lock);
3738
3739 if (!hlist_empty(&adapter->fdir_filter_list))
3740 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
3741
3742 hlist_for_each_entry_safe(filter, node, node2,
3743 &adapter->fdir_filter_list, fdir_node) {
3744 ixgbe_fdir_write_perfect_filter_82599(hw,
3745 &filter->filter,
3746 filter->sw_idx,
3747 (filter->action == IXGBE_FDIR_DROP_QUEUE) ?
3748 IXGBE_FDIR_DROP_QUEUE :
3749 adapter->rx_ring[filter->action]->reg_idx);
3750 }
3751
3752 spin_unlock(&adapter->fdir_perfect_lock);
3753 }
3754
3755 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3756 {
3757 struct net_device *netdev = adapter->netdev;
3758 struct ixgbe_hw *hw = &adapter->hw;
3759 int i;
3760
3761 ixgbe_configure_pb(adapter);
3762 #ifdef CONFIG_IXGBE_DCB
3763 ixgbe_configure_dcb(adapter);
3764 #endif
3765
3766 ixgbe_set_rx_mode(netdev);
3767 ixgbe_restore_vlan(adapter);
3768
3769 #ifdef IXGBE_FCOE
3770 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3771 ixgbe_configure_fcoe(adapter);
3772
3773 #endif /* IXGBE_FCOE */
3774 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3775 for (i = 0; i < adapter->num_tx_queues; i++)
3776 adapter->tx_ring[i]->atr_sample_rate =
3777 adapter->atr_sample_rate;
3778 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3779 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
3780 ixgbe_init_fdir_perfect_82599(&adapter->hw,
3781 adapter->fdir_pballoc);
3782 ixgbe_fdir_filter_restore(adapter);
3783 }
3784 ixgbe_configure_virtualization(adapter);
3785
3786 ixgbe_configure_tx(adapter);
3787 ixgbe_configure_rx(adapter);
3788 }
3789
3790 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3791 {
3792 switch (hw->phy.type) {
3793 case ixgbe_phy_sfp_avago:
3794 case ixgbe_phy_sfp_ftl:
3795 case ixgbe_phy_sfp_intel:
3796 case ixgbe_phy_sfp_unknown:
3797 case ixgbe_phy_sfp_passive_tyco:
3798 case ixgbe_phy_sfp_passive_unknown:
3799 case ixgbe_phy_sfp_active_unknown:
3800 case ixgbe_phy_sfp_ftl_active:
3801 return true;
3802 default:
3803 return false;
3804 }
3805 }
3806
3807 /**
3808 * ixgbe_sfp_link_config - set up SFP+ link
3809 * @adapter: pointer to private adapter struct
3810 **/
3811 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3812 {
3813 /*
3814 * We are assuming the worst case scenerio here, and that
3815 * is that an SFP was inserted/removed after the reset
3816 * but before SFP detection was enabled. As such the best
3817 * solution is to just start searching as soon as we start
3818 */
3819 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3820 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3821
3822 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3823 }
3824
3825 /**
3826 * ixgbe_non_sfp_link_config - set up non-SFP+ link
3827 * @hw: pointer to private hardware struct
3828 *
3829 * Returns 0 on success, negative on failure
3830 **/
3831 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3832 {
3833 u32 autoneg;
3834 bool negotiation, link_up = false;
3835 u32 ret = IXGBE_ERR_LINK_SETUP;
3836
3837 if (hw->mac.ops.check_link)
3838 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3839
3840 if (ret)
3841 goto link_cfg_out;
3842
3843 autoneg = hw->phy.autoneg_advertised;
3844 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3845 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3846 &negotiation);
3847 if (ret)
3848 goto link_cfg_out;
3849
3850 if (hw->mac.ops.setup_link)
3851 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3852 link_cfg_out:
3853 return ret;
3854 }
3855
3856 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3857 {
3858 struct ixgbe_hw *hw = &adapter->hw;
3859 u32 gpie = 0;
3860
3861 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3862 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3863 IXGBE_GPIE_OCD;
3864 gpie |= IXGBE_GPIE_EIAME;
3865 /*
3866 * use EIAM to auto-mask when MSI-X interrupt is asserted
3867 * this saves a register write for every interrupt
3868 */
3869 switch (hw->mac.type) {
3870 case ixgbe_mac_82598EB:
3871 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3872 break;
3873 case ixgbe_mac_82599EB:
3874 case ixgbe_mac_X540:
3875 default:
3876 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3877 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3878 break;
3879 }
3880 } else {
3881 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3882 * specifically only auto mask tx and rx interrupts */
3883 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3884 }
3885
3886 /* XXX: to interrupt immediately for EICS writes, enable this */
3887 /* gpie |= IXGBE_GPIE_EIMEN; */
3888
3889 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3890 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3891 gpie |= IXGBE_GPIE_VTMODE_64;
3892 }
3893
3894 /* Enable fan failure interrupt */
3895 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3896 gpie |= IXGBE_SDP1_GPIEN;
3897
3898 if (hw->mac.type == ixgbe_mac_82599EB) {
3899 gpie |= IXGBE_SDP1_GPIEN;
3900 gpie |= IXGBE_SDP2_GPIEN;
3901 }
3902
3903 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3904 }
3905
3906 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3907 {
3908 struct ixgbe_hw *hw = &adapter->hw;
3909 int err;
3910 u32 ctrl_ext;
3911
3912 ixgbe_get_hw_control(adapter);
3913 ixgbe_setup_gpie(adapter);
3914
3915 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3916 ixgbe_configure_msix(adapter);
3917 else
3918 ixgbe_configure_msi_and_legacy(adapter);
3919
3920 /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3921 if (hw->mac.ops.enable_tx_laser &&
3922 ((hw->phy.multispeed_fiber) ||
3923 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3924 (hw->mac.type == ixgbe_mac_82599EB))))
3925 hw->mac.ops.enable_tx_laser(hw);
3926
3927 clear_bit(__IXGBE_DOWN, &adapter->state);
3928 ixgbe_napi_enable_all(adapter);
3929
3930 if (ixgbe_is_sfp(hw)) {
3931 ixgbe_sfp_link_config(adapter);
3932 } else {
3933 err = ixgbe_non_sfp_link_config(hw);
3934 if (err)
3935 e_err(probe, "link_config FAILED %d\n", err);
3936 }
3937
3938 /* clear any pending interrupts, may auto mask */
3939 IXGBE_READ_REG(hw, IXGBE_EICR);
3940 ixgbe_irq_enable(adapter, true, true);
3941
3942 /*
3943 * If this adapter has a fan, check to see if we had a failure
3944 * before we enabled the interrupt.
3945 */
3946 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3947 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3948 if (esdp & IXGBE_ESDP_SDP1)
3949 e_crit(drv, "Fan has stopped, replace the adapter\n");
3950 }
3951
3952 /* enable transmits */
3953 netif_tx_start_all_queues(adapter->netdev);
3954
3955 /* bring the link up in the watchdog, this could race with our first
3956 * link up interrupt but shouldn't be a problem */
3957 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3958 adapter->link_check_timeout = jiffies;
3959 mod_timer(&adapter->service_timer, jiffies);
3960
3961 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3962 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3963 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3964 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3965
3966 return 0;
3967 }
3968
3969 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3970 {
3971 WARN_ON(in_interrupt());
3972 /* put off any impending NetWatchDogTimeout */
3973 adapter->netdev->trans_start = jiffies;
3974
3975 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3976 usleep_range(1000, 2000);
3977 ixgbe_down(adapter);
3978 /*
3979 * If SR-IOV enabled then wait a bit before bringing the adapter
3980 * back up to give the VFs time to respond to the reset. The
3981 * two second wait is based upon the watchdog timer cycle in
3982 * the VF driver.
3983 */
3984 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3985 msleep(2000);
3986 ixgbe_up(adapter);
3987 clear_bit(__IXGBE_RESETTING, &adapter->state);
3988 }
3989
3990 int ixgbe_up(struct ixgbe_adapter *adapter)
3991 {
3992 /* hardware has been reset, we need to reload some things */
3993 ixgbe_configure(adapter);
3994
3995 return ixgbe_up_complete(adapter);
3996 }
3997
3998 void ixgbe_reset(struct ixgbe_adapter *adapter)
3999 {
4000 struct ixgbe_hw *hw = &adapter->hw;
4001 int err;
4002
4003 /* lock SFP init bit to prevent race conditions with the watchdog */
4004 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
4005 usleep_range(1000, 2000);
4006
4007 /* clear all SFP and link config related flags while holding SFP_INIT */
4008 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
4009 IXGBE_FLAG2_SFP_NEEDS_RESET);
4010 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
4011
4012 err = hw->mac.ops.init_hw(hw);
4013 switch (err) {
4014 case 0:
4015 case IXGBE_ERR_SFP_NOT_PRESENT:
4016 case IXGBE_ERR_SFP_NOT_SUPPORTED:
4017 break;
4018 case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4019 e_dev_err("master disable timed out\n");
4020 break;
4021 case IXGBE_ERR_EEPROM_VERSION:
4022 /* We are running on a pre-production device, log a warning */
4023 e_dev_warn("This device is a pre-production adapter/LOM. "
4024 "Please be aware there may be issuesassociated with "
4025 "your hardware. If you are experiencing problems "
4026 "please contact your Intel or hardware "
4027 "representative who provided you with this "
4028 "hardware.\n");
4029 break;
4030 default:
4031 e_dev_err("Hardware Error: %d\n", err);
4032 }
4033
4034 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4035
4036 /* reprogram the RAR[0] in case user changed it. */
4037 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4038 IXGBE_RAH_AV);
4039 }
4040
4041 /**
4042 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4043 * @rx_ring: ring to free buffers from
4044 **/
4045 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4046 {
4047 struct device *dev = rx_ring->dev;
4048 unsigned long size;
4049 u16 i;
4050
4051 /* ring already cleared, nothing to do */
4052 if (!rx_ring->rx_buffer_info)
4053 return;
4054
4055 /* Free all the Rx ring sk_buffs */
4056 for (i = 0; i < rx_ring->count; i++) {
4057 struct ixgbe_rx_buffer *rx_buffer_info;
4058
4059 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4060 if (rx_buffer_info->dma) {
4061 dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4062 rx_ring->rx_buf_len,
4063 DMA_FROM_DEVICE);
4064 rx_buffer_info->dma = 0;
4065 }
4066 if (rx_buffer_info->skb) {
4067 struct sk_buff *skb = rx_buffer_info->skb;
4068 rx_buffer_info->skb = NULL;
4069 do {
4070 struct sk_buff *this = skb;
4071 if (IXGBE_RSC_CB(this)->delay_unmap) {
4072 dma_unmap_single(dev,
4073 IXGBE_RSC_CB(this)->dma,
4074 rx_ring->rx_buf_len,
4075 DMA_FROM_DEVICE);
4076 IXGBE_RSC_CB(this)->dma = 0;
4077 IXGBE_RSC_CB(skb)->delay_unmap = false;
4078 }
4079 skb = skb->prev;
4080 dev_kfree_skb(this);
4081 } while (skb);
4082 }
4083 if (!rx_buffer_info->page)
4084 continue;
4085 if (rx_buffer_info->page_dma) {
4086 dma_unmap_page(dev, rx_buffer_info->page_dma,
4087 PAGE_SIZE / 2, DMA_FROM_DEVICE);
4088 rx_buffer_info->page_dma = 0;
4089 }
4090 put_page(rx_buffer_info->page);
4091 rx_buffer_info->page = NULL;
4092 rx_buffer_info->page_offset = 0;
4093 }
4094
4095 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4096 memset(rx_ring->rx_buffer_info, 0, size);
4097
4098 /* Zero out the descriptor ring */
4099 memset(rx_ring->desc, 0, rx_ring->size);
4100
4101 rx_ring->next_to_clean = 0;
4102 rx_ring->next_to_use = 0;
4103 }
4104
4105 /**
4106 * ixgbe_clean_tx_ring - Free Tx Buffers
4107 * @tx_ring: ring to be cleaned
4108 **/
4109 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4110 {
4111 struct ixgbe_tx_buffer *tx_buffer_info;
4112 unsigned long size;
4113 u16 i;
4114
4115 /* ring already cleared, nothing to do */
4116 if (!tx_ring->tx_buffer_info)
4117 return;
4118
4119 /* Free all the Tx ring sk_buffs */
4120 for (i = 0; i < tx_ring->count; i++) {
4121 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4122 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4123 }
4124
4125 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4126 memset(tx_ring->tx_buffer_info, 0, size);
4127
4128 /* Zero out the descriptor ring */
4129 memset(tx_ring->desc, 0, tx_ring->size);
4130
4131 tx_ring->next_to_use = 0;
4132 tx_ring->next_to_clean = 0;
4133 }
4134
4135 /**
4136 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4137 * @adapter: board private structure
4138 **/
4139 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4140 {
4141 int i;
4142
4143 for (i = 0; i < adapter->num_rx_queues; i++)
4144 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4145 }
4146
4147 /**
4148 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4149 * @adapter: board private structure
4150 **/
4151 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4152 {
4153 int i;
4154
4155 for (i = 0; i < adapter->num_tx_queues; i++)
4156 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4157 }
4158
4159 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
4160 {
4161 struct hlist_node *node, *node2;
4162 struct ixgbe_fdir_filter *filter;
4163
4164 spin_lock(&adapter->fdir_perfect_lock);
4165
4166 hlist_for_each_entry_safe(filter, node, node2,
4167 &adapter->fdir_filter_list, fdir_node) {
4168 hlist_del(&filter->fdir_node);
4169 kfree(filter);
4170 }
4171 adapter->fdir_filter_count = 0;
4172
4173 spin_unlock(&adapter->fdir_perfect_lock);
4174 }
4175
4176 void ixgbe_down(struct ixgbe_adapter *adapter)
4177 {
4178 struct net_device *netdev = adapter->netdev;
4179 struct ixgbe_hw *hw = &adapter->hw;
4180 u32 rxctrl;
4181 int i;
4182 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4183
4184 /* signal that we are down to the interrupt handler */
4185 set_bit(__IXGBE_DOWN, &adapter->state);
4186
4187 /* disable receives */
4188 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4189 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4190
4191 /* disable all enabled rx queues */
4192 for (i = 0; i < adapter->num_rx_queues; i++)
4193 /* this call also flushes the previous write */
4194 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4195
4196 usleep_range(10000, 20000);
4197
4198 netif_tx_stop_all_queues(netdev);
4199
4200 /* call carrier off first to avoid false dev_watchdog timeouts */
4201 netif_carrier_off(netdev);
4202 netif_tx_disable(netdev);
4203
4204 ixgbe_irq_disable(adapter);
4205
4206 ixgbe_napi_disable_all(adapter);
4207
4208 adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4209 IXGBE_FLAG2_RESET_REQUESTED);
4210 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4211
4212 del_timer_sync(&adapter->service_timer);
4213
4214 /* disable receive for all VFs and wait one second */
4215 if (adapter->num_vfs) {
4216 /* ping all the active vfs to let them know we are going down */
4217 ixgbe_ping_all_vfs(adapter);
4218
4219 /* Disable all VFTE/VFRE TX/RX */
4220 ixgbe_disable_tx_rx(adapter);
4221
4222 /* Mark all the VFs as inactive */
4223 for (i = 0 ; i < adapter->num_vfs; i++)
4224 adapter->vfinfo[i].clear_to_send = 0;
4225 }
4226
4227 /* Cleanup the affinity_hint CPU mask memory and callback */
4228 for (i = 0; i < num_q_vectors; i++) {
4229 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4230 /* clear the affinity_mask in the IRQ descriptor */
4231 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4232 /* release the CPU mask memory */
4233 free_cpumask_var(q_vector->affinity_mask);
4234 }
4235
4236 /* disable transmits in the hardware now that interrupts are off */
4237 for (i = 0; i < adapter->num_tx_queues; i++) {
4238 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4239 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4240 }
4241
4242 /* Disable the Tx DMA engine on 82599 and X540 */
4243 switch (hw->mac.type) {
4244 case ixgbe_mac_82599EB:
4245 case ixgbe_mac_X540:
4246 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4247 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4248 ~IXGBE_DMATXCTL_TE));
4249 break;
4250 default:
4251 break;
4252 }
4253
4254 if (!pci_channel_offline(adapter->pdev))
4255 ixgbe_reset(adapter);
4256
4257 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4258 if (hw->mac.ops.disable_tx_laser &&
4259 ((hw->phy.multispeed_fiber) ||
4260 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4261 (hw->mac.type == ixgbe_mac_82599EB))))
4262 hw->mac.ops.disable_tx_laser(hw);
4263
4264 ixgbe_clean_all_tx_rings(adapter);
4265 ixgbe_clean_all_rx_rings(adapter);
4266
4267 #ifdef CONFIG_IXGBE_DCA
4268 /* since we reset the hardware DCA settings were cleared */
4269 ixgbe_setup_dca(adapter);
4270 #endif
4271 }
4272
4273 /**
4274 * ixgbe_poll - NAPI Rx polling callback
4275 * @napi: structure for representing this polling device
4276 * @budget: how many packets driver is allowed to clean
4277 *
4278 * This function is used for legacy and MSI, NAPI mode
4279 **/
4280 static int ixgbe_poll(struct napi_struct *napi, int budget)
4281 {
4282 struct ixgbe_q_vector *q_vector =
4283 container_of(napi, struct ixgbe_q_vector, napi);
4284 struct ixgbe_adapter *adapter = q_vector->adapter;
4285 int tx_clean_complete, work_done = 0;
4286
4287 #ifdef CONFIG_IXGBE_DCA
4288 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4289 ixgbe_update_dca(q_vector);
4290 #endif
4291
4292 tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4293 ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4294
4295 if (!tx_clean_complete)
4296 work_done = budget;
4297
4298 /* If budget not fully consumed, exit the polling mode */
4299 if (work_done < budget) {
4300 napi_complete(napi);
4301 if (adapter->rx_itr_setting & 1)
4302 ixgbe_set_itr(adapter);
4303 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4304 ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4305 }
4306 return work_done;
4307 }
4308
4309 /**
4310 * ixgbe_tx_timeout - Respond to a Tx Hang
4311 * @netdev: network interface device structure
4312 **/
4313 static void ixgbe_tx_timeout(struct net_device *netdev)
4314 {
4315 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4316
4317 /* Do the reset outside of interrupt context */
4318 ixgbe_tx_timeout_reset(adapter);
4319 }
4320
4321 /**
4322 * ixgbe_set_rss_queues: Allocate queues for RSS
4323 * @adapter: board private structure to initialize
4324 *
4325 * This is our "base" multiqueue mode. RSS (Receive Side Scaling) will try
4326 * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4327 *
4328 **/
4329 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4330 {
4331 bool ret = false;
4332 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4333
4334 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4335 f->mask = 0xF;
4336 adapter->num_rx_queues = f->indices;
4337 adapter->num_tx_queues = f->indices;
4338 ret = true;
4339 } else {
4340 ret = false;
4341 }
4342
4343 return ret;
4344 }
4345
4346 /**
4347 * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4348 * @adapter: board private structure to initialize
4349 *
4350 * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4351 * to the original CPU that initiated the Tx session. This runs in addition
4352 * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4353 * Rx load across CPUs using RSS.
4354 *
4355 **/
4356 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4357 {
4358 bool ret = false;
4359 struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4360
4361 f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4362 f_fdir->mask = 0;
4363
4364 /* Flow Director must have RSS enabled */
4365 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4366 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4367 adapter->num_tx_queues = f_fdir->indices;
4368 adapter->num_rx_queues = f_fdir->indices;
4369 ret = true;
4370 } else {
4371 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4372 }
4373 return ret;
4374 }
4375
4376 #ifdef IXGBE_FCOE
4377 /**
4378 * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4379 * @adapter: board private structure to initialize
4380 *
4381 * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4382 * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4383 * rx queues out of the max number of rx queues, instead, it is used as the
4384 * index of the first rx queue used by FCoE.
4385 *
4386 **/
4387 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4388 {
4389 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4390
4391 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4392 return false;
4393
4394 f->indices = min((int)num_online_cpus(), f->indices);
4395
4396 adapter->num_rx_queues = 1;
4397 adapter->num_tx_queues = 1;
4398
4399 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4400 e_info(probe, "FCoE enabled with RSS\n");
4401 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4402 ixgbe_set_fdir_queues(adapter);
4403 else
4404 ixgbe_set_rss_queues(adapter);
4405 }
4406
4407 /* adding FCoE rx rings to the end */
4408 f->mask = adapter->num_rx_queues;
4409 adapter->num_rx_queues += f->indices;
4410 adapter->num_tx_queues += f->indices;
4411
4412 return true;
4413 }
4414 #endif /* IXGBE_FCOE */
4415
4416 /* Artificial max queue cap per traffic class in DCB mode */
4417 #define DCB_QUEUE_CAP 8
4418
4419 #ifdef CONFIG_IXGBE_DCB
4420 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4421 {
4422 int per_tc_q, q, i, offset = 0;
4423 struct net_device *dev = adapter->netdev;
4424 int tcs = netdev_get_num_tc(dev);
4425
4426 if (!tcs)
4427 return false;
4428
4429 /* Map queue offset and counts onto allocated tx queues */
4430 per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4431 q = min((int)num_online_cpus(), per_tc_q);
4432
4433 for (i = 0; i < tcs; i++) {
4434 netdev_set_prio_tc_map(dev, i, i);
4435 netdev_set_tc_queue(dev, i, q, offset);
4436 offset += q;
4437 }
4438
4439 adapter->num_tx_queues = q * tcs;
4440 adapter->num_rx_queues = q * tcs;
4441
4442 #ifdef IXGBE_FCOE
4443 /* FCoE enabled queues require special configuration indexed
4444 * by feature specific indices and mask. Here we map FCoE
4445 * indices onto the DCB queue pairs allowing FCoE to own
4446 * configuration later.
4447 */
4448 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4449 int tc;
4450 struct ixgbe_ring_feature *f =
4451 &adapter->ring_feature[RING_F_FCOE];
4452
4453 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4454 f->indices = dev->tc_to_txq[tc].count;
4455 f->mask = dev->tc_to_txq[tc].offset;
4456 }
4457 #endif
4458
4459 return true;
4460 }
4461 #endif
4462
4463 /**
4464 * ixgbe_set_sriov_queues: Allocate queues for IOV use
4465 * @adapter: board private structure to initialize
4466 *
4467 * IOV doesn't actually use anything, so just NAK the
4468 * request for now and let the other queue routines
4469 * figure out what to do.
4470 */
4471 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4472 {
4473 return false;
4474 }
4475
4476 /*
4477 * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4478 * @adapter: board private structure to initialize
4479 *
4480 * This is the top level queue allocation routine. The order here is very
4481 * important, starting with the "most" number of features turned on at once,
4482 * and ending with the smallest set of features. This way large combinations
4483 * can be allocated if they're turned on, and smaller combinations are the
4484 * fallthrough conditions.
4485 *
4486 **/
4487 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4488 {
4489 /* Start with base case */
4490 adapter->num_rx_queues = 1;
4491 adapter->num_tx_queues = 1;
4492 adapter->num_rx_pools = adapter->num_rx_queues;
4493 adapter->num_rx_queues_per_pool = 1;
4494
4495 if (ixgbe_set_sriov_queues(adapter))
4496 goto done;
4497
4498 #ifdef CONFIG_IXGBE_DCB
4499 if (ixgbe_set_dcb_queues(adapter))
4500 goto done;
4501
4502 #endif
4503 #ifdef IXGBE_FCOE
4504 if (ixgbe_set_fcoe_queues(adapter))
4505 goto done;
4506
4507 #endif /* IXGBE_FCOE */
4508 if (ixgbe_set_fdir_queues(adapter))
4509 goto done;
4510
4511 if (ixgbe_set_rss_queues(adapter))
4512 goto done;
4513
4514 /* fallback to base case */
4515 adapter->num_rx_queues = 1;
4516 adapter->num_tx_queues = 1;
4517
4518 done:
4519 /* Notify the stack of the (possibly) reduced queue counts. */
4520 netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4521 return netif_set_real_num_rx_queues(adapter->netdev,
4522 adapter->num_rx_queues);
4523 }
4524
4525 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4526 int vectors)
4527 {
4528 int err, vector_threshold;
4529
4530 /* We'll want at least 3 (vector_threshold):
4531 * 1) TxQ[0] Cleanup
4532 * 2) RxQ[0] Cleanup
4533 * 3) Other (Link Status Change, etc.)
4534 * 4) TCP Timer (optional)
4535 */
4536 vector_threshold = MIN_MSIX_COUNT;
4537
4538 /* The more we get, the more we will assign to Tx/Rx Cleanup
4539 * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4540 * Right now, we simply care about how many we'll get; we'll
4541 * set them up later while requesting irq's.
4542 */
4543 while (vectors >= vector_threshold) {
4544 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4545 vectors);
4546 if (!err) /* Success in acquiring all requested vectors. */
4547 break;
4548 else if (err < 0)
4549 vectors = 0; /* Nasty failure, quit now */
4550 else /* err == number of vectors we should try again with */
4551 vectors = err;
4552 }
4553
4554 if (vectors < vector_threshold) {
4555 /* Can't allocate enough MSI-X interrupts? Oh well.
4556 * This just means we'll go with either a single MSI
4557 * vector or fall back to legacy interrupts.
4558 */
4559 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4560 "Unable to allocate MSI-X interrupts\n");
4561 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4562 kfree(adapter->msix_entries);
4563 adapter->msix_entries = NULL;
4564 } else {
4565 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4566 /*
4567 * Adjust for only the vectors we'll use, which is minimum
4568 * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4569 * vectors we were allocated.
4570 */
4571 adapter->num_msix_vectors = min(vectors,
4572 adapter->max_msix_q_vectors + NON_Q_VECTORS);
4573 }
4574 }
4575
4576 /**
4577 * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4578 * @adapter: board private structure to initialize
4579 *
4580 * Cache the descriptor ring offsets for RSS to the assigned rings.
4581 *
4582 **/
4583 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4584 {
4585 int i;
4586
4587 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4588 return false;
4589
4590 for (i = 0; i < adapter->num_rx_queues; i++)
4591 adapter->rx_ring[i]->reg_idx = i;
4592 for (i = 0; i < adapter->num_tx_queues; i++)
4593 adapter->tx_ring[i]->reg_idx = i;
4594
4595 return true;
4596 }
4597
4598 #ifdef CONFIG_IXGBE_DCB
4599
4600 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4601 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4602 unsigned int *tx, unsigned int *rx)
4603 {
4604 struct net_device *dev = adapter->netdev;
4605 struct ixgbe_hw *hw = &adapter->hw;
4606 u8 num_tcs = netdev_get_num_tc(dev);
4607
4608 *tx = 0;
4609 *rx = 0;
4610
4611 switch (hw->mac.type) {
4612 case ixgbe_mac_82598EB:
4613 *tx = tc << 2;
4614 *rx = tc << 3;
4615 break;
4616 case ixgbe_mac_82599EB:
4617 case ixgbe_mac_X540:
4618 if (num_tcs == 8) {
4619 if (tc < 3) {
4620 *tx = tc << 5;
4621 *rx = tc << 4;
4622 } else if (tc < 5) {
4623 *tx = ((tc + 2) << 4);
4624 *rx = tc << 4;
4625 } else if (tc < num_tcs) {
4626 *tx = ((tc + 8) << 3);
4627 *rx = tc << 4;
4628 }
4629 } else if (num_tcs == 4) {
4630 *rx = tc << 5;
4631 switch (tc) {
4632 case 0:
4633 *tx = 0;
4634 break;
4635 case 1:
4636 *tx = 64;
4637 break;
4638 case 2:
4639 *tx = 96;
4640 break;
4641 case 3:
4642 *tx = 112;
4643 break;
4644 default:
4645 break;
4646 }
4647 }
4648 break;
4649 default:
4650 break;
4651 }
4652 }
4653
4654 /**
4655 * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4656 * @adapter: board private structure to initialize
4657 *
4658 * Cache the descriptor ring offsets for DCB to the assigned rings.
4659 *
4660 **/
4661 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4662 {
4663 struct net_device *dev = adapter->netdev;
4664 int i, j, k;
4665 u8 num_tcs = netdev_get_num_tc(dev);
4666
4667 if (!num_tcs)
4668 return false;
4669
4670 for (i = 0, k = 0; i < num_tcs; i++) {
4671 unsigned int tx_s, rx_s;
4672 u16 count = dev->tc_to_txq[i].count;
4673
4674 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4675 for (j = 0; j < count; j++, k++) {
4676 adapter->tx_ring[k]->reg_idx = tx_s + j;
4677 adapter->rx_ring[k]->reg_idx = rx_s + j;
4678 adapter->tx_ring[k]->dcb_tc = i;
4679 adapter->rx_ring[k]->dcb_tc = i;
4680 }
4681 }
4682
4683 return true;
4684 }
4685 #endif
4686
4687 /**
4688 * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4689 * @adapter: board private structure to initialize
4690 *
4691 * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4692 *
4693 **/
4694 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4695 {
4696 int i;
4697 bool ret = false;
4698
4699 if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4700 (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4701 for (i = 0; i < adapter->num_rx_queues; i++)
4702 adapter->rx_ring[i]->reg_idx = i;
4703 for (i = 0; i < adapter->num_tx_queues; i++)
4704 adapter->tx_ring[i]->reg_idx = i;
4705 ret = true;
4706 }
4707
4708 return ret;
4709 }
4710
4711 #ifdef IXGBE_FCOE
4712 /**
4713 * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4714 * @adapter: board private structure to initialize
4715 *
4716 * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4717 *
4718 */
4719 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4720 {
4721 struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4722 int i;
4723 u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4724
4725 if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4726 return false;
4727
4728 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4729 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4730 ixgbe_cache_ring_fdir(adapter);
4731 else
4732 ixgbe_cache_ring_rss(adapter);
4733
4734 fcoe_rx_i = f->mask;
4735 fcoe_tx_i = f->mask;
4736 }
4737 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4738 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4739 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4740 }
4741 return true;
4742 }
4743
4744 #endif /* IXGBE_FCOE */
4745 /**
4746 * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4747 * @adapter: board private structure to initialize
4748 *
4749 * SR-IOV doesn't use any descriptor rings but changes the default if
4750 * no other mapping is used.
4751 *
4752 */
4753 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4754 {
4755 adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4756 adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4757 if (adapter->num_vfs)
4758 return true;
4759 else
4760 return false;
4761 }
4762
4763 /**
4764 * ixgbe_cache_ring_register - Descriptor ring to register mapping
4765 * @adapter: board private structure to initialize
4766 *
4767 * Once we know the feature-set enabled for the device, we'll cache
4768 * the register offset the descriptor ring is assigned to.
4769 *
4770 * Note, the order the various feature calls is important. It must start with
4771 * the "most" features enabled at the same time, then trickle down to the
4772 * least amount of features turned on at once.
4773 **/
4774 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4775 {
4776 /* start with default case */
4777 adapter->rx_ring[0]->reg_idx = 0;
4778 adapter->tx_ring[0]->reg_idx = 0;
4779
4780 if (ixgbe_cache_ring_sriov(adapter))
4781 return;
4782
4783 #ifdef CONFIG_IXGBE_DCB
4784 if (ixgbe_cache_ring_dcb(adapter))
4785 return;
4786 #endif
4787
4788 #ifdef IXGBE_FCOE
4789 if (ixgbe_cache_ring_fcoe(adapter))
4790 return;
4791 #endif /* IXGBE_FCOE */
4792
4793 if (ixgbe_cache_ring_fdir(adapter))
4794 return;
4795
4796 if (ixgbe_cache_ring_rss(adapter))
4797 return;
4798 }
4799
4800 /**
4801 * ixgbe_alloc_queues - Allocate memory for all rings
4802 * @adapter: board private structure to initialize
4803 *
4804 * We allocate one ring per queue at run-time since we don't know the
4805 * number of queues at compile-time. The polling_netdev array is
4806 * intended for Multiqueue, but should work fine with a single queue.
4807 **/
4808 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4809 {
4810 int rx = 0, tx = 0, nid = adapter->node;
4811
4812 if (nid < 0 || !node_online(nid))
4813 nid = first_online_node;
4814
4815 for (; tx < adapter->num_tx_queues; tx++) {
4816 struct ixgbe_ring *ring;
4817
4818 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4819 if (!ring)
4820 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4821 if (!ring)
4822 goto err_allocation;
4823 ring->count = adapter->tx_ring_count;
4824 ring->queue_index = tx;
4825 ring->numa_node = nid;
4826 ring->dev = &adapter->pdev->dev;
4827 ring->netdev = adapter->netdev;
4828
4829 adapter->tx_ring[tx] = ring;
4830 }
4831
4832 for (; rx < adapter->num_rx_queues; rx++) {
4833 struct ixgbe_ring *ring;
4834
4835 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4836 if (!ring)
4837 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4838 if (!ring)
4839 goto err_allocation;
4840 ring->count = adapter->rx_ring_count;
4841 ring->queue_index = rx;
4842 ring->numa_node = nid;
4843 ring->dev = &adapter->pdev->dev;
4844 ring->netdev = adapter->netdev;
4845
4846 adapter->rx_ring[rx] = ring;
4847 }
4848
4849 ixgbe_cache_ring_register(adapter);
4850
4851 return 0;
4852
4853 err_allocation:
4854 while (tx)
4855 kfree(adapter->tx_ring[--tx]);
4856
4857 while (rx)
4858 kfree(adapter->rx_ring[--rx]);
4859 return -ENOMEM;
4860 }
4861
4862 /**
4863 * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4864 * @adapter: board private structure to initialize
4865 *
4866 * Attempt to configure the interrupts using the best available
4867 * capabilities of the hardware and the kernel.
4868 **/
4869 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4870 {
4871 struct ixgbe_hw *hw = &adapter->hw;
4872 int err = 0;
4873 int vector, v_budget;
4874
4875 /*
4876 * It's easy to be greedy for MSI-X vectors, but it really
4877 * doesn't do us much good if we have a lot more vectors
4878 * than CPU's. So let's be conservative and only ask for
4879 * (roughly) the same number of vectors as there are CPU's.
4880 */
4881 v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4882 (int)num_online_cpus()) + NON_Q_VECTORS;
4883
4884 /*
4885 * At the same time, hardware can only support a maximum of
4886 * hw.mac->max_msix_vectors vectors. With features
4887 * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4888 * descriptor queues supported by our device. Thus, we cap it off in
4889 * those rare cases where the cpu count also exceeds our vector limit.
4890 */
4891 v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4892
4893 /* A failure in MSI-X entry allocation isn't fatal, but it does
4894 * mean we disable MSI-X capabilities of the adapter. */
4895 adapter->msix_entries = kcalloc(v_budget,
4896 sizeof(struct msix_entry), GFP_KERNEL);
4897 if (adapter->msix_entries) {
4898 for (vector = 0; vector < v_budget; vector++)
4899 adapter->msix_entries[vector].entry = vector;
4900
4901 ixgbe_acquire_msix_vectors(adapter, v_budget);
4902
4903 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4904 goto out;
4905 }
4906
4907 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4908 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4909 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4910 e_err(probe,
4911 "ATR is not supported while multiple "
4912 "queues are disabled. Disabling Flow Director\n");
4913 }
4914 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4915 adapter->atr_sample_rate = 0;
4916 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4917 ixgbe_disable_sriov(adapter);
4918
4919 err = ixgbe_set_num_queues(adapter);
4920 if (err)
4921 return err;
4922
4923 err = pci_enable_msi(adapter->pdev);
4924 if (!err) {
4925 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4926 } else {
4927 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4928 "Unable to allocate MSI interrupt, "
4929 "falling back to legacy. Error: %d\n", err);
4930 /* reset err */
4931 err = 0;
4932 }
4933
4934 out:
4935 return err;
4936 }
4937
4938 /**
4939 * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4940 * @adapter: board private structure to initialize
4941 *
4942 * We allocate one q_vector per queue interrupt. If allocation fails we
4943 * return -ENOMEM.
4944 **/
4945 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4946 {
4947 int q_idx, num_q_vectors;
4948 struct ixgbe_q_vector *q_vector;
4949 int (*poll)(struct napi_struct *, int);
4950
4951 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4952 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4953 poll = &ixgbe_clean_rxtx_many;
4954 } else {
4955 num_q_vectors = 1;
4956 poll = &ixgbe_poll;
4957 }
4958
4959 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4960 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4961 GFP_KERNEL, adapter->node);
4962 if (!q_vector)
4963 q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4964 GFP_KERNEL);
4965 if (!q_vector)
4966 goto err_out;
4967 q_vector->adapter = adapter;
4968 if (q_vector->tx.count && !q_vector->rx.count)
4969 q_vector->eitr = adapter->tx_eitr_param;
4970 else
4971 q_vector->eitr = adapter->rx_eitr_param;
4972 q_vector->v_idx = q_idx;
4973 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4974 adapter->q_vector[q_idx] = q_vector;
4975 }
4976
4977 return 0;
4978
4979 err_out:
4980 while (q_idx) {
4981 q_idx--;
4982 q_vector = adapter->q_vector[q_idx];
4983 netif_napi_del(&q_vector->napi);
4984 kfree(q_vector);
4985 adapter->q_vector[q_idx] = NULL;
4986 }
4987 return -ENOMEM;
4988 }
4989
4990 /**
4991 * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4992 * @adapter: board private structure to initialize
4993 *
4994 * This function frees the memory allocated to the q_vectors. In addition if
4995 * NAPI is enabled it will delete any references to the NAPI struct prior
4996 * to freeing the q_vector.
4997 **/
4998 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4999 {
5000 int q_idx, num_q_vectors;
5001
5002 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5003 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5004 else
5005 num_q_vectors = 1;
5006
5007 for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
5008 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
5009 adapter->q_vector[q_idx] = NULL;
5010 netif_napi_del(&q_vector->napi);
5011 kfree(q_vector);
5012 }
5013 }
5014
5015 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
5016 {
5017 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5018 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
5019 pci_disable_msix(adapter->pdev);
5020 kfree(adapter->msix_entries);
5021 adapter->msix_entries = NULL;
5022 } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
5023 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
5024 pci_disable_msi(adapter->pdev);
5025 }
5026 }
5027
5028 /**
5029 * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
5030 * @adapter: board private structure to initialize
5031 *
5032 * We determine which interrupt scheme to use based on...
5033 * - Kernel support (MSI, MSI-X)
5034 * - which can be user-defined (via MODULE_PARAM)
5035 * - Hardware queue count (num_*_queues)
5036 * - defined by miscellaneous hardware support/features (RSS, etc.)
5037 **/
5038 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5039 {
5040 int err;
5041
5042 /* Number of supported queues */
5043 err = ixgbe_set_num_queues(adapter);
5044 if (err)
5045 return err;
5046
5047 err = ixgbe_set_interrupt_capability(adapter);
5048 if (err) {
5049 e_dev_err("Unable to setup interrupt capabilities\n");
5050 goto err_set_interrupt;
5051 }
5052
5053 err = ixgbe_alloc_q_vectors(adapter);
5054 if (err) {
5055 e_dev_err("Unable to allocate memory for queue vectors\n");
5056 goto err_alloc_q_vectors;
5057 }
5058
5059 err = ixgbe_alloc_queues(adapter);
5060 if (err) {
5061 e_dev_err("Unable to allocate memory for queues\n");
5062 goto err_alloc_queues;
5063 }
5064
5065 e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5066 (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5067 adapter->num_rx_queues, adapter->num_tx_queues);
5068
5069 set_bit(__IXGBE_DOWN, &adapter->state);
5070
5071 return 0;
5072
5073 err_alloc_queues:
5074 ixgbe_free_q_vectors(adapter);
5075 err_alloc_q_vectors:
5076 ixgbe_reset_interrupt_capability(adapter);
5077 err_set_interrupt:
5078 return err;
5079 }
5080
5081 /**
5082 * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5083 * @adapter: board private structure to clear interrupt scheme on
5084 *
5085 * We go through and clear interrupt specific resources and reset the structure
5086 * to pre-load conditions
5087 **/
5088 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5089 {
5090 int i;
5091
5092 for (i = 0; i < adapter->num_tx_queues; i++) {
5093 kfree(adapter->tx_ring[i]);
5094 adapter->tx_ring[i] = NULL;
5095 }
5096 for (i = 0; i < adapter->num_rx_queues; i++) {
5097 struct ixgbe_ring *ring = adapter->rx_ring[i];
5098
5099 /* ixgbe_get_stats64() might access this ring, we must wait
5100 * a grace period before freeing it.
5101 */
5102 kfree_rcu(ring, rcu);
5103 adapter->rx_ring[i] = NULL;
5104 }
5105
5106 adapter->num_tx_queues = 0;
5107 adapter->num_rx_queues = 0;
5108
5109 ixgbe_free_q_vectors(adapter);
5110 ixgbe_reset_interrupt_capability(adapter);
5111 }
5112
5113 /**
5114 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5115 * @adapter: board private structure to initialize
5116 *
5117 * ixgbe_sw_init initializes the Adapter private data structure.
5118 * Fields are initialized based on PCI device information and
5119 * OS network device settings (MTU size).
5120 **/
5121 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5122 {
5123 struct ixgbe_hw *hw = &adapter->hw;
5124 struct pci_dev *pdev = adapter->pdev;
5125 struct net_device *dev = adapter->netdev;
5126 unsigned int rss;
5127 #ifdef CONFIG_IXGBE_DCB
5128 int j;
5129 struct tc_configuration *tc;
5130 #endif
5131 int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5132
5133 /* PCI config space info */
5134
5135 hw->vendor_id = pdev->vendor;
5136 hw->device_id = pdev->device;
5137 hw->revision_id = pdev->revision;
5138 hw->subsystem_vendor_id = pdev->subsystem_vendor;
5139 hw->subsystem_device_id = pdev->subsystem_device;
5140
5141 /* Set capability flags */
5142 rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5143 adapter->ring_feature[RING_F_RSS].indices = rss;
5144 adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5145 switch (hw->mac.type) {
5146 case ixgbe_mac_82598EB:
5147 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5148 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5149 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5150 break;
5151 case ixgbe_mac_82599EB:
5152 case ixgbe_mac_X540:
5153 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5154 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5155 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5156 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5157 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5158 /* Flow Director hash filters enabled */
5159 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5160 adapter->atr_sample_rate = 20;
5161 adapter->ring_feature[RING_F_FDIR].indices =
5162 IXGBE_MAX_FDIR_INDICES;
5163 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
5164 #ifdef IXGBE_FCOE
5165 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5166 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5167 adapter->ring_feature[RING_F_FCOE].indices = 0;
5168 #ifdef CONFIG_IXGBE_DCB
5169 /* Default traffic class to use for FCoE */
5170 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5171 #endif
5172 #endif /* IXGBE_FCOE */
5173 break;
5174 default:
5175 break;
5176 }
5177
5178 /* n-tuple support exists, always init our spinlock */
5179 spin_lock_init(&adapter->fdir_perfect_lock);
5180
5181 #ifdef CONFIG_IXGBE_DCB
5182 /* Configure DCB traffic classes */
5183 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5184 tc = &adapter->dcb_cfg.tc_config[j];
5185 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5186 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5187 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5188 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5189 tc->dcb_pfc = pfc_disabled;
5190 }
5191 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5192 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5193 adapter->dcb_cfg.pfc_mode_enable = false;
5194 adapter->dcb_set_bitmap = 0x00;
5195 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5196 ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5197 MAX_TRAFFIC_CLASS);
5198
5199 #endif
5200
5201 /* default flow control settings */
5202 hw->fc.requested_mode = ixgbe_fc_full;
5203 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
5204 #ifdef CONFIG_DCB
5205 adapter->last_lfc_mode = hw->fc.current_mode;
5206 #endif
5207 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5208 hw->fc.low_water = FC_LOW_WATER(max_frame);
5209 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5210 hw->fc.send_xon = true;
5211 hw->fc.disable_fc_autoneg = false;
5212
5213 /* enable itr by default in dynamic mode */
5214 adapter->rx_itr_setting = 1;
5215 adapter->rx_eitr_param = 20000;
5216 adapter->tx_itr_setting = 1;
5217 adapter->tx_eitr_param = 10000;
5218
5219 /* set defaults for eitr in MegaBytes */
5220 adapter->eitr_low = 10;
5221 adapter->eitr_high = 20;
5222
5223 /* set default ring sizes */
5224 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5225 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5226
5227 /* initialize eeprom parameters */
5228 if (ixgbe_init_eeprom_params_generic(hw)) {
5229 e_dev_err("EEPROM initialization failed\n");
5230 return -EIO;
5231 }
5232
5233 /* enable rx csum by default */
5234 adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5235
5236 /* get assigned NUMA node */
5237 adapter->node = dev_to_node(&pdev->dev);
5238
5239 set_bit(__IXGBE_DOWN, &adapter->state);
5240
5241 return 0;
5242 }
5243
5244 /**
5245 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5246 * @tx_ring: tx descriptor ring (for a specific queue) to setup
5247 *
5248 * Return 0 on success, negative on failure
5249 **/
5250 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5251 {
5252 struct device *dev = tx_ring->dev;
5253 int size;
5254
5255 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5256 tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5257 if (!tx_ring->tx_buffer_info)
5258 tx_ring->tx_buffer_info = vzalloc(size);
5259 if (!tx_ring->tx_buffer_info)
5260 goto err;
5261
5262 /* round up to nearest 4K */
5263 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5264 tx_ring->size = ALIGN(tx_ring->size, 4096);
5265
5266 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5267 &tx_ring->dma, GFP_KERNEL);
5268 if (!tx_ring->desc)
5269 goto err;
5270
5271 tx_ring->next_to_use = 0;
5272 tx_ring->next_to_clean = 0;
5273 tx_ring->work_limit = tx_ring->count;
5274 return 0;
5275
5276 err:
5277 vfree(tx_ring->tx_buffer_info);
5278 tx_ring->tx_buffer_info = NULL;
5279 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5280 return -ENOMEM;
5281 }
5282
5283 /**
5284 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5285 * @adapter: board private structure
5286 *
5287 * If this function returns with an error, then it's possible one or
5288 * more of the rings is populated (while the rest are not). It is the
5289 * callers duty to clean those orphaned rings.
5290 *
5291 * Return 0 on success, negative on failure
5292 **/
5293 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5294 {
5295 int i, err = 0;
5296
5297 for (i = 0; i < adapter->num_tx_queues; i++) {
5298 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5299 if (!err)
5300 continue;
5301 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5302 break;
5303 }
5304
5305 return err;
5306 }
5307
5308 /**
5309 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5310 * @rx_ring: rx descriptor ring (for a specific queue) to setup
5311 *
5312 * Returns 0 on success, negative on failure
5313 **/
5314 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5315 {
5316 struct device *dev = rx_ring->dev;
5317 int size;
5318
5319 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5320 rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5321 if (!rx_ring->rx_buffer_info)
5322 rx_ring->rx_buffer_info = vzalloc(size);
5323 if (!rx_ring->rx_buffer_info)
5324 goto err;
5325
5326 /* Round up to nearest 4K */
5327 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5328 rx_ring->size = ALIGN(rx_ring->size, 4096);
5329
5330 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5331 &rx_ring->dma, GFP_KERNEL);
5332
5333 if (!rx_ring->desc)
5334 goto err;
5335
5336 rx_ring->next_to_clean = 0;
5337 rx_ring->next_to_use = 0;
5338
5339 return 0;
5340 err:
5341 vfree(rx_ring->rx_buffer_info);
5342 rx_ring->rx_buffer_info = NULL;
5343 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5344 return -ENOMEM;
5345 }
5346
5347 /**
5348 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5349 * @adapter: board private structure
5350 *
5351 * If this function returns with an error, then it's possible one or
5352 * more of the rings is populated (while the rest are not). It is the
5353 * callers duty to clean those orphaned rings.
5354 *
5355 * Return 0 on success, negative on failure
5356 **/
5357 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5358 {
5359 int i, err = 0;
5360
5361 for (i = 0; i < adapter->num_rx_queues; i++) {
5362 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5363 if (!err)
5364 continue;
5365 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5366 break;
5367 }
5368
5369 return err;
5370 }
5371
5372 /**
5373 * ixgbe_free_tx_resources - Free Tx Resources per Queue
5374 * @tx_ring: Tx descriptor ring for a specific queue
5375 *
5376 * Free all transmit software resources
5377 **/
5378 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5379 {
5380 ixgbe_clean_tx_ring(tx_ring);
5381
5382 vfree(tx_ring->tx_buffer_info);
5383 tx_ring->tx_buffer_info = NULL;
5384
5385 /* if not set, then don't free */
5386 if (!tx_ring->desc)
5387 return;
5388
5389 dma_free_coherent(tx_ring->dev, tx_ring->size,
5390 tx_ring->desc, tx_ring->dma);
5391
5392 tx_ring->desc = NULL;
5393 }
5394
5395 /**
5396 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5397 * @adapter: board private structure
5398 *
5399 * Free all transmit software resources
5400 **/
5401 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5402 {
5403 int i;
5404
5405 for (i = 0; i < adapter->num_tx_queues; i++)
5406 if (adapter->tx_ring[i]->desc)
5407 ixgbe_free_tx_resources(adapter->tx_ring[i]);
5408 }
5409
5410 /**
5411 * ixgbe_free_rx_resources - Free Rx Resources
5412 * @rx_ring: ring to clean the resources from
5413 *
5414 * Free all receive software resources
5415 **/
5416 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5417 {
5418 ixgbe_clean_rx_ring(rx_ring);
5419
5420 vfree(rx_ring->rx_buffer_info);
5421 rx_ring->rx_buffer_info = NULL;
5422
5423 /* if not set, then don't free */
5424 if (!rx_ring->desc)
5425 return;
5426
5427 dma_free_coherent(rx_ring->dev, rx_ring->size,
5428 rx_ring->desc, rx_ring->dma);
5429
5430 rx_ring->desc = NULL;
5431 }
5432
5433 /**
5434 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5435 * @adapter: board private structure
5436 *
5437 * Free all receive software resources
5438 **/
5439 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5440 {
5441 int i;
5442
5443 for (i = 0; i < adapter->num_rx_queues; i++)
5444 if (adapter->rx_ring[i]->desc)
5445 ixgbe_free_rx_resources(adapter->rx_ring[i]);
5446 }
5447
5448 /**
5449 * ixgbe_change_mtu - Change the Maximum Transfer Unit
5450 * @netdev: network interface device structure
5451 * @new_mtu: new value for maximum frame size
5452 *
5453 * Returns 0 on success, negative on failure
5454 **/
5455 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5456 {
5457 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5458 struct ixgbe_hw *hw = &adapter->hw;
5459 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5460
5461 /* MTU < 68 is an error and causes problems on some kernels */
5462 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5463 hw->mac.type != ixgbe_mac_X540) {
5464 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5465 return -EINVAL;
5466 } else {
5467 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5468 return -EINVAL;
5469 }
5470
5471 e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5472 /* must set new MTU before calling down or up */
5473 netdev->mtu = new_mtu;
5474
5475 hw->fc.high_water = FC_HIGH_WATER(max_frame);
5476 hw->fc.low_water = FC_LOW_WATER(max_frame);
5477
5478 if (netif_running(netdev))
5479 ixgbe_reinit_locked(adapter);
5480
5481 return 0;
5482 }
5483
5484 /**
5485 * ixgbe_open - Called when a network interface is made active
5486 * @netdev: network interface device structure
5487 *
5488 * Returns 0 on success, negative value on failure
5489 *
5490 * The open entry point is called when a network interface is made
5491 * active by the system (IFF_UP). At this point all resources needed
5492 * for transmit and receive operations are allocated, the interrupt
5493 * handler is registered with the OS, the watchdog timer is started,
5494 * and the stack is notified that the interface is ready.
5495 **/
5496 static int ixgbe_open(struct net_device *netdev)
5497 {
5498 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5499 int err;
5500
5501 /* disallow open during test */
5502 if (test_bit(__IXGBE_TESTING, &adapter->state))
5503 return -EBUSY;
5504
5505 netif_carrier_off(netdev);
5506
5507 /* allocate transmit descriptors */
5508 err = ixgbe_setup_all_tx_resources(adapter);
5509 if (err)
5510 goto err_setup_tx;
5511
5512 /* allocate receive descriptors */
5513 err = ixgbe_setup_all_rx_resources(adapter);
5514 if (err)
5515 goto err_setup_rx;
5516
5517 ixgbe_configure(adapter);
5518
5519 err = ixgbe_request_irq(adapter);
5520 if (err)
5521 goto err_req_irq;
5522
5523 err = ixgbe_up_complete(adapter);
5524 if (err)
5525 goto err_up;
5526
5527 netif_tx_start_all_queues(netdev);
5528
5529 return 0;
5530
5531 err_up:
5532 ixgbe_release_hw_control(adapter);
5533 ixgbe_free_irq(adapter);
5534 err_req_irq:
5535 err_setup_rx:
5536 ixgbe_free_all_rx_resources(adapter);
5537 err_setup_tx:
5538 ixgbe_free_all_tx_resources(adapter);
5539 ixgbe_reset(adapter);
5540
5541 return err;
5542 }
5543
5544 /**
5545 * ixgbe_close - Disables a network interface
5546 * @netdev: network interface device structure
5547 *
5548 * Returns 0, this is not allowed to fail
5549 *
5550 * The close entry point is called when an interface is de-activated
5551 * by the OS. The hardware is still under the drivers control, but
5552 * needs to be disabled. A global MAC reset is issued to stop the
5553 * hardware, and all transmit and receive resources are freed.
5554 **/
5555 static int ixgbe_close(struct net_device *netdev)
5556 {
5557 struct ixgbe_adapter *adapter = netdev_priv(netdev);
5558
5559 ixgbe_down(adapter);
5560 ixgbe_free_irq(adapter);
5561
5562 ixgbe_fdir_filter_exit(adapter);
5563
5564 ixgbe_free_all_tx_resources(adapter);
5565 ixgbe_free_all_rx_resources(adapter);
5566
5567 ixgbe_release_hw_control(adapter);
5568
5569 return 0;
5570 }
5571
5572 #ifdef CONFIG_PM
5573 static int ixgbe_resume(struct pci_dev *pdev)
5574 {
5575 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5576 struct net_device *netdev = adapter->netdev;
5577 u32 err;
5578
5579 pci_set_power_state(pdev, PCI_D0);
5580 pci_restore_state(pdev);
5581 /*
5582 * pci_restore_state clears dev->state_saved so call
5583 * pci_save_state to restore it.
5584 */
5585 pci_save_state(pdev);
5586
5587 err = pci_enable_device_mem(pdev);
5588 if (err) {
5589 e_dev_err("Cannot enable PCI device from suspend\n");
5590 return err;
5591 }
5592 pci_set_master(pdev);
5593
5594 pci_wake_from_d3(pdev, false);
5595
5596 err = ixgbe_init_interrupt_scheme(adapter);
5597 if (err) {
5598 e_dev_err("Cannot initialize interrupts for device\n");
5599 return err;
5600 }
5601
5602 ixgbe_reset(adapter);
5603
5604 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5605
5606 if (netif_running(netdev)) {
5607 err = ixgbe_open(netdev);
5608 if (err)
5609 return err;
5610 }
5611
5612 netif_device_attach(netdev);
5613
5614 return 0;
5615 }
5616 #endif /* CONFIG_PM */
5617
5618 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5619 {
5620 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5621 struct net_device *netdev = adapter->netdev;
5622 struct ixgbe_hw *hw = &adapter->hw;
5623 u32 ctrl, fctrl;
5624 u32 wufc = adapter->wol;
5625 #ifdef CONFIG_PM
5626 int retval = 0;
5627 #endif
5628
5629 netif_device_detach(netdev);
5630
5631 if (netif_running(netdev)) {
5632 ixgbe_down(adapter);
5633 ixgbe_free_irq(adapter);
5634 ixgbe_free_all_tx_resources(adapter);
5635 ixgbe_free_all_rx_resources(adapter);
5636 }
5637
5638 ixgbe_clear_interrupt_scheme(adapter);
5639 #ifdef CONFIG_DCB
5640 kfree(adapter->ixgbe_ieee_pfc);
5641 kfree(adapter->ixgbe_ieee_ets);
5642 #endif
5643
5644 #ifdef CONFIG_PM
5645 retval = pci_save_state(pdev);
5646 if (retval)
5647 return retval;
5648
5649 #endif
5650 if (wufc) {
5651 ixgbe_set_rx_mode(netdev);
5652
5653 /* turn on all-multi mode if wake on multicast is enabled */
5654 if (wufc & IXGBE_WUFC_MC) {
5655 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5656 fctrl |= IXGBE_FCTRL_MPE;
5657 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5658 }
5659
5660 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5661 ctrl |= IXGBE_CTRL_GIO_DIS;
5662 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5663
5664 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5665 } else {
5666 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5667 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5668 }
5669
5670 switch (hw->mac.type) {
5671 case ixgbe_mac_82598EB:
5672 pci_wake_from_d3(pdev, false);
5673 break;
5674 case ixgbe_mac_82599EB:
5675 case ixgbe_mac_X540:
5676 pci_wake_from_d3(pdev, !!wufc);
5677 break;
5678 default:
5679 break;
5680 }
5681
5682 *enable_wake = !!wufc;
5683
5684 ixgbe_release_hw_control(adapter);
5685
5686 pci_disable_device(pdev);
5687
5688 return 0;
5689 }
5690
5691 #ifdef CONFIG_PM
5692 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5693 {
5694 int retval;
5695 bool wake;
5696
5697 retval = __ixgbe_shutdown(pdev, &wake);
5698 if (retval)
5699 return retval;
5700
5701 if (wake) {
5702 pci_prepare_to_sleep(pdev);
5703 } else {
5704 pci_wake_from_d3(pdev, false);
5705 pci_set_power_state(pdev, PCI_D3hot);
5706 }
5707
5708 return 0;
5709 }
5710 #endif /* CONFIG_PM */
5711
5712 static void ixgbe_shutdown(struct pci_dev *pdev)
5713 {
5714 bool wake;
5715
5716 __ixgbe_shutdown(pdev, &wake);
5717
5718 if (system_state == SYSTEM_POWER_OFF) {
5719 pci_wake_from_d3(pdev, wake);
5720 pci_set_power_state(pdev, PCI_D3hot);
5721 }
5722 }
5723
5724 /**
5725 * ixgbe_update_stats - Update the board statistics counters.
5726 * @adapter: board private structure
5727 **/
5728 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5729 {
5730 struct net_device *netdev = adapter->netdev;
5731 struct ixgbe_hw *hw = &adapter->hw;
5732 struct ixgbe_hw_stats *hwstats = &adapter->stats;
5733 u64 total_mpc = 0;
5734 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5735 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5736 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5737 u64 bytes = 0, packets = 0;
5738
5739 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5740 test_bit(__IXGBE_RESETTING, &adapter->state))
5741 return;
5742
5743 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5744 u64 rsc_count = 0;
5745 u64 rsc_flush = 0;
5746 for (i = 0; i < 16; i++)
5747 adapter->hw_rx_no_dma_resources +=
5748 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5749 for (i = 0; i < adapter->num_rx_queues; i++) {
5750 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5751 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5752 }
5753 adapter->rsc_total_count = rsc_count;
5754 adapter->rsc_total_flush = rsc_flush;
5755 }
5756
5757 for (i = 0; i < adapter->num_rx_queues; i++) {
5758 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5759 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5760 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5761 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5762 bytes += rx_ring->stats.bytes;
5763 packets += rx_ring->stats.packets;
5764 }
5765 adapter->non_eop_descs = non_eop_descs;
5766 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5767 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5768 netdev->stats.rx_bytes = bytes;
5769 netdev->stats.rx_packets = packets;
5770
5771 bytes = 0;
5772 packets = 0;
5773 /* gather some stats to the adapter struct that are per queue */
5774 for (i = 0; i < adapter->num_tx_queues; i++) {
5775 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5776 restart_queue += tx_ring->tx_stats.restart_queue;
5777 tx_busy += tx_ring->tx_stats.tx_busy;
5778 bytes += tx_ring->stats.bytes;
5779 packets += tx_ring->stats.packets;
5780 }
5781 adapter->restart_queue = restart_queue;
5782 adapter->tx_busy = tx_busy;
5783 netdev->stats.tx_bytes = bytes;
5784 netdev->stats.tx_packets = packets;
5785
5786 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5787 for (i = 0; i < 8; i++) {
5788 /* for packet buffers not used, the register should read 0 */
5789 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5790 missed_rx += mpc;
5791 hwstats->mpc[i] += mpc;
5792 total_mpc += hwstats->mpc[i];
5793 if (hw->mac.type == ixgbe_mac_82598EB)
5794 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5795 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5796 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5797 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5798 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5799 switch (hw->mac.type) {
5800 case ixgbe_mac_82598EB:
5801 hwstats->pxonrxc[i] +=
5802 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5803 break;
5804 case ixgbe_mac_82599EB:
5805 case ixgbe_mac_X540:
5806 hwstats->pxonrxc[i] +=
5807 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5808 break;
5809 default:
5810 break;
5811 }
5812 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5813 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5814 }
5815 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5816 /* work around hardware counting issue */
5817 hwstats->gprc -= missed_rx;
5818
5819 ixgbe_update_xoff_received(adapter);
5820
5821 /* 82598 hardware only has a 32 bit counter in the high register */
5822 switch (hw->mac.type) {
5823 case ixgbe_mac_82598EB:
5824 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5825 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5826 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5827 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5828 break;
5829 case ixgbe_mac_X540:
5830 /* OS2BMC stats are X540 only*/
5831 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5832 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5833 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5834 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5835 case ixgbe_mac_82599EB:
5836 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5837 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5838 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5839 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5840 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5841 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5842 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5843 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5844 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5845 #ifdef IXGBE_FCOE
5846 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5847 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5848 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5849 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5850 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5851 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5852 #endif /* IXGBE_FCOE */
5853 break;
5854 default:
5855 break;
5856 }
5857 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5858 hwstats->bprc += bprc;
5859 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5860 if (hw->mac.type == ixgbe_mac_82598EB)
5861 hwstats->mprc -= bprc;
5862 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5863 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5864 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5865 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5866 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5867 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5868 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5869 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5870 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5871 hwstats->lxontxc += lxon;
5872 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5873 hwstats->lxofftxc += lxoff;
5874 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5875 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5876 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5877 /*
5878 * 82598 errata - tx of flow control packets is included in tx counters
5879 */
5880 xon_off_tot = lxon + lxoff;
5881 hwstats->gptc -= xon_off_tot;
5882 hwstats->mptc -= xon_off_tot;
5883 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5884 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5885 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5886 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5887 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5888 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5889 hwstats->ptc64 -= xon_off_tot;
5890 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5891 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5892 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5893 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5894 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5895 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5896
5897 /* Fill out the OS statistics structure */
5898 netdev->stats.multicast = hwstats->mprc;
5899
5900 /* Rx Errors */
5901 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5902 netdev->stats.rx_dropped = 0;
5903 netdev->stats.rx_length_errors = hwstats->rlec;
5904 netdev->stats.rx_crc_errors = hwstats->crcerrs;
5905 netdev->stats.rx_missed_errors = total_mpc;
5906 }
5907
5908 /**
5909 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5910 * @adapter - pointer to the device adapter structure
5911 **/
5912 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5913 {
5914 struct ixgbe_hw *hw = &adapter->hw;
5915 int i;
5916
5917 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5918 return;
5919
5920 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5921
5922 /* if interface is down do nothing */
5923 if (test_bit(__IXGBE_DOWN, &adapter->state))
5924 return;
5925
5926 /* do nothing if we are not using signature filters */
5927 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5928 return;
5929
5930 adapter->fdir_overflow++;
5931
5932 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5933 for (i = 0; i < adapter->num_tx_queues; i++)
5934 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5935 &(adapter->tx_ring[i]->state));
5936 /* re-enable flow director interrupts */
5937 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5938 } else {
5939 e_err(probe, "failed to finish FDIR re-initialization, "
5940 "ignored adding FDIR ATR filters\n");
5941 }
5942 }
5943
5944 /**
5945 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5946 * @adapter - pointer to the device adapter structure
5947 *
5948 * This function serves two purposes. First it strobes the interrupt lines
5949 * in order to make certain interrupts are occuring. Secondly it sets the
5950 * bits needed to check for TX hangs. As a result we should immediately
5951 * determine if a hang has occured.
5952 */
5953 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5954 {
5955 struct ixgbe_hw *hw = &adapter->hw;
5956 u64 eics = 0;
5957 int i;
5958
5959 /* If we're down or resetting, just bail */
5960 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5961 test_bit(__IXGBE_RESETTING, &adapter->state))
5962 return;
5963
5964 /* Force detection of hung controller */
5965 if (netif_carrier_ok(adapter->netdev)) {
5966 for (i = 0; i < adapter->num_tx_queues; i++)
5967 set_check_for_tx_hang(adapter->tx_ring[i]);
5968 }
5969
5970 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5971 /*
5972 * for legacy and MSI interrupts don't set any bits
5973 * that are enabled for EIAM, because this operation
5974 * would set *both* EIMS and EICS for any bit in EIAM
5975 */
5976 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5977 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5978 } else {
5979 /* get one bit for every active tx/rx interrupt vector */
5980 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5981 struct ixgbe_q_vector *qv = adapter->q_vector[i];
5982 if (qv->rx.count || qv->tx.count)
5983 eics |= ((u64)1 << i);
5984 }
5985 }
5986
5987 /* Cause software interrupt to ensure rings are cleaned */
5988 ixgbe_irq_rearm_queues(adapter, eics);
5989
5990 }
5991
5992 /**
5993 * ixgbe_watchdog_update_link - update the link status
5994 * @adapter - pointer to the device adapter structure
5995 * @link_speed - pointer to a u32 to store the link_speed
5996 **/
5997 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5998 {
5999 struct ixgbe_hw *hw = &adapter->hw;
6000 u32 link_speed = adapter->link_speed;
6001 bool link_up = adapter->link_up;
6002 int i;
6003
6004 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
6005 return;
6006
6007 if (hw->mac.ops.check_link) {
6008 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
6009 } else {
6010 /* always assume link is up, if no check link function */
6011 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
6012 link_up = true;
6013 }
6014 if (link_up) {
6015 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6016 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
6017 hw->mac.ops.fc_enable(hw, i);
6018 } else {
6019 hw->mac.ops.fc_enable(hw, 0);
6020 }
6021 }
6022
6023 if (link_up ||
6024 time_after(jiffies, (adapter->link_check_timeout +
6025 IXGBE_TRY_LINK_TIMEOUT))) {
6026 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6027 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
6028 IXGBE_WRITE_FLUSH(hw);
6029 }
6030
6031 adapter->link_up = link_up;
6032 adapter->link_speed = link_speed;
6033 }
6034
6035 /**
6036 * ixgbe_watchdog_link_is_up - update netif_carrier status and
6037 * print link up message
6038 * @adapter - pointer to the device adapter structure
6039 **/
6040 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6041 {
6042 struct net_device *netdev = adapter->netdev;
6043 struct ixgbe_hw *hw = &adapter->hw;
6044 u32 link_speed = adapter->link_speed;
6045 bool flow_rx, flow_tx;
6046
6047 /* only continue if link was previously down */
6048 if (netif_carrier_ok(netdev))
6049 return;
6050
6051 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6052
6053 switch (hw->mac.type) {
6054 case ixgbe_mac_82598EB: {
6055 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6056 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6057 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6058 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6059 }
6060 break;
6061 case ixgbe_mac_X540:
6062 case ixgbe_mac_82599EB: {
6063 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6064 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6065 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6066 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6067 }
6068 break;
6069 default:
6070 flow_tx = false;
6071 flow_rx = false;
6072 break;
6073 }
6074 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6075 (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6076 "10 Gbps" :
6077 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6078 "1 Gbps" :
6079 (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6080 "100 Mbps" :
6081 "unknown speed"))),
6082 ((flow_rx && flow_tx) ? "RX/TX" :
6083 (flow_rx ? "RX" :
6084 (flow_tx ? "TX" : "None"))));
6085
6086 netif_carrier_on(netdev);
6087 #ifdef HAVE_IPLINK_VF_CONFIG
6088 ixgbe_check_vf_rate_limit(adapter);
6089 #endif /* HAVE_IPLINK_VF_CONFIG */
6090 }
6091
6092 /**
6093 * ixgbe_watchdog_link_is_down - update netif_carrier status and
6094 * print link down message
6095 * @adapter - pointer to the adapter structure
6096 **/
6097 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6098 {
6099 struct net_device *netdev = adapter->netdev;
6100 struct ixgbe_hw *hw = &adapter->hw;
6101
6102 adapter->link_up = false;
6103 adapter->link_speed = 0;
6104
6105 /* only continue if link was up previously */
6106 if (!netif_carrier_ok(netdev))
6107 return;
6108
6109 /* poll for SFP+ cable when link is down */
6110 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6111 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6112
6113 e_info(drv, "NIC Link is Down\n");
6114 netif_carrier_off(netdev);
6115 }
6116
6117 /**
6118 * ixgbe_watchdog_flush_tx - flush queues on link down
6119 * @adapter - pointer to the device adapter structure
6120 **/
6121 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6122 {
6123 int i;
6124 int some_tx_pending = 0;
6125
6126 if (!netif_carrier_ok(adapter->netdev)) {
6127 for (i = 0; i < adapter->num_tx_queues; i++) {
6128 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6129 if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6130 some_tx_pending = 1;
6131 break;
6132 }
6133 }
6134
6135 if (some_tx_pending) {
6136 /* We've lost link, so the controller stops DMA,
6137 * but we've got queued Tx work that's never going
6138 * to get done, so reset controller to flush Tx.
6139 * (Do the reset outside of interrupt context).
6140 */
6141 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6142 }
6143 }
6144 }
6145
6146 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6147 {
6148 u32 ssvpc;
6149
6150 /* Do not perform spoof check for 82598 */
6151 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6152 return;
6153
6154 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6155
6156 /*
6157 * ssvpc register is cleared on read, if zero then no
6158 * spoofed packets in the last interval.
6159 */
6160 if (!ssvpc)
6161 return;
6162
6163 e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6164 }
6165
6166 /**
6167 * ixgbe_watchdog_subtask - check and bring link up
6168 * @adapter - pointer to the device adapter structure
6169 **/
6170 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6171 {
6172 /* if interface is down do nothing */
6173 if (test_bit(__IXGBE_DOWN, &adapter->state))
6174 return;
6175
6176 ixgbe_watchdog_update_link(adapter);
6177
6178 if (adapter->link_up)
6179 ixgbe_watchdog_link_is_up(adapter);
6180 else
6181 ixgbe_watchdog_link_is_down(adapter);
6182
6183 ixgbe_spoof_check(adapter);
6184 ixgbe_update_stats(adapter);
6185
6186 ixgbe_watchdog_flush_tx(adapter);
6187 }
6188
6189 /**
6190 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6191 * @adapter - the ixgbe adapter structure
6192 **/
6193 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6194 {
6195 struct ixgbe_hw *hw = &adapter->hw;
6196 s32 err;
6197
6198 /* not searching for SFP so there is nothing to do here */
6199 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6200 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6201 return;
6202
6203 /* someone else is in init, wait until next service event */
6204 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6205 return;
6206
6207 err = hw->phy.ops.identify_sfp(hw);
6208 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6209 goto sfp_out;
6210
6211 if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6212 /* If no cable is present, then we need to reset
6213 * the next time we find a good cable. */
6214 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6215 }
6216
6217 /* exit on error */
6218 if (err)
6219 goto sfp_out;
6220
6221 /* exit if reset not needed */
6222 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6223 goto sfp_out;
6224
6225 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6226
6227 /*
6228 * A module may be identified correctly, but the EEPROM may not have
6229 * support for that module. setup_sfp() will fail in that case, so
6230 * we should not allow that module to load.
6231 */
6232 if (hw->mac.type == ixgbe_mac_82598EB)
6233 err = hw->phy.ops.reset(hw);
6234 else
6235 err = hw->mac.ops.setup_sfp(hw);
6236
6237 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6238 goto sfp_out;
6239
6240 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6241 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6242
6243 sfp_out:
6244 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6245
6246 if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6247 (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6248 e_dev_err("failed to initialize because an unsupported "
6249 "SFP+ module type was detected.\n");
6250 e_dev_err("Reload the driver after installing a "
6251 "supported module.\n");
6252 unregister_netdev(adapter->netdev);
6253 }
6254 }
6255
6256 /**
6257 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6258 * @adapter - the ixgbe adapter structure
6259 **/
6260 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6261 {
6262 struct ixgbe_hw *hw = &adapter->hw;
6263 u32 autoneg;
6264 bool negotiation;
6265
6266 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6267 return;
6268
6269 /* someone else is in init, wait until next service event */
6270 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6271 return;
6272
6273 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6274
6275 autoneg = hw->phy.autoneg_advertised;
6276 if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6277 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6278 hw->mac.autotry_restart = false;
6279 if (hw->mac.ops.setup_link)
6280 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6281
6282 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6283 adapter->link_check_timeout = jiffies;
6284 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6285 }
6286
6287 /**
6288 * ixgbe_service_timer - Timer Call-back
6289 * @data: pointer to adapter cast into an unsigned long
6290 **/
6291 static void ixgbe_service_timer(unsigned long data)
6292 {
6293 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6294 unsigned long next_event_offset;
6295
6296 /* poll faster when waiting for link */
6297 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6298 next_event_offset = HZ / 10;
6299 else
6300 next_event_offset = HZ * 2;
6301
6302 /* Reset the timer */
6303 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6304
6305 ixgbe_service_event_schedule(adapter);
6306 }
6307
6308 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6309 {
6310 if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6311 return;
6312
6313 adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6314
6315 /* If we're already down or resetting, just bail */
6316 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6317 test_bit(__IXGBE_RESETTING, &adapter->state))
6318 return;
6319
6320 ixgbe_dump(adapter);
6321 netdev_err(adapter->netdev, "Reset adapter\n");
6322 adapter->tx_timeout_count++;
6323
6324 ixgbe_reinit_locked(adapter);
6325 }
6326
6327 /**
6328 * ixgbe_service_task - manages and runs subtasks
6329 * @work: pointer to work_struct containing our data
6330 **/
6331 static void ixgbe_service_task(struct work_struct *work)
6332 {
6333 struct ixgbe_adapter *adapter = container_of(work,
6334 struct ixgbe_adapter,
6335 service_task);
6336
6337 ixgbe_reset_subtask(adapter);
6338 ixgbe_sfp_detection_subtask(adapter);
6339 ixgbe_sfp_link_config_subtask(adapter);
6340 ixgbe_check_overtemp_subtask(adapter);
6341 ixgbe_watchdog_subtask(adapter);
6342 ixgbe_fdir_reinit_subtask(adapter);
6343 ixgbe_check_hang_subtask(adapter);
6344
6345 ixgbe_service_event_complete(adapter);
6346 }
6347
6348 void ixgbe_tx_ctxtdesc(struct ixgbe_ring *tx_ring, u32 vlan_macip_lens,
6349 u32 fcoe_sof_eof, u32 type_tucmd, u32 mss_l4len_idx)
6350 {
6351 struct ixgbe_adv_tx_context_desc *context_desc;
6352 u16 i = tx_ring->next_to_use;
6353
6354 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6355
6356 i++;
6357 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
6358
6359 /* set bits to identify this as an advanced context descriptor */
6360 type_tucmd |= IXGBE_TXD_CMD_DEXT | IXGBE_ADVTXD_DTYP_CTXT;
6361
6362 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6363 context_desc->seqnum_seed = cpu_to_le32(fcoe_sof_eof);
6364 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd);
6365 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6366 }
6367
6368 static int ixgbe_tso(struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6369 u32 tx_flags, __be16 protocol, u8 *hdr_len)
6370 {
6371 int err;
6372 u32 vlan_macip_lens, type_tucmd;
6373 u32 mss_l4len_idx, l4len;
6374
6375 if (!skb_is_gso(skb))
6376 return 0;
6377
6378 if (skb_header_cloned(skb)) {
6379 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6380 if (err)
6381 return err;
6382 }
6383
6384 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6385 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
6386
6387 if (protocol == __constant_htons(ETH_P_IP)) {
6388 struct iphdr *iph = ip_hdr(skb);
6389 iph->tot_len = 0;
6390 iph->check = 0;
6391 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6392 iph->daddr, 0,
6393 IPPROTO_TCP,
6394 0);
6395 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6396 } else if (skb_is_gso_v6(skb)) {
6397 ipv6_hdr(skb)->payload_len = 0;
6398 tcp_hdr(skb)->check =
6399 ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6400 &ipv6_hdr(skb)->daddr,
6401 0, IPPROTO_TCP, 0);
6402 }
6403
6404 l4len = tcp_hdrlen(skb);
6405 *hdr_len = skb_transport_offset(skb) + l4len;
6406
6407 /* mss_l4len_id: use 1 as index for TSO */
6408 mss_l4len_idx = l4len << IXGBE_ADVTXD_L4LEN_SHIFT;
6409 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
6410 mss_l4len_idx |= 1 << IXGBE_ADVTXD_IDX_SHIFT;
6411
6412 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
6413 vlan_macip_lens = skb_network_header_len(skb);
6414 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6415 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6416
6417 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0, type_tucmd,
6418 mss_l4len_idx);
6419
6420 return 1;
6421 }
6422
6423 static bool ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
6424 struct sk_buff *skb, u32 tx_flags,
6425 __be16 protocol)
6426 {
6427 u32 vlan_macip_lens = 0;
6428 u32 mss_l4len_idx = 0;
6429 u32 type_tucmd = 0;
6430
6431 if (skb->ip_summed != CHECKSUM_PARTIAL) {
6432 if (!(tx_flags & IXGBE_TX_FLAGS_VLAN))
6433 return false;
6434 } else {
6435 u8 l4_hdr = 0;
6436 switch (protocol) {
6437 case __constant_htons(ETH_P_IP):
6438 vlan_macip_lens |= skb_network_header_len(skb);
6439 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
6440 l4_hdr = ip_hdr(skb)->protocol;
6441 break;
6442 case __constant_htons(ETH_P_IPV6):
6443 vlan_macip_lens |= skb_network_header_len(skb);
6444 l4_hdr = ipv6_hdr(skb)->nexthdr;
6445 break;
6446 default:
6447 if (unlikely(net_ratelimit())) {
6448 dev_warn(tx_ring->dev,
6449 "partial checksum but proto=%x!\n",
6450 skb->protocol);
6451 }
6452 break;
6453 }
6454
6455 switch (l4_hdr) {
6456 case IPPROTO_TCP:
6457 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6458 mss_l4len_idx = tcp_hdrlen(skb) <<
6459 IXGBE_ADVTXD_L4LEN_SHIFT;
6460 break;
6461 case IPPROTO_SCTP:
6462 type_tucmd |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6463 mss_l4len_idx = sizeof(struct sctphdr) <<
6464 IXGBE_ADVTXD_L4LEN_SHIFT;
6465 break;
6466 case IPPROTO_UDP:
6467 mss_l4len_idx = sizeof(struct udphdr) <<
6468 IXGBE_ADVTXD_L4LEN_SHIFT;
6469 break;
6470 default:
6471 if (unlikely(net_ratelimit())) {
6472 dev_warn(tx_ring->dev,
6473 "partial checksum but l4 proto=%x!\n",
6474 skb->protocol);
6475 }
6476 break;
6477 }
6478 }
6479
6480 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
6481 vlan_macip_lens |= tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
6482
6483 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, 0,
6484 type_tucmd, mss_l4len_idx);
6485
6486 return (skb->ip_summed == CHECKSUM_PARTIAL);
6487 }
6488
6489 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6490 struct ixgbe_ring *tx_ring,
6491 struct sk_buff *skb, u32 tx_flags,
6492 unsigned int first, const u8 hdr_len)
6493 {
6494 struct device *dev = tx_ring->dev;
6495 struct ixgbe_tx_buffer *tx_buffer_info;
6496 unsigned int len;
6497 unsigned int total = skb->len;
6498 unsigned int offset = 0, size, count = 0;
6499 unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6500 unsigned int f;
6501 unsigned int bytecount = skb->len;
6502 u16 gso_segs = 1;
6503 u16 i;
6504
6505 i = tx_ring->next_to_use;
6506
6507 if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6508 /* excluding fcoe_crc_eof for FCoE */
6509 total -= sizeof(struct fcoe_crc_eof);
6510
6511 len = min(skb_headlen(skb), total);
6512 while (len) {
6513 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6514 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6515
6516 tx_buffer_info->length = size;
6517 tx_buffer_info->mapped_as_page = false;
6518 tx_buffer_info->dma = dma_map_single(dev,
6519 skb->data + offset,
6520 size, DMA_TO_DEVICE);
6521 if (dma_mapping_error(dev, tx_buffer_info->dma))
6522 goto dma_error;
6523 tx_buffer_info->time_stamp = jiffies;
6524 tx_buffer_info->next_to_watch = i;
6525
6526 len -= size;
6527 total -= size;
6528 offset += size;
6529 count++;
6530
6531 if (len) {
6532 i++;
6533 if (i == tx_ring->count)
6534 i = 0;
6535 }
6536 }
6537
6538 for (f = 0; f < nr_frags; f++) {
6539 struct skb_frag_struct *frag;
6540
6541 frag = &skb_shinfo(skb)->frags[f];
6542 len = min((unsigned int)frag->size, total);
6543 offset = frag->page_offset;
6544
6545 while (len) {
6546 i++;
6547 if (i == tx_ring->count)
6548 i = 0;
6549
6550 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6551 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6552
6553 tx_buffer_info->length = size;
6554 tx_buffer_info->dma = dma_map_page(dev,
6555 frag->page,
6556 offset, size,
6557 DMA_TO_DEVICE);
6558 tx_buffer_info->mapped_as_page = true;
6559 if (dma_mapping_error(dev, tx_buffer_info->dma))
6560 goto dma_error;
6561 tx_buffer_info->time_stamp = jiffies;
6562 tx_buffer_info->next_to_watch = i;
6563
6564 len -= size;
6565 total -= size;
6566 offset += size;
6567 count++;
6568 }
6569 if (total == 0)
6570 break;
6571 }
6572
6573 if (tx_flags & IXGBE_TX_FLAGS_TSO)
6574 gso_segs = skb_shinfo(skb)->gso_segs;
6575 #ifdef IXGBE_FCOE
6576 /* adjust for FCoE Sequence Offload */
6577 else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6578 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6579 skb_shinfo(skb)->gso_size);
6580 #endif /* IXGBE_FCOE */
6581 bytecount += (gso_segs - 1) * hdr_len;
6582
6583 /* multiply data chunks by size of headers */
6584 tx_ring->tx_buffer_info[i].bytecount = bytecount;
6585 tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6586 tx_ring->tx_buffer_info[i].skb = skb;
6587 tx_ring->tx_buffer_info[first].next_to_watch = i;
6588
6589 return count;
6590
6591 dma_error:
6592 e_dev_err("TX DMA map failed\n");
6593
6594 /* clear timestamp and dma mappings for failed tx_buffer_info map */
6595 tx_buffer_info->dma = 0;
6596 tx_buffer_info->time_stamp = 0;
6597 tx_buffer_info->next_to_watch = 0;
6598 if (count)
6599 count--;
6600
6601 /* clear timestamp and dma mappings for remaining portion of packet */
6602 while (count--) {
6603 if (i == 0)
6604 i += tx_ring->count;
6605 i--;
6606 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6607 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6608 }
6609
6610 return 0;
6611 }
6612
6613 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6614 int tx_flags, int count, u32 paylen, u8 hdr_len)
6615 {
6616 union ixgbe_adv_tx_desc *tx_desc = NULL;
6617 struct ixgbe_tx_buffer *tx_buffer_info;
6618 u32 olinfo_status = 0, cmd_type_len = 0;
6619 unsigned int i;
6620 u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6621
6622 cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6623
6624 cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6625
6626 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6627 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6628
6629 if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6630 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6631
6632 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6633 IXGBE_ADVTXD_POPTS_SHIFT;
6634
6635 /* use index 1 context for tso */
6636 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6637 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6638 olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6639 IXGBE_ADVTXD_POPTS_SHIFT;
6640
6641 } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6642 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6643 IXGBE_ADVTXD_POPTS_SHIFT;
6644
6645 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6646 olinfo_status |= IXGBE_ADVTXD_CC;
6647 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6648 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6649 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6650 }
6651
6652 olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6653
6654 i = tx_ring->next_to_use;
6655 while (count--) {
6656 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6657 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6658 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6659 tx_desc->read.cmd_type_len =
6660 cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6661 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6662 i++;
6663 if (i == tx_ring->count)
6664 i = 0;
6665 }
6666
6667 tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6668
6669 /*
6670 * Force memory writes to complete before letting h/w
6671 * know there are new descriptors to fetch. (Only
6672 * applicable for weak-ordered memory model archs,
6673 * such as IA-64).
6674 */
6675 wmb();
6676
6677 tx_ring->next_to_use = i;
6678 writel(i, tx_ring->tail);
6679 }
6680
6681 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6682 u32 tx_flags, __be16 protocol)
6683 {
6684 struct ixgbe_q_vector *q_vector = ring->q_vector;
6685 union ixgbe_atr_hash_dword input = { .dword = 0 };
6686 union ixgbe_atr_hash_dword common = { .dword = 0 };
6687 union {
6688 unsigned char *network;
6689 struct iphdr *ipv4;
6690 struct ipv6hdr *ipv6;
6691 } hdr;
6692 struct tcphdr *th;
6693 __be16 vlan_id;
6694
6695 /* if ring doesn't have a interrupt vector, cannot perform ATR */
6696 if (!q_vector)
6697 return;
6698
6699 /* do nothing if sampling is disabled */
6700 if (!ring->atr_sample_rate)
6701 return;
6702
6703 ring->atr_count++;
6704
6705 /* snag network header to get L4 type and address */
6706 hdr.network = skb_network_header(skb);
6707
6708 /* Currently only IPv4/IPv6 with TCP is supported */
6709 if ((protocol != __constant_htons(ETH_P_IPV6) ||
6710 hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6711 (protocol != __constant_htons(ETH_P_IP) ||
6712 hdr.ipv4->protocol != IPPROTO_TCP))
6713 return;
6714
6715 th = tcp_hdr(skb);
6716
6717 /* skip this packet since the socket is closing */
6718 if (th->fin)
6719 return;
6720
6721 /* sample on all syn packets or once every atr sample count */
6722 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6723 return;
6724
6725 /* reset sample count */
6726 ring->atr_count = 0;
6727
6728 vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6729
6730 /*
6731 * src and dst are inverted, think how the receiver sees them
6732 *
6733 * The input is broken into two sections, a non-compressed section
6734 * containing vm_pool, vlan_id, and flow_type. The rest of the data
6735 * is XORed together and stored in the compressed dword.
6736 */
6737 input.formatted.vlan_id = vlan_id;
6738
6739 /*
6740 * since src port and flex bytes occupy the same word XOR them together
6741 * and write the value to source port portion of compressed dword
6742 */
6743 if (vlan_id)
6744 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6745 else
6746 common.port.src ^= th->dest ^ protocol;
6747 common.port.dst ^= th->source;
6748
6749 if (protocol == __constant_htons(ETH_P_IP)) {
6750 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6751 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6752 } else {
6753 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6754 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6755 hdr.ipv6->saddr.s6_addr32[1] ^
6756 hdr.ipv6->saddr.s6_addr32[2] ^
6757 hdr.ipv6->saddr.s6_addr32[3] ^
6758 hdr.ipv6->daddr.s6_addr32[0] ^
6759 hdr.ipv6->daddr.s6_addr32[1] ^
6760 hdr.ipv6->daddr.s6_addr32[2] ^
6761 hdr.ipv6->daddr.s6_addr32[3];
6762 }
6763
6764 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6765 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6766 input, common, ring->queue_index);
6767 }
6768
6769 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6770 {
6771 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6772 /* Herbert's original patch had:
6773 * smp_mb__after_netif_stop_queue();
6774 * but since that doesn't exist yet, just open code it. */
6775 smp_mb();
6776
6777 /* We need to check again in a case another CPU has just
6778 * made room available. */
6779 if (likely(ixgbe_desc_unused(tx_ring) < size))
6780 return -EBUSY;
6781
6782 /* A reprieve! - use start_queue because it doesn't call schedule */
6783 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6784 ++tx_ring->tx_stats.restart_queue;
6785 return 0;
6786 }
6787
6788 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
6789 {
6790 if (likely(ixgbe_desc_unused(tx_ring) >= size))
6791 return 0;
6792 return __ixgbe_maybe_stop_tx(tx_ring, size);
6793 }
6794
6795 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6796 {
6797 struct ixgbe_adapter *adapter = netdev_priv(dev);
6798 int txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
6799 smp_processor_id();
6800 #ifdef IXGBE_FCOE
6801 __be16 protocol = vlan_get_protocol(skb);
6802
6803 if (((protocol == htons(ETH_P_FCOE)) ||
6804 (protocol == htons(ETH_P_FIP))) &&
6805 (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6806 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6807 txq += adapter->ring_feature[RING_F_FCOE].mask;
6808 return txq;
6809 }
6810 #endif
6811
6812 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6813 while (unlikely(txq >= dev->real_num_tx_queues))
6814 txq -= dev->real_num_tx_queues;
6815 return txq;
6816 }
6817
6818 return skb_tx_hash(dev, skb);
6819 }
6820
6821 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6822 struct ixgbe_adapter *adapter,
6823 struct ixgbe_ring *tx_ring)
6824 {
6825 int tso;
6826 u32 tx_flags = 0;
6827 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6828 unsigned short f;
6829 #endif
6830 u16 first;
6831 u16 count = TXD_USE_COUNT(skb_headlen(skb));
6832 __be16 protocol;
6833 u8 hdr_len = 0;
6834
6835 /*
6836 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
6837 * + 1 desc for skb_head_len/IXGBE_MAX_DATA_PER_TXD,
6838 * + 2 desc gap to keep tail from touching head,
6839 * + 1 desc for context descriptor,
6840 * otherwise try next time
6841 */
6842 #if PAGE_SIZE > IXGBE_MAX_DATA_PER_TXD
6843 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6844 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6845 #else
6846 count += skb_shinfo(skb)->nr_frags;
6847 #endif
6848 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
6849 tx_ring->tx_stats.tx_busy++;
6850 return NETDEV_TX_BUSY;
6851 }
6852
6853 protocol = vlan_get_protocol(skb);
6854
6855 if (vlan_tx_tag_present(skb)) {
6856 tx_flags |= vlan_tx_tag_get(skb);
6857 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6858 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6859 tx_flags |= tx_ring->dcb_tc << 13;
6860 }
6861 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6862 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6863 } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6864 skb->priority != TC_PRIO_CONTROL) {
6865 tx_flags |= tx_ring->dcb_tc << 13;
6866 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6867 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6868 }
6869
6870 #ifdef IXGBE_FCOE
6871 /* for FCoE with DCB, we force the priority to what
6872 * was specified by the switch */
6873 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6874 (protocol == htons(ETH_P_FCOE)))
6875 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6876
6877 #endif
6878 /* record the location of the first descriptor for this packet */
6879 first = tx_ring->next_to_use;
6880
6881 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6882 #ifdef IXGBE_FCOE
6883 /* setup tx offload for FCoE */
6884 tso = ixgbe_fso(tx_ring, skb, tx_flags, &hdr_len);
6885 if (tso < 0)
6886 goto out_drop;
6887 else if (tso)
6888 tx_flags |= IXGBE_TX_FLAGS_FSO;
6889 #endif /* IXGBE_FCOE */
6890 } else {
6891 if (protocol == htons(ETH_P_IP))
6892 tx_flags |= IXGBE_TX_FLAGS_IPV4;
6893 tso = ixgbe_tso(tx_ring, skb, tx_flags, protocol, &hdr_len);
6894 if (tso < 0)
6895 goto out_drop;
6896 else if (tso)
6897 tx_flags |= IXGBE_TX_FLAGS_TSO;
6898 else if (ixgbe_tx_csum(tx_ring, skb, tx_flags, protocol))
6899 tx_flags |= IXGBE_TX_FLAGS_CSUM;
6900 }
6901
6902 count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6903 if (count) {
6904 /* add the ATR filter if ATR is on */
6905 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6906 ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6907 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6908 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6909
6910 } else {
6911 tx_ring->tx_buffer_info[first].time_stamp = 0;
6912 tx_ring->next_to_use = first;
6913 goto out_drop;
6914 }
6915
6916 return NETDEV_TX_OK;
6917
6918 out_drop:
6919 dev_kfree_skb_any(skb);
6920 return NETDEV_TX_OK;
6921 }
6922
6923 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6924 {
6925 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6926 struct ixgbe_ring *tx_ring;
6927
6928 tx_ring = adapter->tx_ring[skb->queue_mapping];
6929 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6930 }
6931
6932 /**
6933 * ixgbe_set_mac - Change the Ethernet Address of the NIC
6934 * @netdev: network interface device structure
6935 * @p: pointer to an address structure
6936 *
6937 * Returns 0 on success, negative on failure
6938 **/
6939 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6940 {
6941 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6942 struct ixgbe_hw *hw = &adapter->hw;
6943 struct sockaddr *addr = p;
6944
6945 if (!is_valid_ether_addr(addr->sa_data))
6946 return -EADDRNOTAVAIL;
6947
6948 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6949 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6950
6951 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6952 IXGBE_RAH_AV);
6953
6954 return 0;
6955 }
6956
6957 static int
6958 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6959 {
6960 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6961 struct ixgbe_hw *hw = &adapter->hw;
6962 u16 value;
6963 int rc;
6964
6965 if (prtad != hw->phy.mdio.prtad)
6966 return -EINVAL;
6967 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6968 if (!rc)
6969 rc = value;
6970 return rc;
6971 }
6972
6973 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6974 u16 addr, u16 value)
6975 {
6976 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6977 struct ixgbe_hw *hw = &adapter->hw;
6978
6979 if (prtad != hw->phy.mdio.prtad)
6980 return -EINVAL;
6981 return hw->phy.ops.write_reg(hw, addr, devad, value);
6982 }
6983
6984 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6985 {
6986 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6987
6988 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6989 }
6990
6991 /**
6992 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6993 * netdev->dev_addrs
6994 * @netdev: network interface device structure
6995 *
6996 * Returns non-zero on failure
6997 **/
6998 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6999 {
7000 int err = 0;
7001 struct ixgbe_adapter *adapter = netdev_priv(dev);
7002 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7003
7004 if (is_valid_ether_addr(mac->san_addr)) {
7005 rtnl_lock();
7006 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7007 rtnl_unlock();
7008 }
7009 return err;
7010 }
7011
7012 /**
7013 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7014 * netdev->dev_addrs
7015 * @netdev: network interface device structure
7016 *
7017 * Returns non-zero on failure
7018 **/
7019 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7020 {
7021 int err = 0;
7022 struct ixgbe_adapter *adapter = netdev_priv(dev);
7023 struct ixgbe_mac_info *mac = &adapter->hw.mac;
7024
7025 if (is_valid_ether_addr(mac->san_addr)) {
7026 rtnl_lock();
7027 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7028 rtnl_unlock();
7029 }
7030 return err;
7031 }
7032
7033 #ifdef CONFIG_NET_POLL_CONTROLLER
7034 /*
7035 * Polling 'interrupt' - used by things like netconsole to send skbs
7036 * without having to re-enable interrupts. It's not called while
7037 * the interrupt routine is executing.
7038 */
7039 static void ixgbe_netpoll(struct net_device *netdev)
7040 {
7041 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7042 int i;
7043
7044 /* if interface is down do nothing */
7045 if (test_bit(__IXGBE_DOWN, &adapter->state))
7046 return;
7047
7048 adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7049 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7050 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7051 for (i = 0; i < num_q_vectors; i++) {
7052 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7053 ixgbe_msix_clean_many(0, q_vector);
7054 }
7055 } else {
7056 ixgbe_intr(adapter->pdev->irq, netdev);
7057 }
7058 adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7059 }
7060 #endif
7061
7062 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7063 struct rtnl_link_stats64 *stats)
7064 {
7065 struct ixgbe_adapter *adapter = netdev_priv(netdev);
7066 int i;
7067
7068 rcu_read_lock();
7069 for (i = 0; i < adapter->num_rx_queues; i++) {
7070 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7071 u64 bytes, packets;
7072 unsigned int start;
7073
7074 if (ring) {
7075 do {
7076 start = u64_stats_fetch_begin_bh(&ring->syncp);
7077 packets = ring->stats.packets;
7078 bytes = ring->stats.bytes;
7079 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7080 stats->rx_packets += packets;
7081 stats->rx_bytes += bytes;
7082 }
7083 }
7084
7085 for (i = 0; i < adapter->num_tx_queues; i++) {
7086 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7087 u64 bytes, packets;
7088 unsigned int start;
7089
7090 if (ring) {
7091 do {
7092 start = u64_stats_fetch_begin_bh(&ring->syncp);
7093 packets = ring->stats.packets;
7094 bytes = ring->stats.bytes;
7095 } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7096 stats->tx_packets += packets;
7097 stats->tx_bytes += bytes;
7098 }
7099 }
7100 rcu_read_unlock();
7101 /* following stats updated by ixgbe_watchdog_task() */
7102 stats->multicast = netdev->stats.multicast;
7103 stats->rx_errors = netdev->stats.rx_errors;
7104 stats->rx_length_errors = netdev->stats.rx_length_errors;
7105 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
7106 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7107 return stats;
7108 }
7109
7110 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7111 * #adapter: pointer to ixgbe_adapter
7112 * @tc: number of traffic classes currently enabled
7113 *
7114 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7115 * 802.1Q priority maps to a packet buffer that exists.
7116 */
7117 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7118 {
7119 struct ixgbe_hw *hw = &adapter->hw;
7120 u32 reg, rsave;
7121 int i;
7122
7123 /* 82598 have a static priority to TC mapping that can not
7124 * be changed so no validation is needed.
7125 */
7126 if (hw->mac.type == ixgbe_mac_82598EB)
7127 return;
7128
7129 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7130 rsave = reg;
7131
7132 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7133 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7134
7135 /* If up2tc is out of bounds default to zero */
7136 if (up2tc > tc)
7137 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7138 }
7139
7140 if (reg != rsave)
7141 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7142
7143 return;
7144 }
7145
7146
7147 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7148 * classes.
7149 *
7150 * @netdev: net device to configure
7151 * @tc: number of traffic classes to enable
7152 */
7153 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7154 {
7155 struct ixgbe_adapter *adapter = netdev_priv(dev);
7156 struct ixgbe_hw *hw = &adapter->hw;
7157
7158 /* If DCB is anabled do not remove traffic classes, multiple
7159 * traffic classes are required to implement DCB
7160 */
7161 if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7162 return 0;
7163
7164 /* Hardware supports up to 8 traffic classes */
7165 if (tc > MAX_TRAFFIC_CLASS ||
7166 (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7167 return -EINVAL;
7168
7169 /* Hardware has to reinitialize queues and interrupts to
7170 * match packet buffer alignment. Unfortunantly, the
7171 * hardware is not flexible enough to do this dynamically.
7172 */
7173 if (netif_running(dev))
7174 ixgbe_close(dev);
7175 ixgbe_clear_interrupt_scheme(adapter);
7176
7177 if (tc)
7178 netdev_set_num_tc(dev, tc);
7179 else
7180 netdev_reset_tc(dev);
7181
7182 ixgbe_init_interrupt_scheme(adapter);
7183 ixgbe_validate_rtr(adapter, tc);
7184 if (netif_running(dev))
7185 ixgbe_open(dev);
7186
7187 return 0;
7188 }
7189
7190 static const struct net_device_ops ixgbe_netdev_ops = {
7191 .ndo_open = ixgbe_open,
7192 .ndo_stop = ixgbe_close,
7193 .ndo_start_xmit = ixgbe_xmit_frame,
7194 .ndo_select_queue = ixgbe_select_queue,
7195 .ndo_set_rx_mode = ixgbe_set_rx_mode,
7196 .ndo_set_multicast_list = ixgbe_set_rx_mode,
7197 .ndo_validate_addr = eth_validate_addr,
7198 .ndo_set_mac_address = ixgbe_set_mac,
7199 .ndo_change_mtu = ixgbe_change_mtu,
7200 .ndo_tx_timeout = ixgbe_tx_timeout,
7201 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
7202 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
7203 .ndo_do_ioctl = ixgbe_ioctl,
7204 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
7205 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
7206 .ndo_set_vf_tx_rate = ixgbe_ndo_set_vf_bw,
7207 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
7208 .ndo_get_stats64 = ixgbe_get_stats64,
7209 .ndo_setup_tc = ixgbe_setup_tc,
7210 #ifdef CONFIG_NET_POLL_CONTROLLER
7211 .ndo_poll_controller = ixgbe_netpoll,
7212 #endif
7213 #ifdef IXGBE_FCOE
7214 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7215 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7216 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7217 .ndo_fcoe_enable = ixgbe_fcoe_enable,
7218 .ndo_fcoe_disable = ixgbe_fcoe_disable,
7219 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7220 #endif /* IXGBE_FCOE */
7221 };
7222
7223 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7224 const struct ixgbe_info *ii)
7225 {
7226 #ifdef CONFIG_PCI_IOV
7227 struct ixgbe_hw *hw = &adapter->hw;
7228 int err;
7229 int num_vf_macvlans, i;
7230 struct vf_macvlans *mv_list;
7231
7232 if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7233 return;
7234
7235 /* The 82599 supports up to 64 VFs per physical function
7236 * but this implementation limits allocation to 63 so that
7237 * basic networking resources are still available to the
7238 * physical function
7239 */
7240 adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7241 adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7242 err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7243 if (err) {
7244 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7245 goto err_novfs;
7246 }
7247
7248 num_vf_macvlans = hw->mac.num_rar_entries -
7249 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7250
7251 adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7252 sizeof(struct vf_macvlans),
7253 GFP_KERNEL);
7254 if (mv_list) {
7255 /* Initialize list of VF macvlans */
7256 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7257 for (i = 0; i < num_vf_macvlans; i++) {
7258 mv_list->vf = -1;
7259 mv_list->free = true;
7260 mv_list->rar_entry = hw->mac.num_rar_entries -
7261 (i + adapter->num_vfs + 1);
7262 list_add(&mv_list->l, &adapter->vf_mvs.l);
7263 mv_list++;
7264 }
7265 }
7266
7267 /* If call to enable VFs succeeded then allocate memory
7268 * for per VF control structures.
7269 */
7270 adapter->vfinfo =
7271 kcalloc(adapter->num_vfs,
7272 sizeof(struct vf_data_storage), GFP_KERNEL);
7273 if (adapter->vfinfo) {
7274 /* Now that we're sure SR-IOV is enabled
7275 * and memory allocated set up the mailbox parameters
7276 */
7277 ixgbe_init_mbx_params_pf(hw);
7278 memcpy(&hw->mbx.ops, ii->mbx_ops,
7279 sizeof(hw->mbx.ops));
7280
7281 /* Disable RSC when in SR-IOV mode */
7282 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7283 IXGBE_FLAG2_RSC_ENABLED);
7284 return;
7285 }
7286
7287 /* Oh oh */
7288 e_err(probe, "Unable to allocate memory for VF Data Storage - "
7289 "SRIOV disabled\n");
7290 pci_disable_sriov(adapter->pdev);
7291
7292 err_novfs:
7293 adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7294 adapter->num_vfs = 0;
7295 #endif /* CONFIG_PCI_IOV */
7296 }
7297
7298 /**
7299 * ixgbe_probe - Device Initialization Routine
7300 * @pdev: PCI device information struct
7301 * @ent: entry in ixgbe_pci_tbl
7302 *
7303 * Returns 0 on success, negative on failure
7304 *
7305 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7306 * The OS initialization, configuring of the adapter private structure,
7307 * and a hardware reset occur.
7308 **/
7309 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7310 const struct pci_device_id *ent)
7311 {
7312 struct net_device *netdev;
7313 struct ixgbe_adapter *adapter = NULL;
7314 struct ixgbe_hw *hw;
7315 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7316 static int cards_found;
7317 int i, err, pci_using_dac;
7318 u8 part_str[IXGBE_PBANUM_LENGTH];
7319 unsigned int indices = num_possible_cpus();
7320 #ifdef IXGBE_FCOE
7321 u16 device_caps;
7322 #endif
7323 u32 eec;
7324
7325 /* Catch broken hardware that put the wrong VF device ID in
7326 * the PCIe SR-IOV capability.
7327 */
7328 if (pdev->is_virtfn) {
7329 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7330 pci_name(pdev), pdev->vendor, pdev->device);
7331 return -EINVAL;
7332 }
7333
7334 err = pci_enable_device_mem(pdev);
7335 if (err)
7336 return err;
7337
7338 if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7339 !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7340 pci_using_dac = 1;
7341 } else {
7342 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7343 if (err) {
7344 err = dma_set_coherent_mask(&pdev->dev,
7345 DMA_BIT_MASK(32));
7346 if (err) {
7347 dev_err(&pdev->dev,
7348 "No usable DMA configuration, aborting\n");
7349 goto err_dma;
7350 }
7351 }
7352 pci_using_dac = 0;
7353 }
7354
7355 err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7356 IORESOURCE_MEM), ixgbe_driver_name);
7357 if (err) {
7358 dev_err(&pdev->dev,
7359 "pci_request_selected_regions failed 0x%x\n", err);
7360 goto err_pci_reg;
7361 }
7362
7363 pci_enable_pcie_error_reporting(pdev);
7364
7365 pci_set_master(pdev);
7366 pci_save_state(pdev);
7367
7368 #ifdef CONFIG_IXGBE_DCB
7369 indices *= MAX_TRAFFIC_CLASS;
7370 #endif
7371
7372 if (ii->mac == ixgbe_mac_82598EB)
7373 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7374 else
7375 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7376
7377 #ifdef IXGBE_FCOE
7378 indices += min_t(unsigned int, num_possible_cpus(),
7379 IXGBE_MAX_FCOE_INDICES);
7380 #endif
7381 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7382 if (!netdev) {
7383 err = -ENOMEM;
7384 goto err_alloc_etherdev;
7385 }
7386
7387 SET_NETDEV_DEV(netdev, &pdev->dev);
7388
7389 adapter = netdev_priv(netdev);
7390 pci_set_drvdata(pdev, adapter);
7391
7392 adapter->netdev = netdev;
7393 adapter->pdev = pdev;
7394 hw = &adapter->hw;
7395 hw->back = adapter;
7396 adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7397
7398 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7399 pci_resource_len(pdev, 0));
7400 if (!hw->hw_addr) {
7401 err = -EIO;
7402 goto err_ioremap;
7403 }
7404
7405 for (i = 1; i <= 5; i++) {
7406 if (pci_resource_len(pdev, i) == 0)
7407 continue;
7408 }
7409
7410 netdev->netdev_ops = &ixgbe_netdev_ops;
7411 ixgbe_set_ethtool_ops(netdev);
7412 netdev->watchdog_timeo = 5 * HZ;
7413 strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7414
7415 adapter->bd_number = cards_found;
7416
7417 /* Setup hw api */
7418 memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7419 hw->mac.type = ii->mac;
7420
7421 /* EEPROM */
7422 memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7423 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7424 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7425 if (!(eec & (1 << 8)))
7426 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7427
7428 /* PHY */
7429 memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7430 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7431 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7432 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7433 hw->phy.mdio.mmds = 0;
7434 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7435 hw->phy.mdio.dev = netdev;
7436 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7437 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7438
7439 ii->get_invariants(hw);
7440
7441 /* setup the private structure */
7442 err = ixgbe_sw_init(adapter);
7443 if (err)
7444 goto err_sw_init;
7445
7446 /* Make it possible the adapter to be woken up via WOL */
7447 switch (adapter->hw.mac.type) {
7448 case ixgbe_mac_82599EB:
7449 case ixgbe_mac_X540:
7450 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7451 break;
7452 default:
7453 break;
7454 }
7455
7456 /*
7457 * If there is a fan on this device and it has failed log the
7458 * failure.
7459 */
7460 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7461 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7462 if (esdp & IXGBE_ESDP_SDP1)
7463 e_crit(probe, "Fan has stopped, replace the adapter\n");
7464 }
7465
7466 /* reset_hw fills in the perm_addr as well */
7467 hw->phy.reset_if_overtemp = true;
7468 err = hw->mac.ops.reset_hw(hw);
7469 hw->phy.reset_if_overtemp = false;
7470 if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7471 hw->mac.type == ixgbe_mac_82598EB) {
7472 err = 0;
7473 } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7474 e_dev_err("failed to load because an unsupported SFP+ "
7475 "module type was detected.\n");
7476 e_dev_err("Reload the driver after installing a supported "
7477 "module.\n");
7478 goto err_sw_init;
7479 } else if (err) {
7480 e_dev_err("HW Init failed: %d\n", err);
7481 goto err_sw_init;
7482 }
7483
7484 ixgbe_probe_vf(adapter, ii);
7485
7486 netdev->features = NETIF_F_SG |
7487 NETIF_F_IP_CSUM |
7488 NETIF_F_HW_VLAN_TX |
7489 NETIF_F_HW_VLAN_RX |
7490 NETIF_F_HW_VLAN_FILTER;
7491
7492 netdev->features |= NETIF_F_IPV6_CSUM;
7493 netdev->features |= NETIF_F_TSO;
7494 netdev->features |= NETIF_F_TSO6;
7495 netdev->features |= NETIF_F_GRO;
7496 netdev->features |= NETIF_F_RXHASH;
7497
7498 switch (adapter->hw.mac.type) {
7499 case ixgbe_mac_82599EB:
7500 case ixgbe_mac_X540:
7501 netdev->features |= NETIF_F_SCTP_CSUM;
7502 break;
7503 default:
7504 break;
7505 }
7506
7507 netdev->vlan_features |= NETIF_F_TSO;
7508 netdev->vlan_features |= NETIF_F_TSO6;
7509 netdev->vlan_features |= NETIF_F_IP_CSUM;
7510 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7511 netdev->vlan_features |= NETIF_F_SG;
7512
7513 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7514 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7515 IXGBE_FLAG_DCB_ENABLED);
7516
7517 #ifdef CONFIG_IXGBE_DCB
7518 netdev->dcbnl_ops = &dcbnl_ops;
7519 #endif
7520
7521 #ifdef IXGBE_FCOE
7522 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7523 if (hw->mac.ops.get_device_caps) {
7524 hw->mac.ops.get_device_caps(hw, &device_caps);
7525 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7526 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7527 }
7528 }
7529 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7530 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7531 netdev->vlan_features |= NETIF_F_FSO;
7532 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7533 }
7534 #endif /* IXGBE_FCOE */
7535 if (pci_using_dac) {
7536 netdev->features |= NETIF_F_HIGHDMA;
7537 netdev->vlan_features |= NETIF_F_HIGHDMA;
7538 }
7539
7540 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7541 netdev->features |= NETIF_F_LRO;
7542
7543 /* make sure the EEPROM is good */
7544 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7545 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7546 err = -EIO;
7547 goto err_eeprom;
7548 }
7549
7550 memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7551 memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7552
7553 if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7554 e_dev_err("invalid MAC address\n");
7555 err = -EIO;
7556 goto err_eeprom;
7557 }
7558
7559 /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7560 if (hw->mac.ops.disable_tx_laser &&
7561 ((hw->phy.multispeed_fiber) ||
7562 ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7563 (hw->mac.type == ixgbe_mac_82599EB))))
7564 hw->mac.ops.disable_tx_laser(hw);
7565
7566 setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7567 (unsigned long) adapter);
7568
7569 INIT_WORK(&adapter->service_task, ixgbe_service_task);
7570 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7571
7572 err = ixgbe_init_interrupt_scheme(adapter);
7573 if (err)
7574 goto err_sw_init;
7575
7576 if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7577 netdev->features &= ~NETIF_F_RXHASH;
7578
7579 switch (pdev->device) {
7580 case IXGBE_DEV_ID_82599_SFP:
7581 /* Only this subdevice supports WOL */
7582 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7583 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7584 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7585 break;
7586 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7587 /* All except this subdevice support WOL */
7588 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7589 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7590 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7591 break;
7592 case IXGBE_DEV_ID_82599_KX4:
7593 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7594 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7595 break;
7596 default:
7597 adapter->wol = 0;
7598 break;
7599 }
7600 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7601
7602 /* pick up the PCI bus settings for reporting later */
7603 hw->mac.ops.get_bus_info(hw);
7604
7605 /* print bus type/speed/width info */
7606 e_dev_info("(PCI Express:%s:%s) %pM\n",
7607 (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7608 hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7609 "Unknown"),
7610 (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7611 hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7612 hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7613 "Unknown"),
7614 netdev->dev_addr);
7615
7616 err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7617 if (err)
7618 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7619 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7620 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7621 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7622 part_str);
7623 else
7624 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7625 hw->mac.type, hw->phy.type, part_str);
7626
7627 if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7628 e_dev_warn("PCI-Express bandwidth available for this card is "
7629 "not sufficient for optimal performance.\n");
7630 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7631 "is required.\n");
7632 }
7633
7634 /* save off EEPROM version number */
7635 hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7636
7637 /* reset the hardware with the new settings */
7638 err = hw->mac.ops.start_hw(hw);
7639
7640 if (err == IXGBE_ERR_EEPROM_VERSION) {
7641 /* We are running on a pre-production device, log a warning */
7642 e_dev_warn("This device is a pre-production adapter/LOM. "
7643 "Please be aware there may be issues associated "
7644 "with your hardware. If you are experiencing "
7645 "problems please contact your Intel or hardware "
7646 "representative who provided you with this "
7647 "hardware.\n");
7648 }
7649 strcpy(netdev->name, "eth%d");
7650 err = register_netdev(netdev);
7651 if (err)
7652 goto err_register;
7653
7654 /* carrier off reporting is important to ethtool even BEFORE open */
7655 netif_carrier_off(netdev);
7656
7657 #ifdef CONFIG_IXGBE_DCA
7658 if (dca_add_requester(&pdev->dev) == 0) {
7659 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7660 ixgbe_setup_dca(adapter);
7661 }
7662 #endif
7663 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7664 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7665 for (i = 0; i < adapter->num_vfs; i++)
7666 ixgbe_vf_configuration(pdev, (i | 0x10000000));
7667 }
7668
7669 /* Inform firmware of driver version */
7670 if (hw->mac.ops.set_fw_drv_ver)
7671 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD,
7672 FW_CEM_UNUSED_VER);
7673
7674 /* add san mac addr to netdev */
7675 ixgbe_add_sanmac_netdev(netdev);
7676
7677 e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7678 cards_found++;
7679 return 0;
7680
7681 err_register:
7682 ixgbe_release_hw_control(adapter);
7683 ixgbe_clear_interrupt_scheme(adapter);
7684 err_sw_init:
7685 err_eeprom:
7686 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7687 ixgbe_disable_sriov(adapter);
7688 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7689 iounmap(hw->hw_addr);
7690 err_ioremap:
7691 free_netdev(netdev);
7692 err_alloc_etherdev:
7693 pci_release_selected_regions(pdev,
7694 pci_select_bars(pdev, IORESOURCE_MEM));
7695 err_pci_reg:
7696 err_dma:
7697 pci_disable_device(pdev);
7698 return err;
7699 }
7700
7701 /**
7702 * ixgbe_remove - Device Removal Routine
7703 * @pdev: PCI device information struct
7704 *
7705 * ixgbe_remove is called by the PCI subsystem to alert the driver
7706 * that it should release a PCI device. The could be caused by a
7707 * Hot-Plug event, or because the driver is going to be removed from
7708 * memory.
7709 **/
7710 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7711 {
7712 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7713 struct net_device *netdev = adapter->netdev;
7714
7715 set_bit(__IXGBE_DOWN, &adapter->state);
7716 cancel_work_sync(&adapter->service_task);
7717
7718 #ifdef CONFIG_IXGBE_DCA
7719 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7720 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7721 dca_remove_requester(&pdev->dev);
7722 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7723 }
7724
7725 #endif
7726 #ifdef IXGBE_FCOE
7727 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7728 ixgbe_cleanup_fcoe(adapter);
7729
7730 #endif /* IXGBE_FCOE */
7731
7732 /* remove the added san mac */
7733 ixgbe_del_sanmac_netdev(netdev);
7734
7735 if (netdev->reg_state == NETREG_REGISTERED)
7736 unregister_netdev(netdev);
7737
7738 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7739 ixgbe_disable_sriov(adapter);
7740
7741 ixgbe_clear_interrupt_scheme(adapter);
7742
7743 ixgbe_release_hw_control(adapter);
7744
7745 iounmap(adapter->hw.hw_addr);
7746 pci_release_selected_regions(pdev, pci_select_bars(pdev,
7747 IORESOURCE_MEM));
7748
7749 e_dev_info("complete\n");
7750
7751 free_netdev(netdev);
7752
7753 pci_disable_pcie_error_reporting(pdev);
7754
7755 pci_disable_device(pdev);
7756 }
7757
7758 /**
7759 * ixgbe_io_error_detected - called when PCI error is detected
7760 * @pdev: Pointer to PCI device
7761 * @state: The current pci connection state
7762 *
7763 * This function is called after a PCI bus error affecting
7764 * this device has been detected.
7765 */
7766 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7767 pci_channel_state_t state)
7768 {
7769 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7770 struct net_device *netdev = adapter->netdev;
7771
7772 netif_device_detach(netdev);
7773
7774 if (state == pci_channel_io_perm_failure)
7775 return PCI_ERS_RESULT_DISCONNECT;
7776
7777 if (netif_running(netdev))
7778 ixgbe_down(adapter);
7779 pci_disable_device(pdev);
7780
7781 /* Request a slot reset. */
7782 return PCI_ERS_RESULT_NEED_RESET;
7783 }
7784
7785 /**
7786 * ixgbe_io_slot_reset - called after the pci bus has been reset.
7787 * @pdev: Pointer to PCI device
7788 *
7789 * Restart the card from scratch, as if from a cold-boot.
7790 */
7791 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7792 {
7793 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7794 pci_ers_result_t result;
7795 int err;
7796
7797 if (pci_enable_device_mem(pdev)) {
7798 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7799 result = PCI_ERS_RESULT_DISCONNECT;
7800 } else {
7801 pci_set_master(pdev);
7802 pci_restore_state(pdev);
7803 pci_save_state(pdev);
7804
7805 pci_wake_from_d3(pdev, false);
7806
7807 ixgbe_reset(adapter);
7808 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7809 result = PCI_ERS_RESULT_RECOVERED;
7810 }
7811
7812 err = pci_cleanup_aer_uncorrect_error_status(pdev);
7813 if (err) {
7814 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7815 "failed 0x%0x\n", err);
7816 /* non-fatal, continue */
7817 }
7818
7819 return result;
7820 }
7821
7822 /**
7823 * ixgbe_io_resume - called when traffic can start flowing again.
7824 * @pdev: Pointer to PCI device
7825 *
7826 * This callback is called when the error recovery driver tells us that
7827 * its OK to resume normal operation.
7828 */
7829 static void ixgbe_io_resume(struct pci_dev *pdev)
7830 {
7831 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7832 struct net_device *netdev = adapter->netdev;
7833
7834 if (netif_running(netdev)) {
7835 if (ixgbe_up(adapter)) {
7836 e_info(probe, "ixgbe_up failed after reset\n");
7837 return;
7838 }
7839 }
7840
7841 netif_device_attach(netdev);
7842 }
7843
7844 static struct pci_error_handlers ixgbe_err_handler = {
7845 .error_detected = ixgbe_io_error_detected,
7846 .slot_reset = ixgbe_io_slot_reset,
7847 .resume = ixgbe_io_resume,
7848 };
7849
7850 static struct pci_driver ixgbe_driver = {
7851 .name = ixgbe_driver_name,
7852 .id_table = ixgbe_pci_tbl,
7853 .probe = ixgbe_probe,
7854 .remove = __devexit_p(ixgbe_remove),
7855 #ifdef CONFIG_PM
7856 .suspend = ixgbe_suspend,
7857 .resume = ixgbe_resume,
7858 #endif
7859 .shutdown = ixgbe_shutdown,
7860 .err_handler = &ixgbe_err_handler
7861 };
7862
7863 /**
7864 * ixgbe_init_module - Driver Registration Routine
7865 *
7866 * ixgbe_init_module is the first routine called when the driver is
7867 * loaded. All it does is register with the PCI subsystem.
7868 **/
7869 static int __init ixgbe_init_module(void)
7870 {
7871 int ret;
7872 pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7873 pr_info("%s\n", ixgbe_copyright);
7874
7875 #ifdef CONFIG_IXGBE_DCA
7876 dca_register_notify(&dca_notifier);
7877 #endif
7878
7879 ret = pci_register_driver(&ixgbe_driver);
7880 return ret;
7881 }
7882
7883 module_init(ixgbe_init_module);
7884
7885 /**
7886 * ixgbe_exit_module - Driver Exit Cleanup Routine
7887 *
7888 * ixgbe_exit_module is called just before the driver is removed
7889 * from memory.
7890 **/
7891 static void __exit ixgbe_exit_module(void)
7892 {
7893 #ifdef CONFIG_IXGBE_DCA
7894 dca_unregister_notify(&dca_notifier);
7895 #endif
7896 pci_unregister_driver(&ixgbe_driver);
7897 rcu_barrier(); /* Wait for completion of call_rcu()'s */
7898 }
7899
7900 #ifdef CONFIG_IXGBE_DCA
7901 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7902 void *p)
7903 {
7904 int ret_val;
7905
7906 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7907 __ixgbe_notify_dca);
7908
7909 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7910 }
7911
7912 #endif /* CONFIG_IXGBE_DCA */
7913
7914 module_exit(ixgbe_exit_module);
7915
7916 /* ixgbe_main.c */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree