drivers/scsi/qla4xxx/ql4_def.h

   1 /*
   2  * QLogic iSCSI HBA Driver
   3  * Copyright (c)  2003-2006 QLogic Corporation
   4  *
   5  * See LICENSE.qla4xxx for copyright and licensing details.
   6  */
   7
   8 #ifndef __QL4_DEF_H
   9 #define __QL4_DEF_H
  10
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/types.h>
  14 #include <linux/module.h>
  15 #include <linux/list.h>
  16 #include <linux/pci.h>
  17 #include <linux/dma-mapping.h>
  18 #include <linux/sched.h>
  19 #include <linux/slab.h>
  20 #include <linux/dmapool.h>
  21 #include <linux/mempool.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/workqueue.h>
  24 #include <linux/delay.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/mutex.h>
  27
  28 #include <net/tcp.h>
  29 #include <scsi/scsi.h>
  30 #include <scsi/scsi_host.h>
  31 #include <scsi/scsi_device.h>
  32 #include <scsi/scsi_cmnd.h>
  33 #include <scsi/scsi_transport.h>
  34 #include <scsi/scsi_transport_iscsi.h>
  35
  36
  37 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4010
  38 #define PCI_DEVICE_ID_QLOGIC_ISP4010    0x4010
  39 #endif
  40
  41 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4022
  42 #define PCI_DEVICE_ID_QLOGIC_ISP4022    0x4022
  43 #endif
  44
  45 #ifndef PCI_DEVICE_ID_QLOGIC_ISP4032
  46 #define PCI_DEVICE_ID_QLOGIC_ISP4032    0x4032
  47 #endif
  48
  49 #define QLA_SUCCESS                     0
  50 #define QLA_ERROR                       1
  51
  52 /*
  53  * Data bit definitions
  54  */
  55 #define BIT_0   0x1
  56 #define BIT_1   0x2
  57 #define BIT_2   0x4
  58 #define BIT_3   0x8
  59 #define BIT_4   0x10
  60 #define BIT_5   0x20
  61 #define BIT_6   0x40
  62 #define BIT_7   0x80
  63 #define BIT_8   0x100
  64 #define BIT_9   0x200
  65 #define BIT_10  0x400
  66 #define BIT_11  0x800
  67 #define BIT_12  0x1000
  68 #define BIT_13  0x2000
  69 #define BIT_14  0x4000
  70 #define BIT_15  0x8000
  71 #define BIT_16  0x10000
  72 #define BIT_17  0x20000
  73 #define BIT_18  0x40000
  74 #define BIT_19  0x80000
  75 #define BIT_20  0x100000
  76 #define BIT_21  0x200000
  77 #define BIT_22  0x400000
  78 #define BIT_23  0x800000
  79 #define BIT_24  0x1000000
  80 #define BIT_25  0x2000000
  81 #define BIT_26  0x4000000
  82 #define BIT_27  0x8000000
  83 #define BIT_28  0x10000000
  84 #define BIT_29  0x20000000
  85 #define BIT_30  0x40000000
  86 #define BIT_31  0x80000000
  87
  88 /*
  89  * Host adapter default definitions
  90  ***********************************/
  91 #define MAX_HBAS                16
  92 #define MAX_BUSES               1
  93 #define MAX_TARGETS             (MAX_PRST_DEV_DB_ENTRIES +  MAX_DEV_DB_ENTRIES)
  94 #define MAX_LUNS                0xffff
  95 #define MAX_AEN_ENTRIES         256 /* should be > EXT_DEF_MAX_AEN_QUEUE */
  96 #define MAX_DDB_ENTRIES         (MAX_PRST_DEV_DB_ENTRIES + MAX_DEV_DB_ENTRIES)
  97 #define MAX_PDU_ENTRIES         32
  98 #define INVALID_ENTRY           0xFFFF
  99 #define MAX_CMDS_TO_RISC        1024
 100 #define MAX_SRBS                MAX_CMDS_TO_RISC
 101 #define MBOX_AEN_REG_COUNT      5
 102 #define MAX_INIT_RETRIES        5
 103 #define IOCB_HIWAT_CUSHION      16
 104
 105 /*
 106  * Buffer sizes
 107  */
 108 #define REQUEST_QUEUE_DEPTH             MAX_CMDS_TO_RISC
 109 #define RESPONSE_QUEUE_DEPTH            64
 110 #define QUEUE_SIZE                      64
 111 #define DMA_BUFFER_SIZE                 512
 112
 113 /*
 114  * Misc
 115  */
 116 #define MAC_ADDR_LEN                    6       /* in bytes */
 117 #define IP_ADDR_LEN                     4       /* in bytes */
 118 #define DRIVER_NAME                     "qla4xxx"
 119
 120 #define MAX_LINKED_CMDS_PER_LUN         3
 121 #define MAX_REQS_SERVICED_PER_INTR      16
 122
 123 #define ISCSI_IPADDR_SIZE               4       /* IP address size */
 124 #define ISCSI_ALIAS_SIZE                32      /* ISCSI Alais name size */
 125 #define ISCSI_NAME_SIZE                 255     /* ISCSI Name size -
 126                                                  * usually a string */
 127
 128 #define LSDW(x) ((u32)((u64)(x)))
 129 #define MSDW(x) ((u32)((((u64)(x)) >> 16) >> 16))
 130
 131 /*
 132  * Retry & Timeout Values
 133  */
 134 #define MBOX_TOV                        60
 135 #define SOFT_RESET_TOV                  30
 136 #define RESET_INTR_TOV                  3
 137 #define SEMAPHORE_TOV                   10
 138 #define ADAPTER_INIT_TOV                120
 139 #define ADAPTER_RESET_TOV               180
 140 #define EXTEND_CMD_TOV                  60
 141 #define WAIT_CMD_TOV                    30
 142 #define EH_WAIT_CMD_TOV                 120
 143 #define FIRMWARE_UP_TOV                 60
 144 #define RESET_FIRMWARE_TOV              30
 145 #define LOGOUT_TOV                      10
 146 #define IOCB_TOV_MARGIN                 10
 147 #define RELOGIN_TOV                     18
 148 #define ISNS_DEREG_TOV                  5
 149
 150 #define MAX_RESET_HA_RETRIES            2
 151
 152 /*
 153  * SCSI Request Block structure  (srb)  that is placed
 154  * on cmd->SCp location of every I/O     [We have 22 bytes available]
 155  */
 156 struct srb {
 157         struct list_head list;  /* (8)   */
 158         struct scsi_qla_host *ha;       /* HA the SP is queued on */
 159         struct ddb_entry        *ddb;
 160         uint16_t flags;         /* (1) Status flags. */
 161
 162 #define SRB_DMA_VALID           BIT_3   /* DMA Buffer mapped. */
 163 #define SRB_GOT_SENSE           BIT_4   /* sense data recieved. */
 164         uint8_t state;          /* (1) Status flags. */
 165
 166 #define SRB_NO_QUEUE_STATE       0      /* Request is in between states */
 167 #define SRB_FREE_STATE           1
 168 #define SRB_ACTIVE_STATE         3
 169 #define SRB_ACTIVE_TIMEOUT_STATE 4
 170 #define SRB_SUSPENDED_STATE      7      /* Request in suspended state */
 171
 172         struct scsi_cmnd *cmd;  /* (4) SCSI command block */
 173         dma_addr_t dma_handle;  /* (4) for unmap of single transfers */
 174         atomic_t ref_count;     /* reference count for this srb */
 175         uint32_t fw_ddb_index;
 176         uint8_t err_id;         /* error id */
 177 #define SRB_ERR_PORT       1    /* Request failed because "port down" */
 178 #define SRB_ERR_LOOP       2    /* Request failed because "loop down" */
 179 #define SRB_ERR_DEVICE     3    /* Request failed because "device error" */
 180 #define SRB_ERR_OTHER      4
 181
 182         uint16_t reserved;
 183         uint16_t iocb_tov;
 184         uint16_t iocb_cnt;      /* Number of used iocbs */
 185         uint16_t cc_stat;
 186         u_long r_start;         /* Time we recieve a cmd from OS */
 187         u_long u_start;         /* Time when we handed the cmd to F/W */
 188 };
 189
 190         /*
 191          * Device Database (DDB) structure
 192          */
 193 struct ddb_entry {
 194         struct list_head list;  /* ddb list */
 195         struct scsi_qla_host *ha;
 196         struct iscsi_cls_session *sess;
 197         struct iscsi_cls_conn *conn;
 198
 199         atomic_t state;         /* DDB State */
 200
 201         unsigned long flags;    /* DDB Flags */
 202
 203         unsigned long dev_scan_wait_to_start_relogin;
 204         unsigned long dev_scan_wait_to_complete_relogin;
 205
 206         uint16_t os_target_id;  /* Target ID */
 207         uint16_t fw_ddb_index;  /* DDB firmware index */
 208         uint8_t reserved[2];
 209         uint32_t fw_ddb_device_state; /* F/W Device State  -- see ql4_fw.h */
 210
 211         uint32_t CmdSn;
 212         uint16_t target_session_id;
 213         uint16_t connection_id;
 214         uint16_t exe_throttle;  /* Max mumber of cmds outstanding
 215                                  * simultaneously */
 216         uint16_t task_mgmt_timeout; /* Min time for task mgmt cmds to
 217                                      * complete */
 218         uint16_t default_relogin_timeout; /*  Max time to wait for
 219                                            *  relogin to complete */
 220         uint16_t tcp_source_port_num;
 221         uint32_t default_time2wait; /* Default Min time between
 222                                      * relogins (+aens) */
 223
 224         atomic_t port_down_timer; /* Device connection timer */
 225         atomic_t retry_relogin_timer; /* Min Time between relogins
 226                                        * (4000 only) */
 227         atomic_t relogin_timer; /* Max Time to wait for relogin to complete */
 228         atomic_t relogin_retry_count; /* Num of times relogin has been
 229                                        * retried */
 230
 231         uint16_t port;
 232         uint32_t tpgt;
 233         uint8_t ip_addr[ISCSI_IPADDR_SIZE];
 234         uint8_t iscsi_name[ISCSI_NAME_SIZE];    /* 72 x48 */
 235         uint8_t iscsi_alias[0x20];
 236 };
 237
 238 /*
 239  * DDB states.
 240  */
 241 #define DDB_STATE_DEAD          0       /* We can no longer talk to
 242                                          * this device */
 243 #define DDB_STATE_ONLINE        1       /* Device ready to accept
 244                                          * commands */
 245 #define DDB_STATE_MISSING       2       /* Device logged off, trying
 246                                          * to re-login */
 247
 248 /*
 249  * DDB flags.
 250  */
 251 #define DF_RELOGIN              0       /* Relogin to device */
 252 #define DF_NO_RELOGIN           1       /* Do not relogin if IOCTL
 253                                          * logged it out */
 254 #define DF_ISNS_DISCOVERED      2       /* Device was discovered via iSNS */
 255 #define DF_FO_MASKED            3
 256
 257 /*
 258  * Asynchronous Event Queue structure
 259  */
 260 struct aen {
 261         uint32_t mbox_sts[MBOX_AEN_REG_COUNT];
 262 };
 263
 264
 265 #include "ql4_fw.h"
 266 #include "ql4_nvram.h"
 267
 268 /*
 269  * Linux Host Adapter structure
 270  */
 271 struct scsi_qla_host {
 272         /* Linux adapter configuration data */
 273         struct Scsi_Host *host; /* pointer to host data */
 274         uint32_t tot_ddbs;
 275         unsigned long flags;
 276
 277 #define AF_ONLINE                     0 /* 0x00000001 */
 278 #define AF_INIT_DONE                  1 /* 0x00000002 */
 279 #define AF_MBOX_COMMAND               2 /* 0x00000004 */
 280 #define AF_MBOX_COMMAND_DONE          3 /* 0x00000008 */
 281 #define AF_INTERRUPTS_ON              6 /* 0x00000040 Not Used */
 282 #define AF_GET_CRASH_RECORD           7 /* 0x00000080 */
 283 #define AF_LINK_UP                    8 /* 0x00000100 */
 284 #define AF_IRQ_ATTACHED              10 /* 0x00000400 */
 285 #define AF_ISNS_CMD_IN_PROCESS       12 /* 0x00001000 */
 286 #define AF_ISNS_CMD_DONE             13 /* 0x00002000 */
 287
 288         unsigned long dpc_flags;
 289
 290 #define DPC_RESET_HA                  1 /* 0x00000002 */
 291 #define DPC_RETRY_RESET_HA            2 /* 0x00000004 */
 292 #define DPC_RELOGIN_DEVICE            3 /* 0x00000008 */
 293 #define DPC_RESET_HA_DESTROY_DDB_LIST 4 /* 0x00000010 */
 294 #define DPC_RESET_HA_INTR             5 /* 0x00000020 */
 295 #define DPC_ISNS_RESTART              7 /* 0x00000080 */
 296 #define DPC_AEN                       9 /* 0x00000200 */
 297 #define DPC_GET_DHCP_IP_ADDR         15 /* 0x00008000 */
 298
 299         uint16_t        iocb_cnt;
 300         uint16_t        iocb_hiwat;
 301
 302         /* SRB cache. */
 303 #define SRB_MIN_REQ     128
 304         mempool_t *srb_mempool;
 305
 306         /* pci information */
 307         struct pci_dev *pdev;
 308
 309         struct isp_reg __iomem *reg; /* Base I/O address */
 310         unsigned long pio_address;
 311         unsigned long pio_length;
 312 #define MIN_IOBASE_LEN          0x100
 313
 314         uint16_t req_q_count;
 315         uint8_t marker_needed;
 316         uint8_t rsvd1;
 317
 318         unsigned long host_no;
 319
 320         /* NVRAM registers */
 321         struct eeprom_data *nvram;
 322         spinlock_t hardware_lock ____cacheline_aligned;
 323         uint32_t   eeprom_cmd_data;
 324
 325         /* Counters for general statistics */
 326         uint64_t isr_count;
 327         uint64_t adapter_error_count;
 328         uint64_t device_error_count;
 329         uint64_t total_io_count;
 330         uint64_t total_mbytes_xferred;
 331         uint64_t link_failure_count;
 332         uint64_t invalid_crc_count;
 333         uint32_t bytes_xfered;
 334         uint32_t spurious_int_count;
 335         uint32_t aborted_io_count;
 336         uint32_t io_timeout_count;
 337         uint32_t mailbox_timeout_count;
 338         uint32_t seconds_since_last_intr;
 339         uint32_t seconds_since_last_heartbeat;
 340         uint32_t mac_index;
 341
 342         /* Info Needed for Management App */
 343         /* --- From GetFwVersion --- */
 344         uint32_t firmware_version[2];
 345         uint32_t patch_number;
 346         uint32_t build_number;
 347
 348         /* --- From Init_FW --- */
 349         /* init_cb_t *init_cb; */
 350         uint16_t firmware_options;
 351         uint16_t tcp_options;
 352         uint8_t ip_address[IP_ADDR_LEN];
 353         uint8_t subnet_mask[IP_ADDR_LEN];
 354         uint8_t gateway[IP_ADDR_LEN];
 355         uint8_t alias[32];
 356         uint8_t name_string[256];
 357         uint8_t heartbeat_interval;
 358         uint8_t rsvd;
 359
 360         /* --- From FlashSysInfo --- */
 361         uint8_t my_mac[MAC_ADDR_LEN];
 362         uint8_t serial_number[16];
 363
 364         /* --- From GetFwState --- */
 365         uint32_t firmware_state;
 366         uint32_t board_id;
 367         uint32_t addl_fw_state;
 368
 369         /* Linux kernel thread */
 370         struct workqueue_struct *dpc_thread;
 371         struct work_struct dpc_work;
 372
 373         /* Linux timer thread */
 374         struct timer_list timer;
 375         uint32_t timer_active;
 376
 377         /* Recovery Timers */
 378         uint32_t port_down_retry_count;
 379         uint32_t discovery_wait;
 380         atomic_t check_relogin_timeouts;
 381         uint32_t retry_reset_ha_cnt;
 382         uint32_t isp_reset_timer;       /* reset test timer */
 383         uint32_t nic_reset_timer;       /* simulated nic reset test timer */
 384         int eh_start;
 385         struct list_head free_srb_q;
 386         uint16_t free_srb_q_count;
 387         uint16_t num_srbs_allocated;
 388
 389         /* DMA Memory Block */
 390         void *queues;
 391         dma_addr_t queues_dma;
 392         unsigned long queues_len;
 393
 394 #define MEM_ALIGN_VALUE \
 395             ((max(REQUEST_QUEUE_DEPTH, RESPONSE_QUEUE_DEPTH)) * \
 396              sizeof(struct queue_entry))
 397         /* request and response queue variables */
 398         dma_addr_t request_dma;
 399         struct queue_entry *request_ring;
 400         struct queue_entry *request_ptr;
 401         dma_addr_t response_dma;
 402         struct queue_entry *response_ring;
 403         struct queue_entry *response_ptr;
 404         dma_addr_t shadow_regs_dma;
 405         struct shadow_regs *shadow_regs;
 406         uint16_t request_in;    /* Current indexes. */
 407         uint16_t request_out;
 408         uint16_t response_in;
 409         uint16_t response_out;
 410
 411         /* aen queue variables */
 412         uint16_t aen_q_count;   /* Number of available aen_q entries */
 413         uint16_t aen_in;        /* Current indexes */
 414         uint16_t aen_out;
 415         struct aen aen_q[MAX_AEN_ENTRIES];
 416
 417         /* This mutex protects several threads to do mailbox commands
 418          * concurrently.
 419          */
 420         struct mutex  mbox_sem;
 421
 422         /* temporary mailbox status registers */
 423         volatile uint8_t mbox_status_count;
 424         volatile uint32_t mbox_status[MBOX_REG_COUNT];
 425
 426         /* local device database list (contains internal ddb entries) */
 427         struct list_head ddb_list;
 428
 429         /* Map ddb_list entry by FW ddb index */
 430         struct ddb_entry *fw_ddb_index_map[MAX_DDB_ENTRIES];
 431
 432 };
 433
 434 static inline int is_qla4010(struct scsi_qla_host *ha)
 435 {
 436         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4010;
 437 }
 438
 439 static inline int is_qla4022(struct scsi_qla_host *ha)
 440 {
 441         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4022;
 442 }
 443
 444 static inline int is_qla4032(struct scsi_qla_host *ha)
 445 {
 446         return ha->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP4032;
 447 }
 448
 449 static inline int adapter_up(struct scsi_qla_host *ha)
 450 {
 451         return (test_bit(AF_ONLINE, &ha->flags) != 0) &&
 452                 (test_bit(AF_LINK_UP, &ha->flags) != 0);
 453 }
 454
 455 static inline struct scsi_qla_host* to_qla_host(struct Scsi_Host *shost)
 456 {
 457         return (struct scsi_qla_host *)shost->hostdata;
 458 }
 459
 460 static inline void __iomem* isp_semaphore(struct scsi_qla_host *ha)
 461 {
 462         return (is_qla4010(ha) ?
 463                 &ha->reg->u1.isp4010.nvram :
 464                 &ha->reg->u1.isp4022.semaphore);
 465 }
 466
 467 static inline void __iomem* isp_nvram(struct scsi_qla_host *ha)
 468 {
 469         return (is_qla4010(ha) ?
 470                 &ha->reg->u1.isp4010.nvram :
 471                 &ha->reg->u1.isp4022.nvram);
 472 }
 473
 474 static inline void __iomem* isp_ext_hw_conf(struct scsi_qla_host *ha)
 475 {
 476         return (is_qla4010(ha) ?
 477                 &ha->reg->u2.isp4010.ext_hw_conf :
 478                 &ha->reg->u2.isp4022.p0.ext_hw_conf);
 479 }
 480
 481 static inline void __iomem* isp_port_status(struct scsi_qla_host *ha)
 482 {
 483         return (is_qla4010(ha) ?
 484                 &ha->reg->u2.isp4010.port_status :
 485                 &ha->reg->u2.isp4022.p0.port_status);
 486 }
 487
 488 static inline void __iomem* isp_port_ctrl(struct scsi_qla_host *ha)
 489 {
 490         return (is_qla4010(ha) ?
 491                 &ha->reg->u2.isp4010.port_ctrl :
 492                 &ha->reg->u2.isp4022.p0.port_ctrl);
 493 }
 494
 495 static inline void __iomem* isp_port_error_status(struct scsi_qla_host *ha)
 496 {
 497         return (is_qla4010(ha) ?
 498                 &ha->reg->u2.isp4010.port_err_status :
 499                 &ha->reg->u2.isp4022.p0.port_err_status);
 500 }
 501
 502 static inline void __iomem * isp_gp_out(struct scsi_qla_host *ha)
 503 {
 504         return (is_qla4010(ha) ?
 505                 &ha->reg->u2.isp4010.gp_out :
 506                 &ha->reg->u2.isp4022.p0.gp_out);
 507 }
 508
 509 static inline int eeprom_ext_hw_conf_offset(struct scsi_qla_host *ha)
 510 {
 511         return (is_qla4010(ha) ?
 512                 offsetof(struct eeprom_data, isp4010.ext_hw_conf) / 2 :
 513                 offsetof(struct eeprom_data, isp4022.ext_hw_conf) / 2);
 514 }
 515
 516 int ql4xxx_sem_spinlock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 517 void ql4xxx_sem_unlock(struct scsi_qla_host * ha, u32 sem_mask);
 518 int ql4xxx_sem_lock(struct scsi_qla_host * ha, u32 sem_mask, u32 sem_bits);
 519
 520 static inline int ql4xxx_lock_flash(struct scsi_qla_host *a)
 521 {
 522         if (is_qla4010(a))
 523                 return ql4xxx_sem_spinlock(a, QL4010_FLASH_SEM_MASK,
 524                                            QL4010_FLASH_SEM_BITS);
 525         else
 526                 return ql4xxx_sem_spinlock(a, QL4022_FLASH_SEM_MASK,
 527                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 528                                             (a->mac_index)) << 13);
 529 }
 530
 531 static inline void ql4xxx_unlock_flash(struct scsi_qla_host *a)
 532 {
 533         if (is_qla4010(a))
 534                 ql4xxx_sem_unlock(a, QL4010_FLASH_SEM_MASK);
 535         else
 536                 ql4xxx_sem_unlock(a, QL4022_FLASH_SEM_MASK);
 537 }
 538
 539 static inline int ql4xxx_lock_nvram(struct scsi_qla_host *a)
 540 {
 541         if (is_qla4010(a))
 542                 return ql4xxx_sem_spinlock(a, QL4010_NVRAM_SEM_MASK,
 543                                            QL4010_NVRAM_SEM_BITS);
 544         else
 545                 return ql4xxx_sem_spinlock(a, QL4022_NVRAM_SEM_MASK,
 546                                            (QL4022_RESOURCE_BITS_BASE_CODE |
 547                                             (a->mac_index)) << 10);
 548 }
 549
 550 static inline void ql4xxx_unlock_nvram(struct scsi_qla_host *a)
 551 {
 552         if (is_qla4010(a))
 553                 ql4xxx_sem_unlock(a, QL4010_NVRAM_SEM_MASK);
 554         else
 555                 ql4xxx_sem_unlock(a, QL4022_NVRAM_SEM_MASK);
 556 }
 557
 558 static inline int ql4xxx_lock_drvr(struct scsi_qla_host *a)
 559 {
 560         if (is_qla4010(a))
 561                 return ql4xxx_sem_lock(a, QL4010_DRVR_SEM_MASK,
 562                                        QL4010_DRVR_SEM_BITS);
 563         else
 564                 return ql4xxx_sem_lock(a, QL4022_DRVR_SEM_MASK,
 565                                        (QL4022_RESOURCE_BITS_BASE_CODE |
 566                                         (a->mac_index)) << 1);
 567 }
 568
 569 static inline void ql4xxx_unlock_drvr(struct scsi_qla_host *a)
 570 {
 571         if (is_qla4010(a))
 572                 ql4xxx_sem_unlock(a, QL4010_DRVR_SEM_MASK);
 573         else
 574                 ql4xxx_sem_unlock(a, QL4022_DRVR_SEM_MASK);
 575 }
 576
 577 /*---------------------------------------------------------------------------*/
 578
 579 /* Defines for qla4xxx_initialize_adapter() and qla4xxx_recover_adapter() */
 580 #define PRESERVE_DDB_LIST       0
 581 #define REBUILD_DDB_LIST        1
 582
 583 /* Defines for process_aen() */
 584 #define PROCESS_ALL_AENS         0
 585 #define FLUSH_DDB_CHANGED_AENS   1
 586 #define RELOGIN_DDB_CHANGED_AENS 2
 587
 588 #include "ql4_version.h"
 589 #include "ql4_glbl.h"
 590 #include "ql4_dbg.h"
 591 #include "ql4_inline.h"
 592
 593
 594 #endif  /*_QLA4XXX_H */