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[PATCH] sky2: turn off PHY IRQ on shutdown
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / sky2.c
blob4661b1e5a8c66e548ef7f34248f23f3da1e5efd6
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
35 #include <linux/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43
44 #include <asm/irq.h>
45
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
48 #endif
49
50 #include "sky2.h"
51
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.5"
54 #define PFX DRV_NAME " "
55
56 /*
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
59 * similar to Tigon3. A transmit can require several elements;
60 * a receive requires one (or two if using 64 bit dma).
61 */
62
63 #define RX_LE_SIZE 512
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define ETH_JUMBO_MTU 9000
78 #define TX_WATCHDOG (5 * HZ)
79 #define NAPI_WEIGHT 64
80 #define PHY_RETRIES 1000
81
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
83
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
88
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
92
93 static int copybreak __read_mostly = 256;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
96
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
100
101 static int idle_timeout = 100;
102 module_param(idle_timeout, int, 0);
103 MODULE_PARM_DESC(idle_timeout, "Idle timeout workaround for lost interrupts (ms)");
104
105 static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) },
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) },
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) },
132 { 0 }
133 };
134
135 MODULE_DEVICE_TABLE(pci, sky2_id_table);
136
137 /* Avoid conditionals by using array */
138 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
139 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
140 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
141
142 /* This driver supports yukon2 chipset only */
143 static const char *yukon2_name[] = {
144 "XL", /* 0xb3 */
145 "EC Ultra", /* 0xb4 */
146 "UNKNOWN", /* 0xb5 */
147 "EC", /* 0xb6 */
148 "FE", /* 0xb7 */
149 };
150
151 /* Access to external PHY */
152 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
153 {
154 int i;
155
156 gma_write16(hw, port, GM_SMI_DATA, val);
157 gma_write16(hw, port, GM_SMI_CTRL,
158 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
159
160 for (i = 0; i < PHY_RETRIES; i++) {
161 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
162 return 0;
163 udelay(1);
164 }
165
166 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
167 return -ETIMEDOUT;
168 }
169
170 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
171 {
172 int i;
173
174 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
175 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
176
177 for (i = 0; i < PHY_RETRIES; i++) {
178 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
179 *val = gma_read16(hw, port, GM_SMI_DATA);
180 return 0;
181 }
182
183 udelay(1);
184 }
185
186 return -ETIMEDOUT;
187 }
188
189 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
190 {
191 u16 v;
192
193 if (__gm_phy_read(hw, port, reg, &v) != 0)
194 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
195 return v;
196 }
197
198 static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
199 {
200 u16 power_control;
201 u32 reg1;
202 int vaux;
203
204 pr_debug("sky2_set_power_state %d\n", state);
205 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
206
207 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_PMC);
208 vaux = (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
209 (power_control & PCI_PM_CAP_PME_D3cold);
210
211 power_control = sky2_pci_read16(hw, hw->pm_cap + PCI_PM_CTRL);
212
213 power_control |= PCI_PM_CTRL_PME_STATUS;
214 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
215
216 switch (state) {
217 case PCI_D0:
218 /* switch power to VCC (WA for VAUX problem) */
219 sky2_write8(hw, B0_POWER_CTRL,
220 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
221
222 /* disable Core Clock Division, */
223 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
224
225 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
226 /* enable bits are inverted */
227 sky2_write8(hw, B2_Y2_CLK_GATE,
228 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
229 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
230 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
231 else
232 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
233
234 /* Turn off phy power saving */
235 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
236 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
237
238 /* looks like this XL is back asswards .. */
239 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
240 reg1 |= PCI_Y2_PHY1_COMA;
241 if (hw->ports > 1)
242 reg1 |= PCI_Y2_PHY2_COMA;
243 }
244 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
245 udelay(100);
246
247 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
248 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
249 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
250 reg1 &= P_ASPM_CONTROL_MSK;
251 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
252 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
253 }
254
255 break;
256
257 case PCI_D3hot:
258 case PCI_D3cold:
259 /* Turn on phy power saving */
260 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
261 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
262 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
263 else
264 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
265 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
266 udelay(100);
267
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
270 else
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
276
277 /* switch power to VAUX */
278 if (vaux && state != PCI_D3cold)
279 sky2_write8(hw, B0_POWER_CTRL,
280 (PC_VAUX_ENA | PC_VCC_ENA |
281 PC_VAUX_ON | PC_VCC_OFF));
282 break;
283 default:
284 printk(KERN_ERR PFX "Unknown power state %d\n", state);
285 }
286
287 sky2_pci_write16(hw, hw->pm_cap + PCI_PM_CTRL, power_control);
288 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
289 }
290
291 static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
292 {
293 u16 reg;
294
295 /* disable all GMAC IRQ's */
296 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
297 /* disable PHY IRQs */
298 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
299
300 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
301 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
302 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
303 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
304
305 reg = gma_read16(hw, port, GM_RX_CTRL);
306 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
307 gma_write16(hw, port, GM_RX_CTRL, reg);
308 }
309
310 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
311 {
312 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
313 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
314
315 if (sky2->autoneg == AUTONEG_ENABLE &&
316 !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
317 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
318
319 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
320 PHY_M_EC_MAC_S_MSK);
321 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
322
323 if (hw->chip_id == CHIP_ID_YUKON_EC)
324 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
325 else
326 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
327
328 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
329 }
330
331 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
332 if (hw->copper) {
333 if (hw->chip_id == CHIP_ID_YUKON_FE) {
334 /* enable automatic crossover */
335 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
336 } else {
337 /* disable energy detect */
338 ctrl &= ~PHY_M_PC_EN_DET_MSK;
339
340 /* enable automatic crossover */
341 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
342
343 if (sky2->autoneg == AUTONEG_ENABLE &&
344 (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) {
345 ctrl &= ~PHY_M_PC_DSC_MSK;
346 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
347 }
348 }
349 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
350 } else {
351 /* workaround for deviation #4.88 (CRC errors) */
352 /* disable Automatic Crossover */
353
354 ctrl &= ~PHY_M_PC_MDIX_MSK;
355 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
356
357 if (hw->chip_id == CHIP_ID_YUKON_XL) {
358 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
359 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
360 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
361 ctrl &= ~PHY_M_MAC_MD_MSK;
362 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
363 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
364
365 /* select page 1 to access Fiber registers */
366 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
367 }
368 }
369
370 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
371 if (sky2->autoneg == AUTONEG_DISABLE)
372 ctrl &= ~PHY_CT_ANE;
373 else
374 ctrl |= PHY_CT_ANE;
375
376 ctrl |= PHY_CT_RESET;
377 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
378
379 ctrl = 0;
380 ct1000 = 0;
381 adv = PHY_AN_CSMA;
382
383 if (sky2->autoneg == AUTONEG_ENABLE) {
384 if (hw->copper) {
385 if (sky2->advertising & ADVERTISED_1000baseT_Full)
386 ct1000 |= PHY_M_1000C_AFD;
387 if (sky2->advertising & ADVERTISED_1000baseT_Half)
388 ct1000 |= PHY_M_1000C_AHD;
389 if (sky2->advertising & ADVERTISED_100baseT_Full)
390 adv |= PHY_M_AN_100_FD;
391 if (sky2->advertising & ADVERTISED_100baseT_Half)
392 adv |= PHY_M_AN_100_HD;
393 if (sky2->advertising & ADVERTISED_10baseT_Full)
394 adv |= PHY_M_AN_10_FD;
395 if (sky2->advertising & ADVERTISED_10baseT_Half)
396 adv |= PHY_M_AN_10_HD;
397 } else /* special defines for FIBER (88E1011S only) */
398 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
399
400 /* Set Flow-control capabilities */
401 if (sky2->tx_pause && sky2->rx_pause)
402 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
403 else if (sky2->rx_pause && !sky2->tx_pause)
404 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
405 else if (!sky2->rx_pause && sky2->tx_pause)
406 adv |= PHY_AN_PAUSE_ASYM; /* local */
407
408 /* Restart Auto-negotiation */
409 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
410 } else {
411 /* forced speed/duplex settings */
412 ct1000 = PHY_M_1000C_MSE;
413
414 if (sky2->duplex == DUPLEX_FULL)
415 ctrl |= PHY_CT_DUP_MD;
416
417 switch (sky2->speed) {
418 case SPEED_1000:
419 ctrl |= PHY_CT_SP1000;
420 break;
421 case SPEED_100:
422 ctrl |= PHY_CT_SP100;
423 break;
424 }
425
426 ctrl |= PHY_CT_RESET;
427 }
428
429 if (hw->chip_id != CHIP_ID_YUKON_FE)
430 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
431
432 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
433 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
434
435 /* Setup Phy LED's */
436 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
437 ledover = 0;
438
439 switch (hw->chip_id) {
440 case CHIP_ID_YUKON_FE:
441 /* on 88E3082 these bits are at 11..9 (shifted left) */
442 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
443
444 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
445
446 /* delete ACT LED control bits */
447 ctrl &= ~PHY_M_FELP_LED1_MSK;
448 /* change ACT LED control to blink mode */
449 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
450 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
451 break;
452
453 case CHIP_ID_YUKON_XL:
454 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
455
456 /* select page 3 to access LED control register */
457 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
458
459 /* set LED Function Control register */
460 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
461 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
462 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
463 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
464 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
465
466 /* set Polarity Control register */
467 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
468 (PHY_M_POLC_LS1_P_MIX(4) |
469 PHY_M_POLC_IS0_P_MIX(4) |
470 PHY_M_POLC_LOS_CTRL(2) |
471 PHY_M_POLC_INIT_CTRL(2) |
472 PHY_M_POLC_STA1_CTRL(2) |
473 PHY_M_POLC_STA0_CTRL(2)));
474
475 /* restore page register */
476 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
477 break;
478 case CHIP_ID_YUKON_EC_U:
479 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
480
481 /* select page 3 to access LED control register */
482 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
483
484 /* set LED Function Control register */
485 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
486 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
487 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
488 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
489 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
490
491 /* set Blink Rate in LED Timer Control Register */
492 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
493 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
494 /* restore page register */
495 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
496 break;
497
498 default:
499 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
500 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
501 /* turn off the Rx LED (LED_RX) */
502 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
503 }
504
505 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == CHIP_REV_YU_EC_A1) {
506 /* apply fixes in PHY AFE */
507 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
509
510 /* increase differential signal amplitude in 10BASE-T */
511 gm_phy_write(hw, port, 0x18, 0xaa99);
512 gm_phy_write(hw, port, 0x17, 0x2011);
513
514 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
515 gm_phy_write(hw, port, 0x18, 0xa204);
516 gm_phy_write(hw, port, 0x17, 0x2002);
517
518 /* set page register to 0 */
519 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
520 } else {
521 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
522
523 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
524 /* turn on 100 Mbps LED (LED_LINK100) */
525 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
526 }
527
528 if (ledover)
529 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
530
531 }
532 /* Enable phy interrupt on auto-negotiation complete (or link up) */
533 if (sky2->autoneg == AUTONEG_ENABLE)
534 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
535 else
536 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
537 }
538
539 /* Force a renegotiation */
540 static void sky2_phy_reinit(struct sky2_port *sky2)
541 {
542 spin_lock_bh(&sky2->phy_lock);
543 sky2_phy_init(sky2->hw, sky2->port);
544 spin_unlock_bh(&sky2->phy_lock);
545 }
546
547 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
548 {
549 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
550 u16 reg;
551 int i;
552 const u8 *addr = hw->dev[port]->dev_addr;
553
554 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
555 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
556
557 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
558
559 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
560 /* WA DEV_472 -- looks like crossed wires on port 2 */
561 /* clear GMAC 1 Control reset */
562 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
563 do {
564 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
565 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
566 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
567 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
568 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
569 }
570
571 if (sky2->autoneg == AUTONEG_DISABLE) {
572 reg = gma_read16(hw, port, GM_GP_CTRL);
573 reg |= GM_GPCR_AU_ALL_DIS;
574 gma_write16(hw, port, GM_GP_CTRL, reg);
575 gma_read16(hw, port, GM_GP_CTRL);
576
577 switch (sky2->speed) {
578 case SPEED_1000:
579 reg &= ~GM_GPCR_SPEED_100;
580 reg |= GM_GPCR_SPEED_1000;
581 break;
582 case SPEED_100:
583 reg &= ~GM_GPCR_SPEED_1000;
584 reg |= GM_GPCR_SPEED_100;
585 break;
586 case SPEED_10:
587 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
588 break;
589 }
590
591 if (sky2->duplex == DUPLEX_FULL)
592 reg |= GM_GPCR_DUP_FULL;
593
594 /* turn off pause in 10/100mbps half duplex */
595 else if (sky2->speed != SPEED_1000 &&
596 hw->chip_id != CHIP_ID_YUKON_EC_U)
597 sky2->tx_pause = sky2->rx_pause = 0;
598 } else
599 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
600
601 if (!sky2->tx_pause && !sky2->rx_pause) {
602 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
603 reg |=
604 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
605 } else if (sky2->tx_pause && !sky2->rx_pause) {
606 /* disable Rx flow-control */
607 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
608 }
609
610 gma_write16(hw, port, GM_GP_CTRL, reg);
611
612 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
613
614 spin_lock_bh(&sky2->phy_lock);
615 sky2_phy_init(hw, port);
616 spin_unlock_bh(&sky2->phy_lock);
617
618 /* MIB clear */
619 reg = gma_read16(hw, port, GM_PHY_ADDR);
620 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
621
622 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
623 gma_read16(hw, port, i);
624 gma_write16(hw, port, GM_PHY_ADDR, reg);
625
626 /* transmit control */
627 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
628
629 /* receive control reg: unicast + multicast + no FCS */
630 gma_write16(hw, port, GM_RX_CTRL,
631 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
632
633 /* transmit flow control */
634 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
635
636 /* transmit parameter */
637 gma_write16(hw, port, GM_TX_PARAM,
638 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
639 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
640 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
641 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
642
643 /* serial mode register */
644 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
645 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
646
647 if (hw->dev[port]->mtu > ETH_DATA_LEN)
648 reg |= GM_SMOD_JUMBO_ENA;
649
650 gma_write16(hw, port, GM_SERIAL_MODE, reg);
651
652 /* virtual address for data */
653 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
654
655 /* physical address: used for pause frames */
656 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
657
658 /* ignore counter overflows */
659 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
660 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
661 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
662
663 /* Configure Rx MAC FIFO */
664 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
665 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
666 GMF_OPER_ON | GMF_RX_F_FL_ON);
667
668 /* Flush Rx MAC FIFO on any flow control or error */
669 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
670
671 /* Set threshold to 0xa (64 bytes)
672 * ASF disabled so no need to do WA dev #4.30
673 */
674 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
675
676 /* Configure Tx MAC FIFO */
677 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
678 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
679
680 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
681 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 512/8);
682 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
683 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
684 /* set Tx GMAC FIFO Almost Empty Threshold */
685 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
686 /* Disable Store & Forward mode for TX */
687 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
688 }
689 }
690
691 }
692
693 /* Assign Ram Buffer allocation.
694 * start and end are in units of 4k bytes
695 * ram registers are in units of 64bit words
696 */
697 static void sky2_ramset(struct sky2_hw *hw, u16 q, u8 startk, u8 endk)
698 {
699 u32 start, end;
700
701 start = startk * 4096/8;
702 end = (endk * 4096/8) - 1;
703
704 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
705 sky2_write32(hw, RB_ADDR(q, RB_START), start);
706 sky2_write32(hw, RB_ADDR(q, RB_END), end);
707 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
708 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
709
710 if (q == Q_R1 || q == Q_R2) {
711 u32 space = (endk - startk) * 4096/8;
712 u32 tp = space - space/4;
713
714 /* On receive queue's set the thresholds
715 * give receiver priority when > 3/4 full
716 * send pause when down to 2K
717 */
718 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
719 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
720
721 tp = space - 2048/8;
722 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
723 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
724 } else {
725 /* Enable store & forward on Tx queue's because
726 * Tx FIFO is only 1K on Yukon
727 */
728 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
729 }
730
731 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
732 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
733 }
734
735 /* Setup Bus Memory Interface */
736 static void sky2_qset(struct sky2_hw *hw, u16 q)
737 {
738 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
739 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
740 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
741 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
742 }
743
744 /* Setup prefetch unit registers. This is the interface between
745 * hardware and driver list elements
746 */
747 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
748 u64 addr, u32 last)
749 {
750 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
751 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
752 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
753 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
754 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
755 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
756
757 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
758 }
759
760 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
761 {
762 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
763
764 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
765 return le;
766 }
767
768 /* Update chip's next pointer */
769 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
770 {
771 wmb();
772 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
773 mmiowb();
774 }
775
776
777 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
778 {
779 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
780 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
781 return le;
782 }
783
784 /* Return high part of DMA address (could be 32 or 64 bit) */
785 static inline u32 high32(dma_addr_t a)
786 {
787 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
788 }
789
790 /* Build description to hardware about buffer */
791 static void sky2_rx_add(struct sky2_port *sky2, dma_addr_t map)
792 {
793 struct sky2_rx_le *le;
794 u32 hi = high32(map);
795 u16 len = sky2->rx_bufsize;
796
797 if (sky2->rx_addr64 != hi) {
798 le = sky2_next_rx(sky2);
799 le->addr = cpu_to_le32(hi);
800 le->ctrl = 0;
801 le->opcode = OP_ADDR64 | HW_OWNER;
802 sky2->rx_addr64 = high32(map + len);
803 }
804
805 le = sky2_next_rx(sky2);
806 le->addr = cpu_to_le32((u32) map);
807 le->length = cpu_to_le16(len);
808 le->ctrl = 0;
809 le->opcode = OP_PACKET | HW_OWNER;
810 }
811
812
813 /* Tell chip where to start receive checksum.
814 * Actually has two checksums, but set both same to avoid possible byte
815 * order problems.
816 */
817 static void rx_set_checksum(struct sky2_port *sky2)
818 {
819 struct sky2_rx_le *le;
820
821 le = sky2_next_rx(sky2);
822 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
823 le->ctrl = 0;
824 le->opcode = OP_TCPSTART | HW_OWNER;
825
826 sky2_write32(sky2->hw,
827 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
828 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
829
830 }
831
832 /*
833 * The RX Stop command will not work for Yukon-2 if the BMU does not
834 * reach the end of packet and since we can't make sure that we have
835 * incoming data, we must reset the BMU while it is not doing a DMA
836 * transfer. Since it is possible that the RX path is still active,
837 * the RX RAM buffer will be stopped first, so any possible incoming
838 * data will not trigger a DMA. After the RAM buffer is stopped, the
839 * BMU is polled until any DMA in progress is ended and only then it
840 * will be reset.
841 */
842 static void sky2_rx_stop(struct sky2_port *sky2)
843 {
844 struct sky2_hw *hw = sky2->hw;
845 unsigned rxq = rxqaddr[sky2->port];
846 int i;
847
848 /* disable the RAM Buffer receive queue */
849 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
850
851 for (i = 0; i < 0xffff; i++)
852 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
853 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
854 goto stopped;
855
856 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
857 sky2->netdev->name);
858 stopped:
859 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
860
861 /* reset the Rx prefetch unit */
862 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
863 }
864
865 /* Clean out receive buffer area, assumes receiver hardware stopped */
866 static void sky2_rx_clean(struct sky2_port *sky2)
867 {
868 unsigned i;
869
870 memset(sky2->rx_le, 0, RX_LE_BYTES);
871 for (i = 0; i < sky2->rx_pending; i++) {
872 struct ring_info *re = sky2->rx_ring + i;
873
874 if (re->skb) {
875 pci_unmap_single(sky2->hw->pdev,
876 re->mapaddr, sky2->rx_bufsize,
877 PCI_DMA_FROMDEVICE);
878 kfree_skb(re->skb);
879 re->skb = NULL;
880 }
881 }
882 }
883
884 /* Basic MII support */
885 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
886 {
887 struct mii_ioctl_data *data = if_mii(ifr);
888 struct sky2_port *sky2 = netdev_priv(dev);
889 struct sky2_hw *hw = sky2->hw;
890 int err = -EOPNOTSUPP;
891
892 if (!netif_running(dev))
893 return -ENODEV; /* Phy still in reset */
894
895 switch (cmd) {
896 case SIOCGMIIPHY:
897 data->phy_id = PHY_ADDR_MARV;
898
899 /* fallthru */
900 case SIOCGMIIREG: {
901 u16 val = 0;
902
903 spin_lock_bh(&sky2->phy_lock);
904 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
905 spin_unlock_bh(&sky2->phy_lock);
906
907 data->val_out = val;
908 break;
909 }
910
911 case SIOCSMIIREG:
912 if (!capable(CAP_NET_ADMIN))
913 return -EPERM;
914
915 spin_lock_bh(&sky2->phy_lock);
916 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
917 data->val_in);
918 spin_unlock_bh(&sky2->phy_lock);
919 break;
920 }
921 return err;
922 }
923
924 #ifdef SKY2_VLAN_TAG_USED
925 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
926 {
927 struct sky2_port *sky2 = netdev_priv(dev);
928 struct sky2_hw *hw = sky2->hw;
929 u16 port = sky2->port;
930
931 spin_lock_bh(&sky2->tx_lock);
932
933 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
934 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
935 sky2->vlgrp = grp;
936
937 spin_unlock_bh(&sky2->tx_lock);
938 }
939
940 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
941 {
942 struct sky2_port *sky2 = netdev_priv(dev);
943 struct sky2_hw *hw = sky2->hw;
944 u16 port = sky2->port;
945
946 spin_lock_bh(&sky2->tx_lock);
947
948 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
949 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
950 if (sky2->vlgrp)
951 sky2->vlgrp->vlan_devices[vid] = NULL;
952
953 spin_unlock_bh(&sky2->tx_lock);
954 }
955 #endif
956
957 /*
958 * It appears the hardware has a bug in the FIFO logic that
959 * cause it to hang if the FIFO gets overrun and the receive buffer
960 * is not aligned. ALso alloc_skb() won't align properly if slab
961 * debugging is enabled.
962 */
963 static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask)
964 {
965 struct sk_buff *skb;
966
967 skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask);
968 if (likely(skb)) {
969 unsigned long p = (unsigned long) skb->data;
970 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
971 }
972
973 return skb;
974 }
975
976 /*
977 * Allocate and setup receiver buffer pool.
978 * In case of 64 bit dma, there are 2X as many list elements
979 * available as ring entries
980 * and need to reserve one list element so we don't wrap around.
981 */
982 static int sky2_rx_start(struct sky2_port *sky2)
983 {
984 struct sky2_hw *hw = sky2->hw;
985 unsigned rxq = rxqaddr[sky2->port];
986 int i;
987 unsigned thresh;
988
989 sky2->rx_put = sky2->rx_next = 0;
990 sky2_qset(hw, rxq);
991
992 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev >= 2) {
993 /* MAC Rx RAM Read is controlled by hardware */
994 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
995 }
996
997 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
998
999 rx_set_checksum(sky2);
1000 for (i = 0; i < sky2->rx_pending; i++) {
1001 struct ring_info *re = sky2->rx_ring + i;
1002
1003 re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL);
1004 if (!re->skb)
1005 goto nomem;
1006
1007 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
1008 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1009 sky2_rx_add(sky2, re->mapaddr);
1010 }
1011
1012
1013 /*
1014 * The receiver hangs if it receives frames larger than the
1015 * packet buffer. As a workaround, truncate oversize frames, but
1016 * the register is limited to 9 bits, so if you do frames > 2052
1017 * you better get the MTU right!
1018 */
1019 thresh = (sky2->rx_bufsize - 8) / sizeof(u32);
1020 if (thresh > 0x1ff)
1021 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1022 else {
1023 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1024 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1025 }
1026
1027
1028 /* Tell chip about available buffers */
1029 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1030 return 0;
1031 nomem:
1032 sky2_rx_clean(sky2);
1033 return -ENOMEM;
1034 }
1035
1036 /* Bring up network interface. */
1037 static int sky2_up(struct net_device *dev)
1038 {
1039 struct sky2_port *sky2 = netdev_priv(dev);
1040 struct sky2_hw *hw = sky2->hw;
1041 unsigned port = sky2->port;
1042 u32 ramsize, rxspace, imask;
1043 int cap, err = -ENOMEM;
1044 struct net_device *otherdev = hw->dev[sky2->port^1];
1045
1046 /*
1047 * On dual port PCI-X card, there is an problem where status
1048 * can be received out of order due to split transactions
1049 */
1050 if (otherdev && netif_running(otherdev) &&
1051 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1052 struct sky2_port *osky2 = netdev_priv(otherdev);
1053 u16 cmd;
1054
1055 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1056 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1057 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1058
1059 sky2->rx_csum = 0;
1060 osky2->rx_csum = 0;
1061 }
1062
1063 if (netif_msg_ifup(sky2))
1064 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1065
1066 /* must be power of 2 */
1067 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1068 TX_RING_SIZE *
1069 sizeof(struct sky2_tx_le),
1070 &sky2->tx_le_map);
1071 if (!sky2->tx_le)
1072 goto err_out;
1073
1074 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1075 GFP_KERNEL);
1076 if (!sky2->tx_ring)
1077 goto err_out;
1078 sky2->tx_prod = sky2->tx_cons = 0;
1079
1080 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1081 &sky2->rx_le_map);
1082 if (!sky2->rx_le)
1083 goto err_out;
1084 memset(sky2->rx_le, 0, RX_LE_BYTES);
1085
1086 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct ring_info),
1087 GFP_KERNEL);
1088 if (!sky2->rx_ring)
1089 goto err_out;
1090
1091 sky2_mac_init(hw, port);
1092
1093 /* Determine available ram buffer space (in 4K blocks).
1094 * Note: not sure about the FE setting below yet
1095 */
1096 if (hw->chip_id == CHIP_ID_YUKON_FE)
1097 ramsize = 4;
1098 else
1099 ramsize = sky2_read8(hw, B2_E_0);
1100
1101 /* Give transmitter one third (rounded up) */
1102 rxspace = ramsize - (ramsize + 2) / 3;
1103
1104 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1105 sky2_ramset(hw, txqaddr[port], rxspace, ramsize);
1106
1107 /* Make sure SyncQ is disabled */
1108 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1109 RB_RST_SET);
1110
1111 sky2_qset(hw, txqaddr[port]);
1112
1113 /* Set almost empty threshold */
1114 if (hw->chip_id == CHIP_ID_YUKON_EC_U && hw->chip_rev == 1)
1115 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
1116
1117 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1118 TX_RING_SIZE - 1);
1119
1120 err = sky2_rx_start(sky2);
1121 if (err)
1122 goto err_out;
1123
1124 /* Enable interrupts from phy/mac for port */
1125 imask = sky2_read32(hw, B0_IMSK);
1126 imask |= portirq_msk[port];
1127 sky2_write32(hw, B0_IMSK, imask);
1128
1129 return 0;
1130
1131 err_out:
1132 if (sky2->rx_le) {
1133 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1134 sky2->rx_le, sky2->rx_le_map);
1135 sky2->rx_le = NULL;
1136 }
1137 if (sky2->tx_le) {
1138 pci_free_consistent(hw->pdev,
1139 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1140 sky2->tx_le, sky2->tx_le_map);
1141 sky2->tx_le = NULL;
1142 }
1143 kfree(sky2->tx_ring);
1144 kfree(sky2->rx_ring);
1145
1146 sky2->tx_ring = NULL;
1147 sky2->rx_ring = NULL;
1148 return err;
1149 }
1150
1151 /* Modular subtraction in ring */
1152 static inline int tx_dist(unsigned tail, unsigned head)
1153 {
1154 return (head - tail) & (TX_RING_SIZE - 1);
1155 }
1156
1157 /* Number of list elements available for next tx */
1158 static inline int tx_avail(const struct sky2_port *sky2)
1159 {
1160 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1161 }
1162
1163 /* Estimate of number of transmit list elements required */
1164 static unsigned tx_le_req(const struct sk_buff *skb)
1165 {
1166 unsigned count;
1167
1168 count = sizeof(dma_addr_t) / sizeof(u32);
1169 count += skb_shinfo(skb)->nr_frags * count;
1170
1171 if (skb_is_gso(skb))
1172 ++count;
1173
1174 if (skb->ip_summed == CHECKSUM_HW)
1175 ++count;
1176
1177 return count;
1178 }
1179
1180 /*
1181 * Put one packet in ring for transmit.
1182 * A single packet can generate multiple list elements, and
1183 * the number of ring elements will probably be less than the number
1184 * of list elements used.
1185 *
1186 * No BH disabling for tx_lock here (like tg3)
1187 */
1188 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1189 {
1190 struct sky2_port *sky2 = netdev_priv(dev);
1191 struct sky2_hw *hw = sky2->hw;
1192 struct sky2_tx_le *le = NULL;
1193 struct tx_ring_info *re;
1194 unsigned i, len;
1195 int avail;
1196 dma_addr_t mapping;
1197 u32 addr64;
1198 u16 mss;
1199 u8 ctrl;
1200
1201 /* No BH disabling for tx_lock here. We are running in BH disabled
1202 * context and TX reclaim runs via poll inside of a software
1203 * interrupt, and no related locks in IRQ processing.
1204 */
1205 if (!spin_trylock(&sky2->tx_lock))
1206 return NETDEV_TX_LOCKED;
1207
1208 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1209 /* There is a known but harmless race with lockless tx
1210 * and netif_stop_queue.
1211 */
1212 if (!netif_queue_stopped(dev)) {
1213 netif_stop_queue(dev);
1214 if (net_ratelimit())
1215 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1216 dev->name);
1217 }
1218 spin_unlock(&sky2->tx_lock);
1219
1220 return NETDEV_TX_BUSY;
1221 }
1222
1223 if (unlikely(netif_msg_tx_queued(sky2)))
1224 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1225 dev->name, sky2->tx_prod, skb->len);
1226
1227 len = skb_headlen(skb);
1228 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1229 addr64 = high32(mapping);
1230
1231 re = sky2->tx_ring + sky2->tx_prod;
1232
1233 /* Send high bits if changed or crosses boundary */
1234 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1235 le = get_tx_le(sky2);
1236 le->tx.addr = cpu_to_le32(addr64);
1237 le->ctrl = 0;
1238 le->opcode = OP_ADDR64 | HW_OWNER;
1239 sky2->tx_addr64 = high32(mapping + len);
1240 }
1241
1242 /* Check for TCP Segmentation Offload */
1243 mss = skb_shinfo(skb)->gso_size;
1244 if (mss != 0) {
1245 /* just drop the packet if non-linear expansion fails */
1246 if (skb_header_cloned(skb) &&
1247 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1248 dev_kfree_skb(skb);
1249 goto out_unlock;
1250 }
1251
1252 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1253 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1254 mss += ETH_HLEN;
1255 }
1256
1257 if (mss != sky2->tx_last_mss) {
1258 le = get_tx_le(sky2);
1259 le->tx.tso.size = cpu_to_le16(mss);
1260 le->tx.tso.rsvd = 0;
1261 le->opcode = OP_LRGLEN | HW_OWNER;
1262 le->ctrl = 0;
1263 sky2->tx_last_mss = mss;
1264 }
1265
1266 ctrl = 0;
1267 #ifdef SKY2_VLAN_TAG_USED
1268 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1269 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1270 if (!le) {
1271 le = get_tx_le(sky2);
1272 le->tx.addr = 0;
1273 le->opcode = OP_VLAN|HW_OWNER;
1274 le->ctrl = 0;
1275 } else
1276 le->opcode |= OP_VLAN;
1277 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1278 ctrl |= INS_VLAN;
1279 }
1280 #endif
1281
1282 /* Handle TCP checksum offload */
1283 if (skb->ip_summed == CHECKSUM_HW) {
1284 u16 hdr = skb->h.raw - skb->data;
1285 u16 offset = hdr + skb->csum;
1286
1287 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1288 if (skb->nh.iph->protocol == IPPROTO_UDP)
1289 ctrl |= UDPTCP;
1290
1291 le = get_tx_le(sky2);
1292 le->tx.csum.start = cpu_to_le16(hdr);
1293 le->tx.csum.offset = cpu_to_le16(offset);
1294 le->length = 0; /* initial checksum value */
1295 le->ctrl = 1; /* one packet */
1296 le->opcode = OP_TCPLISW | HW_OWNER;
1297 }
1298
1299 le = get_tx_le(sky2);
1300 le->tx.addr = cpu_to_le32((u32) mapping);
1301 le->length = cpu_to_le16(len);
1302 le->ctrl = ctrl;
1303 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1304
1305 /* Record the transmit mapping info */
1306 re->skb = skb;
1307 pci_unmap_addr_set(re, mapaddr, mapping);
1308
1309 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1310 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1311 struct tx_ring_info *fre;
1312
1313 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1314 frag->size, PCI_DMA_TODEVICE);
1315 addr64 = high32(mapping);
1316 if (addr64 != sky2->tx_addr64) {
1317 le = get_tx_le(sky2);
1318 le->tx.addr = cpu_to_le32(addr64);
1319 le->ctrl = 0;
1320 le->opcode = OP_ADDR64 | HW_OWNER;
1321 sky2->tx_addr64 = addr64;
1322 }
1323
1324 le = get_tx_le(sky2);
1325 le->tx.addr = cpu_to_le32((u32) mapping);
1326 le->length = cpu_to_le16(frag->size);
1327 le->ctrl = ctrl;
1328 le->opcode = OP_BUFFER | HW_OWNER;
1329
1330 fre = sky2->tx_ring
1331 + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE);
1332 pci_unmap_addr_set(fre, mapaddr, mapping);
1333 }
1334
1335 re->idx = sky2->tx_prod;
1336 le->ctrl |= EOP;
1337
1338 avail = tx_avail(sky2);
1339 if (mss != 0 || avail < TX_MIN_PENDING) {
1340 le->ctrl |= FRC_STAT;
1341 if (avail <= MAX_SKB_TX_LE)
1342 netif_stop_queue(dev);
1343 }
1344
1345 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1346
1347 out_unlock:
1348 spin_unlock(&sky2->tx_lock);
1349
1350 dev->trans_start = jiffies;
1351 return NETDEV_TX_OK;
1352 }
1353
1354 /*
1355 * Free ring elements from starting at tx_cons until "done"
1356 *
1357 * NB: the hardware will tell us about partial completion of multi-part
1358 * buffers; these are deferred until completion.
1359 */
1360 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1361 {
1362 struct net_device *dev = sky2->netdev;
1363 struct pci_dev *pdev = sky2->hw->pdev;
1364 u16 nxt, put;
1365 unsigned i;
1366
1367 BUG_ON(done >= TX_RING_SIZE);
1368
1369 if (unlikely(netif_msg_tx_done(sky2)))
1370 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1371 dev->name, done);
1372
1373 for (put = sky2->tx_cons; put != done; put = nxt) {
1374 struct tx_ring_info *re = sky2->tx_ring + put;
1375 struct sk_buff *skb = re->skb;
1376
1377 nxt = re->idx;
1378 BUG_ON(nxt >= TX_RING_SIZE);
1379 prefetch(sky2->tx_ring + nxt);
1380
1381 /* Check for partial status */
1382 if (tx_dist(put, done) < tx_dist(put, nxt))
1383 break;
1384
1385 skb = re->skb;
1386 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1387 skb_headlen(skb), PCI_DMA_TODEVICE);
1388
1389 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1390 struct tx_ring_info *fre;
1391 fre = sky2->tx_ring + RING_NEXT(put + i, TX_RING_SIZE);
1392 pci_unmap_page(pdev, pci_unmap_addr(fre, mapaddr),
1393 skb_shinfo(skb)->frags[i].size,
1394 PCI_DMA_TODEVICE);
1395 }
1396
1397 dev_kfree_skb(skb);
1398 }
1399
1400 sky2->tx_cons = put;
1401 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1402 netif_wake_queue(dev);
1403 }
1404
1405 /* Cleanup all untransmitted buffers, assume transmitter not running */
1406 static void sky2_tx_clean(struct sky2_port *sky2)
1407 {
1408 spin_lock_bh(&sky2->tx_lock);
1409 sky2_tx_complete(sky2, sky2->tx_prod);
1410 spin_unlock_bh(&sky2->tx_lock);
1411 }
1412
1413 /* Network shutdown */
1414 static int sky2_down(struct net_device *dev)
1415 {
1416 struct sky2_port *sky2 = netdev_priv(dev);
1417 struct sky2_hw *hw = sky2->hw;
1418 unsigned port = sky2->port;
1419 u16 ctrl;
1420 u32 imask;
1421
1422 /* Never really got started! */
1423 if (!sky2->tx_le)
1424 return 0;
1425
1426 if (netif_msg_ifdown(sky2))
1427 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1428
1429 /* Stop more packets from being queued */
1430 netif_stop_queue(dev);
1431
1432 /* Disable port IRQ */
1433 imask = sky2_read32(hw, B0_IMSK);
1434 imask &= ~portirq_msk[port];
1435 sky2_write32(hw, B0_IMSK, imask);
1436
1437 sky2_phy_reset(hw, port);
1438
1439 /* Stop transmitter */
1440 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1441 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1442
1443 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1444 RB_RST_SET | RB_DIS_OP_MD);
1445
1446 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1447 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1448 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1449
1450 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1451
1452 /* Workaround shared GMAC reset */
1453 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1454 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1455 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1456
1457 /* Disable Force Sync bit and Enable Alloc bit */
1458 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1459 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1460
1461 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1462 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1463 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1464
1465 /* Reset the PCI FIFO of the async Tx queue */
1466 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1467 BMU_RST_SET | BMU_FIFO_RST);
1468
1469 /* Reset the Tx prefetch units */
1470 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1471 PREF_UNIT_RST_SET);
1472
1473 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1474
1475 sky2_rx_stop(sky2);
1476
1477 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1478 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1479
1480 /* turn off LED's */
1481 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1482
1483 synchronize_irq(hw->pdev->irq);
1484
1485 sky2_tx_clean(sky2);
1486 sky2_rx_clean(sky2);
1487
1488 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1489 sky2->rx_le, sky2->rx_le_map);
1490 kfree(sky2->rx_ring);
1491
1492 pci_free_consistent(hw->pdev,
1493 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1494 sky2->tx_le, sky2->tx_le_map);
1495 kfree(sky2->tx_ring);
1496
1497 sky2->tx_le = NULL;
1498 sky2->rx_le = NULL;
1499
1500 sky2->rx_ring = NULL;
1501 sky2->tx_ring = NULL;
1502
1503 return 0;
1504 }
1505
1506 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1507 {
1508 if (!hw->copper)
1509 return SPEED_1000;
1510
1511 if (hw->chip_id == CHIP_ID_YUKON_FE)
1512 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1513
1514 switch (aux & PHY_M_PS_SPEED_MSK) {
1515 case PHY_M_PS_SPEED_1000:
1516 return SPEED_1000;
1517 case PHY_M_PS_SPEED_100:
1518 return SPEED_100;
1519 default:
1520 return SPEED_10;
1521 }
1522 }
1523
1524 static void sky2_link_up(struct sky2_port *sky2)
1525 {
1526 struct sky2_hw *hw = sky2->hw;
1527 unsigned port = sky2->port;
1528 u16 reg;
1529
1530 /* Enable Transmit FIFO Underrun */
1531 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1532
1533 reg = gma_read16(hw, port, GM_GP_CTRL);
1534 if (sky2->autoneg == AUTONEG_DISABLE) {
1535 reg |= GM_GPCR_AU_ALL_DIS;
1536
1537 /* Is write/read necessary? Copied from sky2_mac_init */
1538 gma_write16(hw, port, GM_GP_CTRL, reg);
1539 gma_read16(hw, port, GM_GP_CTRL);
1540
1541 switch (sky2->speed) {
1542 case SPEED_1000:
1543 reg &= ~GM_GPCR_SPEED_100;
1544 reg |= GM_GPCR_SPEED_1000;
1545 break;
1546 case SPEED_100:
1547 reg &= ~GM_GPCR_SPEED_1000;
1548 reg |= GM_GPCR_SPEED_100;
1549 break;
1550 case SPEED_10:
1551 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
1552 break;
1553 }
1554 } else
1555 reg &= ~GM_GPCR_AU_ALL_DIS;
1556
1557 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1558 reg |= GM_GPCR_DUP_FULL;
1559
1560 /* enable Rx/Tx */
1561 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1562 gma_write16(hw, port, GM_GP_CTRL, reg);
1563 gma_read16(hw, port, GM_GP_CTRL);
1564
1565 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1566
1567 netif_carrier_on(sky2->netdev);
1568 netif_wake_queue(sky2->netdev);
1569
1570 /* Turn on link LED */
1571 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1572 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1573
1574 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U) {
1575 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1576 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1577
1578 switch(sky2->speed) {
1579 case SPEED_10:
1580 led |= PHY_M_LEDC_INIT_CTRL(7);
1581 break;
1582
1583 case SPEED_100:
1584 led |= PHY_M_LEDC_STA1_CTRL(7);
1585 break;
1586
1587 case SPEED_1000:
1588 led |= PHY_M_LEDC_STA0_CTRL(7);
1589 break;
1590 }
1591
1592 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1593 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1594 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1595 }
1596
1597 if (netif_msg_link(sky2))
1598 printk(KERN_INFO PFX
1599 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1600 sky2->netdev->name, sky2->speed,
1601 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1602 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1603 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1604 }
1605
1606 static void sky2_link_down(struct sky2_port *sky2)
1607 {
1608 struct sky2_hw *hw = sky2->hw;
1609 unsigned port = sky2->port;
1610 u16 reg;
1611
1612 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1613
1614 reg = gma_read16(hw, port, GM_GP_CTRL);
1615 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1616 gma_write16(hw, port, GM_GP_CTRL, reg);
1617 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1618
1619 if (sky2->rx_pause && !sky2->tx_pause) {
1620 /* restore Asymmetric Pause bit */
1621 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1622 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1623 | PHY_M_AN_ASP);
1624 }
1625
1626 netif_carrier_off(sky2->netdev);
1627 netif_stop_queue(sky2->netdev);
1628
1629 /* Turn on link LED */
1630 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1631
1632 if (netif_msg_link(sky2))
1633 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1634 sky2_phy_init(hw, port);
1635 }
1636
1637 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1638 {
1639 struct sky2_hw *hw = sky2->hw;
1640 unsigned port = sky2->port;
1641 u16 lpa;
1642
1643 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1644
1645 if (lpa & PHY_M_AN_RF) {
1646 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1647 return -1;
1648 }
1649
1650 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1651 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1652 printk(KERN_ERR PFX "%s: master/slave fault",
1653 sky2->netdev->name);
1654 return -1;
1655 }
1656
1657 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1658 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1659 sky2->netdev->name);
1660 return -1;
1661 }
1662
1663 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1664
1665 sky2->speed = sky2_phy_speed(hw, aux);
1666
1667 /* Pause bits are offset (9..8) */
1668 if (hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)
1669 aux >>= 6;
1670
1671 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1672 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1673
1674 if ((sky2->tx_pause || sky2->rx_pause)
1675 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1676 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1677 else
1678 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1679
1680 return 0;
1681 }
1682
1683 /* Interrupt from PHY */
1684 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1685 {
1686 struct net_device *dev = hw->dev[port];
1687 struct sky2_port *sky2 = netdev_priv(dev);
1688 u16 istatus, phystat;
1689
1690 if (!netif_running(dev))
1691 return;
1692
1693 spin_lock(&sky2->phy_lock);
1694 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1695 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1696
1697 if (netif_msg_intr(sky2))
1698 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1699 sky2->netdev->name, istatus, phystat);
1700
1701 if (istatus & PHY_M_IS_AN_COMPL) {
1702 if (sky2_autoneg_done(sky2, phystat) == 0)
1703 sky2_link_up(sky2);
1704 goto out;
1705 }
1706
1707 if (istatus & PHY_M_IS_LSP_CHANGE)
1708 sky2->speed = sky2_phy_speed(hw, phystat);
1709
1710 if (istatus & PHY_M_IS_DUP_CHANGE)
1711 sky2->duplex =
1712 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1713
1714 if (istatus & PHY_M_IS_LST_CHANGE) {
1715 if (phystat & PHY_M_PS_LINK_UP)
1716 sky2_link_up(sky2);
1717 else
1718 sky2_link_down(sky2);
1719 }
1720 out:
1721 spin_unlock(&sky2->phy_lock);
1722 }
1723
1724
1725 /* Transmit timeout is only called if we are running, carries is up
1726 * and tx queue is full (stopped).
1727 */
1728 static void sky2_tx_timeout(struct net_device *dev)
1729 {
1730 struct sky2_port *sky2 = netdev_priv(dev);
1731 struct sky2_hw *hw = sky2->hw;
1732 unsigned txq = txqaddr[sky2->port];
1733 u16 report, done;
1734
1735 if (netif_msg_timer(sky2))
1736 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1737
1738 report = sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX);
1739 done = sky2_read16(hw, Q_ADDR(txq, Q_DONE));
1740
1741 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1742 dev->name,
1743 sky2->tx_cons, sky2->tx_prod, report, done);
1744
1745 if (report != done) {
1746 printk(KERN_INFO PFX "status burst pending (irq moderation?)\n");
1747
1748 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1749 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1750 } else if (report != sky2->tx_cons) {
1751 printk(KERN_INFO PFX "status report lost?\n");
1752
1753 spin_lock_bh(&sky2->tx_lock);
1754 sky2_tx_complete(sky2, report);
1755 spin_unlock_bh(&sky2->tx_lock);
1756 } else {
1757 printk(KERN_INFO PFX "hardware hung? flushing\n");
1758
1759 sky2_write32(hw, Q_ADDR(txq, Q_CSR), BMU_STOP);
1760 sky2_write32(hw, Y2_QADDR(txq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1761
1762 sky2_tx_clean(sky2);
1763
1764 sky2_qset(hw, txq);
1765 sky2_prefetch_init(hw, txq, sky2->tx_le_map, TX_RING_SIZE - 1);
1766 }
1767 }
1768
1769
1770 /* Want receive buffer size to be multiple of 64 bits
1771 * and incl room for vlan and truncation
1772 */
1773 static inline unsigned sky2_buf_size(int mtu)
1774 {
1775 return ALIGN(mtu + ETH_HLEN + VLAN_HLEN, 8) + 8;
1776 }
1777
1778 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1779 {
1780 struct sky2_port *sky2 = netdev_priv(dev);
1781 struct sky2_hw *hw = sky2->hw;
1782 int err;
1783 u16 ctl, mode;
1784 u32 imask;
1785
1786 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1787 return -EINVAL;
1788
1789 if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
1790 return -EINVAL;
1791
1792 if (!netif_running(dev)) {
1793 dev->mtu = new_mtu;
1794 return 0;
1795 }
1796
1797 imask = sky2_read32(hw, B0_IMSK);
1798 sky2_write32(hw, B0_IMSK, 0);
1799
1800 dev->trans_start = jiffies; /* prevent tx timeout */
1801 netif_stop_queue(dev);
1802 netif_poll_disable(hw->dev[0]);
1803
1804 synchronize_irq(hw->pdev->irq);
1805
1806 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1807 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1808 sky2_rx_stop(sky2);
1809 sky2_rx_clean(sky2);
1810
1811 dev->mtu = new_mtu;
1812 sky2->rx_bufsize = sky2_buf_size(new_mtu);
1813 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1814 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1815
1816 if (dev->mtu > ETH_DATA_LEN)
1817 mode |= GM_SMOD_JUMBO_ENA;
1818
1819 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1820
1821 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1822
1823 err = sky2_rx_start(sky2);
1824 sky2_write32(hw, B0_IMSK, imask);
1825
1826 if (err)
1827 dev_close(dev);
1828 else {
1829 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1830
1831 netif_poll_enable(hw->dev[0]);
1832 netif_wake_queue(dev);
1833 }
1834
1835 return err;
1836 }
1837
1838 /*
1839 * Receive one packet.
1840 * For small packets or errors, just reuse existing skb.
1841 * For larger packets, get new buffer.
1842 */
1843 static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1844 u16 length, u32 status)
1845 {
1846 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1847 struct sk_buff *skb = NULL;
1848
1849 if (unlikely(netif_msg_rx_status(sky2)))
1850 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1851 sky2->netdev->name, sky2->rx_next, status, length);
1852
1853 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1854 prefetch(sky2->rx_ring + sky2->rx_next);
1855
1856 if (status & GMR_FS_ANY_ERR)
1857 goto error;
1858
1859 if (!(status & GMR_FS_RX_OK))
1860 goto resubmit;
1861
1862 if (length > sky2->netdev->mtu + ETH_HLEN)
1863 goto oversize;
1864
1865 if (length < copybreak) {
1866 skb = alloc_skb(length + 2, GFP_ATOMIC);
1867 if (!skb)
1868 goto resubmit;
1869
1870 skb_reserve(skb, 2);
1871 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1872 length, PCI_DMA_FROMDEVICE);
1873 memcpy(skb->data, re->skb->data, length);
1874 skb->ip_summed = re->skb->ip_summed;
1875 skb->csum = re->skb->csum;
1876 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1877 length, PCI_DMA_FROMDEVICE);
1878 } else {
1879 struct sk_buff *nskb;
1880
1881 nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC);
1882 if (!nskb)
1883 goto resubmit;
1884
1885 skb = re->skb;
1886 re->skb = nskb;
1887 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1888 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1889 prefetch(skb->data);
1890
1891 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1892 sky2->rx_bufsize, PCI_DMA_FROMDEVICE);
1893 }
1894
1895 skb_put(skb, length);
1896 resubmit:
1897 re->skb->ip_summed = CHECKSUM_NONE;
1898 sky2_rx_add(sky2, re->mapaddr);
1899
1900 return skb;
1901
1902 oversize:
1903 ++sky2->net_stats.rx_over_errors;
1904 goto resubmit;
1905
1906 error:
1907 ++sky2->net_stats.rx_errors;
1908
1909 if (netif_msg_rx_err(sky2) && net_ratelimit())
1910 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1911 sky2->netdev->name, status, length);
1912
1913 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1914 sky2->net_stats.rx_length_errors++;
1915 if (status & GMR_FS_FRAGMENT)
1916 sky2->net_stats.rx_frame_errors++;
1917 if (status & GMR_FS_CRC_ERR)
1918 sky2->net_stats.rx_crc_errors++;
1919 if (status & GMR_FS_RX_FF_OV)
1920 sky2->net_stats.rx_fifo_errors++;
1921
1922 goto resubmit;
1923 }
1924
1925 /* Transmit complete */
1926 static inline void sky2_tx_done(struct net_device *dev, u16 last)
1927 {
1928 struct sky2_port *sky2 = netdev_priv(dev);
1929
1930 if (netif_running(dev)) {
1931 spin_lock(&sky2->tx_lock);
1932 sky2_tx_complete(sky2, last);
1933 spin_unlock(&sky2->tx_lock);
1934 }
1935 }
1936
1937 /* Is status ring empty or is there more to do? */
1938 static inline int sky2_more_work(const struct sky2_hw *hw)
1939 {
1940 return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX));
1941 }
1942
1943 /* Process status response ring */
1944 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
1945 {
1946 struct sky2_port *sky2;
1947 int work_done = 0;
1948 unsigned buf_write[2] = { 0, 0 };
1949 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1950
1951 rmb();
1952
1953 while (hw->st_idx != hwidx) {
1954 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1955 struct net_device *dev;
1956 struct sk_buff *skb;
1957 u32 status;
1958 u16 length;
1959
1960 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
1961
1962 BUG_ON(le->link >= 2);
1963 dev = hw->dev[le->link];
1964
1965 sky2 = netdev_priv(dev);
1966 length = le->length;
1967 status = le->status;
1968
1969 switch (le->opcode & ~HW_OWNER) {
1970 case OP_RXSTAT:
1971 skb = sky2_receive(sky2, length, status);
1972 if (!skb)
1973 break;
1974
1975 skb->dev = dev;
1976 skb->protocol = eth_type_trans(skb, dev);
1977 dev->last_rx = jiffies;
1978
1979 #ifdef SKY2_VLAN_TAG_USED
1980 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1981 vlan_hwaccel_receive_skb(skb,
1982 sky2->vlgrp,
1983 be16_to_cpu(sky2->rx_tag));
1984 } else
1985 #endif
1986 netif_receive_skb(skb);
1987
1988 /* Update receiver after 16 frames */
1989 if (++buf_write[le->link] == RX_BUF_WRITE) {
1990 sky2_put_idx(hw, rxqaddr[le->link],
1991 sky2->rx_put);
1992 buf_write[le->link] = 0;
1993 }
1994
1995 /* Stop after net poll weight */
1996 if (++work_done >= to_do)
1997 goto exit_loop;
1998 break;
1999
2000 #ifdef SKY2_VLAN_TAG_USED
2001 case OP_RXVLAN:
2002 sky2->rx_tag = length;
2003 break;
2004
2005 case OP_RXCHKSVLAN:
2006 sky2->rx_tag = length;
2007 /* fall through */
2008 #endif
2009 case OP_RXCHKS:
2010 skb = sky2->rx_ring[sky2->rx_next].skb;
2011 skb->ip_summed = CHECKSUM_HW;
2012 skb->csum = le16_to_cpu(status);
2013 break;
2014
2015 case OP_TXINDEXLE:
2016 /* TX index reports status for both ports */
2017 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2018 sky2_tx_done(hw->dev[0], status & 0xfff);
2019 if (hw->dev[1])
2020 sky2_tx_done(hw->dev[1],
2021 ((status >> 24) & 0xff)
2022 | (u16)(length & 0xf) << 8);
2023 break;
2024
2025 default:
2026 if (net_ratelimit())
2027 printk(KERN_WARNING PFX
2028 "unknown status opcode 0x%x\n", le->opcode);
2029 goto exit_loop;
2030 }
2031 }
2032
2033 exit_loop:
2034 if (buf_write[0]) {
2035 sky2 = netdev_priv(hw->dev[0]);
2036 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2037 }
2038
2039 if (buf_write[1]) {
2040 sky2 = netdev_priv(hw->dev[1]);
2041 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2042 }
2043
2044 return work_done;
2045 }
2046
2047 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2048 {
2049 struct net_device *dev = hw->dev[port];
2050
2051 if (net_ratelimit())
2052 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2053 dev->name, status);
2054
2055 if (status & Y2_IS_PAR_RD1) {
2056 if (net_ratelimit())
2057 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2058 dev->name);
2059 /* Clear IRQ */
2060 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2061 }
2062
2063 if (status & Y2_IS_PAR_WR1) {
2064 if (net_ratelimit())
2065 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2066 dev->name);
2067
2068 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2069 }
2070
2071 if (status & Y2_IS_PAR_MAC1) {
2072 if (net_ratelimit())
2073 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2074 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2075 }
2076
2077 if (status & Y2_IS_PAR_RX1) {
2078 if (net_ratelimit())
2079 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2080 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2081 }
2082
2083 if (status & Y2_IS_TCP_TXA1) {
2084 if (net_ratelimit())
2085 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2086 dev->name);
2087 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2088 }
2089 }
2090
2091 static void sky2_hw_intr(struct sky2_hw *hw)
2092 {
2093 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2094
2095 if (status & Y2_IS_TIST_OV)
2096 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2097
2098 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2099 u16 pci_err;
2100
2101 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2102 if (net_ratelimit())
2103 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
2104 pci_name(hw->pdev), pci_err);
2105
2106 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2107 sky2_pci_write16(hw, PCI_STATUS,
2108 pci_err | PCI_STATUS_ERROR_BITS);
2109 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2110 }
2111
2112 if (status & Y2_IS_PCI_EXP) {
2113 /* PCI-Express uncorrectable Error occurred */
2114 u32 pex_err;
2115
2116 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2117
2118 if (net_ratelimit())
2119 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
2120 pci_name(hw->pdev), pex_err);
2121
2122 /* clear the interrupt */
2123 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2124 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2125 0xffffffffUL);
2126 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2127
2128 if (pex_err & PEX_FATAL_ERRORS) {
2129 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2130 hwmsk &= ~Y2_IS_PCI_EXP;
2131 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2132 }
2133 }
2134
2135 if (status & Y2_HWE_L1_MASK)
2136 sky2_hw_error(hw, 0, status);
2137 status >>= 8;
2138 if (status & Y2_HWE_L1_MASK)
2139 sky2_hw_error(hw, 1, status);
2140 }
2141
2142 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2143 {
2144 struct net_device *dev = hw->dev[port];
2145 struct sky2_port *sky2 = netdev_priv(dev);
2146 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2147
2148 if (netif_msg_intr(sky2))
2149 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2150 dev->name, status);
2151
2152 if (status & GM_IS_RX_FF_OR) {
2153 ++sky2->net_stats.rx_fifo_errors;
2154 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2155 }
2156
2157 if (status & GM_IS_TX_FF_UR) {
2158 ++sky2->net_stats.tx_fifo_errors;
2159 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2160 }
2161 }
2162
2163 /* This should never happen it is a fatal situation */
2164 static void sky2_descriptor_error(struct sky2_hw *hw, unsigned port,
2165 const char *rxtx, u32 mask)
2166 {
2167 struct net_device *dev = hw->dev[port];
2168 struct sky2_port *sky2 = netdev_priv(dev);
2169 u32 imask;
2170
2171 printk(KERN_ERR PFX "%s: %s descriptor error (hardware problem)\n",
2172 dev ? dev->name : "<not registered>", rxtx);
2173
2174 imask = sky2_read32(hw, B0_IMSK);
2175 imask &= ~mask;
2176 sky2_write32(hw, B0_IMSK, imask);
2177
2178 if (dev) {
2179 spin_lock(&sky2->phy_lock);
2180 sky2_link_down(sky2);
2181 spin_unlock(&sky2->phy_lock);
2182 }
2183 }
2184
2185 /* If idle then force a fake soft NAPI poll once a second
2186 * to work around cases where sharing an edge triggered interrupt.
2187 */
2188 static inline void sky2_idle_start(struct sky2_hw *hw)
2189 {
2190 if (idle_timeout > 0)
2191 mod_timer(&hw->idle_timer,
2192 jiffies + msecs_to_jiffies(idle_timeout));
2193 }
2194
2195 static void sky2_idle(unsigned long arg)
2196 {
2197 struct sky2_hw *hw = (struct sky2_hw *) arg;
2198 struct net_device *dev = hw->dev[0];
2199
2200 if (__netif_rx_schedule_prep(dev))
2201 __netif_rx_schedule(dev);
2202
2203 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2204 }
2205
2206
2207 static int sky2_poll(struct net_device *dev0, int *budget)
2208 {
2209 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2210 int work_limit = min(dev0->quota, *budget);
2211 int work_done = 0;
2212 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2213
2214 if (status & Y2_IS_HW_ERR)
2215 sky2_hw_intr(hw);
2216
2217 if (status & Y2_IS_IRQ_PHY1)
2218 sky2_phy_intr(hw, 0);
2219
2220 if (status & Y2_IS_IRQ_PHY2)
2221 sky2_phy_intr(hw, 1);
2222
2223 if (status & Y2_IS_IRQ_MAC1)
2224 sky2_mac_intr(hw, 0);
2225
2226 if (status & Y2_IS_IRQ_MAC2)
2227 sky2_mac_intr(hw, 1);
2228
2229 if (status & Y2_IS_CHK_RX1)
2230 sky2_descriptor_error(hw, 0, "receive", Y2_IS_CHK_RX1);
2231
2232 if (status & Y2_IS_CHK_RX2)
2233 sky2_descriptor_error(hw, 1, "receive", Y2_IS_CHK_RX2);
2234
2235 if (status & Y2_IS_CHK_TXA1)
2236 sky2_descriptor_error(hw, 0, "transmit", Y2_IS_CHK_TXA1);
2237
2238 if (status & Y2_IS_CHK_TXA2)
2239 sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2);
2240
2241 work_done = sky2_status_intr(hw, work_limit);
2242 *budget -= work_done;
2243 dev0->quota -= work_done;
2244
2245 if (status & Y2_IS_STAT_BMU)
2246 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2247
2248 if (sky2_more_work(hw))
2249 return 1;
2250
2251 netif_rx_complete(dev0);
2252
2253 sky2_read32(hw, B0_Y2_SP_LISR);
2254 return 0;
2255 }
2256
2257 static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
2258 {
2259 struct sky2_hw *hw = dev_id;
2260 struct net_device *dev0 = hw->dev[0];
2261 u32 status;
2262
2263 /* Reading this mask interrupts as side effect */
2264 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2265 if (status == 0 || status == ~0)
2266 return IRQ_NONE;
2267
2268 prefetch(&hw->st_le[hw->st_idx]);
2269 if (likely(__netif_rx_schedule_prep(dev0)))
2270 __netif_rx_schedule(dev0);
2271
2272 return IRQ_HANDLED;
2273 }
2274
2275 #ifdef CONFIG_NET_POLL_CONTROLLER
2276 static void sky2_netpoll(struct net_device *dev)
2277 {
2278 struct sky2_port *sky2 = netdev_priv(dev);
2279 struct net_device *dev0 = sky2->hw->dev[0];
2280
2281 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2282 __netif_rx_schedule(dev0);
2283 }
2284 #endif
2285
2286 /* Chip internal frequency for clock calculations */
2287 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2288 {
2289 switch (hw->chip_id) {
2290 case CHIP_ID_YUKON_EC:
2291 case CHIP_ID_YUKON_EC_U:
2292 return 125; /* 125 Mhz */
2293 case CHIP_ID_YUKON_FE:
2294 return 100; /* 100 Mhz */
2295 default: /* YUKON_XL */
2296 return 156; /* 156 Mhz */
2297 }
2298 }
2299
2300 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2301 {
2302 return sky2_mhz(hw) * us;
2303 }
2304
2305 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2306 {
2307 return clk / sky2_mhz(hw);
2308 }
2309
2310
2311 static int sky2_reset(struct sky2_hw *hw)
2312 {
2313 u16 status;
2314 u8 t8, pmd_type;
2315 int i;
2316
2317 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2318
2319 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2320 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2321 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
2322 pci_name(hw->pdev), hw->chip_id);
2323 return -EOPNOTSUPP;
2324 }
2325
2326 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2327
2328 /* This rev is really old, and requires untested workarounds */
2329 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2330 printk(KERN_ERR PFX "%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2331 pci_name(hw->pdev), yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2332 hw->chip_id, hw->chip_rev);
2333 return -EOPNOTSUPP;
2334 }
2335
2336 /* disable ASF */
2337 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
2338 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2339 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2340 }
2341
2342 /* do a SW reset */
2343 sky2_write8(hw, B0_CTST, CS_RST_SET);
2344 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2345
2346 /* clear PCI errors, if any */
2347 status = sky2_pci_read16(hw, PCI_STATUS);
2348
2349 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2350 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2351
2352
2353 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2354
2355 /* clear any PEX errors */
2356 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2357 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2358
2359
2360 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2361 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2362
2363 hw->ports = 1;
2364 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2365 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2366 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2367 ++hw->ports;
2368 }
2369
2370 sky2_set_power_state(hw, PCI_D0);
2371
2372 for (i = 0; i < hw->ports; i++) {
2373 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2374 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2375 }
2376
2377 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2378
2379 /* Clear I2C IRQ noise */
2380 sky2_write32(hw, B2_I2C_IRQ, 1);
2381
2382 /* turn off hardware timer (unused) */
2383 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2384 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2385
2386 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2387
2388 /* Turn off descriptor polling */
2389 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2390
2391 /* Turn off receive timestamp */
2392 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2393 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2394
2395 /* enable the Tx Arbiters */
2396 for (i = 0; i < hw->ports; i++)
2397 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2398
2399 /* Initialize ram interface */
2400 for (i = 0; i < hw->ports; i++) {
2401 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2402
2403 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2404 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2405 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2406 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2407 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2408 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2409 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2410 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2411 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2412 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2413 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2414 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2415 }
2416
2417 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2418
2419 for (i = 0; i < hw->ports; i++)
2420 sky2_phy_reset(hw, i);
2421
2422 memset(hw->st_le, 0, STATUS_LE_BYTES);
2423 hw->st_idx = 0;
2424
2425 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2426 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2427
2428 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2429 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2430
2431 /* Set the list last index */
2432 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2433
2434 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2435 sky2_write8(hw, STAT_FIFO_WM, 16);
2436
2437 /* set Status-FIFO ISR watermark */
2438 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2439 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2440 else
2441 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2442
2443 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2444 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2445 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2446
2447 /* enable status unit */
2448 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2449
2450 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2451 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2452 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2453
2454 return 0;
2455 }
2456
2457 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2458 {
2459 u32 modes;
2460 if (hw->copper) {
2461 modes = SUPPORTED_10baseT_Half
2462 | SUPPORTED_10baseT_Full
2463 | SUPPORTED_100baseT_Half
2464 | SUPPORTED_100baseT_Full
2465 | SUPPORTED_Autoneg | SUPPORTED_TP;
2466
2467 if (hw->chip_id != CHIP_ID_YUKON_FE)
2468 modes |= SUPPORTED_1000baseT_Half
2469 | SUPPORTED_1000baseT_Full;
2470 } else
2471 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2472 | SUPPORTED_Autoneg;
2473 return modes;
2474 }
2475
2476 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2477 {
2478 struct sky2_port *sky2 = netdev_priv(dev);
2479 struct sky2_hw *hw = sky2->hw;
2480
2481 ecmd->transceiver = XCVR_INTERNAL;
2482 ecmd->supported = sky2_supported_modes(hw);
2483 ecmd->phy_address = PHY_ADDR_MARV;
2484 if (hw->copper) {
2485 ecmd->supported = SUPPORTED_10baseT_Half
2486 | SUPPORTED_10baseT_Full
2487 | SUPPORTED_100baseT_Half
2488 | SUPPORTED_100baseT_Full
2489 | SUPPORTED_1000baseT_Half
2490 | SUPPORTED_1000baseT_Full
2491 | SUPPORTED_Autoneg | SUPPORTED_TP;
2492 ecmd->port = PORT_TP;
2493 } else
2494 ecmd->port = PORT_FIBRE;
2495
2496 ecmd->advertising = sky2->advertising;
2497 ecmd->autoneg = sky2->autoneg;
2498 ecmd->speed = sky2->speed;
2499 ecmd->duplex = sky2->duplex;
2500 return 0;
2501 }
2502
2503 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2504 {
2505 struct sky2_port *sky2 = netdev_priv(dev);
2506 const struct sky2_hw *hw = sky2->hw;
2507 u32 supported = sky2_supported_modes(hw);
2508
2509 if (ecmd->autoneg == AUTONEG_ENABLE) {
2510 ecmd->advertising = supported;
2511 sky2->duplex = -1;
2512 sky2->speed = -1;
2513 } else {
2514 u32 setting;
2515
2516 switch (ecmd->speed) {
2517 case SPEED_1000:
2518 if (ecmd->duplex == DUPLEX_FULL)
2519 setting = SUPPORTED_1000baseT_Full;
2520 else if (ecmd->duplex == DUPLEX_HALF)
2521 setting = SUPPORTED_1000baseT_Half;
2522 else
2523 return -EINVAL;
2524 break;
2525 case SPEED_100:
2526 if (ecmd->duplex == DUPLEX_FULL)
2527 setting = SUPPORTED_100baseT_Full;
2528 else if (ecmd->duplex == DUPLEX_HALF)
2529 setting = SUPPORTED_100baseT_Half;
2530 else
2531 return -EINVAL;
2532 break;
2533
2534 case SPEED_10:
2535 if (ecmd->duplex == DUPLEX_FULL)
2536 setting = SUPPORTED_10baseT_Full;
2537 else if (ecmd->duplex == DUPLEX_HALF)
2538 setting = SUPPORTED_10baseT_Half;
2539 else
2540 return -EINVAL;
2541 break;
2542 default:
2543 return -EINVAL;
2544 }
2545
2546 if ((setting & supported) == 0)
2547 return -EINVAL;
2548
2549 sky2->speed = ecmd->speed;
2550 sky2->duplex = ecmd->duplex;
2551 }
2552
2553 sky2->autoneg = ecmd->autoneg;
2554 sky2->advertising = ecmd->advertising;
2555
2556 if (netif_running(dev))
2557 sky2_phy_reinit(sky2);
2558
2559 return 0;
2560 }
2561
2562 static void sky2_get_drvinfo(struct net_device *dev,
2563 struct ethtool_drvinfo *info)
2564 {
2565 struct sky2_port *sky2 = netdev_priv(dev);
2566
2567 strcpy(info->driver, DRV_NAME);
2568 strcpy(info->version, DRV_VERSION);
2569 strcpy(info->fw_version, "N/A");
2570 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2571 }
2572
2573 static const struct sky2_stat {
2574 char name[ETH_GSTRING_LEN];
2575 u16 offset;
2576 } sky2_stats[] = {
2577 { "tx_bytes", GM_TXO_OK_HI },
2578 { "rx_bytes", GM_RXO_OK_HI },
2579 { "tx_broadcast", GM_TXF_BC_OK },
2580 { "rx_broadcast", GM_RXF_BC_OK },
2581 { "tx_multicast", GM_TXF_MC_OK },
2582 { "rx_multicast", GM_RXF_MC_OK },
2583 { "tx_unicast", GM_TXF_UC_OK },
2584 { "rx_unicast", GM_RXF_UC_OK },
2585 { "tx_mac_pause", GM_TXF_MPAUSE },
2586 { "rx_mac_pause", GM_RXF_MPAUSE },
2587 { "collisions", GM_TXF_COL },
2588 { "late_collision",GM_TXF_LAT_COL },
2589 { "aborted", GM_TXF_ABO_COL },
2590 { "single_collisions", GM_TXF_SNG_COL },
2591 { "multi_collisions", GM_TXF_MUL_COL },
2592
2593 { "rx_short", GM_RXF_SHT },
2594 { "rx_runt", GM_RXE_FRAG },
2595 { "rx_64_byte_packets", GM_RXF_64B },
2596 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2597 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2598 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2599 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2600 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2601 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2602 { "rx_too_long", GM_RXF_LNG_ERR },
2603 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2604 { "rx_jabber", GM_RXF_JAB_PKT },
2605 { "rx_fcs_error", GM_RXF_FCS_ERR },
2606
2607 { "tx_64_byte_packets", GM_TXF_64B },
2608 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2609 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2610 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2611 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2612 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2613 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2614 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2615 };
2616
2617 static u32 sky2_get_rx_csum(struct net_device *dev)
2618 {
2619 struct sky2_port *sky2 = netdev_priv(dev);
2620
2621 return sky2->rx_csum;
2622 }
2623
2624 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2625 {
2626 struct sky2_port *sky2 = netdev_priv(dev);
2627
2628 sky2->rx_csum = data;
2629
2630 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2631 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2632
2633 return 0;
2634 }
2635
2636 static u32 sky2_get_msglevel(struct net_device *netdev)
2637 {
2638 struct sky2_port *sky2 = netdev_priv(netdev);
2639 return sky2->msg_enable;
2640 }
2641
2642 static int sky2_nway_reset(struct net_device *dev)
2643 {
2644 struct sky2_port *sky2 = netdev_priv(dev);
2645
2646 if (sky2->autoneg != AUTONEG_ENABLE)
2647 return -EINVAL;
2648
2649 sky2_phy_reinit(sky2);
2650
2651 return 0;
2652 }
2653
2654 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2655 {
2656 struct sky2_hw *hw = sky2->hw;
2657 unsigned port = sky2->port;
2658 int i;
2659
2660 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2661 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2662 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2663 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2664
2665 for (i = 2; i < count; i++)
2666 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2667 }
2668
2669 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2670 {
2671 struct sky2_port *sky2 = netdev_priv(netdev);
2672 sky2->msg_enable = value;
2673 }
2674
2675 static int sky2_get_stats_count(struct net_device *dev)
2676 {
2677 return ARRAY_SIZE(sky2_stats);
2678 }
2679
2680 static void sky2_get_ethtool_stats(struct net_device *dev,
2681 struct ethtool_stats *stats, u64 * data)
2682 {
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684
2685 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2686 }
2687
2688 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2689 {
2690 int i;
2691
2692 switch (stringset) {
2693 case ETH_SS_STATS:
2694 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2695 memcpy(data + i * ETH_GSTRING_LEN,
2696 sky2_stats[i].name, ETH_GSTRING_LEN);
2697 break;
2698 }
2699 }
2700
2701 /* Use hardware MIB variables for critical path statistics and
2702 * transmit feedback not reported at interrupt.
2703 * Other errors are accounted for in interrupt handler.
2704 */
2705 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2706 {
2707 struct sky2_port *sky2 = netdev_priv(dev);
2708 u64 data[13];
2709
2710 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2711
2712 sky2->net_stats.tx_bytes = data[0];
2713 sky2->net_stats.rx_bytes = data[1];
2714 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2715 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2716 sky2->net_stats.multicast = data[3] + data[5];
2717 sky2->net_stats.collisions = data[10];
2718 sky2->net_stats.tx_aborted_errors = data[12];
2719
2720 return &sky2->net_stats;
2721 }
2722
2723 static int sky2_set_mac_address(struct net_device *dev, void *p)
2724 {
2725 struct sky2_port *sky2 = netdev_priv(dev);
2726 struct sky2_hw *hw = sky2->hw;
2727 unsigned port = sky2->port;
2728 const struct sockaddr *addr = p;
2729
2730 if (!is_valid_ether_addr(addr->sa_data))
2731 return -EADDRNOTAVAIL;
2732
2733 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2734 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
2735 dev->dev_addr, ETH_ALEN);
2736 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
2737 dev->dev_addr, ETH_ALEN);
2738
2739 /* virtual address for data */
2740 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
2741
2742 /* physical address: used for pause frames */
2743 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
2744
2745 return 0;
2746 }
2747
2748 static void sky2_set_multicast(struct net_device *dev)
2749 {
2750 struct sky2_port *sky2 = netdev_priv(dev);
2751 struct sky2_hw *hw = sky2->hw;
2752 unsigned port = sky2->port;
2753 struct dev_mc_list *list = dev->mc_list;
2754 u16 reg;
2755 u8 filter[8];
2756
2757 memset(filter, 0, sizeof(filter));
2758
2759 reg = gma_read16(hw, port, GM_RX_CTRL);
2760 reg |= GM_RXCR_UCF_ENA;
2761
2762 if (dev->flags & IFF_PROMISC) /* promiscuous */
2763 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2764 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2765 memset(filter, 0xff, sizeof(filter));
2766 else if (dev->mc_count == 0) /* no multicast */
2767 reg &= ~GM_RXCR_MCF_ENA;
2768 else {
2769 int i;
2770 reg |= GM_RXCR_MCF_ENA;
2771
2772 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2773 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2774 filter[bit / 8] |= 1 << (bit % 8);
2775 }
2776 }
2777
2778 gma_write16(hw, port, GM_MC_ADDR_H1,
2779 (u16) filter[0] | ((u16) filter[1] << 8));
2780 gma_write16(hw, port, GM_MC_ADDR_H2,
2781 (u16) filter[2] | ((u16) filter[3] << 8));
2782 gma_write16(hw, port, GM_MC_ADDR_H3,
2783 (u16) filter[4] | ((u16) filter[5] << 8));
2784 gma_write16(hw, port, GM_MC_ADDR_H4,
2785 (u16) filter[6] | ((u16) filter[7] << 8));
2786
2787 gma_write16(hw, port, GM_RX_CTRL, reg);
2788 }
2789
2790 /* Can have one global because blinking is controlled by
2791 * ethtool and that is always under RTNL mutex
2792 */
2793 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2794 {
2795 u16 pg;
2796
2797 switch (hw->chip_id) {
2798 case CHIP_ID_YUKON_XL:
2799 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2800 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2801 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2802 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2803 PHY_M_LEDC_INIT_CTRL(7) |
2804 PHY_M_LEDC_STA1_CTRL(7) |
2805 PHY_M_LEDC_STA0_CTRL(7))
2806 : 0);
2807
2808 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2809 break;
2810
2811 default:
2812 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2813 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2814 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2815 PHY_M_LED_MO_10(MO_LED_ON) |
2816 PHY_M_LED_MO_100(MO_LED_ON) |
2817 PHY_M_LED_MO_1000(MO_LED_ON) |
2818 PHY_M_LED_MO_RX(MO_LED_ON)
2819 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2820 PHY_M_LED_MO_10(MO_LED_OFF) |
2821 PHY_M_LED_MO_100(MO_LED_OFF) |
2822 PHY_M_LED_MO_1000(MO_LED_OFF) |
2823 PHY_M_LED_MO_RX(MO_LED_OFF));
2824
2825 }
2826 }
2827
2828 /* blink LED's for finding board */
2829 static int sky2_phys_id(struct net_device *dev, u32 data)
2830 {
2831 struct sky2_port *sky2 = netdev_priv(dev);
2832 struct sky2_hw *hw = sky2->hw;
2833 unsigned port = sky2->port;
2834 u16 ledctrl, ledover = 0;
2835 long ms;
2836 int interrupted;
2837 int onoff = 1;
2838
2839 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2840 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2841 else
2842 ms = data * 1000;
2843
2844 /* save initial values */
2845 spin_lock_bh(&sky2->phy_lock);
2846 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2847 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2848 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2849 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2850 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2851 } else {
2852 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2853 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2854 }
2855
2856 interrupted = 0;
2857 while (!interrupted && ms > 0) {
2858 sky2_led(hw, port, onoff);
2859 onoff = !onoff;
2860
2861 spin_unlock_bh(&sky2->phy_lock);
2862 interrupted = msleep_interruptible(250);
2863 spin_lock_bh(&sky2->phy_lock);
2864
2865 ms -= 250;
2866 }
2867
2868 /* resume regularly scheduled programming */
2869 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2870 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2871 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2872 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2873 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2874 } else {
2875 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2876 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2877 }
2878 spin_unlock_bh(&sky2->phy_lock);
2879
2880 return 0;
2881 }
2882
2883 static void sky2_get_pauseparam(struct net_device *dev,
2884 struct ethtool_pauseparam *ecmd)
2885 {
2886 struct sky2_port *sky2 = netdev_priv(dev);
2887
2888 ecmd->tx_pause = sky2->tx_pause;
2889 ecmd->rx_pause = sky2->rx_pause;
2890 ecmd->autoneg = sky2->autoneg;
2891 }
2892
2893 static int sky2_set_pauseparam(struct net_device *dev,
2894 struct ethtool_pauseparam *ecmd)
2895 {
2896 struct sky2_port *sky2 = netdev_priv(dev);
2897 int err = 0;
2898
2899 sky2->autoneg = ecmd->autoneg;
2900 sky2->tx_pause = ecmd->tx_pause != 0;
2901 sky2->rx_pause = ecmd->rx_pause != 0;
2902
2903 sky2_phy_reinit(sky2);
2904
2905 return err;
2906 }
2907
2908 static int sky2_get_coalesce(struct net_device *dev,
2909 struct ethtool_coalesce *ecmd)
2910 {
2911 struct sky2_port *sky2 = netdev_priv(dev);
2912 struct sky2_hw *hw = sky2->hw;
2913
2914 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
2915 ecmd->tx_coalesce_usecs = 0;
2916 else {
2917 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
2918 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
2919 }
2920 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
2921
2922 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
2923 ecmd->rx_coalesce_usecs = 0;
2924 else {
2925 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
2926 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
2927 }
2928 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
2929
2930 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
2931 ecmd->rx_coalesce_usecs_irq = 0;
2932 else {
2933 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
2934 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
2935 }
2936
2937 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
2938
2939 return 0;
2940 }
2941
2942 /* Note: this affect both ports */
2943 static int sky2_set_coalesce(struct net_device *dev,
2944 struct ethtool_coalesce *ecmd)
2945 {
2946 struct sky2_port *sky2 = netdev_priv(dev);
2947 struct sky2_hw *hw = sky2->hw;
2948 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
2949
2950 if (ecmd->tx_coalesce_usecs > tmax ||
2951 ecmd->rx_coalesce_usecs > tmax ||
2952 ecmd->rx_coalesce_usecs_irq > tmax)
2953 return -EINVAL;
2954
2955 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
2956 return -EINVAL;
2957 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
2958 return -EINVAL;
2959 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
2960 return -EINVAL;
2961
2962 if (ecmd->tx_coalesce_usecs == 0)
2963 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
2964 else {
2965 sky2_write32(hw, STAT_TX_TIMER_INI,
2966 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
2967 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2968 }
2969 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
2970
2971 if (ecmd->rx_coalesce_usecs == 0)
2972 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
2973 else {
2974 sky2_write32(hw, STAT_LEV_TIMER_INI,
2975 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
2976 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2977 }
2978 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
2979
2980 if (ecmd->rx_coalesce_usecs_irq == 0)
2981 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
2982 else {
2983 sky2_write32(hw, STAT_ISR_TIMER_INI,
2984 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
2985 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2986 }
2987 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
2988 return 0;
2989 }
2990
2991 static void sky2_get_ringparam(struct net_device *dev,
2992 struct ethtool_ringparam *ering)
2993 {
2994 struct sky2_port *sky2 = netdev_priv(dev);
2995
2996 ering->rx_max_pending = RX_MAX_PENDING;
2997 ering->rx_mini_max_pending = 0;
2998 ering->rx_jumbo_max_pending = 0;
2999 ering->tx_max_pending = TX_RING_SIZE - 1;
3000
3001 ering->rx_pending = sky2->rx_pending;
3002 ering->rx_mini_pending = 0;
3003 ering->rx_jumbo_pending = 0;
3004 ering->tx_pending = sky2->tx_pending;
3005 }
3006
3007 static int sky2_set_ringparam(struct net_device *dev,
3008 struct ethtool_ringparam *ering)
3009 {
3010 struct sky2_port *sky2 = netdev_priv(dev);
3011 int err = 0;
3012
3013 if (ering->rx_pending > RX_MAX_PENDING ||
3014 ering->rx_pending < 8 ||
3015 ering->tx_pending < MAX_SKB_TX_LE ||
3016 ering->tx_pending > TX_RING_SIZE - 1)
3017 return -EINVAL;
3018
3019 if (netif_running(dev))
3020 sky2_down(dev);
3021
3022 sky2->rx_pending = ering->rx_pending;
3023 sky2->tx_pending = ering->tx_pending;
3024
3025 if (netif_running(dev)) {
3026 err = sky2_up(dev);
3027 if (err)
3028 dev_close(dev);
3029 else
3030 sky2_set_multicast(dev);
3031 }
3032
3033 return err;
3034 }
3035
3036 static int sky2_get_regs_len(struct net_device *dev)
3037 {
3038 return 0x4000;
3039 }
3040
3041 /*
3042 * Returns copy of control register region
3043 * Note: access to the RAM address register set will cause timeouts.
3044 */
3045 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3046 void *p)
3047 {
3048 const struct sky2_port *sky2 = netdev_priv(dev);
3049 const void __iomem *io = sky2->hw->regs;
3050
3051 BUG_ON(regs->len < B3_RI_WTO_R1);
3052 regs->version = 1;
3053 memset(p, 0, regs->len);
3054
3055 memcpy_fromio(p, io, B3_RAM_ADDR);
3056
3057 memcpy_fromio(p + B3_RI_WTO_R1,
3058 io + B3_RI_WTO_R1,
3059 regs->len - B3_RI_WTO_R1);
3060 }
3061
3062 static struct ethtool_ops sky2_ethtool_ops = {
3063 .get_settings = sky2_get_settings,
3064 .set_settings = sky2_set_settings,
3065 .get_drvinfo = sky2_get_drvinfo,
3066 .get_msglevel = sky2_get_msglevel,
3067 .set_msglevel = sky2_set_msglevel,
3068 .nway_reset = sky2_nway_reset,
3069 .get_regs_len = sky2_get_regs_len,
3070 .get_regs = sky2_get_regs,
3071 .get_link = ethtool_op_get_link,
3072 .get_sg = ethtool_op_get_sg,
3073 .set_sg = ethtool_op_set_sg,
3074 .get_tx_csum = ethtool_op_get_tx_csum,
3075 .set_tx_csum = ethtool_op_set_tx_csum,
3076 .get_tso = ethtool_op_get_tso,
3077 .set_tso = ethtool_op_set_tso,
3078 .get_rx_csum = sky2_get_rx_csum,
3079 .set_rx_csum = sky2_set_rx_csum,
3080 .get_strings = sky2_get_strings,
3081 .get_coalesce = sky2_get_coalesce,
3082 .set_coalesce = sky2_set_coalesce,
3083 .get_ringparam = sky2_get_ringparam,
3084 .set_ringparam = sky2_set_ringparam,
3085 .get_pauseparam = sky2_get_pauseparam,
3086 .set_pauseparam = sky2_set_pauseparam,
3087 .phys_id = sky2_phys_id,
3088 .get_stats_count = sky2_get_stats_count,
3089 .get_ethtool_stats = sky2_get_ethtool_stats,
3090 .get_perm_addr = ethtool_op_get_perm_addr,
3091 };
3092
3093 /* Initialize network device */
3094 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3095 unsigned port, int highmem)
3096 {
3097 struct sky2_port *sky2;
3098 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3099
3100 if (!dev) {
3101 printk(KERN_ERR "sky2 etherdev alloc failed");
3102 return NULL;
3103 }
3104
3105 SET_MODULE_OWNER(dev);
3106 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3107 dev->irq = hw->pdev->irq;
3108 dev->open = sky2_up;
3109 dev->stop = sky2_down;
3110 dev->do_ioctl = sky2_ioctl;
3111 dev->hard_start_xmit = sky2_xmit_frame;
3112 dev->get_stats = sky2_get_stats;
3113 dev->set_multicast_list = sky2_set_multicast;
3114 dev->set_mac_address = sky2_set_mac_address;
3115 dev->change_mtu = sky2_change_mtu;
3116 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3117 dev->tx_timeout = sky2_tx_timeout;
3118 dev->watchdog_timeo = TX_WATCHDOG;
3119 if (port == 0)
3120 dev->poll = sky2_poll;
3121 dev->weight = NAPI_WEIGHT;
3122 #ifdef CONFIG_NET_POLL_CONTROLLER
3123 dev->poll_controller = sky2_netpoll;
3124 #endif
3125
3126 sky2 = netdev_priv(dev);
3127 sky2->netdev = dev;
3128 sky2->hw = hw;
3129 sky2->msg_enable = netif_msg_init(debug, default_msg);
3130
3131 spin_lock_init(&sky2->tx_lock);
3132 /* Auto speed and flow control */
3133 sky2->autoneg = AUTONEG_ENABLE;
3134 sky2->tx_pause = 1;
3135 sky2->rx_pause = 1;
3136 sky2->duplex = -1;
3137 sky2->speed = -1;
3138 sky2->advertising = sky2_supported_modes(hw);
3139 sky2->rx_csum = 1;
3140
3141 spin_lock_init(&sky2->phy_lock);
3142 sky2->tx_pending = TX_DEF_PENDING;
3143 sky2->rx_pending = RX_DEF_PENDING;
3144 sky2->rx_bufsize = sky2_buf_size(ETH_DATA_LEN);
3145
3146 hw->dev[port] = dev;
3147
3148 sky2->port = port;
3149
3150 dev->features |= NETIF_F_LLTX;
3151 if (hw->chip_id != CHIP_ID_YUKON_EC_U)
3152 dev->features |= NETIF_F_TSO;
3153 if (highmem)
3154 dev->features |= NETIF_F_HIGHDMA;
3155 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3156
3157 #ifdef SKY2_VLAN_TAG_USED
3158 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3159 dev->vlan_rx_register = sky2_vlan_rx_register;
3160 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3161 #endif
3162
3163 /* read the mac address */
3164 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3165 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3166
3167 /* device is off until link detection */
3168 netif_carrier_off(dev);
3169 netif_stop_queue(dev);
3170
3171 return dev;
3172 }
3173
3174 static void __devinit sky2_show_addr(struct net_device *dev)
3175 {
3176 const struct sky2_port *sky2 = netdev_priv(dev);
3177
3178 if (netif_msg_probe(sky2))
3179 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3180 dev->name,
3181 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3182 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3183 }
3184
3185 /* Handle software interrupt used during MSI test */
3186 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id,
3187 struct pt_regs *regs)
3188 {
3189 struct sky2_hw *hw = dev_id;
3190 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3191
3192 if (status == 0)
3193 return IRQ_NONE;
3194
3195 if (status & Y2_IS_IRQ_SW) {
3196 hw->msi_detected = 1;
3197 wake_up(&hw->msi_wait);
3198 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3199 }
3200 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3201
3202 return IRQ_HANDLED;
3203 }
3204
3205 /* Test interrupt path by forcing a a software IRQ */
3206 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3207 {
3208 struct pci_dev *pdev = hw->pdev;
3209 int err;
3210
3211 init_waitqueue_head (&hw->msi_wait);
3212
3213 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3214
3215 err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw);
3216 if (err) {
3217 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3218 pci_name(pdev), pdev->irq);
3219 return err;
3220 }
3221
3222 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3223 sky2_read8(hw, B0_CTST);
3224
3225 wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10);
3226
3227 if (!hw->msi_detected) {
3228 /* MSI test failed, go back to INTx mode */
3229 printk(KERN_INFO PFX "%s: No interrupt generated using MSI, "
3230 "switching to INTx mode.\n",
3231 pci_name(pdev));
3232
3233 err = -EOPNOTSUPP;
3234 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3235 }
3236
3237 sky2_write32(hw, B0_IMSK, 0);
3238 sky2_read32(hw, B0_IMSK);
3239
3240 free_irq(pdev->irq, hw);
3241
3242 return err;
3243 }
3244
3245 static int __devinit sky2_probe(struct pci_dev *pdev,
3246 const struct pci_device_id *ent)
3247 {
3248 struct net_device *dev, *dev1 = NULL;
3249 struct sky2_hw *hw;
3250 int err, pm_cap, using_dac = 0;
3251
3252 err = pci_enable_device(pdev);
3253 if (err) {
3254 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
3255 pci_name(pdev));
3256 goto err_out;
3257 }
3258
3259 err = pci_request_regions(pdev, DRV_NAME);
3260 if (err) {
3261 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
3262 pci_name(pdev));
3263 goto err_out;
3264 }
3265
3266 pci_set_master(pdev);
3267
3268 /* Find power-management capability. */
3269 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3270 if (pm_cap == 0) {
3271 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
3272 "aborting.\n");
3273 err = -EIO;
3274 goto err_out_free_regions;
3275 }
3276
3277 if (sizeof(dma_addr_t) > sizeof(u32) &&
3278 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3279 using_dac = 1;
3280 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3281 if (err < 0) {
3282 printk(KERN_ERR PFX "%s unable to obtain 64 bit DMA "
3283 "for consistent allocations\n", pci_name(pdev));
3284 goto err_out_free_regions;
3285 }
3286
3287 } else {
3288 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3289 if (err) {
3290 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
3291 pci_name(pdev));
3292 goto err_out_free_regions;
3293 }
3294 }
3295
3296 err = -ENOMEM;
3297 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3298 if (!hw) {
3299 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
3300 pci_name(pdev));
3301 goto err_out_free_regions;
3302 }
3303
3304 hw->pdev = pdev;
3305
3306 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3307 if (!hw->regs) {
3308 printk(KERN_ERR PFX "%s: cannot map device registers\n",
3309 pci_name(pdev));
3310 goto err_out_free_hw;
3311 }
3312 hw->pm_cap = pm_cap;
3313
3314 #ifdef __BIG_ENDIAN
3315 /* byte swap descriptors in hardware */
3316 {
3317 u32 reg;
3318
3319 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3320 reg |= PCI_REV_DESC;
3321 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3322 }
3323 #endif
3324
3325 /* ring for status responses */
3326 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3327 &hw->st_dma);
3328 if (!hw->st_le)
3329 goto err_out_iounmap;
3330
3331 err = sky2_reset(hw);
3332 if (err)
3333 goto err_out_iounmap;
3334
3335 printk(KERN_INFO PFX "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3336 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3337 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3338 hw->chip_id, hw->chip_rev);
3339
3340 dev = sky2_init_netdev(hw, 0, using_dac);
3341 if (!dev)
3342 goto err_out_free_pci;
3343
3344 err = register_netdev(dev);
3345 if (err) {
3346 printk(KERN_ERR PFX "%s: cannot register net device\n",
3347 pci_name(pdev));
3348 goto err_out_free_netdev;
3349 }
3350
3351 sky2_show_addr(dev);
3352
3353 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
3354 if (register_netdev(dev1) == 0)
3355 sky2_show_addr(dev1);
3356 else {
3357 /* Failure to register second port need not be fatal */
3358 printk(KERN_WARNING PFX
3359 "register of second port failed\n");
3360 hw->dev[1] = NULL;
3361 free_netdev(dev1);
3362 }
3363 }
3364
3365 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3366 err = sky2_test_msi(hw);
3367 if (err == -EOPNOTSUPP)
3368 pci_disable_msi(pdev);
3369 else if (err)
3370 goto err_out_unregister;
3371 }
3372
3373 err = request_irq(pdev->irq, sky2_intr, IRQF_SHARED, DRV_NAME, hw);
3374 if (err) {
3375 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
3376 pci_name(pdev), pdev->irq);
3377 goto err_out_unregister;
3378 }
3379
3380 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3381
3382 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3383 sky2_idle_start(hw);
3384
3385 pci_set_drvdata(pdev, hw);
3386
3387 return 0;
3388
3389 err_out_unregister:
3390 pci_disable_msi(pdev);
3391 if (dev1) {
3392 unregister_netdev(dev1);
3393 free_netdev(dev1);
3394 }
3395 unregister_netdev(dev);
3396 err_out_free_netdev:
3397 free_netdev(dev);
3398 err_out_free_pci:
3399 sky2_write8(hw, B0_CTST, CS_RST_SET);
3400 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3401 err_out_iounmap:
3402 iounmap(hw->regs);
3403 err_out_free_hw:
3404 kfree(hw);
3405 err_out_free_regions:
3406 pci_release_regions(pdev);
3407 pci_disable_device(pdev);
3408 err_out:
3409 return err;
3410 }
3411
3412 static void __devexit sky2_remove(struct pci_dev *pdev)
3413 {
3414 struct sky2_hw *hw = pci_get_drvdata(pdev);
3415 struct net_device *dev0, *dev1;
3416
3417 if (!hw)
3418 return;
3419
3420 del_timer_sync(&hw->idle_timer);
3421
3422 sky2_write32(hw, B0_IMSK, 0);
3423 synchronize_irq(hw->pdev->irq);
3424
3425 dev0 = hw->dev[0];
3426 dev1 = hw->dev[1];
3427 if (dev1)
3428 unregister_netdev(dev1);
3429 unregister_netdev(dev0);
3430
3431 sky2_set_power_state(hw, PCI_D3hot);
3432 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3433 sky2_write8(hw, B0_CTST, CS_RST_SET);
3434 sky2_read8(hw, B0_CTST);
3435
3436 free_irq(pdev->irq, hw);
3437 pci_disable_msi(pdev);
3438 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3439 pci_release_regions(pdev);
3440 pci_disable_device(pdev);
3441
3442 if (dev1)
3443 free_netdev(dev1);
3444 free_netdev(dev0);
3445 iounmap(hw->regs);
3446 kfree(hw);
3447
3448 pci_set_drvdata(pdev, NULL);
3449 }
3450
3451 #ifdef CONFIG_PM
3452 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3453 {
3454 struct sky2_hw *hw = pci_get_drvdata(pdev);
3455 int i;
3456 pci_power_t pstate = pci_choose_state(pdev, state);
3457
3458 if (!(pstate == PCI_D3hot || pstate == PCI_D3cold))
3459 return -EINVAL;
3460
3461 del_timer_sync(&hw->idle_timer);
3462 netif_poll_disable(hw->dev[0]);
3463
3464 for (i = 0; i < hw->ports; i++) {
3465 struct net_device *dev = hw->dev[i];
3466
3467 if (netif_running(dev)) {
3468 sky2_down(dev);
3469 netif_device_detach(dev);
3470 }
3471 }
3472
3473 sky2_write32(hw, B0_IMSK, 0);
3474 pci_save_state(pdev);
3475 sky2_set_power_state(hw, pstate);
3476 return 0;
3477 }
3478
3479 static int sky2_resume(struct pci_dev *pdev)
3480 {
3481 struct sky2_hw *hw = pci_get_drvdata(pdev);
3482 int i, err;
3483
3484 pci_restore_state(pdev);
3485 pci_enable_wake(pdev, PCI_D0, 0);
3486 sky2_set_power_state(hw, PCI_D0);
3487
3488 err = sky2_reset(hw);
3489 if (err)
3490 goto out;
3491
3492 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3493
3494 for (i = 0; i < hw->ports; i++) {
3495 struct net_device *dev = hw->dev[i];
3496 if (netif_running(dev)) {
3497 netif_device_attach(dev);
3498
3499 err = sky2_up(dev);
3500 if (err) {
3501 printk(KERN_ERR PFX "%s: could not up: %d\n",
3502 dev->name, err);
3503 dev_close(dev);
3504 goto out;
3505 }
3506 }
3507 }
3508
3509 netif_poll_enable(hw->dev[0]);
3510 sky2_idle_start(hw);
3511 out:
3512 return err;
3513 }
3514 #endif
3515
3516 static struct pci_driver sky2_driver = {
3517 .name = DRV_NAME,
3518 .id_table = sky2_id_table,
3519 .probe = sky2_probe,
3520 .remove = __devexit_p(sky2_remove),
3521 #ifdef CONFIG_PM
3522 .suspend = sky2_suspend,
3523 .resume = sky2_resume,
3524 #endif
3525 };
3526
3527 static int __init sky2_init_module(void)
3528 {
3529 return pci_register_driver(&sky2_driver);
3530 }
3531
3532 static void __exit sky2_cleanup_module(void)
3533 {
3534 pci_unregister_driver(&sky2_driver);
3535 }
3536
3537 module_init(sky2_init_module);
3538 module_exit(sky2_cleanup_module);
3539
3540 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3541 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3542 MODULE_LICENSE("GPL");
3543 MODULE_VERSION(DRV_VERSION);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree