drivers/rtc/rtc-pxa.c

   1 /*
   2  * Real Time Clock interface for XScale PXA27x and PXA3xx
   3  *
   4  * Copyright (C) 2008 Robert Jarzmik
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #include <linux/init.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/module.h>
  25 #include <linux/rtc.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/io.h>
  29 #include <linux/slab.h>
  30
  31 #include <mach/hardware.h>
  32
  33 #define TIMER_FREQ              CLOCK_TICK_RATE
  34 #define RTC_DEF_DIVIDER         (32768 - 1)
  35 #define RTC_DEF_TRIM            0
  36 #define MAXFREQ_PERIODIC        1000
  37
  38 /*
  39  * PXA Registers and bits definitions
  40  */
  41 #define RTSR_PICE       (1 << 15)       /* Periodic interrupt count enable */
  42 #define RTSR_PIALE      (1 << 14)       /* Periodic interrupt Alarm enable */
  43 #define RTSR_PIAL       (1 << 13)       /* Periodic interrupt detected */
  44 #define RTSR_SWALE2     (1 << 11)       /* RTC stopwatch alarm2 enable */
  45 #define RTSR_SWAL2      (1 << 10)       /* RTC stopwatch alarm2 detected */
  46 #define RTSR_SWALE1     (1 << 9)        /* RTC stopwatch alarm1 enable */
  47 #define RTSR_SWAL1      (1 << 8)        /* RTC stopwatch alarm1 detected */
  48 #define RTSR_RDALE2     (1 << 7)        /* RTC alarm2 enable */
  49 #define RTSR_RDAL2      (1 << 6)        /* RTC alarm2 detected */
  50 #define RTSR_RDALE1     (1 << 5)        /* RTC alarm1 enable */
  51 #define RTSR_RDAL1      (1 << 4)        /* RTC alarm1 detected */
  52 #define RTSR_HZE        (1 << 3)        /* HZ interrupt enable */
  53 #define RTSR_ALE        (1 << 2)        /* RTC alarm interrupt enable */
  54 #define RTSR_HZ         (1 << 1)        /* HZ rising-edge detected */
  55 #define RTSR_AL         (1 << 0)        /* RTC alarm detected */
  56 #define RTSR_TRIG_MASK  (RTSR_AL | RTSR_HZ | RTSR_RDAL1 | RTSR_RDAL2\
  57                          | RTSR_SWAL1 | RTSR_SWAL2)
  58 #define RYxR_YEAR_S     9
  59 #define RYxR_YEAR_MASK  (0xfff << RYxR_YEAR_S)
  60 #define RYxR_MONTH_S    5
  61 #define RYxR_MONTH_MASK (0xf << RYxR_MONTH_S)
  62 #define RYxR_DAY_MASK   0x1f
  63 #define RDxR_HOUR_S     12
  64 #define RDxR_HOUR_MASK  (0x1f << RDxR_HOUR_S)
  65 #define RDxR_MIN_S      6
  66 #define RDxR_MIN_MASK   (0x3f << RDxR_MIN_S)
  67 #define RDxR_SEC_MASK   0x3f
  68
  69 #define RTSR            0x08
  70 #define RTTR            0x0c
  71 #define RDCR            0x10
  72 #define RYCR            0x14
  73 #define RDAR1           0x18
  74 #define RYAR1           0x1c
  75 #define RTCPICR         0x34
  76 #define PIAR            0x38
  77
  78 #define rtc_readl(pxa_rtc, reg) \
  79         __raw_readl((pxa_rtc)->base + (reg))
  80 #define rtc_writel(pxa_rtc, reg, value) \
  81         __raw_writel((value), (pxa_rtc)->base + (reg))
  82
  83 struct pxa_rtc {
  84         struct resource *ress;
  85         void __iomem            *base;
  86         int                     irq_1Hz;
  87         int                     irq_Alrm;
  88         struct rtc_device       *rtc;
  89         spinlock_t              lock;           /* Protects this structure */
  90 };
  91
  92 static u32 ryxr_calc(struct rtc_time *tm)
  93 {
  94         return ((tm->tm_year + 1900) << RYxR_YEAR_S)
  95                 | ((tm->tm_mon + 1) << RYxR_MONTH_S)
  96                 | tm->tm_mday;
  97 }
  98
  99 static u32 rdxr_calc(struct rtc_time *tm)
 100 {
 101         return (tm->tm_hour << RDxR_HOUR_S) | (tm->tm_min << RDxR_MIN_S)
 102                 | tm->tm_sec;
 103 }
 104
 105 static void tm_calc(u32 rycr, u32 rdcr, struct rtc_time *tm)
 106 {
 107         tm->tm_year = ((rycr & RYxR_YEAR_MASK) >> RYxR_YEAR_S) - 1900;
 108         tm->tm_mon = (((rycr & RYxR_MONTH_MASK) >> RYxR_MONTH_S)) - 1;
 109         tm->tm_mday = (rycr & RYxR_DAY_MASK);
 110         tm->tm_hour = (rdcr & RDxR_HOUR_MASK) >> RDxR_HOUR_S;
 111         tm->tm_min = (rdcr & RDxR_MIN_MASK) >> RDxR_MIN_S;
 112         tm->tm_sec = rdcr & RDxR_SEC_MASK;
 113 }
 114
 115 static void rtsr_clear_bits(struct pxa_rtc *pxa_rtc, u32 mask)
 116 {
 117         u32 rtsr;
 118
 119         rtsr = rtc_readl(pxa_rtc, RTSR);
 120         rtsr &= ~RTSR_TRIG_MASK;
 121         rtsr &= ~mask;
 122         rtc_writel(pxa_rtc, RTSR, rtsr);
 123 }
 124
 125 static void rtsr_set_bits(struct pxa_rtc *pxa_rtc, u32 mask)
 126 {
 127         u32 rtsr;
 128
 129         rtsr = rtc_readl(pxa_rtc, RTSR);
 130         rtsr &= ~RTSR_TRIG_MASK;
 131         rtsr |= mask;
 132         rtc_writel(pxa_rtc, RTSR, rtsr);
 133 }
 134
 135 static irqreturn_t pxa_rtc_irq(int irq, void *dev_id)
 136 {
 137         struct platform_device *pdev = to_platform_device(dev_id);
 138         struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
 139         u32 rtsr;
 140         unsigned long events = 0;
 141
 142         spin_lock(&pxa_rtc->lock);
 143
 144         /* clear interrupt sources */
 145         rtsr = rtc_readl(pxa_rtc, RTSR);
 146         rtc_writel(pxa_rtc, RTSR, rtsr);
 147
 148         /* temporary disable rtc interrupts */
 149         rtsr_clear_bits(pxa_rtc, RTSR_RDALE1 | RTSR_PIALE | RTSR_HZE);
 150
 151         /* clear alarm interrupt if it has occurred */
 152         if (rtsr & RTSR_RDAL1)
 153                 rtsr &= ~RTSR_RDALE1;
 154
 155         /* update irq data & counter */
 156         if (rtsr & RTSR_RDAL1)
 157                 events |= RTC_AF | RTC_IRQF;
 158         if (rtsr & RTSR_HZ)
 159                 events |= RTC_UF | RTC_IRQF;
 160         if (rtsr & RTSR_PIAL)
 161                 events |= RTC_PF | RTC_IRQF;
 162
 163         rtc_update_irq(pxa_rtc->rtc, 1, events);
 164
 165         /* enable back rtc interrupts */
 166         rtc_writel(pxa_rtc, RTSR, rtsr & ~RTSR_TRIG_MASK);
 167
 168         spin_unlock(&pxa_rtc->lock);
 169         return IRQ_HANDLED;
 170 }
 171
 172 static int pxa_rtc_open(struct device *dev)
 173 {
 174         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 175         int ret;
 176
 177         ret = request_irq(pxa_rtc->irq_1Hz, pxa_rtc_irq, IRQF_DISABLED,
 178                           "rtc 1Hz", dev);
 179         if (ret < 0) {
 180                 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_1Hz,
 181                         ret);
 182                 goto err_irq_1Hz;
 183         }
 184         ret = request_irq(pxa_rtc->irq_Alrm, pxa_rtc_irq, IRQF_DISABLED,
 185                           "rtc Alrm", dev);
 186         if (ret < 0) {
 187                 dev_err(dev, "can't get irq %i, err %d\n", pxa_rtc->irq_Alrm,
 188                         ret);
 189                 goto err_irq_Alrm;
 190         }
 191
 192         return 0;
 193
 194 err_irq_Alrm:
 195         free_irq(pxa_rtc->irq_1Hz, dev);
 196 err_irq_1Hz:
 197         return ret;
 198 }
 199
 200 static void pxa_rtc_release(struct device *dev)
 201 {
 202         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 203
 204         spin_lock_irq(&pxa_rtc->lock);
 205         rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
 206         spin_unlock_irq(&pxa_rtc->lock);
 207
 208         free_irq(pxa_rtc->irq_Alrm, dev);
 209         free_irq(pxa_rtc->irq_1Hz, dev);
 210 }
 211
 212 static int pxa_periodic_irq_set_freq(struct device *dev, int freq)
 213 {
 214         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 215         int period_ms;
 216
 217         if (freq < 1 || freq > MAXFREQ_PERIODIC)
 218                 return -EINVAL;
 219
 220         period_ms = 1000 / freq;
 221         rtc_writel(pxa_rtc, PIAR, period_ms);
 222
 223         return 0;
 224 }
 225
 226 static int pxa_periodic_irq_set_state(struct device *dev, int enabled)
 227 {
 228         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 229
 230         if (enabled)
 231                 rtsr_set_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
 232         else
 233                 rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_PICE);
 234
 235         return 0;
 236 }
 237
 238 static int pxa_alarm_irq_enable(struct device *dev, unsigned int enabled)
 239 {
 240         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 241
 242         spin_lock_irq(&pxa_rtc->lock);
 243
 244         if (enabled)
 245                 rtsr_set_bits(pxa_rtc, RTSR_RDALE1);
 246         else
 247                 rtsr_clear_bits(pxa_rtc, RTSR_RDALE1);
 248
 249         spin_unlock_irq(&pxa_rtc->lock);
 250         return 0;
 251 }
 252
 253 static int pxa_update_irq_enable(struct device *dev, unsigned int enabled)
 254 {
 255         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 256
 257         spin_lock_irq(&pxa_rtc->lock);
 258
 259         if (enabled)
 260                 rtsr_set_bits(pxa_rtc, RTSR_HZE);
 261         else
 262                 rtsr_clear_bits(pxa_rtc, RTSR_HZE);
 263
 264         spin_unlock_irq(&pxa_rtc->lock);
 265         return 0;
 266 }
 267
 268 static int pxa_rtc_read_time(struct device *dev, struct rtc_time *tm)
 269 {
 270         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 271         u32 rycr, rdcr;
 272
 273         rycr = rtc_readl(pxa_rtc, RYCR);
 274         rdcr = rtc_readl(pxa_rtc, RDCR);
 275
 276         tm_calc(rycr, rdcr, tm);
 277         return 0;
 278 }
 279
 280 static int pxa_rtc_set_time(struct device *dev, struct rtc_time *tm)
 281 {
 282         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 283
 284         rtc_writel(pxa_rtc, RYCR, ryxr_calc(tm));
 285         rtc_writel(pxa_rtc, RDCR, rdxr_calc(tm));
 286
 287         return 0;
 288 }
 289
 290 static int pxa_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 291 {
 292         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 293         u32 rtsr, ryar, rdar;
 294
 295         ryar = rtc_readl(pxa_rtc, RYAR1);
 296         rdar = rtc_readl(pxa_rtc, RDAR1);
 297         tm_calc(ryar, rdar, &alrm->time);
 298
 299         rtsr = rtc_readl(pxa_rtc, RTSR);
 300         alrm->enabled = (rtsr & RTSR_RDALE1) ? 1 : 0;
 301         alrm->pending = (rtsr & RTSR_RDAL1) ? 1 : 0;
 302         return 0;
 303 }
 304
 305 static int pxa_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
 306 {
 307         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 308         u32 rtsr;
 309
 310         spin_lock_irq(&pxa_rtc->lock);
 311
 312         rtc_writel(pxa_rtc, RYAR1, ryxr_calc(&alrm->time));
 313         rtc_writel(pxa_rtc, RDAR1, rdxr_calc(&alrm->time));
 314
 315         rtsr = rtc_readl(pxa_rtc, RTSR);
 316         if (alrm->enabled)
 317                 rtsr |= RTSR_RDALE1;
 318         else
 319                 rtsr &= ~RTSR_RDALE1;
 320         rtc_writel(pxa_rtc, RTSR, rtsr);
 321
 322         spin_unlock_irq(&pxa_rtc->lock);
 323
 324         return 0;
 325 }
 326
 327 static int pxa_rtc_proc(struct device *dev, struct seq_file *seq)
 328 {
 329         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 330
 331         seq_printf(seq, "trim/divider\t: 0x%08x\n", rtc_readl(pxa_rtc, RTTR));
 332         seq_printf(seq, "update_IRQ\t: %s\n",
 333                    (rtc_readl(pxa_rtc, RTSR) & RTSR_HZE) ? "yes" : "no");
 334         seq_printf(seq, "periodic_IRQ\t: %s\n",
 335                    (rtc_readl(pxa_rtc, RTSR) & RTSR_PIALE) ? "yes" : "no");
 336         seq_printf(seq, "periodic_freq\t: %u\n", rtc_readl(pxa_rtc, PIAR));
 337
 338         return 0;
 339 }
 340
 341 static const struct rtc_class_ops pxa_rtc_ops = {
 342         .open = pxa_rtc_open,
 343         .release = pxa_rtc_release,
 344         .read_time = pxa_rtc_read_time,
 345         .set_time = pxa_rtc_set_time,
 346         .read_alarm = pxa_rtc_read_alarm,
 347         .set_alarm = pxa_rtc_set_alarm,
 348         .alarm_irq_enable = pxa_alarm_irq_enable,
 349         .update_irq_enable = pxa_update_irq_enable,
 350         .proc = pxa_rtc_proc,
 351         .irq_set_state = pxa_periodic_irq_set_state,
 352         .irq_set_freq = pxa_periodic_irq_set_freq,
 353 };
 354
 355 static int __init pxa_rtc_probe(struct platform_device *pdev)
 356 {
 357         struct device *dev = &pdev->dev;
 358         struct pxa_rtc *pxa_rtc;
 359         int ret;
 360         u32 rttr;
 361
 362         pxa_rtc = kzalloc(sizeof(struct pxa_rtc), GFP_KERNEL);
 363         if (!pxa_rtc)
 364                 return -ENOMEM;
 365
 366         spin_lock_init(&pxa_rtc->lock);
 367         platform_set_drvdata(pdev, pxa_rtc);
 368
 369         ret = -ENXIO;
 370         pxa_rtc->ress = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 371         if (!pxa_rtc->ress) {
 372                 dev_err(dev, "No I/O memory resource defined\n");
 373                 goto err_ress;
 374         }
 375
 376         pxa_rtc->irq_1Hz = platform_get_irq(pdev, 0);
 377         if (pxa_rtc->irq_1Hz < 0) {
 378                 dev_err(dev, "No 1Hz IRQ resource defined\n");
 379                 goto err_ress;
 380         }
 381         pxa_rtc->irq_Alrm = platform_get_irq(pdev, 1);
 382         if (pxa_rtc->irq_Alrm < 0) {
 383                 dev_err(dev, "No alarm IRQ resource defined\n");
 384                 goto err_ress;
 385         }
 386
 387         ret = -ENOMEM;
 388         pxa_rtc->base = ioremap(pxa_rtc->ress->start,
 389                                 resource_size(pxa_rtc->ress));
 390         if (!pxa_rtc->base) {
 391                 dev_err(&pdev->dev, "Unable to map pxa RTC I/O memory\n");
 392                 goto err_map;
 393         }
 394
 395         /*
 396          * If the clock divider is uninitialized then reset it to the
 397          * default value to get the 1Hz clock.
 398          */
 399         if (rtc_readl(pxa_rtc, RTTR) == 0) {
 400                 rttr = RTC_DEF_DIVIDER + (RTC_DEF_TRIM << 16);
 401                 rtc_writel(pxa_rtc, RTTR, rttr);
 402                 dev_warn(dev, "warning: initializing default clock"
 403                          " divider/trim value\n");
 404         }
 405
 406         rtsr_clear_bits(pxa_rtc, RTSR_PIALE | RTSR_RDALE1 | RTSR_HZE);
 407
 408         pxa_rtc->rtc = rtc_device_register("pxa-rtc", &pdev->dev, &pxa_rtc_ops,
 409                                            THIS_MODULE);
 410         ret = PTR_ERR(pxa_rtc->rtc);
 411         if (IS_ERR(pxa_rtc->rtc)) {
 412                 dev_err(dev, "Failed to register RTC device -> %d\n", ret);
 413                 goto err_rtc_reg;
 414         }
 415
 416         device_init_wakeup(dev, 1);
 417
 418         return 0;
 419
 420 err_rtc_reg:
 421          iounmap(pxa_rtc->base);
 422 err_ress:
 423 err_map:
 424         kfree(pxa_rtc);
 425         return ret;
 426 }
 427
 428 static int __exit pxa_rtc_remove(struct platform_device *pdev)
 429 {
 430         struct pxa_rtc *pxa_rtc = platform_get_drvdata(pdev);
 431
 432         rtc_device_unregister(pxa_rtc->rtc);
 433
 434         spin_lock_irq(&pxa_rtc->lock);
 435         iounmap(pxa_rtc->base);
 436         spin_unlock_irq(&pxa_rtc->lock);
 437
 438         kfree(pxa_rtc);
 439
 440         return 0;
 441 }
 442
 443 #ifdef CONFIG_PM
 444 static int pxa_rtc_suspend(struct device *dev)
 445 {
 446         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 447
 448         if (device_may_wakeup(dev))
 449                 enable_irq_wake(pxa_rtc->irq_Alrm);
 450         return 0;
 451 }
 452
 453 static int pxa_rtc_resume(struct device *dev)
 454 {
 455         struct pxa_rtc *pxa_rtc = dev_get_drvdata(dev);
 456
 457         if (device_may_wakeup(dev))
 458                 disable_irq_wake(pxa_rtc->irq_Alrm);
 459         return 0;
 460 }
 461
 462 static const struct dev_pm_ops pxa_rtc_pm_ops = {
 463         .suspend        = pxa_rtc_suspend,
 464         .resume         = pxa_rtc_resume,
 465 };
 466 #endif
 467
 468 static struct platform_driver pxa_rtc_driver = {
 469         .remove         = __exit_p(pxa_rtc_remove),
 470         .driver         = {
 471                 .name   = "pxa-rtc",
 472 #ifdef CONFIG_PM
 473                 .pm     = &pxa_rtc_pm_ops,
 474 #endif
 475         },
 476 };
 477
 478 static int __init pxa_rtc_init(void)
 479 {
 480         if (cpu_is_pxa27x() || cpu_is_pxa3xx())
 481                 return platform_driver_probe(&pxa_rtc_driver, pxa_rtc_probe);
 482
 483         return -ENODEV;
 484 }
 485
 486 static void __exit pxa_rtc_exit(void)
 487 {
 488         platform_driver_unregister(&pxa_rtc_driver);
 489 }
 490
 491 module_init(pxa_rtc_init);
 492 module_exit(pxa_rtc_exit);
 493
 494 MODULE_AUTHOR("Robert Jarzmik <robert.jarzmik@free.fr>");
 495 MODULE_DESCRIPTION("PXA27x/PXA3xx Realtime Clock Driver (RTC)");
 496 MODULE_LICENSE("GPL");
 497 MODULE_ALIAS("platform:pxa-rtc");