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i2c-omap: Don't write IE state in unidle if 0
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / i2c / busses / i2c-omap.c
bloba64a192c44a4bd908de8b1fc560bc5ab7eb644dd
1 /*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
39 #include <linux/io.h>
40
41 /* I2C controller revisions */
42 #define OMAP_I2C_REV_2 0x20
43
44 /* I2C controller revisions present on specific hardware */
45 #define OMAP_I2C_REV_ON_2430 0x36
46 #define OMAP_I2C_REV_ON_3430 0x3C
47
48 /* timeout waiting for the controller to respond */
49 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
50
51 #define OMAP_I2C_REV_REG 0x00
52 #define OMAP_I2C_IE_REG 0x04
53 #define OMAP_I2C_STAT_REG 0x08
54 #define OMAP_I2C_IV_REG 0x0c
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56 #define OMAP_I2C_WE_REG 0x0c
57 #define OMAP_I2C_SYSS_REG 0x10
58 #define OMAP_I2C_BUF_REG 0x14
59 #define OMAP_I2C_CNT_REG 0x18
60 #define OMAP_I2C_DATA_REG 0x1c
61 #define OMAP_I2C_SYSC_REG 0x20
62 #define OMAP_I2C_CON_REG 0x24
63 #define OMAP_I2C_OA_REG 0x28
64 #define OMAP_I2C_SA_REG 0x2c
65 #define OMAP_I2C_PSC_REG 0x30
66 #define OMAP_I2C_SCLL_REG 0x34
67 #define OMAP_I2C_SCLH_REG 0x38
68 #define OMAP_I2C_SYSTEST_REG 0x3c
69 #define OMAP_I2C_BUFSTAT_REG 0x40
70
71 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
72 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
73 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
74 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
75 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
76 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
77 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
78 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
79
80 /* I2C Status Register (OMAP_I2C_STAT): */
81 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
82 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
83 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
84 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
85 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
86 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
87 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
88 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
89 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
90 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
91 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
92 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
93
94 /* I2C WE wakeup enable register */
95 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
96 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
97 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
98 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
99 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
100 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
101 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
102 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
103 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
104 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
105
106 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
107 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
108 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
109 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
110 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
111
112 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
113 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
114 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
115 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
116 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
117
118 /* I2C Configuration Register (OMAP_I2C_CON): */
119 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
120 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
121 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
122 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
123 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
124 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
125 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
126 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
127 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
128 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
129
130 /* I2C SCL time value when Master */
131 #define OMAP_I2C_SCLL_HSSCLL 8
132 #define OMAP_I2C_SCLH_HSSCLH 8
133
134 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
135 #ifdef DEBUG
136 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
137 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
138 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
139 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
140 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
141 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
142 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
143 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
144 #endif
145
146 /* OCP_SYSSTATUS bit definitions */
147 #define SYSS_RESETDONE_MASK (1 << 0)
148
149 /* OCP_SYSCONFIG bit definitions */
150 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
151 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
152 #define SYSC_ENAWAKEUP_MASK (1 << 2)
153 #define SYSC_SOFTRESET_MASK (1 << 1)
154 #define SYSC_AUTOIDLE_MASK (1 << 0)
155
156 #define SYSC_IDLEMODE_SMART 0x2
157 #define SYSC_CLOCKACTIVITY_FCLK 0x2
158
159
160 struct omap_i2c_dev {
161 struct device *dev;
162 void __iomem *base; /* virtual */
163 int irq;
164 struct clk *iclk; /* Interface clock */
165 struct clk *fclk; /* Functional clock */
166 struct completion cmd_complete;
167 struct resource *ioarea;
168 u32 speed; /* Speed of bus in Khz */
169 u16 cmd_err;
170 u8 *buf;
171 size_t buf_len;
172 struct i2c_adapter adapter;
173 u8 fifo_size; /* use as flag and value
174 * fifo_size==0 implies no fifo
175 * if set, should be trsh+1
176 */
177 u8 rev;
178 unsigned b_hw:1; /* bad h/w fixes */
179 unsigned idle:1;
180 u16 iestate; /* Saved interrupt register */
181 u16 pscstate;
182 u16 scllstate;
183 u16 sclhstate;
184 u16 bufstate;
185 u16 syscstate;
186 u16 westate;
187 };
188
189 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
190 int reg, u16 val)
191 {
192 __raw_writew(val, i2c_dev->base + reg);
193 }
194
195 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
196 {
197 return __raw_readw(i2c_dev->base + reg);
198 }
199
200 static int __init omap_i2c_get_clocks(struct omap_i2c_dev *dev)
201 {
202 int ret;
203
204 dev->iclk = clk_get(dev->dev, "ick");
205 if (IS_ERR(dev->iclk)) {
206 ret = PTR_ERR(dev->iclk);
207 dev->iclk = NULL;
208 return ret;
209 }
210
211 dev->fclk = clk_get(dev->dev, "fck");
212 if (IS_ERR(dev->fclk)) {
213 ret = PTR_ERR(dev->fclk);
214 if (dev->iclk != NULL) {
215 clk_put(dev->iclk);
216 dev->iclk = NULL;
217 }
218 dev->fclk = NULL;
219 return ret;
220 }
221
222 return 0;
223 }
224
225 static void omap_i2c_put_clocks(struct omap_i2c_dev *dev)
226 {
227 clk_put(dev->fclk);
228 dev->fclk = NULL;
229 clk_put(dev->iclk);
230 dev->iclk = NULL;
231 }
232
233 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
234 {
235 WARN_ON(!dev->idle);
236
237 clk_enable(dev->iclk);
238 clk_enable(dev->fclk);
239 if (cpu_is_omap34xx()) {
240 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
241 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
242 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
243 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
244 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
245 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
246 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
247 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
248 }
249 dev->idle = 0;
250
251 /*
252 * Don't write to this register if the IE state is 0 as it can
253 * cause deadlock.
254 */
255 if (dev->iestate)
256 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
257 }
258
259 static void omap_i2c_idle(struct omap_i2c_dev *dev)
260 {
261 u16 iv;
262
263 WARN_ON(dev->idle);
264
265 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
266 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
267 if (dev->rev < OMAP_I2C_REV_2) {
268 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
269 } else {
270 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
271
272 /* Flush posted write before the dev->idle store occurs */
273 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
274 }
275 dev->idle = 1;
276 clk_disable(dev->fclk);
277 clk_disable(dev->iclk);
278 }
279
280 static int omap_i2c_init(struct omap_i2c_dev *dev)
281 {
282 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
283 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
284 unsigned long fclk_rate = 12000000;
285 unsigned long timeout;
286 unsigned long internal_clk = 0;
287
288 if (dev->rev >= OMAP_I2C_REV_2) {
289 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
290 /* For some reason we need to set the EN bit before the
291 * reset done bit gets set. */
292 timeout = jiffies + OMAP_I2C_TIMEOUT;
293 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
294 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
295 SYSS_RESETDONE_MASK)) {
296 if (time_after(jiffies, timeout)) {
297 dev_warn(dev->dev, "timeout waiting "
298 "for controller reset\n");
299 return -ETIMEDOUT;
300 }
301 msleep(1);
302 }
303
304 /* SYSC register is cleared by the reset; rewrite it */
305 if (dev->rev == OMAP_I2C_REV_ON_2430) {
306
307 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
308 SYSC_AUTOIDLE_MASK);
309
310 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
311 dev->syscstate = SYSC_AUTOIDLE_MASK;
312 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
313 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
314 __ffs(SYSC_SIDLEMODE_MASK));
315 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
316 __ffs(SYSC_CLOCKACTIVITY_MASK));
317
318 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
319 dev->syscstate);
320 /*
321 * Enabling all wakup sources to stop I2C freezing on
322 * WFI instruction.
323 * REVISIT: Some wkup sources might not be needed.
324 */
325 dev->westate = OMAP_I2C_WE_ALL;
326 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
327 }
328 }
329 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
330
331 if (cpu_class_is_omap1()) {
332 /*
333 * The I2C functional clock is the armxor_ck, so there's
334 * no need to get "armxor_ck" separately. Now, if OMAP2420
335 * always returns 12MHz for the functional clock, we can
336 * do this bit unconditionally.
337 */
338 fclk_rate = clk_get_rate(dev->fclk);
339
340 /* TRM for 5912 says the I2C clock must be prescaled to be
341 * between 7 - 12 MHz. The XOR input clock is typically
342 * 12, 13 or 19.2 MHz. So we should have code that produces:
343 *
344 * XOR MHz Divider Prescaler
345 * 12 1 0
346 * 13 2 1
347 * 19.2 2 1
348 */
349 if (fclk_rate > 12000000)
350 psc = fclk_rate / 12000000;
351 }
352
353 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
354
355 /*
356 * HSI2C controller internal clk rate should be 19.2 Mhz for
357 * HS and for all modes on 2430. On 34xx we can use lower rate
358 * to get longer filter period for better noise suppression.
359 * The filter is iclk (fclk for HS) period.
360 */
361 if (dev->speed > 400 || cpu_is_omap2430())
362 internal_clk = 19200;
363 else if (dev->speed > 100)
364 internal_clk = 9600;
365 else
366 internal_clk = 4000;
367 fclk_rate = clk_get_rate(dev->fclk) / 1000;
368
369 /* Compute prescaler divisor */
370 psc = fclk_rate / internal_clk;
371 psc = psc - 1;
372
373 /* If configured for High Speed */
374 if (dev->speed > 400) {
375 unsigned long scl;
376
377 /* For first phase of HS mode */
378 scl = internal_clk / 400;
379 fsscll = scl - (scl / 3) - 7;
380 fssclh = (scl / 3) - 5;
381
382 /* For second phase of HS mode */
383 scl = fclk_rate / dev->speed;
384 hsscll = scl - (scl / 3) - 7;
385 hssclh = (scl / 3) - 5;
386 } else if (dev->speed > 100) {
387 unsigned long scl;
388
389 /* Fast mode */
390 scl = internal_clk / dev->speed;
391 fsscll = scl - (scl / 3) - 7;
392 fssclh = (scl / 3) - 5;
393 } else {
394 /* Standard mode */
395 fsscll = internal_clk / (dev->speed * 2) - 7;
396 fssclh = internal_clk / (dev->speed * 2) - 5;
397 }
398 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
399 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
400 } else {
401 /* Program desired operating rate */
402 fclk_rate /= (psc + 1) * 1000;
403 if (psc > 2)
404 psc = 2;
405 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
406 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
407 }
408
409 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
410 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
411
412 /* SCL low and high time values */
413 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
414 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
415
416 if (dev->fifo_size) {
417 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
418 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
419 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
420 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
421 }
422
423 /* Take the I2C module out of reset: */
424 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
425
426 /* Enable interrupts */
427 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
428 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
429 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
430 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
431 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
432 if (cpu_is_omap34xx()) {
433 dev->pscstate = psc;
434 dev->scllstate = scll;
435 dev->sclhstate = sclh;
436 dev->bufstate = buf;
437 }
438 return 0;
439 }
440
441 /*
442 * Waiting on Bus Busy
443 */
444 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
445 {
446 unsigned long timeout;
447
448 timeout = jiffies + OMAP_I2C_TIMEOUT;
449 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
450 if (time_after(jiffies, timeout)) {
451 dev_warn(dev->dev, "timeout waiting for bus ready\n");
452 return -ETIMEDOUT;
453 }
454 msleep(1);
455 }
456
457 return 0;
458 }
459
460 /*
461 * Low level master read/write transaction.
462 */
463 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
464 struct i2c_msg *msg, int stop)
465 {
466 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
467 int r;
468 u16 w;
469
470 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
471 msg->addr, msg->len, msg->flags, stop);
472
473 if (msg->len == 0)
474 return -EINVAL;
475
476 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
477
478 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
479 dev->buf = msg->buf;
480 dev->buf_len = msg->len;
481
482 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
483
484 /* Clear the FIFO Buffers */
485 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
486 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
487 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
488
489 init_completion(&dev->cmd_complete);
490 dev->cmd_err = 0;
491
492 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
493
494 /* High speed configuration */
495 if (dev->speed > 400)
496 w |= OMAP_I2C_CON_OPMODE_HS;
497
498 if (msg->flags & I2C_M_TEN)
499 w |= OMAP_I2C_CON_XA;
500 if (!(msg->flags & I2C_M_RD))
501 w |= OMAP_I2C_CON_TRX;
502
503 if (!dev->b_hw && stop)
504 w |= OMAP_I2C_CON_STP;
505
506 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
507
508 /*
509 * Don't write stt and stp together on some hardware.
510 */
511 if (dev->b_hw && stop) {
512 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
513 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
514 while (con & OMAP_I2C_CON_STT) {
515 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
516
517 /* Let the user know if i2c is in a bad state */
518 if (time_after(jiffies, delay)) {
519 dev_err(dev->dev, "controller timed out "
520 "waiting for start condition to finish\n");
521 return -ETIMEDOUT;
522 }
523 cpu_relax();
524 }
525
526 w |= OMAP_I2C_CON_STP;
527 w &= ~OMAP_I2C_CON_STT;
528 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
529 }
530
531 /*
532 * REVISIT: We should abort the transfer on signals, but the bus goes
533 * into arbitration and we're currently unable to recover from it.
534 */
535 r = wait_for_completion_timeout(&dev->cmd_complete,
536 OMAP_I2C_TIMEOUT);
537 dev->buf_len = 0;
538 if (r < 0)
539 return r;
540 if (r == 0) {
541 dev_err(dev->dev, "controller timed out\n");
542 omap_i2c_init(dev);
543 return -ETIMEDOUT;
544 }
545
546 if (likely(!dev->cmd_err))
547 return 0;
548
549 /* We have an error */
550 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
551 OMAP_I2C_STAT_XUDF)) {
552 omap_i2c_init(dev);
553 return -EIO;
554 }
555
556 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
557 if (msg->flags & I2C_M_IGNORE_NAK)
558 return 0;
559 if (stop) {
560 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
561 w |= OMAP_I2C_CON_STP;
562 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
563 }
564 return -EREMOTEIO;
565 }
566 return -EIO;
567 }
568
569
570 /*
571 * Prepare controller for a transaction and call omap_i2c_xfer_msg
572 * to do the work during IRQ processing.
573 */
574 static int
575 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
576 {
577 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
578 int i;
579 int r;
580
581 omap_i2c_unidle(dev);
582
583 r = omap_i2c_wait_for_bb(dev);
584 if (r < 0)
585 goto out;
586
587 for (i = 0; i < num; i++) {
588 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
589 if (r != 0)
590 break;
591 }
592
593 if (r == 0)
594 r = num;
595 out:
596 omap_i2c_idle(dev);
597 return r;
598 }
599
600 static u32
601 omap_i2c_func(struct i2c_adapter *adap)
602 {
603 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
604 }
605
606 static inline void
607 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
608 {
609 dev->cmd_err |= err;
610 complete(&dev->cmd_complete);
611 }
612
613 static inline void
614 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
615 {
616 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
617 }
618
619 /* rev1 devices are apparently only on some 15xx */
620 #ifdef CONFIG_ARCH_OMAP15XX
621
622 static irqreturn_t
623 omap_i2c_rev1_isr(int this_irq, void *dev_id)
624 {
625 struct omap_i2c_dev *dev = dev_id;
626 u16 iv, w;
627
628 if (dev->idle)
629 return IRQ_NONE;
630
631 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
632 switch (iv) {
633 case 0x00: /* None */
634 break;
635 case 0x01: /* Arbitration lost */
636 dev_err(dev->dev, "Arbitration lost\n");
637 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
638 break;
639 case 0x02: /* No acknowledgement */
640 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
641 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
642 break;
643 case 0x03: /* Register access ready */
644 omap_i2c_complete_cmd(dev, 0);
645 break;
646 case 0x04: /* Receive data ready */
647 if (dev->buf_len) {
648 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
649 *dev->buf++ = w;
650 dev->buf_len--;
651 if (dev->buf_len) {
652 *dev->buf++ = w >> 8;
653 dev->buf_len--;
654 }
655 } else
656 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
657 break;
658 case 0x05: /* Transmit data ready */
659 if (dev->buf_len) {
660 w = *dev->buf++;
661 dev->buf_len--;
662 if (dev->buf_len) {
663 w |= *dev->buf++ << 8;
664 dev->buf_len--;
665 }
666 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
667 } else
668 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
669 break;
670 default:
671 return IRQ_NONE;
672 }
673
674 return IRQ_HANDLED;
675 }
676 #else
677 #define omap_i2c_rev1_isr NULL
678 #endif
679
680 static irqreturn_t
681 omap_i2c_isr(int this_irq, void *dev_id)
682 {
683 struct omap_i2c_dev *dev = dev_id;
684 u16 bits;
685 u16 stat, w;
686 int err, count = 0;
687
688 if (dev->idle)
689 return IRQ_NONE;
690
691 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
692 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
693 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
694 if (count++ == 100) {
695 dev_warn(dev->dev, "Too much work in one IRQ\n");
696 break;
697 }
698
699 err = 0;
700 complete:
701 /*
702 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
703 * acked after the data operation is complete.
704 * Ref: TRM SWPU114Q Figure 18-31
705 */
706 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
707 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
708 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
709
710 if (stat & OMAP_I2C_STAT_NACK) {
711 err |= OMAP_I2C_STAT_NACK;
712 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
713 OMAP_I2C_CON_STP);
714 }
715 if (stat & OMAP_I2C_STAT_AL) {
716 dev_err(dev->dev, "Arbitration lost\n");
717 err |= OMAP_I2C_STAT_AL;
718 }
719 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
720 OMAP_I2C_STAT_AL)) {
721 omap_i2c_ack_stat(dev, stat &
722 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
723 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
724 omap_i2c_complete_cmd(dev, err);
725 return IRQ_HANDLED;
726 }
727 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
728 u8 num_bytes = 1;
729 if (dev->fifo_size) {
730 if (stat & OMAP_I2C_STAT_RRDY)
731 num_bytes = dev->fifo_size;
732 else /* read RXSTAT on RDR interrupt */
733 num_bytes = (omap_i2c_read_reg(dev,
734 OMAP_I2C_BUFSTAT_REG)
735 >> 8) & 0x3F;
736 }
737 while (num_bytes) {
738 num_bytes--;
739 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
740 if (dev->buf_len) {
741 *dev->buf++ = w;
742 dev->buf_len--;
743 /* Data reg from 2430 is 8 bit wide */
744 if (!cpu_is_omap2430() &&
745 !cpu_is_omap34xx()) {
746 if (dev->buf_len) {
747 *dev->buf++ = w >> 8;
748 dev->buf_len--;
749 }
750 }
751 } else {
752 if (stat & OMAP_I2C_STAT_RRDY)
753 dev_err(dev->dev,
754 "RRDY IRQ while no data"
755 " requested\n");
756 if (stat & OMAP_I2C_STAT_RDR)
757 dev_err(dev->dev,
758 "RDR IRQ while no data"
759 " requested\n");
760 break;
761 }
762 }
763 omap_i2c_ack_stat(dev,
764 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
765 continue;
766 }
767 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
768 u8 num_bytes = 1;
769 if (dev->fifo_size) {
770 if (stat & OMAP_I2C_STAT_XRDY)
771 num_bytes = dev->fifo_size;
772 else /* read TXSTAT on XDR interrupt */
773 num_bytes = omap_i2c_read_reg(dev,
774 OMAP_I2C_BUFSTAT_REG)
775 & 0x3F;
776 }
777 while (num_bytes) {
778 num_bytes--;
779 w = 0;
780 if (dev->buf_len) {
781 w = *dev->buf++;
782 dev->buf_len--;
783 /* Data reg from 2430 is 8 bit wide */
784 if (!cpu_is_omap2430() &&
785 !cpu_is_omap34xx()) {
786 if (dev->buf_len) {
787 w |= *dev->buf++ << 8;
788 dev->buf_len--;
789 }
790 }
791 } else {
792 if (stat & OMAP_I2C_STAT_XRDY)
793 dev_err(dev->dev,
794 "XRDY IRQ while no "
795 "data to send\n");
796 if (stat & OMAP_I2C_STAT_XDR)
797 dev_err(dev->dev,
798 "XDR IRQ while no "
799 "data to send\n");
800 break;
801 }
802
803 /*
804 * OMAP3430 Errata 1.153: When an XRDY/XDR
805 * is hit, wait for XUDF before writing data
806 * to DATA_REG. Otherwise some data bytes can
807 * be lost while transferring them from the
808 * memory to the I2C interface.
809 */
810
811 if (dev->rev <= OMAP_I2C_REV_ON_3430) {
812 while (!(stat & OMAP_I2C_STAT_XUDF)) {
813 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
814 omap_i2c_ack_stat(dev, stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
815 err |= OMAP_I2C_STAT_XUDF;
816 goto complete;
817 }
818 cpu_relax();
819 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
820 }
821 }
822
823 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
824 }
825 omap_i2c_ack_stat(dev,
826 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
827 continue;
828 }
829 if (stat & OMAP_I2C_STAT_ROVR) {
830 dev_err(dev->dev, "Receive overrun\n");
831 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
832 }
833 if (stat & OMAP_I2C_STAT_XUDF) {
834 dev_err(dev->dev, "Transmit underflow\n");
835 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
836 }
837 }
838
839 return count ? IRQ_HANDLED : IRQ_NONE;
840 }
841
842 static const struct i2c_algorithm omap_i2c_algo = {
843 .master_xfer = omap_i2c_xfer,
844 .functionality = omap_i2c_func,
845 };
846
847 static int __init
848 omap_i2c_probe(struct platform_device *pdev)
849 {
850 struct omap_i2c_dev *dev;
851 struct i2c_adapter *adap;
852 struct resource *mem, *irq, *ioarea;
853 irq_handler_t isr;
854 int r;
855 u32 speed = 0;
856
857 /* NOTE: driver uses the static register mapping */
858 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
859 if (!mem) {
860 dev_err(&pdev->dev, "no mem resource?\n");
861 return -ENODEV;
862 }
863 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
864 if (!irq) {
865 dev_err(&pdev->dev, "no irq resource?\n");
866 return -ENODEV;
867 }
868
869 ioarea = request_mem_region(mem->start, resource_size(mem),
870 pdev->name);
871 if (!ioarea) {
872 dev_err(&pdev->dev, "I2C region already claimed\n");
873 return -EBUSY;
874 }
875
876 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
877 if (!dev) {
878 r = -ENOMEM;
879 goto err_release_region;
880 }
881
882 if (pdev->dev.platform_data != NULL)
883 speed = *(u32 *)pdev->dev.platform_data;
884 else
885 speed = 100; /* Defualt speed */
886
887 dev->speed = speed;
888 dev->idle = 1;
889 dev->dev = &pdev->dev;
890 dev->irq = irq->start;
891 dev->base = ioremap(mem->start, resource_size(mem));
892 if (!dev->base) {
893 r = -ENOMEM;
894 goto err_free_mem;
895 }
896
897 platform_set_drvdata(pdev, dev);
898
899 if ((r = omap_i2c_get_clocks(dev)) != 0)
900 goto err_iounmap;
901
902 omap_i2c_unidle(dev);
903
904 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
905
906 if (cpu_is_omap2430() || cpu_is_omap34xx()) {
907 u16 s;
908
909 /* Set up the fifo size - Get total size */
910 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
911 dev->fifo_size = 0x8 << s;
912
913 /*
914 * Set up notification threshold as half the total available
915 * size. This is to ensure that we can handle the status on int
916 * call back latencies.
917 */
918 dev->fifo_size = (dev->fifo_size / 2);
919 dev->b_hw = 1; /* Enable hardware fixes */
920 }
921
922 /* reset ASAP, clearing any IRQs */
923 omap_i2c_init(dev);
924
925 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
926 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
927
928 if (r) {
929 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
930 goto err_unuse_clocks;
931 }
932
933 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
934 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
935
936 omap_i2c_idle(dev);
937
938 adap = &dev->adapter;
939 i2c_set_adapdata(adap, dev);
940 adap->owner = THIS_MODULE;
941 adap->class = I2C_CLASS_HWMON;
942 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
943 adap->algo = &omap_i2c_algo;
944 adap->dev.parent = &pdev->dev;
945
946 /* i2c device drivers may be active on return from add_adapter() */
947 adap->nr = pdev->id;
948 r = i2c_add_numbered_adapter(adap);
949 if (r) {
950 dev_err(dev->dev, "failure adding adapter\n");
951 goto err_free_irq;
952 }
953
954 return 0;
955
956 err_free_irq:
957 free_irq(dev->irq, dev);
958 err_unuse_clocks:
959 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
960 omap_i2c_idle(dev);
961 omap_i2c_put_clocks(dev);
962 err_iounmap:
963 iounmap(dev->base);
964 err_free_mem:
965 platform_set_drvdata(pdev, NULL);
966 kfree(dev);
967 err_release_region:
968 release_mem_region(mem->start, resource_size(mem));
969
970 return r;
971 }
972
973 static int
974 omap_i2c_remove(struct platform_device *pdev)
975 {
976 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
977 struct resource *mem;
978
979 platform_set_drvdata(pdev, NULL);
980
981 free_irq(dev->irq, dev);
982 i2c_del_adapter(&dev->adapter);
983 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
984 omap_i2c_put_clocks(dev);
985 iounmap(dev->base);
986 kfree(dev);
987 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
988 release_mem_region(mem->start, resource_size(mem));
989 return 0;
990 }
991
992 static struct platform_driver omap_i2c_driver = {
993 .probe = omap_i2c_probe,
994 .remove = omap_i2c_remove,
995 .driver = {
996 .name = "i2c_omap",
997 .owner = THIS_MODULE,
998 },
999 };
1000
1001 /* I2C may be needed to bring up other drivers */
1002 static int __init
1003 omap_i2c_init_driver(void)
1004 {
1005 return platform_driver_register(&omap_i2c_driver);
1006 }
1007 subsys_initcall(omap_i2c_init_driver);
1008
1009 static void __exit omap_i2c_exit_driver(void)
1010 {
1011 platform_driver_unregister(&omap_i2c_driver);
1012 }
1013 module_exit(omap_i2c_exit_driver);
1014
1015 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1016 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1017 MODULE_LICENSE("GPL");
1018 MODULE_ALIAS("platform:i2c_omap");
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