2 Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: Data structures and registers for the rt73usb module.
24 Supported chipsets: rt2571W & rt2671.
40 * Defaul offset is required for RSSI <-> dBm conversion.
42 #define DEFAULT_RSSI_OFFSET 120
45 * Register layout information.
47 #define CSR_REG_BASE 0x3000
48 #define CSR_REG_SIZE 0x04b0
49 #define EEPROM_BASE 0x0000
50 #define EEPROM_SIZE 0x0100
51 #define BBP_BASE 0x0000
52 #define BBP_SIZE 0x0080
53 #define RF_BASE 0x0000
54 #define RF_SIZE 0x0014
57 * Number of TX queues.
59 #define NUM_TX_QUEUES 4
66 * MCU_LEDCS: LED control for MCU Mailbox.
68 #define MCU_LEDCS_LED_MODE FIELD16(0x001f)
69 #define MCU_LEDCS_RADIO_STATUS FIELD16(0x0020)
70 #define MCU_LEDCS_LINK_BG_STATUS FIELD16(0x0040)
71 #define MCU_LEDCS_LINK_A_STATUS FIELD16(0x0080)
72 #define MCU_LEDCS_POLARITY_GPIO_0 FIELD16(0x0100)
73 #define MCU_LEDCS_POLARITY_GPIO_1 FIELD16(0x0200)
74 #define MCU_LEDCS_POLARITY_GPIO_2 FIELD16(0x0400)
75 #define MCU_LEDCS_POLARITY_GPIO_3 FIELD16(0x0800)
76 #define MCU_LEDCS_POLARITY_GPIO_4 FIELD16(0x1000)
77 #define MCU_LEDCS_POLARITY_ACT FIELD16(0x2000)
78 #define MCU_LEDCS_POLARITY_READY_BG FIELD16(0x4000)
79 #define MCU_LEDCS_POLARITY_READY_A FIELD16(0x8000)
82 * 8051 firmware image.
84 #define FIRMWARE_RT2571 "rt73.bin"
85 #define FIRMWARE_IMAGE_BASE 0x0800
88 * Security key table memory.
89 * 16 entries 32-byte for shared key table
90 * 64 entries 32-byte for pairwise key table
91 * 64 entries 8-byte for pairwise ta key table
93 #define SHARED_KEY_TABLE_BASE 0x1000
94 #define PAIRWISE_KEY_TABLE_BASE 0x1200
95 #define PAIRWISE_TA_TABLE_BASE 0x1a00
97 #define SHARED_KEY_ENTRY(__idx) \
98 ( SHARED_KEY_TABLE_BASE + \
99 ((__idx) * sizeof(struct hw_key_entry)) )
100 #define PAIRWISE_KEY_ENTRY(__idx) \
101 ( PAIRWISE_KEY_TABLE_BASE + \
102 ((__idx) * sizeof(struct hw_key_entry)) )
103 #define PAIRWISE_TA_ENTRY(__idx) \
104 ( PAIRWISE_TA_TABLE_BASE + \
105 ((__idx) * sizeof(struct hw_pairwise_ta_entry)) )
107 struct hw_key_entry
{
111 } __attribute__ ((packed
));
113 struct hw_pairwise_ta_entry
{
117 } __attribute__ ((packed
));
120 * Since NULL frame won't be that long (256 byte),
121 * We steal 16 tail bytes to save debugging settings.
123 #define HW_DEBUG_SETTING_BASE 0x2bf0
126 * On-chip BEACON frame space.
128 #define HW_BEACON_BASE0 0x2400
129 #define HW_BEACON_BASE1 0x2500
130 #define HW_BEACON_BASE2 0x2600
131 #define HW_BEACON_BASE3 0x2700
133 #define HW_BEACON_OFFSET(__index) \
134 ( HW_BEACON_BASE0 + (__index * 0x0100) )
137 * MAC Control/Status Registers(CSR).
138 * Some values are set in TU, whereas 1 TU == 1024 us.
142 * MAC_CSR0: ASIC revision number.
144 #define MAC_CSR0 0x3000
147 * MAC_CSR1: System control register.
148 * SOFT_RESET: Software reset bit, 1: reset, 0: normal.
149 * BBP_RESET: Hardware reset BBP.
150 * HOST_READY: Host is ready after initialization, 1: ready.
152 #define MAC_CSR1 0x3004
153 #define MAC_CSR1_SOFT_RESET FIELD32(0x00000001)
154 #define MAC_CSR1_BBP_RESET FIELD32(0x00000002)
155 #define MAC_CSR1_HOST_READY FIELD32(0x00000004)
158 * MAC_CSR2: STA MAC register 0.
160 #define MAC_CSR2 0x3008
161 #define MAC_CSR2_BYTE0 FIELD32(0x000000ff)
162 #define MAC_CSR2_BYTE1 FIELD32(0x0000ff00)
163 #define MAC_CSR2_BYTE2 FIELD32(0x00ff0000)
164 #define MAC_CSR2_BYTE3 FIELD32(0xff000000)
167 * MAC_CSR3: STA MAC register 1.
168 * UNICAST_TO_ME_MASK:
169 * Used to mask off bits from byte 5 of the MAC address
170 * to determine the UNICAST_TO_ME bit for RX frames.
171 * The full mask is complemented by BSS_ID_MASK:
172 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
174 #define MAC_CSR3 0x300c
175 #define MAC_CSR3_BYTE4 FIELD32(0x000000ff)
176 #define MAC_CSR3_BYTE5 FIELD32(0x0000ff00)
177 #define MAC_CSR3_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
180 * MAC_CSR4: BSSID register 0.
182 #define MAC_CSR4 0x3010
183 #define MAC_CSR4_BYTE0 FIELD32(0x000000ff)
184 #define MAC_CSR4_BYTE1 FIELD32(0x0000ff00)
185 #define MAC_CSR4_BYTE2 FIELD32(0x00ff0000)
186 #define MAC_CSR4_BYTE3 FIELD32(0xff000000)
189 * MAC_CSR5: BSSID register 1.
191 * This mask is used to mask off bits 0 and 1 of byte 5 of the
192 * BSSID. This will make sure that those bits will be ignored
193 * when determining the MY_BSS of RX frames.
194 * 0: 1-BSSID mode (BSS index = 0)
195 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
196 * 2: 2-BSSID mode (BSS index: byte5, bit 1)
197 * 3: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
199 #define MAC_CSR5 0x3014
200 #define MAC_CSR5_BYTE4 FIELD32(0x000000ff)
201 #define MAC_CSR5_BYTE5 FIELD32(0x0000ff00)
202 #define MAC_CSR5_BSS_ID_MASK FIELD32(0x00ff0000)
205 * MAC_CSR6: Maximum frame length register.
207 #define MAC_CSR6 0x3018
208 #define MAC_CSR6_MAX_FRAME_UNIT FIELD32(0x00000fff)
213 #define MAC_CSR7 0x301c
216 * MAC_CSR8: SIFS/EIFS register.
217 * All units are in US.
219 #define MAC_CSR8 0x3020
220 #define MAC_CSR8_SIFS FIELD32(0x000000ff)
221 #define MAC_CSR8_SIFS_AFTER_RX_OFDM FIELD32(0x0000ff00)
222 #define MAC_CSR8_EIFS FIELD32(0xffff0000)
225 * MAC_CSR9: Back-Off control register.
226 * SLOT_TIME: Slot time, default is 20us for 802.11BG.
227 * CWMIN: Bit for Cwmin. default Cwmin is 31 (2^5 - 1).
228 * CWMAX: Bit for Cwmax, default Cwmax is 1023 (2^10 - 1).
229 * CW_SELECT: 1: CWmin/Cwmax select from register, 0:select from TxD.
231 #define MAC_CSR9 0x3024
232 #define MAC_CSR9_SLOT_TIME FIELD32(0x000000ff)
233 #define MAC_CSR9_CWMIN FIELD32(0x00000f00)
234 #define MAC_CSR9_CWMAX FIELD32(0x0000f000)
235 #define MAC_CSR9_CW_SELECT FIELD32(0x00010000)
238 * MAC_CSR10: Power state configuration.
240 #define MAC_CSR10 0x3028
243 * MAC_CSR11: Power saving transition time register.
244 * DELAY_AFTER_TBCN: Delay after Tbcn expired in units of TU.
245 * TBCN_BEFORE_WAKEUP: Number of beacon before wakeup.
246 * WAKEUP_LATENCY: In unit of TU.
248 #define MAC_CSR11 0x302c
249 #define MAC_CSR11_DELAY_AFTER_TBCN FIELD32(0x000000ff)
250 #define MAC_CSR11_TBCN_BEFORE_WAKEUP FIELD32(0x00007f00)
251 #define MAC_CSR11_AUTOWAKE FIELD32(0x00008000)
252 #define MAC_CSR11_WAKEUP_LATENCY FIELD32(0x000f0000)
255 * MAC_CSR12: Manual power control / status register (merge CSR20 & PWRCSR1).
256 * CURRENT_STATE: 0:sleep, 1:awake.
257 * FORCE_WAKEUP: This has higher priority than PUT_TO_SLEEP.
258 * BBP_CURRENT_STATE: 0: BBP sleep, 1: BBP awake.
260 #define MAC_CSR12 0x3030
261 #define MAC_CSR12_CURRENT_STATE FIELD32(0x00000001)
262 #define MAC_CSR12_PUT_TO_SLEEP FIELD32(0x00000002)
263 #define MAC_CSR12_FORCE_WAKEUP FIELD32(0x00000004)
264 #define MAC_CSR12_BBP_CURRENT_STATE FIELD32(0x00000008)
269 #define MAC_CSR13 0x3034
272 * MAC_CSR14: LED control register.
273 * ON_PERIOD: On period, default 70ms.
274 * OFF_PERIOD: Off period, default 30ms.
275 * HW_LED: HW TX activity, 1: normal OFF, 0: normal ON.
276 * SW_LED: s/w LED, 1: ON, 0: OFF.
277 * HW_LED_POLARITY: 0: active low, 1: active high.
279 #define MAC_CSR14 0x3038
280 #define MAC_CSR14_ON_PERIOD FIELD32(0x000000ff)
281 #define MAC_CSR14_OFF_PERIOD FIELD32(0x0000ff00)
282 #define MAC_CSR14_HW_LED FIELD32(0x00010000)
283 #define MAC_CSR14_SW_LED FIELD32(0x00020000)
284 #define MAC_CSR14_HW_LED_POLARITY FIELD32(0x00040000)
285 #define MAC_CSR14_SW_LED2 FIELD32(0x00080000)
288 * MAC_CSR15: NAV control.
290 #define MAC_CSR15 0x303c
293 * TXRX control registers.
294 * Some values are set in TU, whereas 1 TU == 1024 us.
298 * TXRX_CSR0: TX/RX configuration register.
299 * TSF_OFFSET: Default is 24.
300 * AUTO_TX_SEQ: 1: ASIC auto replace sequence nr in outgoing frame.
301 * DISABLE_RX: Disable Rx engine.
302 * DROP_CRC: Drop CRC error.
303 * DROP_PHYSICAL: Drop physical error.
304 * DROP_CONTROL: Drop control frame.
305 * DROP_NOT_TO_ME: Drop not to me unicast frame.
306 * DROP_TO_DS: Drop fram ToDs bit is true.
307 * DROP_VERSION_ERROR: Drop version error frame.
308 * DROP_MULTICAST: Drop multicast frames.
309 * DROP_BORADCAST: Drop broadcast frames.
310 * ROP_ACK_CTS: Drop received ACK and CTS.
312 #define TXRX_CSR0 0x3040
313 #define TXRX_CSR0_RX_ACK_TIMEOUT FIELD32(0x000001ff)
314 #define TXRX_CSR0_TSF_OFFSET FIELD32(0x00007e00)
315 #define TXRX_CSR0_AUTO_TX_SEQ FIELD32(0x00008000)
316 #define TXRX_CSR0_DISABLE_RX FIELD32(0x00010000)
317 #define TXRX_CSR0_DROP_CRC FIELD32(0x00020000)
318 #define TXRX_CSR0_DROP_PHYSICAL FIELD32(0x00040000)
319 #define TXRX_CSR0_DROP_CONTROL FIELD32(0x00080000)
320 #define TXRX_CSR0_DROP_NOT_TO_ME FIELD32(0x00100000)
321 #define TXRX_CSR0_DROP_TO_DS FIELD32(0x00200000)
322 #define TXRX_CSR0_DROP_VERSION_ERROR FIELD32(0x00400000)
323 #define TXRX_CSR0_DROP_MULTICAST FIELD32(0x00800000)
324 #define TXRX_CSR0_DROP_BROADCAST FIELD32(0x01000000)
325 #define TXRX_CSR0_DROP_ACK_CTS FIELD32(0x02000000)
326 #define TXRX_CSR0_TX_WITHOUT_WAITING FIELD32(0x04000000)
331 #define TXRX_CSR1 0x3044
332 #define TXRX_CSR1_BBP_ID0 FIELD32(0x0000007f)
333 #define TXRX_CSR1_BBP_ID0_VALID FIELD32(0x00000080)
334 #define TXRX_CSR1_BBP_ID1 FIELD32(0x00007f00)
335 #define TXRX_CSR1_BBP_ID1_VALID FIELD32(0x00008000)
336 #define TXRX_CSR1_BBP_ID2 FIELD32(0x007f0000)
337 #define TXRX_CSR1_BBP_ID2_VALID FIELD32(0x00800000)
338 #define TXRX_CSR1_BBP_ID3 FIELD32(0x7f000000)
339 #define TXRX_CSR1_BBP_ID3_VALID FIELD32(0x80000000)
344 #define TXRX_CSR2 0x3048
345 #define TXRX_CSR2_BBP_ID0 FIELD32(0x0000007f)
346 #define TXRX_CSR2_BBP_ID0_VALID FIELD32(0x00000080)
347 #define TXRX_CSR2_BBP_ID1 FIELD32(0x00007f00)
348 #define TXRX_CSR2_BBP_ID1_VALID FIELD32(0x00008000)
349 #define TXRX_CSR2_BBP_ID2 FIELD32(0x007f0000)
350 #define TXRX_CSR2_BBP_ID2_VALID FIELD32(0x00800000)
351 #define TXRX_CSR2_BBP_ID3 FIELD32(0x7f000000)
352 #define TXRX_CSR2_BBP_ID3_VALID FIELD32(0x80000000)
357 #define TXRX_CSR3 0x304c
358 #define TXRX_CSR3_BBP_ID0 FIELD32(0x0000007f)
359 #define TXRX_CSR3_BBP_ID0_VALID FIELD32(0x00000080)
360 #define TXRX_CSR3_BBP_ID1 FIELD32(0x00007f00)
361 #define TXRX_CSR3_BBP_ID1_VALID FIELD32(0x00008000)
362 #define TXRX_CSR3_BBP_ID2 FIELD32(0x007f0000)
363 #define TXRX_CSR3_BBP_ID2_VALID FIELD32(0x00800000)
364 #define TXRX_CSR3_BBP_ID3 FIELD32(0x7f000000)
365 #define TXRX_CSR3_BBP_ID3_VALID FIELD32(0x80000000)
368 * TXRX_CSR4: Auto-Responder/Tx-retry register.
369 * AUTORESPOND_PREAMBLE: 0:long, 1:short preamble.
370 * OFDM_TX_RATE_DOWN: 1:enable.
371 * OFDM_TX_RATE_STEP: 0:1-step, 1: 2-step, 2:3-step, 3:4-step.
372 * OFDM_TX_FALLBACK_CCK: 0: Fallback to OFDM 6M only, 1: Fallback to CCK 1M,2M.
374 #define TXRX_CSR4 0x3050
375 #define TXRX_CSR4_TX_ACK_TIMEOUT FIELD32(0x000000ff)
376 #define TXRX_CSR4_CNTL_ACK_POLICY FIELD32(0x00000700)
377 #define TXRX_CSR4_ACK_CTS_PSM FIELD32(0x00010000)
378 #define TXRX_CSR4_AUTORESPOND_ENABLE FIELD32(0x00020000)
379 #define TXRX_CSR4_AUTORESPOND_PREAMBLE FIELD32(0x00040000)
380 #define TXRX_CSR4_OFDM_TX_RATE_DOWN FIELD32(0x00080000)
381 #define TXRX_CSR4_OFDM_TX_RATE_STEP FIELD32(0x00300000)
382 #define TXRX_CSR4_OFDM_TX_FALLBACK_CCK FIELD32(0x00400000)
383 #define TXRX_CSR4_LONG_RETRY_LIMIT FIELD32(0x0f000000)
384 #define TXRX_CSR4_SHORT_RETRY_LIMIT FIELD32(0xf0000000)
389 #define TXRX_CSR5 0x3054
392 * TXRX_CSR6: ACK/CTS payload consumed time
394 #define TXRX_CSR6 0x3058
397 * TXRX_CSR7: OFDM ACK/CTS payload consumed time for 6/9/12/18 mbps.
399 #define TXRX_CSR7 0x305c
400 #define TXRX_CSR7_ACK_CTS_6MBS FIELD32(0x000000ff)
401 #define TXRX_CSR7_ACK_CTS_9MBS FIELD32(0x0000ff00)
402 #define TXRX_CSR7_ACK_CTS_12MBS FIELD32(0x00ff0000)
403 #define TXRX_CSR7_ACK_CTS_18MBS FIELD32(0xff000000)
406 * TXRX_CSR8: OFDM ACK/CTS payload consumed time for 24/36/48/54 mbps.
408 #define TXRX_CSR8 0x3060
409 #define TXRX_CSR8_ACK_CTS_24MBS FIELD32(0x000000ff)
410 #define TXRX_CSR8_ACK_CTS_36MBS FIELD32(0x0000ff00)
411 #define TXRX_CSR8_ACK_CTS_48MBS FIELD32(0x00ff0000)
412 #define TXRX_CSR8_ACK_CTS_54MBS FIELD32(0xff000000)
415 * TXRX_CSR9: Synchronization control register.
416 * BEACON_INTERVAL: In unit of 1/16 TU.
417 * TSF_TICKING: Enable TSF auto counting.
418 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
419 * BEACON_GEN: Enable beacon generator.
421 #define TXRX_CSR9 0x3064
422 #define TXRX_CSR9_BEACON_INTERVAL FIELD32(0x0000ffff)
423 #define TXRX_CSR9_TSF_TICKING FIELD32(0x00010000)
424 #define TXRX_CSR9_TSF_SYNC FIELD32(0x00060000)
425 #define TXRX_CSR9_TBTT_ENABLE FIELD32(0x00080000)
426 #define TXRX_CSR9_BEACON_GEN FIELD32(0x00100000)
427 #define TXRX_CSR9_TIMESTAMP_COMPENSATE FIELD32(0xff000000)
430 * TXRX_CSR10: BEACON alignment.
432 #define TXRX_CSR10 0x3068
435 * TXRX_CSR11: AES mask.
437 #define TXRX_CSR11 0x306c
440 * TXRX_CSR12: TSF low 32.
442 #define TXRX_CSR12 0x3070
443 #define TXRX_CSR12_LOW_TSFTIMER FIELD32(0xffffffff)
446 * TXRX_CSR13: TSF high 32.
448 #define TXRX_CSR13 0x3074
449 #define TXRX_CSR13_HIGH_TSFTIMER FIELD32(0xffffffff)
452 * TXRX_CSR14: TBTT timer.
454 #define TXRX_CSR14 0x3078
457 * TXRX_CSR15: TKIP MIC priority byte "AND" mask.
459 #define TXRX_CSR15 0x307c
462 * PHY control registers.
463 * Some values are set in TU, whereas 1 TU == 1024 us.
467 * PHY_CSR0: RF/PS control.
469 #define PHY_CSR0 0x3080
470 #define PHY_CSR0_PA_PE_BG FIELD32(0x00010000)
471 #define PHY_CSR0_PA_PE_A FIELD32(0x00020000)
476 #define PHY_CSR1 0x3084
477 #define PHY_CSR1_RF_RPI FIELD32(0x00010000)
480 * PHY_CSR2: Pre-TX BBP control.
482 #define PHY_CSR2 0x3088
485 * PHY_CSR3: BBP serial control register.
486 * VALUE: Register value to program into BBP.
487 * REG_NUM: Selected BBP register.
488 * READ_CONTROL: 0: Write BBP, 1: Read BBP.
489 * BUSY: 1: ASIC is busy execute BBP programming.
491 #define PHY_CSR3 0x308c
492 #define PHY_CSR3_VALUE FIELD32(0x000000ff)
493 #define PHY_CSR3_REGNUM FIELD32(0x00007f00)
494 #define PHY_CSR3_READ_CONTROL FIELD32(0x00008000)
495 #define PHY_CSR3_BUSY FIELD32(0x00010000)
498 * PHY_CSR4: RF serial control register
499 * VALUE: Register value (include register id) serial out to RF/IF chip.
500 * NUMBER_OF_BITS: Number of bits used in RFRegValue (I:20, RFMD:22).
501 * IF_SELECT: 1: select IF to program, 0: select RF to program.
502 * PLL_LD: RF PLL_LD status.
503 * BUSY: 1: ASIC is busy execute RF programming.
505 #define PHY_CSR4 0x3090
506 #define PHY_CSR4_VALUE FIELD32(0x00ffffff)
507 #define PHY_CSR4_NUMBER_OF_BITS FIELD32(0x1f000000)
508 #define PHY_CSR4_IF_SELECT FIELD32(0x20000000)
509 #define PHY_CSR4_PLL_LD FIELD32(0x40000000)
510 #define PHY_CSR4_BUSY FIELD32(0x80000000)
513 * PHY_CSR5: RX to TX signal switch timing control.
515 #define PHY_CSR5 0x3094
516 #define PHY_CSR5_IQ_FLIP FIELD32(0x00000004)
519 * PHY_CSR6: TX to RX signal timing control.
521 #define PHY_CSR6 0x3098
522 #define PHY_CSR6_IQ_FLIP FIELD32(0x00000004)
525 * PHY_CSR7: TX DAC switching timing control.
527 #define PHY_CSR7 0x309c
530 * Security control register.
534 * SEC_CSR0: Shared key table control.
536 #define SEC_CSR0 0x30a0
537 #define SEC_CSR0_BSS0_KEY0_VALID FIELD32(0x00000001)
538 #define SEC_CSR0_BSS0_KEY1_VALID FIELD32(0x00000002)
539 #define SEC_CSR0_BSS0_KEY2_VALID FIELD32(0x00000004)
540 #define SEC_CSR0_BSS0_KEY3_VALID FIELD32(0x00000008)
541 #define SEC_CSR0_BSS1_KEY0_VALID FIELD32(0x00000010)
542 #define SEC_CSR0_BSS1_KEY1_VALID FIELD32(0x00000020)
543 #define SEC_CSR0_BSS1_KEY2_VALID FIELD32(0x00000040)
544 #define SEC_CSR0_BSS1_KEY3_VALID FIELD32(0x00000080)
545 #define SEC_CSR0_BSS2_KEY0_VALID FIELD32(0x00000100)
546 #define SEC_CSR0_BSS2_KEY1_VALID FIELD32(0x00000200)
547 #define SEC_CSR0_BSS2_KEY2_VALID FIELD32(0x00000400)
548 #define SEC_CSR0_BSS2_KEY3_VALID FIELD32(0x00000800)
549 #define SEC_CSR0_BSS3_KEY0_VALID FIELD32(0x00001000)
550 #define SEC_CSR0_BSS3_KEY1_VALID FIELD32(0x00002000)
551 #define SEC_CSR0_BSS3_KEY2_VALID FIELD32(0x00004000)
552 #define SEC_CSR0_BSS3_KEY3_VALID FIELD32(0x00008000)
555 * SEC_CSR1: Shared key table security mode register.
557 #define SEC_CSR1 0x30a4
558 #define SEC_CSR1_BSS0_KEY0_CIPHER_ALG FIELD32(0x00000007)
559 #define SEC_CSR1_BSS0_KEY1_CIPHER_ALG FIELD32(0x00000070)
560 #define SEC_CSR1_BSS0_KEY2_CIPHER_ALG FIELD32(0x00000700)
561 #define SEC_CSR1_BSS0_KEY3_CIPHER_ALG FIELD32(0x00007000)
562 #define SEC_CSR1_BSS1_KEY0_CIPHER_ALG FIELD32(0x00070000)
563 #define SEC_CSR1_BSS1_KEY1_CIPHER_ALG FIELD32(0x00700000)
564 #define SEC_CSR1_BSS1_KEY2_CIPHER_ALG FIELD32(0x07000000)
565 #define SEC_CSR1_BSS1_KEY3_CIPHER_ALG FIELD32(0x70000000)
568 * Pairwise key table valid bitmap registers.
569 * SEC_CSR2: pairwise key table valid bitmap 0.
570 * SEC_CSR3: pairwise key table valid bitmap 1.
572 #define SEC_CSR2 0x30a8
573 #define SEC_CSR3 0x30ac
576 * SEC_CSR4: Pairwise key table lookup control.
578 #define SEC_CSR4 0x30b0
579 #define SEC_CSR4_ENABLE_BSS0 FIELD32(0x00000001)
580 #define SEC_CSR4_ENABLE_BSS1 FIELD32(0x00000002)
581 #define SEC_CSR4_ENABLE_BSS2 FIELD32(0x00000004)
582 #define SEC_CSR4_ENABLE_BSS3 FIELD32(0x00000008)
585 * SEC_CSR5: shared key table security mode register.
587 #define SEC_CSR5 0x30b4
588 #define SEC_CSR5_BSS2_KEY0_CIPHER_ALG FIELD32(0x00000007)
589 #define SEC_CSR5_BSS2_KEY1_CIPHER_ALG FIELD32(0x00000070)
590 #define SEC_CSR5_BSS2_KEY2_CIPHER_ALG FIELD32(0x00000700)
591 #define SEC_CSR5_BSS2_KEY3_CIPHER_ALG FIELD32(0x00007000)
592 #define SEC_CSR5_BSS3_KEY0_CIPHER_ALG FIELD32(0x00070000)
593 #define SEC_CSR5_BSS3_KEY1_CIPHER_ALG FIELD32(0x00700000)
594 #define SEC_CSR5_BSS3_KEY2_CIPHER_ALG FIELD32(0x07000000)
595 #define SEC_CSR5_BSS3_KEY3_CIPHER_ALG FIELD32(0x70000000)
598 * STA control registers.
602 * STA_CSR0: RX PLCP error count & RX FCS error count.
604 #define STA_CSR0 0x30c0
605 #define STA_CSR0_FCS_ERROR FIELD32(0x0000ffff)
606 #define STA_CSR0_PLCP_ERROR FIELD32(0xffff0000)
609 * STA_CSR1: RX False CCA count & RX LONG frame count.
611 #define STA_CSR1 0x30c4
612 #define STA_CSR1_PHYSICAL_ERROR FIELD32(0x0000ffff)
613 #define STA_CSR1_FALSE_CCA_ERROR FIELD32(0xffff0000)
616 * STA_CSR2: TX Beacon count and RX FIFO overflow count.
618 #define STA_CSR2 0x30c8
619 #define STA_CSR2_RX_FIFO_OVERFLOW_COUNT FIELD32(0x0000ffff)
620 #define STA_CSR2_RX_OVERFLOW_COUNT FIELD32(0xffff0000)
623 * STA_CSR3: TX Beacon count.
625 #define STA_CSR3 0x30cc
626 #define STA_CSR3_TX_BEACON_COUNT FIELD32(0x0000ffff)
629 * STA_CSR4: TX Retry count.
631 #define STA_CSR4 0x30d0
632 #define STA_CSR4_TX_NO_RETRY_COUNT FIELD32(0x0000ffff)
633 #define STA_CSR4_TX_ONE_RETRY_COUNT FIELD32(0xffff0000)
636 * STA_CSR5: TX Retry count.
638 #define STA_CSR5 0x30d4
639 #define STA_CSR4_TX_MULTI_RETRY_COUNT FIELD32(0x0000ffff)
640 #define STA_CSR4_TX_RETRY_FAIL_COUNT FIELD32(0xffff0000)
643 * QOS control registers.
647 * QOS_CSR1: TXOP holder MAC address register.
649 #define QOS_CSR1 0x30e4
650 #define QOS_CSR1_BYTE4 FIELD32(0x000000ff)
651 #define QOS_CSR1_BYTE5 FIELD32(0x0000ff00)
654 * QOS_CSR2: TXOP holder timeout register.
656 #define QOS_CSR2 0x30e8
659 * RX QOS-CFPOLL MAC address register.
660 * QOS_CSR3: RX QOS-CFPOLL MAC address 0.
661 * QOS_CSR4: RX QOS-CFPOLL MAC address 1.
663 #define QOS_CSR3 0x30ec
664 #define QOS_CSR4 0x30f0
667 * QOS_CSR5: "QosControl" field of the RX QOS-CFPOLL.
669 #define QOS_CSR5 0x30f4
672 * WMM Scheduler Register
676 * AIFSN_CSR: AIFSN for each EDCA AC.
682 #define AIFSN_CSR 0x0400
683 #define AIFSN_CSR_AIFSN0 FIELD32(0x0000000f)
684 #define AIFSN_CSR_AIFSN1 FIELD32(0x000000f0)
685 #define AIFSN_CSR_AIFSN2 FIELD32(0x00000f00)
686 #define AIFSN_CSR_AIFSN3 FIELD32(0x0000f000)
689 * CWMIN_CSR: CWmin for each EDCA AC.
695 #define CWMIN_CSR 0x0404
696 #define CWMIN_CSR_CWMIN0 FIELD32(0x0000000f)
697 #define CWMIN_CSR_CWMIN1 FIELD32(0x000000f0)
698 #define CWMIN_CSR_CWMIN2 FIELD32(0x00000f00)
699 #define CWMIN_CSR_CWMIN3 FIELD32(0x0000f000)
702 * CWMAX_CSR: CWmax for each EDCA AC.
708 #define CWMAX_CSR 0x0408
709 #define CWMAX_CSR_CWMAX0 FIELD32(0x0000000f)
710 #define CWMAX_CSR_CWMAX1 FIELD32(0x000000f0)
711 #define CWMAX_CSR_CWMAX2 FIELD32(0x00000f00)
712 #define CWMAX_CSR_CWMAX3 FIELD32(0x0000f000)
715 * AC_TXOP_CSR0: AC_BK/AC_BE TXOP register.
716 * AC0_TX_OP: For AC_BK, in unit of 32us.
717 * AC1_TX_OP: For AC_BE, in unit of 32us.
719 #define AC_TXOP_CSR0 0x040c
720 #define AC_TXOP_CSR0_AC0_TX_OP FIELD32(0x0000ffff)
721 #define AC_TXOP_CSR0_AC1_TX_OP FIELD32(0xffff0000)
724 * AC_TXOP_CSR1: AC_VO/AC_VI TXOP register.
725 * AC2_TX_OP: For AC_VI, in unit of 32us.
726 * AC3_TX_OP: For AC_VO, in unit of 32us.
728 #define AC_TXOP_CSR1 0x0410
729 #define AC_TXOP_CSR1_AC2_TX_OP FIELD32(0x0000ffff)
730 #define AC_TXOP_CSR1_AC3_TX_OP FIELD32(0xffff0000)
734 * The wordsize of the BBP is 8 bits.
740 #define BBP_R2_BG_MODE FIELD8(0x20)
745 #define BBP_R3_SMART_MODE FIELD8(0x01)
748 * R4: RX antenna control
749 * FRAME_END: 1 - DPDT, 0 - SPDT (Only valid for 802.11G, RF2527 & RF2529)
753 * ANTENNA_CONTROL semantics (guessed):
754 * 0x1: Software controlled antenna switching (fixed or SW diversity)
755 * 0x2: Hardware diversity.
757 #define BBP_R4_RX_ANTENNA_CONTROL FIELD8(0x03)
758 #define BBP_R4_RX_FRAME_END FIELD8(0x20)
763 #define BBP_R77_RX_ANTENNA FIELD8(0x03)
772 #define RF3_TXPOWER FIELD32(0x00003e00)
777 #define RF4_FREQ_OFFSET FIELD32(0x0003f000)
781 * The wordsize of the EEPROM is 16 bits.
787 #define EEPROM_MAC_ADDR_0 0x0002
788 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
789 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
790 #define EEPROM_MAC_ADDR1 0x0003
791 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
792 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
793 #define EEPROM_MAC_ADDR_2 0x0004
794 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
795 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
799 * ANTENNA_NUM: Number of antenna's.
800 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
801 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
802 * FRAME_TYPE: 0: DPDT , 1: SPDT , noted this bit is valid for g only.
803 * DYN_TXAGC: Dynamic TX AGC control.
804 * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0.
805 * RF_TYPE: Rf_type of this adapter.
807 #define EEPROM_ANTENNA 0x0010
808 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
809 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
810 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
811 #define EEPROM_ANTENNA_FRAME_TYPE FIELD16(0x0040)
812 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
813 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
814 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
818 * EXTERNAL_LNA: External LNA.
820 #define EEPROM_NIC 0x0011
821 #define EEPROM_NIC_EXTERNAL_LNA FIELD16(0x0010)
825 * GEO_A: Default geographical setting for 5GHz band
826 * GEO: Default geographical setting.
828 #define EEPROM_GEOGRAPHY 0x0012
829 #define EEPROM_GEOGRAPHY_GEO_A FIELD16(0x00ff)
830 #define EEPROM_GEOGRAPHY_GEO FIELD16(0xff00)
835 #define EEPROM_BBP_START 0x0013
836 #define EEPROM_BBP_SIZE 16
837 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
838 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
841 * EEPROM TXPOWER 802.11G
843 #define EEPROM_TXPOWER_G_START 0x0023
844 #define EEPROM_TXPOWER_G_SIZE 7
845 #define EEPROM_TXPOWER_G_1 FIELD16(0x00ff)
846 #define EEPROM_TXPOWER_G_2 FIELD16(0xff00)
851 #define EEPROM_FREQ 0x002f
852 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
853 #define EEPROM_FREQ_SEQ_MASK FIELD16(0xff00)
854 #define EEPROM_FREQ_SEQ FIELD16(0x0300)
858 * POLARITY_RDY_G: Polarity RDY_G setting.
859 * POLARITY_RDY_A: Polarity RDY_A setting.
860 * POLARITY_ACT: Polarity ACT setting.
861 * POLARITY_GPIO_0: Polarity GPIO0 setting.
862 * POLARITY_GPIO_1: Polarity GPIO1 setting.
863 * POLARITY_GPIO_2: Polarity GPIO2 setting.
864 * POLARITY_GPIO_3: Polarity GPIO3 setting.
865 * POLARITY_GPIO_4: Polarity GPIO4 setting.
866 * LED_MODE: Led mode.
868 #define EEPROM_LED 0x0030
869 #define EEPROM_LED_POLARITY_RDY_G FIELD16(0x0001)
870 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
871 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
872 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
873 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
874 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
875 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
876 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
877 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
880 * EEPROM TXPOWER 802.11A
882 #define EEPROM_TXPOWER_A_START 0x0031
883 #define EEPROM_TXPOWER_A_SIZE 12
884 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
885 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
888 * EEPROM RSSI offset 802.11BG
890 #define EEPROM_RSSI_OFFSET_BG 0x004d
891 #define EEPROM_RSSI_OFFSET_BG_1 FIELD16(0x00ff)
892 #define EEPROM_RSSI_OFFSET_BG_2 FIELD16(0xff00)
895 * EEPROM RSSI offset 802.11A
897 #define EEPROM_RSSI_OFFSET_A 0x004e
898 #define EEPROM_RSSI_OFFSET_A_1 FIELD16(0x00ff)
899 #define EEPROM_RSSI_OFFSET_A_2 FIELD16(0xff00)
902 * DMA descriptor defines.
904 #define TXD_DESC_SIZE ( 6 * sizeof(__le32) )
905 #define TXINFO_SIZE ( 6 * sizeof(__le32) )
906 #define RXD_DESC_SIZE ( 6 * sizeof(__le32) )
909 * TX descriptor format for TX, PRIO and Beacon Ring.
914 * BURST: Next frame belongs to same "burst" event.
915 * TKIP_MIC: ASIC appends TKIP MIC if TKIP is used.
916 * KEY_TABLE: Use per-client pairwise KEY table.
918 * Key index (0~31) to the pairwise KEY table.
919 * 0~3 to shared KEY table 0 (BSS0).
920 * 4~7 to shared KEY table 1 (BSS1).
921 * 8~11 to shared KEY table 2 (BSS2).
922 * 12~15 to shared KEY table 3 (BSS3).
923 * BURST2: For backward compatibility, set to same value as BURST.
925 #define TXD_W0_BURST FIELD32(0x00000001)
926 #define TXD_W0_VALID FIELD32(0x00000002)
927 #define TXD_W0_MORE_FRAG FIELD32(0x00000004)
928 #define TXD_W0_ACK FIELD32(0x00000008)
929 #define TXD_W0_TIMESTAMP FIELD32(0x00000010)
930 #define TXD_W0_OFDM FIELD32(0x00000020)
931 #define TXD_W0_IFS FIELD32(0x00000040)
932 #define TXD_W0_RETRY_MODE FIELD32(0x00000080)
933 #define TXD_W0_TKIP_MIC FIELD32(0x00000100)
934 #define TXD_W0_KEY_TABLE FIELD32(0x00000200)
935 #define TXD_W0_KEY_INDEX FIELD32(0x0000fc00)
936 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
937 #define TXD_W0_BURST2 FIELD32(0x10000000)
938 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
942 * HOST_Q_ID: EDCA/HCCA queue ID.
943 * HW_SEQUENCE: MAC overwrites the frame sequence number.
944 * BUFFER_COUNT: Number of buffers in this TXD.
946 #define TXD_W1_HOST_Q_ID FIELD32(0x0000000f)
947 #define TXD_W1_AIFSN FIELD32(0x000000f0)
948 #define TXD_W1_CWMIN FIELD32(0x00000f00)
949 #define TXD_W1_CWMAX FIELD32(0x0000f000)
950 #define TXD_W1_IV_OFFSET FIELD32(0x003f0000)
951 #define TXD_W1_HW_SEQUENCE FIELD32(0x10000000)
952 #define TXD_W1_BUFFER_COUNT FIELD32(0xe0000000)
955 * Word2: PLCP information
957 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
958 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
959 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
960 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
965 #define TXD_W3_IV FIELD32(0xffffffff)
970 #define TXD_W4_EIV FIELD32(0xffffffff)
974 * FRAME_OFFSET: Frame start offset inside ASIC TXFIFO (after TXINFO field).
975 * PACKET_ID: Driver assigned packet ID to categorize TXResult in interrupt.
976 * WAITING_DMA_DONE_INT: TXD been filled with data
977 * and waiting for TxDoneISR housekeeping.
979 #define TXD_W5_FRAME_OFFSET FIELD32(0x000000ff)
980 #define TXD_W5_PACKET_ID FIELD32(0x0000ff00)
981 #define TXD_W5_TX_POWER FIELD32(0x00ff0000)
982 #define TXD_W5_WAITING_DMA_DONE_INT FIELD32(0x01000000)
985 * RX descriptor format for RX Ring.
990 * CIPHER_ERROR: 1:ICV error, 2:MIC error, 3:invalid key.
991 * KEY_INDEX: Decryption key actually used.
993 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
994 #define RXD_W0_DROP FIELD32(0x00000002)
995 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000004)
996 #define RXD_W0_MULTICAST FIELD32(0x00000008)
997 #define RXD_W0_BROADCAST FIELD32(0x00000010)
998 #define RXD_W0_MY_BSS FIELD32(0x00000020)
999 #define RXD_W0_CRC_ERROR FIELD32(0x00000040)
1000 #define RXD_W0_OFDM FIELD32(0x00000080)
1001 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000300)
1002 #define RXD_W0_KEY_INDEX FIELD32(0x0000fc00)
1003 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1004 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1008 * SIGNAL: RX raw data rate reported by BBP.
1009 * RSSI: RSSI reported by BBP.
1011 #define RXD_W1_SIGNAL FIELD32(0x000000ff)
1012 #define RXD_W1_RSSI_AGC FIELD32(0x00001f00)
1013 #define RXD_W1_RSSI_LNA FIELD32(0x00006000)
1014 #define RXD_W1_FRAME_OFFSET FIELD32(0x7f000000)
1018 * IV: Received IV of originally encrypted.
1020 #define RXD_W2_IV FIELD32(0xffffffff)
1024 * EIV: Received EIV of originally encrypted.
1026 #define RXD_W3_EIV FIELD32(0xffffffff)
1030 * ICV: Received ICV of originally encrypted.
1031 * NOTE: This is a guess, the official definition is "reserved"
1033 #define RXD_W4_ICV FIELD32(0xffffffff)
1036 * the above 20-byte is called RXINFO and will be DMAed to MAC RX block
1037 * and passed to the HOST driver.
1038 * The following fields are for DMA block and HOST usage only.
1039 * Can't be touched by ASIC MAC block.
1045 #define RXD_W5_RESERVED FIELD32(0xffffffff)
1048 * Macro's for converting txpower from EEPROM to mac80211 value
1049 * and from mac80211 value to register value.
1051 #define MIN_TXPOWER 0
1052 #define MAX_TXPOWER 31
1053 #define DEFAULT_TXPOWER 24
1055 #define TXPOWER_FROM_DEV(__txpower) \
1056 (((u8)(__txpower)) > MAX_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
1058 #define TXPOWER_TO_DEV(__txpower) \
1059 clamp_t(char, __txpower, MIN_TXPOWER, MAX_TXPOWER)
1061 #endif /* RT73USB_H */