arch/arm/mach-omap2/mcbsp.c

   1 /*
   2  * linux/arch/arm/mach-omap2/mcbsp.c
   3  *
   4  * Copyright (C) 2008 Instituto Nokia de Tecnologia
   5  * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * Multichannel mode not supported.
  12  */
  13 #include <linux/module.h>
  14 #include <linux/init.h>
  15 #include <linux/clk.h>
  16 #include <linux/err.h>
  17 #include <linux/io.h>
  18 #include <linux/platform_device.h>
  19
  20 #include <mach/irqs.h>
  21 #include <plat/dma.h>
  22 #include <plat/mux.h>
  23 #include <plat/cpu.h>
  24 #include <plat/mcbsp.h>
  25
  26 static void omap2_mcbsp2_mux_setup(void)
  27 {
  28         omap_cfg_reg(Y15_24XX_MCBSP2_CLKX);
  29         omap_cfg_reg(R14_24XX_MCBSP2_FSX);
  30         omap_cfg_reg(W15_24XX_MCBSP2_DR);
  31         omap_cfg_reg(V15_24XX_MCBSP2_DX);
  32         omap_cfg_reg(V14_24XX_GPIO117);
  33         /*
  34          * TODO: Need to add MUX settings for OMAP 2430 SDP
  35          */
  36 }
  37
  38 static void omap2_mcbsp_request(unsigned int id)
  39 {
  40         if (cpu_is_omap2420() && (id == OMAP_MCBSP2))
  41                 omap2_mcbsp2_mux_setup();
  42 }
  43
  44 static struct omap_mcbsp_ops omap2_mcbsp_ops = {
  45         .request        = omap2_mcbsp_request,
  46 };
  47
  48 #ifdef CONFIG_ARCH_OMAP2420
  49 static struct omap_mcbsp_platform_data omap2420_mcbsp_pdata[] = {
  50         {
  51                 .phys_base      = OMAP24XX_MCBSP1_BASE,
  52                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
  53                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
  54                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
  55                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
  56                 .ops            = &omap2_mcbsp_ops,
  57         },
  58         {
  59                 .phys_base      = OMAP24XX_MCBSP2_BASE,
  60                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
  61                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
  62                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
  63                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
  64                 .ops            = &omap2_mcbsp_ops,
  65         },
  66 };
  67 #define OMAP2420_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2420_mcbsp_pdata)
  68 #define OMAP2420_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
  69 #else
  70 #define omap2420_mcbsp_pdata            NULL
  71 #define OMAP2420_MCBSP_PDATA_SZ         0
  72 #define OMAP2420_MCBSP_REG_NUM          0
  73 #endif
  74
  75 #ifdef CONFIG_ARCH_OMAP2430
  76 static struct omap_mcbsp_platform_data omap2430_mcbsp_pdata[] = {
  77         {
  78                 .phys_base      = OMAP24XX_MCBSP1_BASE,
  79                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
  80                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
  81                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
  82                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
  83                 .ops            = &omap2_mcbsp_ops,
  84         },
  85         {
  86                 .phys_base      = OMAP24XX_MCBSP2_BASE,
  87                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
  88                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
  89                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
  90                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
  91                 .ops            = &omap2_mcbsp_ops,
  92         },
  93         {
  94                 .phys_base      = OMAP2430_MCBSP3_BASE,
  95                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
  96                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
  97                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
  98                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
  99                 .ops            = &omap2_mcbsp_ops,
 100         },
 101         {
 102                 .phys_base      = OMAP2430_MCBSP4_BASE,
 103                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
 104                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
 105                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
 106                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
 107                 .ops            = &omap2_mcbsp_ops,
 108         },
 109         {
 110                 .phys_base      = OMAP2430_MCBSP5_BASE,
 111                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
 112                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
 113                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
 114                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
 115                 .ops            = &omap2_mcbsp_ops,
 116         },
 117 };
 118 #define OMAP2430_MCBSP_PDATA_SZ         ARRAY_SIZE(omap2430_mcbsp_pdata)
 119 #define OMAP2430_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 120 #else
 121 #define omap2430_mcbsp_pdata            NULL
 122 #define OMAP2430_MCBSP_PDATA_SZ         0
 123 #define OMAP2430_MCBSP_REG_NUM          0
 124 #endif
 125
 126 #ifdef CONFIG_ARCH_OMAP3
 127 static struct omap_mcbsp_platform_data omap34xx_mcbsp_pdata[] = {
 128         {
 129                 .phys_base      = OMAP34XX_MCBSP1_BASE,
 130                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP1_RX,
 131                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP1_TX,
 132                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
 133                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
 134                 .ops            = &omap2_mcbsp_ops,
 135                 .buffer_size    = 0x6F,
 136         },
 137         {
 138                 .phys_base      = OMAP34XX_MCBSP2_BASE,
 139                 .phys_base_st   = OMAP34XX_MCBSP2_ST_BASE,
 140                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP2_RX,
 141                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP2_TX,
 142                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
 143                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
 144                 .ops            = &omap2_mcbsp_ops,
 145                 .buffer_size    = 0x3FF,
 146         },
 147         {
 148                 .phys_base      = OMAP34XX_MCBSP3_BASE,
 149                 .phys_base_st   = OMAP34XX_MCBSP3_ST_BASE,
 150                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP3_RX,
 151                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP3_TX,
 152                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
 153                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
 154                 .ops            = &omap2_mcbsp_ops,
 155                 .buffer_size    = 0x6F,
 156         },
 157         {
 158                 .phys_base      = OMAP34XX_MCBSP4_BASE,
 159                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP4_RX,
 160                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP4_TX,
 161                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
 162                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
 163                 .ops            = &omap2_mcbsp_ops,
 164                 .buffer_size    = 0x6F,
 165         },
 166         {
 167                 .phys_base      = OMAP34XX_MCBSP5_BASE,
 168                 .dma_rx_sync    = OMAP24XX_DMA_MCBSP5_RX,
 169                 .dma_tx_sync    = OMAP24XX_DMA_MCBSP5_TX,
 170                 .rx_irq         = INT_24XX_MCBSP5_IRQ_RX,
 171                 .tx_irq         = INT_24XX_MCBSP5_IRQ_TX,
 172                 .ops            = &omap2_mcbsp_ops,
 173                 .buffer_size    = 0x6F,
 174         },
 175 };
 176 #define OMAP34XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap34xx_mcbsp_pdata)
 177 #define OMAP34XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 178 #else
 179 #define omap34xx_mcbsp_pdata            NULL
 180 #define OMAP34XX_MCBSP_PDATA_SZ         0
 181 #define OMAP34XX_MCBSP_REG_NUM          0
 182 #endif
 183
 184 static struct omap_mcbsp_platform_data omap44xx_mcbsp_pdata[] = {
 185         {
 186                 .phys_base      = OMAP44XX_MCBSP1_BASE,
 187                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP1_RX,
 188                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP1_TX,
 189                 .rx_irq         = INT_24XX_MCBSP1_IRQ_RX,
 190                 .tx_irq         = INT_24XX_MCBSP1_IRQ_TX,
 191                 .ops            = &omap2_mcbsp_ops,
 192         },
 193         {
 194                 .phys_base      = OMAP44XX_MCBSP2_BASE,
 195                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP2_RX,
 196                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP2_TX,
 197                 .rx_irq         = INT_24XX_MCBSP2_IRQ_RX,
 198                 .tx_irq         = INT_24XX_MCBSP2_IRQ_TX,
 199                 .ops            = &omap2_mcbsp_ops,
 200         },
 201         {
 202                 .phys_base      = OMAP44XX_MCBSP3_BASE,
 203                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP3_RX,
 204                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP3_TX,
 205                 .rx_irq         = INT_24XX_MCBSP3_IRQ_RX,
 206                 .tx_irq         = INT_24XX_MCBSP3_IRQ_TX,
 207                 .ops            = &omap2_mcbsp_ops,
 208         },
 209         {
 210                 .phys_base      = OMAP44XX_MCBSP4_BASE,
 211                 .dma_rx_sync    = OMAP44XX_DMA_MCBSP4_RX,
 212                 .dma_tx_sync    = OMAP44XX_DMA_MCBSP4_TX,
 213                 .rx_irq         = INT_24XX_MCBSP4_IRQ_RX,
 214                 .tx_irq         = INT_24XX_MCBSP4_IRQ_TX,
 215                 .ops            = &omap2_mcbsp_ops,
 216         },
 217 };
 218 #define OMAP44XX_MCBSP_PDATA_SZ         ARRAY_SIZE(omap44xx_mcbsp_pdata)
 219 #define OMAP44XX_MCBSP_REG_NUM          (OMAP_MCBSP_REG_RCCR / sizeof(u32) + 1)
 220
 221 static int __init omap2_mcbsp_init(void)
 222 {
 223         if (cpu_is_omap2420()) {
 224                 omap_mcbsp_count = OMAP2420_MCBSP_PDATA_SZ;
 225                 omap_mcbsp_cache_size = OMAP2420_MCBSP_REG_NUM * sizeof(u16);
 226         } else if (cpu_is_omap2430()) {
 227                 omap_mcbsp_count = OMAP2430_MCBSP_PDATA_SZ;
 228                 omap_mcbsp_cache_size = OMAP2430_MCBSP_REG_NUM * sizeof(u32);
 229         } else if (cpu_is_omap34xx()) {
 230                 omap_mcbsp_count = OMAP34XX_MCBSP_PDATA_SZ;
 231                 omap_mcbsp_cache_size = OMAP34XX_MCBSP_REG_NUM * sizeof(u32);
 232         } else if (cpu_is_omap44xx()) {
 233                 omap_mcbsp_count = OMAP44XX_MCBSP_PDATA_SZ;
 234                 omap_mcbsp_cache_size = OMAP44XX_MCBSP_REG_NUM * sizeof(u32);
 235         }
 236
 237         mcbsp_ptr = kzalloc(omap_mcbsp_count * sizeof(struct omap_mcbsp *),
 238                                                                 GFP_KERNEL);
 239         if (!mcbsp_ptr)
 240                 return -ENOMEM;
 241
 242         if (cpu_is_omap2420())
 243                 omap_mcbsp_register_board_cfg(omap2420_mcbsp_pdata,
 244                                                 OMAP2420_MCBSP_PDATA_SZ);
 245         if (cpu_is_omap2430())
 246                 omap_mcbsp_register_board_cfg(omap2430_mcbsp_pdata,
 247                                                 OMAP2430_MCBSP_PDATA_SZ);
 248         if (cpu_is_omap34xx())
 249                 omap_mcbsp_register_board_cfg(omap34xx_mcbsp_pdata,
 250                                                 OMAP34XX_MCBSP_PDATA_SZ);
 251         if (cpu_is_omap44xx())
 252                 omap_mcbsp_register_board_cfg(omap44xx_mcbsp_pdata,
 253                                                 OMAP44XX_MCBSP_PDATA_SZ);
 254
 255         return omap_mcbsp_init();
 256 }
 257 arch_initcall(omap2_mcbsp_init);