arch/arm/mach-omap2/board-sdp-flash.c

   1 /*
   2  * board-sdp-flash.c
   3  * Modified from mach-omap2/board-3430sdp-flash.c
   4  *
   5  * Copyright (C) 2009 Nokia Corporation
   6  * Copyright (C) 2009 Texas Instruments
   7  *
   8  * Vimal Singh <vimalsingh@ti.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/mtd/physmap.h>
  18 #include <linux/io.h>
  19
  20 #include <plat/gpmc.h>
  21 #include <plat/nand.h>
  22 #include <plat/onenand.h>
  23 #include <plat/tc.h>
  24 #include <mach/board-sdp.h>
  25
  26 #define REG_FPGA_REV                    0x10
  27 #define REG_FPGA_DIP_SWITCH_INPUT2      0x60
  28 #define MAX_SUPPORTED_GPMC_CONFIG       3
  29
  30 #define DEBUG_BASE              0x08000000 /* debug board */
  31
  32 #define PDC_NOR         1
  33 #define PDC_NAND        2
  34 #define PDC_ONENAND     3
  35 #define DBG_MPDB        4
  36
  37 /* various memory sizes */
  38 #define FLASH_SIZE_SDPV1        SZ_64M  /* NOR flash (64 Meg aligned) */
  39 #define FLASH_SIZE_SDPV2        SZ_128M /* NOR flash (256 Meg aligned) */
  40
  41 /*
  42  * SDP3430 V2 Board CS organization
  43  * Different from SDP3430 V1. Now 4 switches used to specify CS
  44  *
  45  * See also the Switch S8 settings in the comments.
  46  *
  47  * REVISIT: Add support for 2430 SDP
  48  */
  49 static const unsigned char chip_sel_sdp[][GPMC_CS_NUM] = {
  50         {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
  51         {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
  52         {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
  53 };
  54
  55 static struct physmap_flash_data sdp_nor_data = {
  56         .width          = 2,
  57 };
  58
  59 static struct resource sdp_nor_resource = {
  60         .flags          = IORESOURCE_MEM,
  61 };
  62
  63 static struct platform_device sdp_nor_device = {
  64         .name           = "physmap-flash",
  65         .id             = 0,
  66         .dev            = {
  67                         .platform_data = &sdp_nor_data,
  68         },
  69         .num_resources  = 1,
  70         .resource       = &sdp_nor_resource,
  71 };
  72
  73 static void
  74 __init board_nor_init(struct flash_partitions sdp_nor_parts, u8 cs)
  75 {
  76         int err;
  77
  78         sdp_nor_data.parts      = sdp_nor_parts.parts;
  79         sdp_nor_data.nr_parts   = sdp_nor_parts.nr_parts;
  80
  81         /* Configure start address and size of NOR device */
  82         if (omap_rev() >= OMAP3430_REV_ES1_0) {
  83                 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV2 - 1,
  84                                 (unsigned long *)&sdp_nor_resource.start);
  85                 sdp_nor_resource.end = sdp_nor_resource.start
  86                                         + FLASH_SIZE_SDPV2 - 1;
  87         } else {
  88                 err = gpmc_cs_request(cs, FLASH_SIZE_SDPV1 - 1,
  89                                 (unsigned long *)&sdp_nor_resource.start);
  90                 sdp_nor_resource.end = sdp_nor_resource.start
  91                                         + FLASH_SIZE_SDPV1 - 1;
  92         }
  93         if (err < 0) {
  94                 printk(KERN_ERR "NOR: Can't request GPMC CS\n");
  95                 return;
  96         }
  97         if (platform_device_register(&sdp_nor_device) < 0)
  98                 printk(KERN_ERR "Unable to register NOR device\n");
  99 }
 100
 101 #if defined(CONFIG_MTD_ONENAND_OMAP2) || \
 102                 defined(CONFIG_MTD_ONENAND_OMAP2_MODULE)
 103 static struct omap_onenand_platform_data board_onenand_data = {
 104         .dma_channel    = -1,   /* disable DMA in OMAP OneNAND driver */
 105 };
 106
 107 static void
 108 __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
 109 {
 110         board_onenand_data.cs           = cs;
 111         board_onenand_data.parts        = sdp_onenand_parts.parts;
 112         board_onenand_data.nr_parts     = sdp_onenand_parts.nr_parts;
 113
 114         gpmc_onenand_init(&board_onenand_data);
 115 }
 116 #else
 117 static void
 118 __init board_onenand_init(struct flash_partitions sdp_onenand_parts, u8 cs)
 119 {
 120 }
 121 #endif /* CONFIG_MTD_ONENAND_OMAP2 || CONFIG_MTD_ONENAND_OMAP2_MODULE */
 122
 123 #if defined(CONFIG_MTD_NAND_OMAP2) || \
 124                 defined(CONFIG_MTD_NAND_OMAP2_MODULE)
 125
 126 /* Note that all values in this struct are in nanoseconds */
 127 static struct gpmc_timings nand_timings = {
 128
 129         .sync_clk = 0,
 130
 131         .cs_on = 0,
 132         .cs_rd_off = 36,
 133         .cs_wr_off = 36,
 134
 135         .adv_on = 6,
 136         .adv_rd_off = 24,
 137         .adv_wr_off = 36,
 138
 139         .we_off = 30,
 140         .oe_off = 48,
 141
 142         .access = 54,
 143         .rd_cycle = 72,
 144         .wr_cycle = 72,
 145
 146         .wr_access = 30,
 147         .wr_data_mux_bus = 0,
 148 };
 149
 150 static struct omap_nand_platform_data sdp_nand_data = {
 151         .nand_setup     = NULL,
 152         .gpmc_t         = &nand_timings,
 153         .dma_channel    = -1,           /* disable DMA in OMAP NAND driver */
 154         .dev_ready      = NULL,
 155         .devsize        = 0,    /* '0' for 8-bit, '1' for 16-bit device */
 156 };
 157
 158 static void
 159 __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
 160 {
 161         sdp_nand_data.cs                = cs;
 162         sdp_nand_data.parts             = sdp_nand_parts.parts;
 163         sdp_nand_data.nr_parts          = sdp_nand_parts.nr_parts;
 164
 165         sdp_nand_data.gpmc_cs_baseaddr  = (void *)(OMAP34XX_GPMC_VIRT +
 166                                                         GPMC_CS0_BASE +
 167                                                         cs * GPMC_CS_SIZE);
 168         sdp_nand_data.gpmc_baseaddr      = (void *) (OMAP34XX_GPMC_VIRT);
 169
 170         gpmc_nand_init(&sdp_nand_data);
 171 }
 172 #else
 173 static void
 174 __init board_nand_init(struct flash_partitions sdp_nand_parts, u8 cs)
 175 {
 176 }
 177 #endif /* CONFIG_MTD_NAND_OMAP2 || CONFIG_MTD_NAND_OMAP2_MODULE */
 178
 179 /**
 180  * get_gpmc0_type - Reads the FPGA DIP_SWITCH_INPUT_REGISTER2 to get
 181  * the various cs values.
 182  */
 183 static u8 get_gpmc0_type(void)
 184 {
 185         u8 cs = 0;
 186         void __iomem *fpga_map_addr;
 187
 188         fpga_map_addr = ioremap(DEBUG_BASE, 4096);
 189         if (!fpga_map_addr)
 190                 return -ENOMEM;
 191
 192         if (!(__raw_readw(fpga_map_addr + REG_FPGA_REV)))
 193                 /* we dont have an DEBUG FPGA??? */
 194                 /* Depend on #defines!! default to strata boot return param */
 195                 goto unmap;
 196
 197         /* S8-DIP-OFF = 1, S8-DIP-ON = 0 */
 198         cs = __raw_readw(fpga_map_addr + REG_FPGA_DIP_SWITCH_INPUT2) & 0xf;
 199
 200         /* ES2.0 SDP's onwards 4 dip switches are provided for CS */
 201         if (omap_rev() >= OMAP3430_REV_ES1_0)
 202                 /* change (S8-1:4=DS-2:0) to (S8-4:1=DS-2:0) */
 203                 cs = ((cs & 8) >> 3) | ((cs & 4) >> 1) |
 204                         ((cs & 2) << 1) | ((cs & 1) << 3);
 205         else
 206                 /* change (S8-1:3=DS-2:0) to (S8-3:1=DS-2:0) */
 207                 cs = ((cs & 4) >> 2) | (cs & 2) | ((cs & 1) << 2);
 208 unmap:
 209         iounmap(fpga_map_addr);
 210         return cs;
 211 }
 212
 213 /**
 214  * sdp3430_flash_init - Identify devices connected to GPMC and register.
 215  *
 216  * @return - void.
 217  */
 218 void __init sdp_flash_init(struct flash_partitions sdp_partition_info[])
 219 {
 220         u8              cs = 0;
 221         u8              norcs = GPMC_CS_NUM + 1;
 222         u8              nandcs = GPMC_CS_NUM + 1;
 223         u8              onenandcs = GPMC_CS_NUM + 1;
 224         u8              idx;
 225         unsigned char   *config_sel = NULL;
 226
 227         /* REVISIT: Is this return correct idx for 2430 SDP?
 228          * for which cs configuration matches for 2430 SDP?
 229          */
 230         idx = get_gpmc0_type();
 231         if (idx >= MAX_SUPPORTED_GPMC_CONFIG) {
 232                 printk(KERN_ERR "%s: Invalid chip select: %d\n", __func__, cs);
 233                 return;
 234         }
 235         config_sel = (unsigned char *)(chip_sel_sdp[idx]);
 236
 237         while (cs < GPMC_CS_NUM) {
 238                 switch (config_sel[cs]) {
 239                 case PDC_NOR:
 240                         if (norcs > GPMC_CS_NUM)
 241                                 norcs = cs;
 242                         break;
 243                 case PDC_NAND:
 244                         if (nandcs > GPMC_CS_NUM)
 245                                 nandcs = cs;
 246                         break;
 247                 case PDC_ONENAND:
 248                         if (onenandcs > GPMC_CS_NUM)
 249                                 onenandcs = cs;
 250                         break;
 251                 };
 252                 cs++;
 253         }
 254
 255         if (norcs > GPMC_CS_NUM)
 256                 printk(KERN_INFO "OneNAND: Unable to find configuration "
 257                                 " in GPMC\n ");
 258         else
 259                 board_nor_init(sdp_partition_info[0], norcs);
 260
 261         if (onenandcs > GPMC_CS_NUM)
 262                 printk(KERN_INFO "OneNAND: Unable to find configuration "
 263                                 " in GPMC\n ");
 264         else
 265                 board_onenand_init(sdp_partition_info[1], onenandcs);
 266
 267         if (nandcs > GPMC_CS_NUM)
 268                 printk(KERN_INFO "NAND: Unable to find configuration "
 269                                 " in GPMC\n ");
 270         else
 271                 board_nand_init(sdp_partition_info[2], nandcs);
 272 }