2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/stddef.h>
22 #include <asm/mipsregs.h>
23 #include <asm/system.h>
24 #include <asm/watch.h>
27 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
28 * the implementation of the "wait" feature differs between CPU families. This
29 * points to the function that implements CPU specific wait.
30 * The wait instruction stops the pipeline and reduces the power consumption of
33 void (*cpu_wait
)(void) = NULL
;
35 static void r3081_wait(void)
37 unsigned long cfg
= read_c0_conf();
38 write_c0_conf(cfg
| R30XX_CONF_HALT
);
41 static void r39xx_wait(void)
45 write_c0_conf(read_c0_conf() | TX39_CONF_HALT
);
49 extern void r4k_wait(void);
52 * This variant is preferable as it allows testing need_resched and going to
53 * sleep depending on the outcome atomically. Unfortunately the "It is
54 * implementation-dependent whether the pipeline restarts when a non-enabled
55 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
56 * using this version a gamble.
58 void r4k_wait_irqoff(void)
62 __asm__(" .set push \n"
67 __asm__(" .globl __pastwait \n"
73 * The RM7000 variant has to handle erratum 38. The workaround is to not
74 * have any pending stores when the WAIT instruction is executed.
76 static void rm7k_wait_irqoff(void)
86 " mtc0 $1, $12 # stalls until W stage \n"
88 " mtc0 $1, $12 # stalls until W stage \n"
93 /* The Au1xxx wait is available only if using 32khz counter or
94 * external timer source, but specifically not CP0 Counter. */
97 static void au1k_wait(void)
102 /* using the wait instruction makes CP0 counter unusable */
103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
114 : : "r" (au1k_wait
));
117 static int __initdata nowait
= 0;
119 static int __init
wait_disable(char *s
)
126 __setup("nowait", wait_disable
);
128 void __init
check_wait(void)
130 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
133 printk("Wait instruction disabled.\n");
137 switch (c
->cputype
) {
140 cpu_wait
= r3081_wait
;
143 cpu_wait
= r39xx_wait
;
146 /* case CPU_R4300: */
161 case CPU_CAVIUM_OCTEON
:
166 cpu_wait
= rm7k_wait_irqoff
;
173 if (read_c0_config7() & MIPS_CONF7_WII
)
174 cpu_wait
= r4k_wait_irqoff
;
179 if ((c
->processor_id
& 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
180 cpu_wait
= r4k_wait_irqoff
;
184 cpu_wait
= r4k_wait_irqoff
;
193 cpu_wait
= au1k_wait
;
197 * WAIT on Rev1.0 has E1, E2, E3 and E16.
198 * WAIT on Rev2.0 and Rev3.0 has E16.
199 * Rev3.1 WAIT is nop, why bother
201 if ((c
->processor_id
& 0xff) <= 0x64)
205 * Another rev is incremeting c0_count at a reduced clock
206 * rate while in WAIT mode. So we basically have the choice
207 * between using the cp0 timer as clocksource or avoiding
208 * the WAIT instruction. Until more details are known,
209 * disable the use of WAIT for 20Kc entirely.
214 if ((c
->processor_id
& 0x00ff) >= 0x40)
222 static inline void check_errata(void)
224 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
226 switch (c
->cputype
) {
229 * Erratum "RPS May Cause Incorrect Instruction Execution"
230 * This code only handles VPE0, any SMP/SMTC/RTOS code
231 * making use of VPE1 will be responsable for that VPE.
233 if ((c
->processor_id
& PRID_REV_MASK
) <= PRID_REV_34K_V1_0_2
)
234 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS
);
241 void __init
check_bugs32(void)
247 * Probe whether cpu has config register by trying to play with
248 * alternate cache bit and see whether it matters.
249 * It's used by cpu_probe to distinguish between R3000A and R3081.
251 static inline int cpu_has_confreg(void)
253 #ifdef CONFIG_CPU_R3000
254 extern unsigned long r3k_cache_size(unsigned long);
255 unsigned long size1
, size2
;
256 unsigned long cfg
= read_c0_conf();
258 size1
= r3k_cache_size(ST0_ISC
);
259 write_c0_conf(cfg
^ R30XX_CONF_AC
);
260 size2
= r3k_cache_size(ST0_ISC
);
262 return size1
!= size2
;
269 * Get the FPU Implementation/Revision.
271 static inline unsigned long cpu_get_fpu_id(void)
273 unsigned long tmp
, fpu_id
;
275 tmp
= read_c0_status();
277 fpu_id
= read_32bit_cp1_register(CP1_REVISION
);
278 write_c0_status(tmp
);
283 * Check the CPU has an FPU the official way.
285 static inline int __cpu_has_fpu(void)
287 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE
);
290 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
293 static inline void cpu_probe_legacy(struct cpuinfo_mips
*c
, unsigned int cpu
)
295 switch (c
->processor_id
& 0xff00) {
297 c
->cputype
= CPU_R2000
;
298 __cpu_name
[cpu
] = "R2000";
299 c
->isa_level
= MIPS_CPU_ISA_I
;
300 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
303 c
->options
|= MIPS_CPU_FPU
;
307 if ((c
->processor_id
& 0xff) == PRID_REV_R3000A
) {
308 if (cpu_has_confreg()) {
309 c
->cputype
= CPU_R3081E
;
310 __cpu_name
[cpu
] = "R3081";
312 c
->cputype
= CPU_R3000A
;
313 __cpu_name
[cpu
] = "R3000A";
317 c
->cputype
= CPU_R3000
;
318 __cpu_name
[cpu
] = "R3000";
320 c
->isa_level
= MIPS_CPU_ISA_I
;
321 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_3K_CACHE
|
324 c
->options
|= MIPS_CPU_FPU
;
328 if (read_c0_config() & CONF_SC
) {
329 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
330 c
->cputype
= CPU_R4400PC
;
331 __cpu_name
[cpu
] = "R4400PC";
333 c
->cputype
= CPU_R4000PC
;
334 __cpu_name
[cpu
] = "R4000PC";
337 if ((c
->processor_id
& 0xff) >= PRID_REV_R4400
) {
338 c
->cputype
= CPU_R4400SC
;
339 __cpu_name
[cpu
] = "R4400SC";
341 c
->cputype
= CPU_R4000SC
;
342 __cpu_name
[cpu
] = "R4000SC";
346 c
->isa_level
= MIPS_CPU_ISA_III
;
347 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
348 MIPS_CPU_WATCH
| MIPS_CPU_VCE
|
352 case PRID_IMP_VR41XX
:
353 switch (c
->processor_id
& 0xf0) {
354 case PRID_REV_VR4111
:
355 c
->cputype
= CPU_VR4111
;
356 __cpu_name
[cpu
] = "NEC VR4111";
358 case PRID_REV_VR4121
:
359 c
->cputype
= CPU_VR4121
;
360 __cpu_name
[cpu
] = "NEC VR4121";
362 case PRID_REV_VR4122
:
363 if ((c
->processor_id
& 0xf) < 0x3) {
364 c
->cputype
= CPU_VR4122
;
365 __cpu_name
[cpu
] = "NEC VR4122";
367 c
->cputype
= CPU_VR4181A
;
368 __cpu_name
[cpu
] = "NEC VR4181A";
371 case PRID_REV_VR4130
:
372 if ((c
->processor_id
& 0xf) < 0x4) {
373 c
->cputype
= CPU_VR4131
;
374 __cpu_name
[cpu
] = "NEC VR4131";
376 c
->cputype
= CPU_VR4133
;
377 __cpu_name
[cpu
] = "NEC VR4133";
381 printk(KERN_INFO
"Unexpected CPU of NEC VR4100 series\n");
382 c
->cputype
= CPU_VR41XX
;
383 __cpu_name
[cpu
] = "NEC Vr41xx";
386 c
->isa_level
= MIPS_CPU_ISA_III
;
387 c
->options
= R4K_OPTS
;
391 c
->cputype
= CPU_R4300
;
392 __cpu_name
[cpu
] = "R4300";
393 c
->isa_level
= MIPS_CPU_ISA_III
;
394 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
399 c
->cputype
= CPU_R4600
;
400 __cpu_name
[cpu
] = "R4600";
401 c
->isa_level
= MIPS_CPU_ISA_III
;
402 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
409 * This processor doesn't have an MMU, so it's not
410 * "real easy" to run Linux on it. It is left purely
411 * for documentation. Commented out because it shares
412 * it's c0_prid id number with the TX3900.
414 c
->cputype
= CPU_R4650
;
415 __cpu_name
[cpu
] = "R4650";
416 c
->isa_level
= MIPS_CPU_ISA_III
;
417 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_LLSC
;
422 c
->isa_level
= MIPS_CPU_ISA_I
;
423 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_TX39_CACHE
;
425 if ((c
->processor_id
& 0xf0) == (PRID_REV_TX3927
& 0xf0)) {
426 c
->cputype
= CPU_TX3927
;
427 __cpu_name
[cpu
] = "TX3927";
430 switch (c
->processor_id
& 0xff) {
431 case PRID_REV_TX3912
:
432 c
->cputype
= CPU_TX3912
;
433 __cpu_name
[cpu
] = "TX3912";
436 case PRID_REV_TX3922
:
437 c
->cputype
= CPU_TX3922
;
438 __cpu_name
[cpu
] = "TX3922";
445 c
->cputype
= CPU_R4700
;
446 __cpu_name
[cpu
] = "R4700";
447 c
->isa_level
= MIPS_CPU_ISA_III
;
448 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
453 c
->cputype
= CPU_TX49XX
;
454 __cpu_name
[cpu
] = "R49XX";
455 c
->isa_level
= MIPS_CPU_ISA_III
;
456 c
->options
= R4K_OPTS
| MIPS_CPU_LLSC
;
457 if (!(c
->processor_id
& 0x08))
458 c
->options
|= MIPS_CPU_FPU
| MIPS_CPU_32FPR
;
462 c
->cputype
= CPU_R5000
;
463 __cpu_name
[cpu
] = "R5000";
464 c
->isa_level
= MIPS_CPU_ISA_IV
;
465 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
470 c
->cputype
= CPU_R5432
;
471 __cpu_name
[cpu
] = "R5432";
472 c
->isa_level
= MIPS_CPU_ISA_IV
;
473 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
474 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
478 c
->cputype
= CPU_R5500
;
479 __cpu_name
[cpu
] = "R5500";
480 c
->isa_level
= MIPS_CPU_ISA_IV
;
481 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
482 MIPS_CPU_WATCH
| MIPS_CPU_LLSC
;
485 case PRID_IMP_NEVADA
:
486 c
->cputype
= CPU_NEVADA
;
487 __cpu_name
[cpu
] = "Nevada";
488 c
->isa_level
= MIPS_CPU_ISA_IV
;
489 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
490 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
;
494 c
->cputype
= CPU_R6000
;
495 __cpu_name
[cpu
] = "R6000";
496 c
->isa_level
= MIPS_CPU_ISA_II
;
497 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
501 case PRID_IMP_R6000A
:
502 c
->cputype
= CPU_R6000A
;
503 __cpu_name
[cpu
] = "R6000A";
504 c
->isa_level
= MIPS_CPU_ISA_II
;
505 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_FPU
|
509 case PRID_IMP_RM7000
:
510 c
->cputype
= CPU_RM7000
;
511 __cpu_name
[cpu
] = "RM7000";
512 c
->isa_level
= MIPS_CPU_ISA_IV
;
513 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
516 * Undocumented RM7000: Bit 29 in the info register of
517 * the RM7000 v2.0 indicates if the TLB has 48 or 64
520 * 29 1 => 64 entry JTLB
523 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
525 case PRID_IMP_RM9000
:
526 c
->cputype
= CPU_RM9000
;
527 __cpu_name
[cpu
] = "RM9000";
528 c
->isa_level
= MIPS_CPU_ISA_IV
;
529 c
->options
= R4K_OPTS
| MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
532 * Bit 29 in the info register of the RM9000
533 * indicates if the TLB has 48 or 64 entries.
535 * 29 1 => 64 entry JTLB
538 c
->tlbsize
= (read_c0_info() & (1 << 29)) ? 64 : 48;
541 c
->cputype
= CPU_R8000
;
542 __cpu_name
[cpu
] = "RM8000";
543 c
->isa_level
= MIPS_CPU_ISA_IV
;
544 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4KEX
|
545 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
547 c
->tlbsize
= 384; /* has weird TLB: 3-way x 128 */
549 case PRID_IMP_R10000
:
550 c
->cputype
= CPU_R10000
;
551 __cpu_name
[cpu
] = "R10000";
552 c
->isa_level
= MIPS_CPU_ISA_IV
;
553 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
554 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
555 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
559 case PRID_IMP_R12000
:
560 c
->cputype
= CPU_R12000
;
561 __cpu_name
[cpu
] = "R12000";
562 c
->isa_level
= MIPS_CPU_ISA_IV
;
563 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
564 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
565 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
569 case PRID_IMP_R14000
:
570 c
->cputype
= CPU_R14000
;
571 __cpu_name
[cpu
] = "R14000";
572 c
->isa_level
= MIPS_CPU_ISA_IV
;
573 c
->options
= MIPS_CPU_TLB
| MIPS_CPU_4K_CACHE
| MIPS_CPU_4KEX
|
574 MIPS_CPU_FPU
| MIPS_CPU_32FPR
|
575 MIPS_CPU_COUNTER
| MIPS_CPU_WATCH
|
579 case PRID_IMP_LOONGSON2
:
580 c
->cputype
= CPU_LOONGSON2
;
581 __cpu_name
[cpu
] = "ICT Loongson-2";
582 c
->isa_level
= MIPS_CPU_ISA_III
;
583 c
->options
= R4K_OPTS
|
584 MIPS_CPU_FPU
| MIPS_CPU_LLSC
|
591 static char unknown_isa
[] __cpuinitdata
= KERN_ERR \
592 "Unsupported ISA type, c0.config0: %d.";
594 static inline unsigned int decode_config0(struct cpuinfo_mips
*c
)
596 unsigned int config0
;
599 config0
= read_c0_config();
601 if (((config0
& MIPS_CONF_MT
) >> 7) == 1)
602 c
->options
|= MIPS_CPU_TLB
;
603 isa
= (config0
& MIPS_CONF_AT
) >> 13;
606 switch ((config0
& MIPS_CONF_AR
) >> 10) {
608 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
611 c
->isa_level
= MIPS_CPU_ISA_M32R2
;
618 switch ((config0
& MIPS_CONF_AR
) >> 10) {
620 c
->isa_level
= MIPS_CPU_ISA_M64R1
;
623 c
->isa_level
= MIPS_CPU_ISA_M64R2
;
633 return config0
& MIPS_CONF_M
;
636 panic(unknown_isa
, config0
);
639 static inline unsigned int decode_config1(struct cpuinfo_mips
*c
)
641 unsigned int config1
;
643 config1
= read_c0_config1();
645 if (config1
& MIPS_CONF1_MD
)
646 c
->ases
|= MIPS_ASE_MDMX
;
647 if (config1
& MIPS_CONF1_WR
)
648 c
->options
|= MIPS_CPU_WATCH
;
649 if (config1
& MIPS_CONF1_CA
)
650 c
->ases
|= MIPS_ASE_MIPS16
;
651 if (config1
& MIPS_CONF1_EP
)
652 c
->options
|= MIPS_CPU_EJTAG
;
653 if (config1
& MIPS_CONF1_FP
) {
654 c
->options
|= MIPS_CPU_FPU
;
655 c
->options
|= MIPS_CPU_32FPR
;
658 c
->tlbsize
= ((config1
& MIPS_CONF1_TLBS
) >> 25) + 1;
660 return config1
& MIPS_CONF_M
;
663 static inline unsigned int decode_config2(struct cpuinfo_mips
*c
)
665 unsigned int config2
;
667 config2
= read_c0_config2();
669 if (config2
& MIPS_CONF2_SL
)
670 c
->scache
.flags
&= ~MIPS_CACHE_NOT_PRESENT
;
672 return config2
& MIPS_CONF_M
;
675 static inline unsigned int decode_config3(struct cpuinfo_mips
*c
)
677 unsigned int config3
;
679 config3
= read_c0_config3();
681 if (config3
& MIPS_CONF3_SM
)
682 c
->ases
|= MIPS_ASE_SMARTMIPS
;
683 if (config3
& MIPS_CONF3_DSP
)
684 c
->ases
|= MIPS_ASE_DSP
;
685 if (config3
& MIPS_CONF3_VINT
)
686 c
->options
|= MIPS_CPU_VINT
;
687 if (config3
& MIPS_CONF3_VEIC
)
688 c
->options
|= MIPS_CPU_VEIC
;
689 if (config3
& MIPS_CONF3_MT
)
690 c
->ases
|= MIPS_ASE_MIPSMT
;
691 if (config3
& MIPS_CONF3_ULRI
)
692 c
->options
|= MIPS_CPU_ULRI
;
694 return config3
& MIPS_CONF_M
;
697 static void __cpuinit
decode_configs(struct cpuinfo_mips
*c
)
701 /* MIPS32 or MIPS64 compliant CPU. */
702 c
->options
= MIPS_CPU_4KEX
| MIPS_CPU_4K_CACHE
| MIPS_CPU_COUNTER
|
703 MIPS_CPU_DIVEC
| MIPS_CPU_LLSC
| MIPS_CPU_MCHECK
;
705 c
->scache
.flags
= MIPS_CACHE_NOT_PRESENT
;
707 ok
= decode_config0(c
); /* Read Config registers. */
708 BUG_ON(!ok
); /* Arch spec violation! */
710 ok
= decode_config1(c
);
712 ok
= decode_config2(c
);
714 ok
= decode_config3(c
);
716 mips_probe_watch_registers(c
);
719 #ifdef CONFIG_CPU_MIPSR2
720 extern void spram_config(void);
722 static inline void spram_config(void) {}
725 static inline void cpu_probe_mips(struct cpuinfo_mips
*c
, unsigned int cpu
)
728 switch (c
->processor_id
& 0xff00) {
730 c
->cputype
= CPU_4KC
;
731 __cpu_name
[cpu
] = "MIPS 4Kc";
734 c
->cputype
= CPU_4KEC
;
735 __cpu_name
[cpu
] = "MIPS 4KEc";
737 case PRID_IMP_4KECR2
:
738 c
->cputype
= CPU_4KEC
;
739 __cpu_name
[cpu
] = "MIPS 4KEc";
743 c
->cputype
= CPU_4KSC
;
744 __cpu_name
[cpu
] = "MIPS 4KSc";
747 c
->cputype
= CPU_5KC
;
748 __cpu_name
[cpu
] = "MIPS 5Kc";
751 c
->cputype
= CPU_20KC
;
752 __cpu_name
[cpu
] = "MIPS 20Kc";
756 c
->cputype
= CPU_24K
;
757 __cpu_name
[cpu
] = "MIPS 24Kc";
760 c
->cputype
= CPU_25KF
;
761 __cpu_name
[cpu
] = "MIPS 25Kc";
764 c
->cputype
= CPU_34K
;
765 __cpu_name
[cpu
] = "MIPS 34Kc";
768 c
->cputype
= CPU_74K
;
769 __cpu_name
[cpu
] = "MIPS 74Kc";
772 c
->cputype
= CPU_1004K
;
773 __cpu_name
[cpu
] = "MIPS 1004Kc";
780 static inline void cpu_probe_alchemy(struct cpuinfo_mips
*c
, unsigned int cpu
)
783 switch (c
->processor_id
& 0xff00) {
784 case PRID_IMP_AU1_REV1
:
785 case PRID_IMP_AU1_REV2
:
786 switch ((c
->processor_id
>> 24) & 0xff) {
788 c
->cputype
= CPU_AU1000
;
789 __cpu_name
[cpu
] = "Au1000";
792 c
->cputype
= CPU_AU1500
;
793 __cpu_name
[cpu
] = "Au1500";
796 c
->cputype
= CPU_AU1100
;
797 __cpu_name
[cpu
] = "Au1100";
800 c
->cputype
= CPU_AU1550
;
801 __cpu_name
[cpu
] = "Au1550";
804 c
->cputype
= CPU_AU1200
;
805 __cpu_name
[cpu
] = "Au1200";
806 if ((c
->processor_id
& 0xff) == 2) {
807 c
->cputype
= CPU_AU1250
;
808 __cpu_name
[cpu
] = "Au1250";
812 c
->cputype
= CPU_AU1210
;
813 __cpu_name
[cpu
] = "Au1210";
816 panic("Unknown Au Core!");
823 static inline void cpu_probe_sibyte(struct cpuinfo_mips
*c
, unsigned int cpu
)
827 switch (c
->processor_id
& 0xff00) {
829 c
->cputype
= CPU_SB1
;
830 __cpu_name
[cpu
] = "SiByte SB1";
831 /* FPU in pass1 is known to have issues. */
832 if ((c
->processor_id
& 0xff) < 0x02)
833 c
->options
&= ~(MIPS_CPU_FPU
| MIPS_CPU_32FPR
);
836 c
->cputype
= CPU_SB1A
;
837 __cpu_name
[cpu
] = "SiByte SB1A";
842 static inline void cpu_probe_sandcraft(struct cpuinfo_mips
*c
, unsigned int cpu
)
845 switch (c
->processor_id
& 0xff00) {
846 case PRID_IMP_SR71000
:
847 c
->cputype
= CPU_SR71000
;
848 __cpu_name
[cpu
] = "Sandcraft SR71000";
855 static inline void cpu_probe_nxp(struct cpuinfo_mips
*c
, unsigned int cpu
)
858 switch (c
->processor_id
& 0xff00) {
859 case PRID_IMP_PR4450
:
860 c
->cputype
= CPU_PR4450
;
861 __cpu_name
[cpu
] = "Philips PR4450";
862 c
->isa_level
= MIPS_CPU_ISA_M32R1
;
867 static inline void cpu_probe_broadcom(struct cpuinfo_mips
*c
, unsigned int cpu
)
870 switch (c
->processor_id
& 0xff00) {
871 case PRID_IMP_BCM3302
:
872 c
->cputype
= CPU_BCM3302
;
873 __cpu_name
[cpu
] = "Broadcom BCM3302";
875 case PRID_IMP_BCM4710
:
876 c
->cputype
= CPU_BCM4710
;
877 __cpu_name
[cpu
] = "Broadcom BCM4710";
882 static inline void cpu_probe_cavium(struct cpuinfo_mips
*c
, unsigned int cpu
)
885 switch (c
->processor_id
& 0xff00) {
886 case PRID_IMP_CAVIUM_CN38XX
:
887 case PRID_IMP_CAVIUM_CN31XX
:
888 case PRID_IMP_CAVIUM_CN30XX
:
889 case PRID_IMP_CAVIUM_CN58XX
:
890 case PRID_IMP_CAVIUM_CN56XX
:
891 case PRID_IMP_CAVIUM_CN50XX
:
892 case PRID_IMP_CAVIUM_CN52XX
:
893 c
->cputype
= CPU_CAVIUM_OCTEON
;
894 __cpu_name
[cpu
] = "Cavium Octeon";
897 printk(KERN_INFO
"Unknown Octeon chip!\n");
898 c
->cputype
= CPU_UNKNOWN
;
903 const char *__cpu_name
[NR_CPUS
];
905 __cpuinit
void cpu_probe(void)
907 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
908 unsigned int cpu
= smp_processor_id();
910 c
->processor_id
= PRID_IMP_UNKNOWN
;
911 c
->fpu_id
= FPIR_IMP_NONE
;
912 c
->cputype
= CPU_UNKNOWN
;
914 c
->processor_id
= read_c0_prid();
915 switch (c
->processor_id
& 0xff0000) {
916 case PRID_COMP_LEGACY
:
917 cpu_probe_legacy(c
, cpu
);
920 cpu_probe_mips(c
, cpu
);
922 case PRID_COMP_ALCHEMY
:
923 cpu_probe_alchemy(c
, cpu
);
925 case PRID_COMP_SIBYTE
:
926 cpu_probe_sibyte(c
, cpu
);
928 case PRID_COMP_BROADCOM
:
929 cpu_probe_broadcom(c
, cpu
);
931 case PRID_COMP_SANDCRAFT
:
932 cpu_probe_sandcraft(c
, cpu
);
935 cpu_probe_nxp(c
, cpu
);
937 case PRID_COMP_CAVIUM
:
938 cpu_probe_cavium(c
, cpu
);
942 BUG_ON(!__cpu_name
[cpu
]);
943 BUG_ON(c
->cputype
== CPU_UNKNOWN
);
946 * Platform code can force the cpu type to optimize code
947 * generation. In that case be sure the cpu type is correctly
948 * manually setup otherwise it could trigger some nasty bugs.
950 BUG_ON(current_cpu_type() != c
->cputype
);
952 if (c
->options
& MIPS_CPU_FPU
) {
953 c
->fpu_id
= cpu_get_fpu_id();
955 if (c
->isa_level
== MIPS_CPU_ISA_M32R1
||
956 c
->isa_level
== MIPS_CPU_ISA_M32R2
||
957 c
->isa_level
== MIPS_CPU_ISA_M64R1
||
958 c
->isa_level
== MIPS_CPU_ISA_M64R2
) {
959 if (c
->fpu_id
& MIPS_FPIR_3D
)
960 c
->ases
|= MIPS_ASE_MIPS3D
;
965 c
->srsets
= ((read_c0_srsctl() >> 26) & 0x0f) + 1;
970 __cpuinit
void cpu_report(void)
972 struct cpuinfo_mips
*c
= ¤t_cpu_data
;
974 printk(KERN_INFO
"CPU revision is: %08x (%s)\n",
975 c
->processor_id
, cpu_name_string());
976 if (c
->options
& MIPS_CPU_FPU
)
977 printk(KERN_INFO
"FPU revision is: %08x\n", c
->fpu_id
);