3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
11 /* general, but fairly heavy, debugging */
14 /* heavy debugging: */
15 /* -- logs putc[s], so everytime a char is displayed, it's logged */
16 #undef MATROXFB_DEBUG_HEAVY
18 /* This one _could_ cause infinite loops */
19 /* It _does_ cause lots and lots of messages during idle loops */
20 #undef MATROXFB_DEBUG_LOOP
22 /* Debug register calls, too? */
23 #undef MATROXFB_DEBUG_REG
25 /* Guard accelerator accesses with spin_lock_irqsave... */
26 #undef MATROXFB_USE_SPINLOCKS
28 #include <linux/module.h>
29 #include <linux/kernel.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
33 #include <linux/slab.h>
34 #include <linux/delay.h>
36 #include <linux/console.h>
37 #include <linux/selection.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/timer.h>
41 #include <linux/pci.h>
42 #include <linux/spinlock.h>
46 #include <asm/unaligned.h>
51 #if defined(CONFIG_PPC_PMAC)
53 #include <asm/pci-bridge.h>
54 #include "../macmodes.h"
57 /* always compile support for 32MB... It cost almost nothing */
58 #define CONFIG_FB_MATROX_32MB
63 #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x));
65 #ifdef MATROXFB_DEBUG_HEAVY
66 #define DBG_HEAVY(x) DBG(x)
67 #else /* MATROXFB_DEBUG_HEAVY */
68 #define DBG_HEAVY(x) /* DBG_HEAVY */
69 #endif /* MATROXFB_DEBUG_HEAVY */
71 #ifdef MATROXFB_DEBUG_LOOP
72 #define DBG_LOOP(x) DBG(x)
73 #else /* MATROXFB_DEBUG_LOOP */
74 #define DBG_LOOP(x) /* DBG_LOOP */
75 #endif /* MATROXFB_DEBUG_LOOP */
77 #ifdef MATROXFB_DEBUG_REG
78 #define DBG_REG(x) DBG(x)
79 #else /* MATROXFB_DEBUG_REG */
80 #define DBG_REG(x) /* DBG_REG */
81 #endif /* MATROXFB_DEBUG_REG */
83 #else /* MATROXFB_DEBUG */
85 #define DBG(x) /* DBG */
86 #define DBG_HEAVY(x) /* DBG_HEAVY */
87 #define DBG_REG(x) /* DBG_REG */
88 #define DBG_LOOP(x) /* DBG_LOOP */
90 #endif /* MATROXFB_DEBUG */
93 #define dprintk(X...) printk(X)
98 #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF
99 #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A
101 #ifndef PCI_SS_VENDOR_ID_MATROX
102 #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX
105 #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP
106 #define PCI_SS_ID_MATROX_GENERIC 0xFF00
107 #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01
108 #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02
109 #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03
110 #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04
111 #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05
112 #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001
113 #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179
114 #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */
115 #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */
118 #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR
119 #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR
120 #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR
122 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
124 /* G-series and Mystique have (almost) same DAC */
126 #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G)
127 #define NEED_DAC1064 1
134 static inline unsigned int mga_readb(vaddr_t va
, unsigned int offs
) {
135 return readb(va
.vaddr
+ offs
);
138 static inline void mga_writeb(vaddr_t va
, unsigned int offs
, u_int8_t value
) {
139 writeb(value
, va
.vaddr
+ offs
);
142 static inline void mga_writew(vaddr_t va
, unsigned int offs
, u_int16_t value
) {
143 writew(value
, va
.vaddr
+ offs
);
146 static inline u_int32_t
mga_readl(vaddr_t va
, unsigned int offs
) {
147 return readl(va
.vaddr
+ offs
);
150 static inline void mga_writel(vaddr_t va
, unsigned int offs
, u_int32_t value
) {
151 writel(value
, va
.vaddr
+ offs
);
154 static inline void mga_memcpy_toio(vaddr_t va
, const void* src
, int len
) {
155 #if defined(__alpha__) || defined(__i386__) || defined(__x86_64__)
157 * memcpy_toio works for us if:
158 * (1) Copies data as 32bit quantities, not byte after byte,
159 * (2) Performs LE ordered stores, and
160 * (3) It copes with unaligned source (destination is guaranteed to be page
161 * aligned and length is guaranteed to be multiple of 4).
163 memcpy_toio(va
.vaddr
, src
, len
);
165 u_int32_t __iomem
* addr
= va
.vaddr
;
167 if ((unsigned long)src
& 3) {
169 fb_writel(get_unaligned((u32
*)src
), addr
);
176 fb_writel(*(u32
*)src
, addr
);
185 static inline void vaddr_add(vaddr_t
* va
, unsigned long offs
) {
189 static inline void __iomem
* vaddr_va(vaddr_t va
) {
193 #define MGA_IOREMAP_NORMAL 0
194 #define MGA_IOREMAP_NOCACHE 1
196 #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE
197 #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE
198 static inline int mga_ioremap(unsigned long phys
, unsigned long size
, int flags
, vaddr_t
* virt
) {
199 if (flags
& MGA_IOREMAP_NOCACHE
)
200 virt
->vaddr
= ioremap_nocache(phys
, size
);
202 virt
->vaddr
= ioremap(phys
, size
);
203 return (virt
->vaddr
== NULL
); /* 0, !0... 0, error_code in future */
206 static inline void mga_iounmap(vaddr_t va
) {
211 unsigned int pixclock
;
214 unsigned int HDisplay
;
215 unsigned int HSyncStart
;
216 unsigned int HSyncEnd
;
218 unsigned int VDisplay
;
219 unsigned int VSyncStart
;
220 unsigned int VSyncEnd
;
225 unsigned int delay
; /* CRTC delay */
228 enum { M_SYSTEM_PLL
, M_PIXEL_PLL_A
, M_PIXEL_PLL_B
, M_PIXEL_PLL_C
, M_VIDEO_PLL
};
230 struct matrox_pll_cache
{
233 unsigned int mnp_key
;
234 unsigned int mnp_value
;
238 struct matrox_pll_limits
{
243 struct matrox_pll_features
{
244 unsigned int vco_freq_min
;
245 unsigned int ref_freq
;
246 unsigned int feed_div_min
;
247 unsigned int feed_div_max
;
248 unsigned int in_div_min
;
249 unsigned int in_div_max
;
250 unsigned int post_shift_max
;
255 unsigned int final_bppShift
;
256 unsigned int cmap_len
;
264 struct matrox_fb_info
;
266 struct matrox_DAC1064_features
{
271 /* current hardware status */
283 struct matrox_crtc2
{
287 struct matrox_hw_state
{
288 u_int32_t MXoptionReg
;
289 unsigned char DACclk
[6];
290 unsigned char DACreg
[80];
291 unsigned char MiscOutReg
;
292 unsigned char DACpal
[768];
293 unsigned char CRTC
[25];
294 unsigned char CRTCEXT
[9];
295 unsigned char SEQ
[5];
296 /* unused for MGA mode, but who knows... */
297 unsigned char GCTL
[9];
298 /* unused for MGA mode, but who knows... */
299 unsigned char ATTR
[21];
302 struct mavenregs maven
;
304 struct matrox_crtc2 crtc2
;
307 struct matrox_accel_data
{
308 #ifdef CONFIG_FB_MATROX_MILLENIUM
309 unsigned char ramdac_rev
;
311 u_int32_t m_dwg_rect
;
315 struct v4l2_queryctrl
;
318 struct matrox_altout
{
320 int (*compute
)(void* altout_dev
, struct my_timming
* input
);
321 int (*program
)(void* altout_dev
);
322 int (*start
)(void* altout_dev
);
323 int (*verifymode
)(void* altout_dev
, u_int32_t mode
);
324 int (*getqueryctrl
)(void* altout_dev
,
325 struct v4l2_queryctrl
* ctrl
);
326 int (*getctrl
)(void* altout_dev
,
327 struct v4l2_control
* ctrl
);
328 int (*setctrl
)(void* altout_dev
,
329 struct v4l2_control
* ctrl
);
332 #define MATROXFB_SRC_NONE 0
333 #define MATROXFB_SRC_CRTC1 1
334 #define MATROXFB_SRC_CRTC2 2
336 enum mga_chip
{ MGA_2064
, MGA_2164
, MGA_1064
, MGA_1164
, MGA_G100
, MGA_G200
, MGA_G400
, MGA_G450
, MGA_G550
};
339 unsigned int bios_valid
: 1;
340 unsigned int pins_len
;
341 unsigned char pins
[128];
343 unsigned char vMaj
, vMin
, vRev
;
346 unsigned char state
, tvout
;
350 struct matrox_switch
;
351 struct matroxfb_driver
;
352 struct matroxfb_dh_fb_info
;
354 struct matrox_vsync
{
355 wait_queue_head_t wait
;
359 struct matrox_fb_info
{
360 struct fb_info fbcon
;
362 struct list_head next_fb
;
366 unsigned int usecount
;
368 unsigned int userusecount
;
369 unsigned long irq_flags
;
371 struct matroxfb_par curr
;
372 struct matrox_hw_state hw
;
374 struct matrox_accel_data accel
;
376 struct pci_dev
* pcidev
;
379 struct matrox_vsync vsync
;
380 unsigned int pixclock
;
385 struct matrox_vsync vsync
;
386 unsigned int pixclock
;
388 struct matroxfb_dh_fb_info
* info
;
389 struct rw_semaphore lock
;
392 struct rw_semaphore lock
;
394 int brightness
, contrast
, saturation
, hue
, gamma
;
395 int testout
, deflicker
;
398 #define MATROXFB_MAX_OUTPUTS 3
401 struct matrox_altout
* output
;
404 unsigned int default_src
;
405 } outputs
[MATROXFB_MAX_OUTPUTS
];
407 #define MATROXFB_MAX_FB_DRIVERS 5
408 struct matroxfb_driver
* (drivers
[MATROXFB_MAX_FB_DRIVERS
]);
409 void* (drivers_data
[MATROXFB_MAX_FB_DRIVERS
]);
410 unsigned int drivers_count
;
413 unsigned long base
; /* physical */
414 vaddr_t vbase
; /* CPU view */
416 unsigned int len_usable
;
417 unsigned int len_maximum
;
421 unsigned long base
; /* physical */
422 vaddr_t vbase
; /* CPU view */
426 unsigned int max_pixel_clock
;
427 unsigned int max_pixel_clock_panellink
;
429 struct matrox_switch
* hw_switch
;
432 struct matrox_pll_features pll
;
433 struct matrox_DAC1064_features DAC1064
;
467 #ifdef CONFIG_FB_MATROX_32MB
476 unsigned int vgastep
;
477 unsigned int textmode
;
478 unsigned int textstep
;
479 unsigned int textvram
; /* character cells */
480 unsigned int ydstorg
; /* offset in bytes from video start to usable memory */
481 /* 0 except for 6MB Millenium */
485 int panellink
; /* G400 DFP possible (not G450/G550) */
487 unsigned int fbResource
;
490 struct matrox_bios bios
;
492 struct matrox_pll_limits pixel
;
493 struct matrox_pll_limits system
;
494 struct matrox_pll_limits video
;
497 struct matrox_pll_cache pixel
;
498 struct matrox_pll_cache system
;
499 struct matrox_pll_cache video
;
511 u_int32_t mctlwtst_core
;
525 #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon)
527 #define ACCESS_FBINFO2(info, x) (info->x)
528 #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x)
532 #define WPMINFO2 struct matrox_fb_info* minfo
533 #define WPMINFO WPMINFO2 ,
534 #define CPMINFO2 const struct matrox_fb_info* minfo
535 #define CPMINFO CPMINFO2 ,
536 #define PMINFO2 minfo
537 #define PMINFO PMINFO2 ,
539 #define MINFO_FROM(x) struct matrox_fb_info* minfo = x
541 #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x))
543 struct matrox_switch
{
544 int (*preinit
)(WPMINFO2
);
545 void (*reset
)(WPMINFO2
);
546 int (*init
)(WPMINFO
struct my_timming
*);
547 void (*restore
)(WPMINFO2
);
550 struct matroxfb_driver
{
551 struct list_head node
;
553 void* (*probe
)(struct matrox_fb_info
* info
);
554 void (*remove
)(struct matrox_fb_info
* info
, void* data
);
557 int matroxfb_register_driver(struct matroxfb_driver
* drv
);
558 void matroxfb_unregister_driver(struct matroxfb_driver
* drv
);
560 #define PCI_OPTION_REG 0x40
561 #define PCI_OPTION_ENABLE_ROM 0x40000000
563 #define PCI_MGA_INDEX 0x44
564 #define PCI_MGA_DATA 0x48
565 #define PCI_OPTION2_REG 0x50
566 #define PCI_OPTION3_REG 0x54
567 #define PCI_MEMMISC_REG 0x58
569 #define M_DWGCTL 0x1C00
570 #define M_MACCESS 0x1C04
571 #define M_CTLWTST 0x1C08
573 #define M_PLNWT 0x1C1C
575 #define M_BCOL 0x1C20
576 #define M_FCOL 0x1C24
588 #define M_CXBNDRY 0x1C80
589 #define M_FXBNDRY 0x1C84
590 #define M_YDSTLEN 0x1C88
591 #define M_PITCH 0x1C8C
592 #define M_YDST 0x1C90
593 #define M_YDSTORG 0x1C94
594 #define M_YTOP 0x1C98
595 #define M_YBOT 0x1C9C
598 #define M_CACHEFLUSH 0x1FFF
600 #define M_EXEC 0x0100
602 #define M_DWG_TRAP 0x04
603 #define M_DWG_BITBLT 0x08
604 #define M_DWG_ILOAD 0x09
606 #define M_DWG_LINEAR 0x0080
607 #define M_DWG_SOLID 0x0800
608 #define M_DWG_ARZERO 0x1000
609 #define M_DWG_SGNZERO 0x2000
610 #define M_DWG_SHIFTZERO 0x4000
612 #define M_DWG_REPLACE 0x000C0000
613 #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40)
614 #define M_DWG_XOR 0x00060010
616 #define M_DWG_BFCOL 0x04000000
617 #define M_DWG_BMONOWF 0x08000000
619 #define M_DWG_TRANSC 0x40000000
621 #define M_FIFOSTATUS 0x1E10
622 #define M_STATUS 0x1E14
623 #define M_ICLEAR 0x1E18
626 #define M_VCOUNT 0x1E20
628 #define M_RESET 0x1E40
629 #define M_MEMRDBK 0x1E44
631 #define M_AGP2PLL 0x1E4C
633 #define M_OPMODE 0x1E54
634 #define M_OPMODE_DMA_GEN_WRITE 0x00
635 #define M_OPMODE_DMA_BLIT 0x04
636 #define M_OPMODE_DMA_VECTOR_WRITE 0x08
637 #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */
638 #define M_OPMODE_DMA_BE_8BPP 0x0000
639 #define M_OPMODE_DMA_BE_16BPP 0x0100
640 #define M_OPMODE_DMA_BE_32BPP 0x0200
641 #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */
642 #define M_OPMODE_DIR_BE_8BPP 0x000000
643 #define M_OPMODE_DIR_BE_16BPP 0x010000
644 #define M_OPMODE_DIR_BE_32BPP 0x020000
646 #define M_ATTR_INDEX 0x1FC0
647 #define M_ATTR_DATA 0x1FC1
649 #define M_MISC_REG 0x1FC2
650 #define M_3C2_RD 0x1FC2
652 #define M_SEQ_INDEX 0x1FC4
653 #define M_SEQ_DATA 0x1FC5
655 #define M_SEQ1_SCROFF 0x20
657 #define M_MISC_REG_READ 0x1FCC
659 #define M_GRAPHICS_INDEX 0x1FCE
660 #define M_GRAPHICS_DATA 0x1FCF
662 #define M_CRTC_INDEX 0x1FD4
664 #define M_ATTR_RESET 0x1FDA
665 #define M_3DA_WR 0x1FDA
666 #define M_INSTS1 0x1FDA
668 #define M_EXTVGA_INDEX 0x1FDE
669 #define M_EXTVGA_DATA 0x1FDF
672 #define M_SRCORG 0x2CB4
673 #define M_DSTORG 0x2CB8
675 #define M_RAMDAC_BASE 0x3C00
677 /* fortunately, same on TVP3026 and MGA1064 */
678 #define M_DAC_REG (M_RAMDAC_BASE+0)
679 #define M_DAC_VAL (M_RAMDAC_BASE+1)
680 #define M_PALETTE_MASK (M_RAMDAC_BASE+2)
682 #define M_X_INDEX 0x00
683 #define M_X_DATAREG 0x0A
685 #define DAC_XGENIOCTRL 0x2A
686 #define DAC_XGENIODATA 0x2B
688 #define M_C2CTL 0x3C10
690 #define MX_OPTION_BSWAP 0x00000000
692 #ifdef __LITTLE_ENDIAN
693 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
694 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
695 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
696 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
697 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT)
700 #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */
701 #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT)
702 #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT)
703 #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */
704 #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT)
706 #error "Byte ordering have to be defined. Cannot continue."
710 #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr))
711 #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr))
712 #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val))
713 #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val))
714 #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val))
715 #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1))
716 #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port))
718 #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n))
720 #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000)
723 #ifdef CONFIG_FB_MATROX_MILLENIUM
724 #define isInterleave(x) (x->interleave)
725 #define isMillenium(x) (x->millenium)
726 #define isMilleniumII(x) (x->milleniumII)
728 #define isInterleave(x) (0)
729 #define isMillenium(x) (0)
730 #define isMilleniumII(x) (0)
733 #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC))
734 #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC))
735 #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags)
736 #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags)
737 extern void matroxfb_DAC_out(CPMINFO
int reg
, int val
);
738 extern int matroxfb_DAC_in(CPMINFO
int reg
);
739 extern void matroxfb_var2my(struct fb_var_screeninfo
* fvsi
, struct my_timming
* mt
);
740 extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc
);
741 extern int matroxfb_enable_irq(WPMINFO
int reenable
);
743 #ifdef MATROXFB_USE_SPINLOCKS
744 #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags);
745 #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags);
746 #define CRITFLAGS unsigned long critflags;
753 #endif /* __MATROXFB_H__ */