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Merge git://git.infradead.org/users/dwmw2/random-2.6
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / firewire / fw-ohci.c
blob251416f2148f36c72cdd8afa0ac74a792c7db5fa
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/gfp.h>
25 #include <linux/init.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel.h>
28 #include <linux/mm.h>
29 #include <linux/module.h>
30 #include <linux/moduleparam.h>
31 #include <linux/pci.h>
32 #include <linux/spinlock.h>
33
34 #include <asm/page.h>
35 #include <asm/system.h>
36
37 #ifdef CONFIG_PPC_PMAC
38 #include <asm/pmac_feature.h>
39 #endif
40
41 #include "fw-ohci.h"
42 #include "fw-transaction.h"
43
44 #define DESCRIPTOR_OUTPUT_MORE 0
45 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
46 #define DESCRIPTOR_INPUT_MORE (2 << 12)
47 #define DESCRIPTOR_INPUT_LAST (3 << 12)
48 #define DESCRIPTOR_STATUS (1 << 11)
49 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
50 #define DESCRIPTOR_PING (1 << 7)
51 #define DESCRIPTOR_YY (1 << 6)
52 #define DESCRIPTOR_NO_IRQ (0 << 4)
53 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
54 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
55 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
56 #define DESCRIPTOR_WAIT (3 << 0)
57
58 struct descriptor {
59 __le16 req_count;
60 __le16 control;
61 __le32 data_address;
62 __le32 branch_address;
63 __le16 res_count;
64 __le16 transfer_status;
65 } __attribute__((aligned(16)));
66
67 struct db_descriptor {
68 __le16 first_size;
69 __le16 control;
70 __le16 second_req_count;
71 __le16 first_req_count;
72 __le32 branch_address;
73 __le16 second_res_count;
74 __le16 first_res_count;
75 __le32 reserved0;
76 __le32 first_buffer;
77 __le32 second_buffer;
78 __le32 reserved1;
79 } __attribute__((aligned(16)));
80
81 #define CONTROL_SET(regs) (regs)
82 #define CONTROL_CLEAR(regs) ((regs) + 4)
83 #define COMMAND_PTR(regs) ((regs) + 12)
84 #define CONTEXT_MATCH(regs) ((regs) + 16)
85
86 struct ar_buffer {
87 struct descriptor descriptor;
88 struct ar_buffer *next;
89 __le32 data[0];
90 };
91
92 struct ar_context {
93 struct fw_ohci *ohci;
94 struct ar_buffer *current_buffer;
95 struct ar_buffer *last_buffer;
96 void *pointer;
97 u32 regs;
98 struct tasklet_struct tasklet;
99 };
100
101 struct context;
102
103 typedef int (*descriptor_callback_t)(struct context *ctx,
104 struct descriptor *d,
105 struct descriptor *last);
106
107 /*
108 * A buffer that contains a block of DMA-able coherent memory used for
109 * storing a portion of a DMA descriptor program.
110 */
111 struct descriptor_buffer {
112 struct list_head list;
113 dma_addr_t buffer_bus;
114 size_t buffer_size;
115 size_t used;
116 struct descriptor buffer[0];
117 };
118
119 struct context {
120 struct fw_ohci *ohci;
121 u32 regs;
122 int total_allocation;
123
124 /*
125 * List of page-sized buffers for storing DMA descriptors.
126 * Head of list contains buffers in use and tail of list contains
127 * free buffers.
128 */
129 struct list_head buffer_list;
130
131 /*
132 * Pointer to a buffer inside buffer_list that contains the tail
133 * end of the current DMA program.
134 */
135 struct descriptor_buffer *buffer_tail;
136
137 /*
138 * The descriptor containing the branch address of the first
139 * descriptor that has not yet been filled by the device.
140 */
141 struct descriptor *last;
142
143 /*
144 * The last descriptor in the DMA program. It contains the branch
145 * address that must be updated upon appending a new descriptor.
146 */
147 struct descriptor *prev;
148
149 descriptor_callback_t callback;
150
151 struct tasklet_struct tasklet;
152 };
153
154 #define IT_HEADER_SY(v) ((v) << 0)
155 #define IT_HEADER_TCODE(v) ((v) << 4)
156 #define IT_HEADER_CHANNEL(v) ((v) << 8)
157 #define IT_HEADER_TAG(v) ((v) << 14)
158 #define IT_HEADER_SPEED(v) ((v) << 16)
159 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
160
161 struct iso_context {
162 struct fw_iso_context base;
163 struct context context;
164 int excess_bytes;
165 void *header;
166 size_t header_length;
167 };
168
169 #define CONFIG_ROM_SIZE 1024
170
171 struct fw_ohci {
172 struct fw_card card;
173
174 __iomem char *registers;
175 dma_addr_t self_id_bus;
176 __le32 *self_id_cpu;
177 struct tasklet_struct bus_reset_tasklet;
178 int node_id;
179 int generation;
180 int request_generation; /* for timestamping incoming requests */
181 u32 bus_seconds;
182
183 bool use_dualbuffer;
184 bool old_uninorth;
185 bool bus_reset_packet_quirk;
186
187 /*
188 * Spinlock for accessing fw_ohci data. Never call out of
189 * this driver with this lock held.
190 */
191 spinlock_t lock;
192 u32 self_id_buffer[512];
193
194 /* Config rom buffers */
195 __be32 *config_rom;
196 dma_addr_t config_rom_bus;
197 __be32 *next_config_rom;
198 dma_addr_t next_config_rom_bus;
199 u32 next_header;
200
201 struct ar_context ar_request_ctx;
202 struct ar_context ar_response_ctx;
203 struct context at_request_ctx;
204 struct context at_response_ctx;
205
206 u32 it_context_mask;
207 struct iso_context *it_context_list;
208 u32 ir_context_mask;
209 struct iso_context *ir_context_list;
210 };
211
212 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
213 {
214 return container_of(card, struct fw_ohci, card);
215 }
216
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
223
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
228
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0x2
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
232
233 #define FW_OHCI_MAJOR 240
234 #define OHCI1394_REGISTER_SIZE 0x800
235 #define OHCI_LOOP_COUNT 500
236 #define OHCI1394_PCI_HCI_Control 0x40
237 #define SELF_ID_BUF_SIZE 0x800
238 #define OHCI_TCODE_PHY_PACKET 0x0e
239 #define OHCI_VERSION_1_1 0x010010
240
241 static char ohci_driver_name[] = KBUILD_MODNAME;
242
243 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
244
245 #define OHCI_PARAM_DEBUG_AT_AR 1
246 #define OHCI_PARAM_DEBUG_SELFIDS 2
247 #define OHCI_PARAM_DEBUG_IRQS 4
248 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
249
250 static int param_debug;
251 module_param_named(debug, param_debug, int, 0644);
252 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
253 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
254 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
255 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
256 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
257 ", or a combination, or all = -1)");
258
259 static void log_irqs(u32 evt)
260 {
261 if (likely(!(param_debug &
262 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
263 return;
264
265 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
266 !(evt & OHCI1394_busReset))
267 return;
268
269 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
270 evt & OHCI1394_selfIDComplete ? " selfID" : "",
271 evt & OHCI1394_RQPkt ? " AR_req" : "",
272 evt & OHCI1394_RSPkt ? " AR_resp" : "",
273 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
274 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
275 evt & OHCI1394_isochRx ? " IR" : "",
276 evt & OHCI1394_isochTx ? " IT" : "",
277 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
278 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
279 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
280 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
281 evt & OHCI1394_busReset ? " busReset" : "",
282 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
283 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
284 OHCI1394_respTxComplete | OHCI1394_isochRx |
285 OHCI1394_isochTx | OHCI1394_postedWriteErr |
286 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
287 OHCI1394_regAccessFail | OHCI1394_busReset)
288 ? " ?" : "");
289 }
290
291 static const char *speed[] = {
292 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
293 };
294 static const char *power[] = {
295 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
296 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
297 };
298 static const char port[] = { '.', '-', 'p', 'c', };
299
300 static char _p(u32 *s, int shift)
301 {
302 return port[*s >> shift & 3];
303 }
304
305 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
306 {
307 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
308 return;
309
310 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
311 self_id_count, generation, node_id);
312
313 for (; self_id_count--; ++s)
314 if ((*s & 1 << 23) == 0)
315 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
316 "%s gc=%d %s %s%s%s\n",
317 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
318 speed[*s >> 14 & 3], *s >> 16 & 63,
319 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
320 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
321 else
322 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
323 *s, *s >> 24 & 63,
324 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
325 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
326 }
327
328 static const char *evts[] = {
329 [0x00] = "evt_no_status", [0x01] = "-reserved-",
330 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
331 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
332 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
333 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
334 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
335 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
336 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
337 [0x10] = "-reserved-", [0x11] = "ack_complete",
338 [0x12] = "ack_pending ", [0x13] = "-reserved-",
339 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
340 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
341 [0x18] = "-reserved-", [0x19] = "-reserved-",
342 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
343 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
344 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
345 [0x20] = "pending/cancelled",
346 };
347 static const char *tcodes[] = {
348 [0x0] = "QW req", [0x1] = "BW req",
349 [0x2] = "W resp", [0x3] = "-reserved-",
350 [0x4] = "QR req", [0x5] = "BR req",
351 [0x6] = "QR resp", [0x7] = "BR resp",
352 [0x8] = "cycle start", [0x9] = "Lk req",
353 [0xa] = "async stream packet", [0xb] = "Lk resp",
354 [0xc] = "-reserved-", [0xd] = "-reserved-",
355 [0xe] = "link internal", [0xf] = "-reserved-",
356 };
357 static const char *phys[] = {
358 [0x0] = "phy config packet", [0x1] = "link-on packet",
359 [0x2] = "self-id packet", [0x3] = "-reserved-",
360 };
361
362 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
363 {
364 int tcode = header[0] >> 4 & 0xf;
365 char specific[12];
366
367 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
368 return;
369
370 if (unlikely(evt >= ARRAY_SIZE(evts)))
371 evt = 0x1f;
372
373 if (evt == OHCI1394_evt_bus_reset) {
374 fw_notify("A%c evt_bus_reset, generation %d\n",
375 dir, (header[2] >> 16) & 0xff);
376 return;
377 }
378
379 if (header[0] == ~header[1]) {
380 fw_notify("A%c %s, %s, %08x\n",
381 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
382 return;
383 }
384
385 switch (tcode) {
386 case 0x0: case 0x6: case 0x8:
387 snprintf(specific, sizeof(specific), " = %08x",
388 be32_to_cpu((__force __be32)header[3]));
389 break;
390 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
391 snprintf(specific, sizeof(specific), " %x,%x",
392 header[3] >> 16, header[3] & 0xffff);
393 break;
394 default:
395 specific[0] = '\0';
396 }
397
398 switch (tcode) {
399 case 0xe: case 0xa:
400 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
401 break;
402 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
403 fw_notify("A%c spd %x tl %02x, "
404 "%04x -> %04x, %s, "
405 "%s, %04x%08x%s\n",
406 dir, speed, header[0] >> 10 & 0x3f,
407 header[1] >> 16, header[0] >> 16, evts[evt],
408 tcodes[tcode], header[1] & 0xffff, header[2], specific);
409 break;
410 default:
411 fw_notify("A%c spd %x tl %02x, "
412 "%04x -> %04x, %s, "
413 "%s%s\n",
414 dir, speed, header[0] >> 10 & 0x3f,
415 header[1] >> 16, header[0] >> 16, evts[evt],
416 tcodes[tcode], specific);
417 }
418 }
419
420 #else
421
422 #define log_irqs(evt)
423 #define log_selfids(node_id, generation, self_id_count, sid)
424 #define log_ar_at_event(dir, speed, header, evt)
425
426 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
427
428 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
429 {
430 writel(data, ohci->registers + offset);
431 }
432
433 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
434 {
435 return readl(ohci->registers + offset);
436 }
437
438 static inline void flush_writes(const struct fw_ohci *ohci)
439 {
440 /* Do a dummy read to flush writes. */
441 reg_read(ohci, OHCI1394_Version);
442 }
443
444 static int
445 ohci_update_phy_reg(struct fw_card *card, int addr,
446 int clear_bits, int set_bits)
447 {
448 struct fw_ohci *ohci = fw_ohci(card);
449 u32 val, old;
450
451 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
452 flush_writes(ohci);
453 msleep(2);
454 val = reg_read(ohci, OHCI1394_PhyControl);
455 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
456 fw_error("failed to set phy reg bits.\n");
457 return -EBUSY;
458 }
459
460 old = OHCI1394_PhyControl_ReadData(val);
461 old = (old & ~clear_bits) | set_bits;
462 reg_write(ohci, OHCI1394_PhyControl,
463 OHCI1394_PhyControl_Write(addr, old));
464
465 return 0;
466 }
467
468 static int ar_context_add_page(struct ar_context *ctx)
469 {
470 struct device *dev = ctx->ohci->card.device;
471 struct ar_buffer *ab;
472 dma_addr_t uninitialized_var(ab_bus);
473 size_t offset;
474
475 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
476 if (ab == NULL)
477 return -ENOMEM;
478
479 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
480 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
481 DESCRIPTOR_STATUS |
482 DESCRIPTOR_BRANCH_ALWAYS);
483 offset = offsetof(struct ar_buffer, data);
484 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
485 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
486 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
487 ab->descriptor.branch_address = 0;
488
489 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
490 ctx->last_buffer->next = ab;
491 ctx->last_buffer = ab;
492
493 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
494 flush_writes(ctx->ohci);
495
496 return 0;
497 }
498
499 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
500 #define cond_le32_to_cpu(v) \
501 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
502 #else
503 #define cond_le32_to_cpu(v) le32_to_cpu(v)
504 #endif
505
506 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
507 {
508 struct fw_ohci *ohci = ctx->ohci;
509 struct fw_packet p;
510 u32 status, length, tcode;
511 int evt;
512
513 p.header[0] = cond_le32_to_cpu(buffer[0]);
514 p.header[1] = cond_le32_to_cpu(buffer[1]);
515 p.header[2] = cond_le32_to_cpu(buffer[2]);
516
517 tcode = (p.header[0] >> 4) & 0x0f;
518 switch (tcode) {
519 case TCODE_WRITE_QUADLET_REQUEST:
520 case TCODE_READ_QUADLET_RESPONSE:
521 p.header[3] = (__force __u32) buffer[3];
522 p.header_length = 16;
523 p.payload_length = 0;
524 break;
525
526 case TCODE_READ_BLOCK_REQUEST :
527 p.header[3] = cond_le32_to_cpu(buffer[3]);
528 p.header_length = 16;
529 p.payload_length = 0;
530 break;
531
532 case TCODE_WRITE_BLOCK_REQUEST:
533 case TCODE_READ_BLOCK_RESPONSE:
534 case TCODE_LOCK_REQUEST:
535 case TCODE_LOCK_RESPONSE:
536 p.header[3] = cond_le32_to_cpu(buffer[3]);
537 p.header_length = 16;
538 p.payload_length = p.header[3] >> 16;
539 break;
540
541 case TCODE_WRITE_RESPONSE:
542 case TCODE_READ_QUADLET_REQUEST:
543 case OHCI_TCODE_PHY_PACKET:
544 p.header_length = 12;
545 p.payload_length = 0;
546 break;
547
548 default:
549 /* FIXME: Stop context, discard everything, and restart? */
550 p.header_length = 0;
551 p.payload_length = 0;
552 }
553
554 p.payload = (void *) buffer + p.header_length;
555
556 /* FIXME: What to do about evt_* errors? */
557 length = (p.header_length + p.payload_length + 3) / 4;
558 status = cond_le32_to_cpu(buffer[length]);
559 evt = (status >> 16) & 0x1f;
560
561 p.ack = evt - 16;
562 p.speed = (status >> 21) & 0x7;
563 p.timestamp = status & 0xffff;
564 p.generation = ohci->request_generation;
565
566 log_ar_at_event('R', p.speed, p.header, evt);
567
568 /*
569 * The OHCI bus reset handler synthesizes a phy packet with
570 * the new generation number when a bus reset happens (see
571 * section 8.4.2.3). This helps us determine when a request
572 * was received and make sure we send the response in the same
573 * generation. We only need this for requests; for responses
574 * we use the unique tlabel for finding the matching
575 * request.
576 *
577 * Alas some chips sometimes emit bus reset packets with a
578 * wrong generation. We set the correct generation for these
579 * at a slightly incorrect time (in bus_reset_tasklet).
580 */
581 if (evt == OHCI1394_evt_bus_reset) {
582 if (!ohci->bus_reset_packet_quirk)
583 ohci->request_generation = (p.header[2] >> 16) & 0xff;
584 } else if (ctx == &ohci->ar_request_ctx) {
585 fw_core_handle_request(&ohci->card, &p);
586 } else {
587 fw_core_handle_response(&ohci->card, &p);
588 }
589
590 return buffer + length + 1;
591 }
592
593 static void ar_context_tasklet(unsigned long data)
594 {
595 struct ar_context *ctx = (struct ar_context *)data;
596 struct fw_ohci *ohci = ctx->ohci;
597 struct ar_buffer *ab;
598 struct descriptor *d;
599 void *buffer, *end;
600
601 ab = ctx->current_buffer;
602 d = &ab->descriptor;
603
604 if (d->res_count == 0) {
605 size_t size, rest, offset;
606 dma_addr_t start_bus;
607 void *start;
608
609 /*
610 * This descriptor is finished and we may have a
611 * packet split across this and the next buffer. We
612 * reuse the page for reassembling the split packet.
613 */
614
615 offset = offsetof(struct ar_buffer, data);
616 start = buffer = ab;
617 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
618
619 ab = ab->next;
620 d = &ab->descriptor;
621 size = buffer + PAGE_SIZE - ctx->pointer;
622 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
623 memmove(buffer, ctx->pointer, size);
624 memcpy(buffer + size, ab->data, rest);
625 ctx->current_buffer = ab;
626 ctx->pointer = (void *) ab->data + rest;
627 end = buffer + size + rest;
628
629 while (buffer < end)
630 buffer = handle_ar_packet(ctx, buffer);
631
632 dma_free_coherent(ohci->card.device, PAGE_SIZE,
633 start, start_bus);
634 ar_context_add_page(ctx);
635 } else {
636 buffer = ctx->pointer;
637 ctx->pointer = end =
638 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
639
640 while (buffer < end)
641 buffer = handle_ar_packet(ctx, buffer);
642 }
643 }
644
645 static int
646 ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci, u32 regs)
647 {
648 struct ar_buffer ab;
649
650 ctx->regs = regs;
651 ctx->ohci = ohci;
652 ctx->last_buffer = &ab;
653 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
654
655 ar_context_add_page(ctx);
656 ar_context_add_page(ctx);
657 ctx->current_buffer = ab.next;
658 ctx->pointer = ctx->current_buffer->data;
659
660 return 0;
661 }
662
663 static void ar_context_run(struct ar_context *ctx)
664 {
665 struct ar_buffer *ab = ctx->current_buffer;
666 dma_addr_t ab_bus;
667 size_t offset;
668
669 offset = offsetof(struct ar_buffer, data);
670 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
671
672 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
673 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
674 flush_writes(ctx->ohci);
675 }
676
677 static struct descriptor *
678 find_branch_descriptor(struct descriptor *d, int z)
679 {
680 int b, key;
681
682 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
683 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
684
685 /* figure out which descriptor the branch address goes in */
686 if (z == 2 && (b == 3 || key == 2))
687 return d;
688 else
689 return d + z - 1;
690 }
691
692 static void context_tasklet(unsigned long data)
693 {
694 struct context *ctx = (struct context *) data;
695 struct descriptor *d, *last;
696 u32 address;
697 int z;
698 struct descriptor_buffer *desc;
699
700 desc = list_entry(ctx->buffer_list.next,
701 struct descriptor_buffer, list);
702 last = ctx->last;
703 while (last->branch_address != 0) {
704 struct descriptor_buffer *old_desc = desc;
705 address = le32_to_cpu(last->branch_address);
706 z = address & 0xf;
707 address &= ~0xf;
708
709 /* If the branch address points to a buffer outside of the
710 * current buffer, advance to the next buffer. */
711 if (address < desc->buffer_bus ||
712 address >= desc->buffer_bus + desc->used)
713 desc = list_entry(desc->list.next,
714 struct descriptor_buffer, list);
715 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
716 last = find_branch_descriptor(d, z);
717
718 if (!ctx->callback(ctx, d, last))
719 break;
720
721 if (old_desc != desc) {
722 /* If we've advanced to the next buffer, move the
723 * previous buffer to the free list. */
724 unsigned long flags;
725 old_desc->used = 0;
726 spin_lock_irqsave(&ctx->ohci->lock, flags);
727 list_move_tail(&old_desc->list, &ctx->buffer_list);
728 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
729 }
730 ctx->last = last;
731 }
732 }
733
734 /*
735 * Allocate a new buffer and add it to the list of free buffers for this
736 * context. Must be called with ohci->lock held.
737 */
738 static int
739 context_add_buffer(struct context *ctx)
740 {
741 struct descriptor_buffer *desc;
742 dma_addr_t uninitialized_var(bus_addr);
743 int offset;
744
745 /*
746 * 16MB of descriptors should be far more than enough for any DMA
747 * program. This will catch run-away userspace or DoS attacks.
748 */
749 if (ctx->total_allocation >= 16*1024*1024)
750 return -ENOMEM;
751
752 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
753 &bus_addr, GFP_ATOMIC);
754 if (!desc)
755 return -ENOMEM;
756
757 offset = (void *)&desc->buffer - (void *)desc;
758 desc->buffer_size = PAGE_SIZE - offset;
759 desc->buffer_bus = bus_addr + offset;
760 desc->used = 0;
761
762 list_add_tail(&desc->list, &ctx->buffer_list);
763 ctx->total_allocation += PAGE_SIZE;
764
765 return 0;
766 }
767
768 static int
769 context_init(struct context *ctx, struct fw_ohci *ohci,
770 u32 regs, descriptor_callback_t callback)
771 {
772 ctx->ohci = ohci;
773 ctx->regs = regs;
774 ctx->total_allocation = 0;
775
776 INIT_LIST_HEAD(&ctx->buffer_list);
777 if (context_add_buffer(ctx) < 0)
778 return -ENOMEM;
779
780 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
781 struct descriptor_buffer, list);
782
783 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
784 ctx->callback = callback;
785
786 /*
787 * We put a dummy descriptor in the buffer that has a NULL
788 * branch address and looks like it's been sent. That way we
789 * have a descriptor to append DMA programs to.
790 */
791 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
792 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
793 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
794 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
795 ctx->last = ctx->buffer_tail->buffer;
796 ctx->prev = ctx->buffer_tail->buffer;
797
798 return 0;
799 }
800
801 static void
802 context_release(struct context *ctx)
803 {
804 struct fw_card *card = &ctx->ohci->card;
805 struct descriptor_buffer *desc, *tmp;
806
807 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
808 dma_free_coherent(card->device, PAGE_SIZE, desc,
809 desc->buffer_bus -
810 ((void *)&desc->buffer - (void *)desc));
811 }
812
813 /* Must be called with ohci->lock held */
814 static struct descriptor *
815 context_get_descriptors(struct context *ctx, int z, dma_addr_t *d_bus)
816 {
817 struct descriptor *d = NULL;
818 struct descriptor_buffer *desc = ctx->buffer_tail;
819
820 if (z * sizeof(*d) > desc->buffer_size)
821 return NULL;
822
823 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
824 /* No room for the descriptor in this buffer, so advance to the
825 * next one. */
826
827 if (desc->list.next == &ctx->buffer_list) {
828 /* If there is no free buffer next in the list,
829 * allocate one. */
830 if (context_add_buffer(ctx) < 0)
831 return NULL;
832 }
833 desc = list_entry(desc->list.next,
834 struct descriptor_buffer, list);
835 ctx->buffer_tail = desc;
836 }
837
838 d = desc->buffer + desc->used / sizeof(*d);
839 memset(d, 0, z * sizeof(*d));
840 *d_bus = desc->buffer_bus + desc->used;
841
842 return d;
843 }
844
845 static void context_run(struct context *ctx, u32 extra)
846 {
847 struct fw_ohci *ohci = ctx->ohci;
848
849 reg_write(ohci, COMMAND_PTR(ctx->regs),
850 le32_to_cpu(ctx->last->branch_address));
851 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
852 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
853 flush_writes(ohci);
854 }
855
856 static void context_append(struct context *ctx,
857 struct descriptor *d, int z, int extra)
858 {
859 dma_addr_t d_bus;
860 struct descriptor_buffer *desc = ctx->buffer_tail;
861
862 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
863
864 desc->used += (z + extra) * sizeof(*d);
865 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
866 ctx->prev = find_branch_descriptor(d, z);
867
868 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
869 flush_writes(ctx->ohci);
870 }
871
872 static void context_stop(struct context *ctx)
873 {
874 u32 reg;
875 int i;
876
877 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
878 flush_writes(ctx->ohci);
879
880 for (i = 0; i < 10; i++) {
881 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
882 if ((reg & CONTEXT_ACTIVE) == 0)
883 break;
884
885 fw_notify("context_stop: still active (0x%08x)\n", reg);
886 mdelay(1);
887 }
888 }
889
890 struct driver_data {
891 struct fw_packet *packet;
892 };
893
894 /*
895 * This function apppends a packet to the DMA queue for transmission.
896 * Must always be called with the ochi->lock held to ensure proper
897 * generation handling and locking around packet queue manipulation.
898 */
899 static int
900 at_context_queue_packet(struct context *ctx, struct fw_packet *packet)
901 {
902 struct fw_ohci *ohci = ctx->ohci;
903 dma_addr_t d_bus, uninitialized_var(payload_bus);
904 struct driver_data *driver_data;
905 struct descriptor *d, *last;
906 __le32 *header;
907 int z, tcode;
908 u32 reg;
909
910 d = context_get_descriptors(ctx, 4, &d_bus);
911 if (d == NULL) {
912 packet->ack = RCODE_SEND_ERROR;
913 return -1;
914 }
915
916 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
917 d[0].res_count = cpu_to_le16(packet->timestamp);
918
919 /*
920 * The DMA format for asyncronous link packets is different
921 * from the IEEE1394 layout, so shift the fields around
922 * accordingly. If header_length is 8, it's a PHY packet, to
923 * which we need to prepend an extra quadlet.
924 */
925
926 header = (__le32 *) &d[1];
927 if (packet->header_length > 8) {
928 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
929 (packet->speed << 16));
930 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
931 (packet->header[0] & 0xffff0000));
932 header[2] = cpu_to_le32(packet->header[2]);
933
934 tcode = (packet->header[0] >> 4) & 0x0f;
935 if (TCODE_IS_BLOCK_PACKET(tcode))
936 header[3] = cpu_to_le32(packet->header[3]);
937 else
938 header[3] = (__force __le32) packet->header[3];
939
940 d[0].req_count = cpu_to_le16(packet->header_length);
941 } else {
942 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
943 (packet->speed << 16));
944 header[1] = cpu_to_le32(packet->header[0]);
945 header[2] = cpu_to_le32(packet->header[1]);
946 d[0].req_count = cpu_to_le16(12);
947 }
948
949 driver_data = (struct driver_data *) &d[3];
950 driver_data->packet = packet;
951 packet->driver_data = driver_data;
952
953 if (packet->payload_length > 0) {
954 payload_bus =
955 dma_map_single(ohci->card.device, packet->payload,
956 packet->payload_length, DMA_TO_DEVICE);
957 if (dma_mapping_error(ohci->card.device, payload_bus)) {
958 packet->ack = RCODE_SEND_ERROR;
959 return -1;
960 }
961
962 d[2].req_count = cpu_to_le16(packet->payload_length);
963 d[2].data_address = cpu_to_le32(payload_bus);
964 last = &d[2];
965 z = 3;
966 } else {
967 last = &d[0];
968 z = 2;
969 }
970
971 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
972 DESCRIPTOR_IRQ_ALWAYS |
973 DESCRIPTOR_BRANCH_ALWAYS);
974
975 /*
976 * If the controller and packet generations don't match, we need to
977 * bail out and try again. If IntEvent.busReset is set, the AT context
978 * is halted, so appending to the context and trying to run it is
979 * futile. Most controllers do the right thing and just flush the AT
980 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
981 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
982 * up stalling out. So we just bail out in software and try again
983 * later, and everyone is happy.
984 * FIXME: Document how the locking works.
985 */
986 if (ohci->generation != packet->generation ||
987 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
988 if (packet->payload_length > 0)
989 dma_unmap_single(ohci->card.device, payload_bus,
990 packet->payload_length, DMA_TO_DEVICE);
991 packet->ack = RCODE_GENERATION;
992 return -1;
993 }
994
995 context_append(ctx, d, z, 4 - z);
996
997 /* If the context isn't already running, start it up. */
998 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
999 if ((reg & CONTEXT_RUN) == 0)
1000 context_run(ctx, 0);
1001
1002 return 0;
1003 }
1004
1005 static int handle_at_packet(struct context *context,
1006 struct descriptor *d,
1007 struct descriptor *last)
1008 {
1009 struct driver_data *driver_data;
1010 struct fw_packet *packet;
1011 struct fw_ohci *ohci = context->ohci;
1012 dma_addr_t payload_bus;
1013 int evt;
1014
1015 if (last->transfer_status == 0)
1016 /* This descriptor isn't done yet, stop iteration. */
1017 return 0;
1018
1019 driver_data = (struct driver_data *) &d[3];
1020 packet = driver_data->packet;
1021 if (packet == NULL)
1022 /* This packet was cancelled, just continue. */
1023 return 1;
1024
1025 payload_bus = le32_to_cpu(last->data_address);
1026 if (payload_bus != 0)
1027 dma_unmap_single(ohci->card.device, payload_bus,
1028 packet->payload_length, DMA_TO_DEVICE);
1029
1030 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1031 packet->timestamp = le16_to_cpu(last->res_count);
1032
1033 log_ar_at_event('T', packet->speed, packet->header, evt);
1034
1035 switch (evt) {
1036 case OHCI1394_evt_timeout:
1037 /* Async response transmit timed out. */
1038 packet->ack = RCODE_CANCELLED;
1039 break;
1040
1041 case OHCI1394_evt_flushed:
1042 /*
1043 * The packet was flushed should give same error as
1044 * when we try to use a stale generation count.
1045 */
1046 packet->ack = RCODE_GENERATION;
1047 break;
1048
1049 case OHCI1394_evt_missing_ack:
1050 /*
1051 * Using a valid (current) generation count, but the
1052 * node is not on the bus or not sending acks.
1053 */
1054 packet->ack = RCODE_NO_ACK;
1055 break;
1056
1057 case ACK_COMPLETE + 0x10:
1058 case ACK_PENDING + 0x10:
1059 case ACK_BUSY_X + 0x10:
1060 case ACK_BUSY_A + 0x10:
1061 case ACK_BUSY_B + 0x10:
1062 case ACK_DATA_ERROR + 0x10:
1063 case ACK_TYPE_ERROR + 0x10:
1064 packet->ack = evt - 0x10;
1065 break;
1066
1067 default:
1068 packet->ack = RCODE_SEND_ERROR;
1069 break;
1070 }
1071
1072 packet->callback(packet, &ohci->card, packet->ack);
1073
1074 return 1;
1075 }
1076
1077 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1078 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1079 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1080 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1081 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1082
1083 static void
1084 handle_local_rom(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1085 {
1086 struct fw_packet response;
1087 int tcode, length, i;
1088
1089 tcode = HEADER_GET_TCODE(packet->header[0]);
1090 if (TCODE_IS_BLOCK_PACKET(tcode))
1091 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1092 else
1093 length = 4;
1094
1095 i = csr - CSR_CONFIG_ROM;
1096 if (i + length > CONFIG_ROM_SIZE) {
1097 fw_fill_response(&response, packet->header,
1098 RCODE_ADDRESS_ERROR, NULL, 0);
1099 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1100 fw_fill_response(&response, packet->header,
1101 RCODE_TYPE_ERROR, NULL, 0);
1102 } else {
1103 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1104 (void *) ohci->config_rom + i, length);
1105 }
1106
1107 fw_core_handle_response(&ohci->card, &response);
1108 }
1109
1110 static void
1111 handle_local_lock(struct fw_ohci *ohci, struct fw_packet *packet, u32 csr)
1112 {
1113 struct fw_packet response;
1114 int tcode, length, ext_tcode, sel;
1115 __be32 *payload, lock_old;
1116 u32 lock_arg, lock_data;
1117
1118 tcode = HEADER_GET_TCODE(packet->header[0]);
1119 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1120 payload = packet->payload;
1121 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1122
1123 if (tcode == TCODE_LOCK_REQUEST &&
1124 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1125 lock_arg = be32_to_cpu(payload[0]);
1126 lock_data = be32_to_cpu(payload[1]);
1127 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1128 lock_arg = 0;
1129 lock_data = 0;
1130 } else {
1131 fw_fill_response(&response, packet->header,
1132 RCODE_TYPE_ERROR, NULL, 0);
1133 goto out;
1134 }
1135
1136 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1137 reg_write(ohci, OHCI1394_CSRData, lock_data);
1138 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1139 reg_write(ohci, OHCI1394_CSRControl, sel);
1140
1141 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1142 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1143 else
1144 fw_notify("swap not done yet\n");
1145
1146 fw_fill_response(&response, packet->header,
1147 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1148 out:
1149 fw_core_handle_response(&ohci->card, &response);
1150 }
1151
1152 static void
1153 handle_local_request(struct context *ctx, struct fw_packet *packet)
1154 {
1155 u64 offset;
1156 u32 csr;
1157
1158 if (ctx == &ctx->ohci->at_request_ctx) {
1159 packet->ack = ACK_PENDING;
1160 packet->callback(packet, &ctx->ohci->card, packet->ack);
1161 }
1162
1163 offset =
1164 ((unsigned long long)
1165 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1166 packet->header[2];
1167 csr = offset - CSR_REGISTER_BASE;
1168
1169 /* Handle config rom reads. */
1170 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1171 handle_local_rom(ctx->ohci, packet, csr);
1172 else switch (csr) {
1173 case CSR_BUS_MANAGER_ID:
1174 case CSR_BANDWIDTH_AVAILABLE:
1175 case CSR_CHANNELS_AVAILABLE_HI:
1176 case CSR_CHANNELS_AVAILABLE_LO:
1177 handle_local_lock(ctx->ohci, packet, csr);
1178 break;
1179 default:
1180 if (ctx == &ctx->ohci->at_request_ctx)
1181 fw_core_handle_request(&ctx->ohci->card, packet);
1182 else
1183 fw_core_handle_response(&ctx->ohci->card, packet);
1184 break;
1185 }
1186
1187 if (ctx == &ctx->ohci->at_response_ctx) {
1188 packet->ack = ACK_COMPLETE;
1189 packet->callback(packet, &ctx->ohci->card, packet->ack);
1190 }
1191 }
1192
1193 static void
1194 at_context_transmit(struct context *ctx, struct fw_packet *packet)
1195 {
1196 unsigned long flags;
1197 int retval;
1198
1199 spin_lock_irqsave(&ctx->ohci->lock, flags);
1200
1201 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1202 ctx->ohci->generation == packet->generation) {
1203 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1204 handle_local_request(ctx, packet);
1205 return;
1206 }
1207
1208 retval = at_context_queue_packet(ctx, packet);
1209 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1210
1211 if (retval < 0)
1212 packet->callback(packet, &ctx->ohci->card, packet->ack);
1213
1214 }
1215
1216 static void bus_reset_tasklet(unsigned long data)
1217 {
1218 struct fw_ohci *ohci = (struct fw_ohci *)data;
1219 int self_id_count, i, j, reg;
1220 int generation, new_generation;
1221 unsigned long flags;
1222 void *free_rom = NULL;
1223 dma_addr_t free_rom_bus = 0;
1224
1225 reg = reg_read(ohci, OHCI1394_NodeID);
1226 if (!(reg & OHCI1394_NodeID_idValid)) {
1227 fw_notify("node ID not valid, new bus reset in progress\n");
1228 return;
1229 }
1230 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1231 fw_notify("malconfigured bus\n");
1232 return;
1233 }
1234 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1235 OHCI1394_NodeID_nodeNumber);
1236
1237 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1238 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1239 fw_notify("inconsistent self IDs\n");
1240 return;
1241 }
1242 /*
1243 * The count in the SelfIDCount register is the number of
1244 * bytes in the self ID receive buffer. Since we also receive
1245 * the inverted quadlets and a header quadlet, we shift one
1246 * bit extra to get the actual number of self IDs.
1247 */
1248 self_id_count = (reg >> 3) & 0x3ff;
1249 if (self_id_count == 0) {
1250 fw_notify("inconsistent self IDs\n");
1251 return;
1252 }
1253 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1254 rmb();
1255
1256 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1257 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1258 fw_notify("inconsistent self IDs\n");
1259 return;
1260 }
1261 ohci->self_id_buffer[j] =
1262 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1263 }
1264 rmb();
1265
1266 /*
1267 * Check the consistency of the self IDs we just read. The
1268 * problem we face is that a new bus reset can start while we
1269 * read out the self IDs from the DMA buffer. If this happens,
1270 * the DMA buffer will be overwritten with new self IDs and we
1271 * will read out inconsistent data. The OHCI specification
1272 * (section 11.2) recommends a technique similar to
1273 * linux/seqlock.h, where we remember the generation of the
1274 * self IDs in the buffer before reading them out and compare
1275 * it to the current generation after reading them out. If
1276 * the two generations match we know we have a consistent set
1277 * of self IDs.
1278 */
1279
1280 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1281 if (new_generation != generation) {
1282 fw_notify("recursive bus reset detected, "
1283 "discarding self ids\n");
1284 return;
1285 }
1286
1287 /* FIXME: Document how the locking works. */
1288 spin_lock_irqsave(&ohci->lock, flags);
1289
1290 ohci->generation = generation;
1291 context_stop(&ohci->at_request_ctx);
1292 context_stop(&ohci->at_response_ctx);
1293 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1294
1295 if (ohci->bus_reset_packet_quirk)
1296 ohci->request_generation = generation;
1297
1298 /*
1299 * This next bit is unrelated to the AT context stuff but we
1300 * have to do it under the spinlock also. If a new config rom
1301 * was set up before this reset, the old one is now no longer
1302 * in use and we can free it. Update the config rom pointers
1303 * to point to the current config rom and clear the
1304 * next_config_rom pointer so a new udpate can take place.
1305 */
1306
1307 if (ohci->next_config_rom != NULL) {
1308 if (ohci->next_config_rom != ohci->config_rom) {
1309 free_rom = ohci->config_rom;
1310 free_rom_bus = ohci->config_rom_bus;
1311 }
1312 ohci->config_rom = ohci->next_config_rom;
1313 ohci->config_rom_bus = ohci->next_config_rom_bus;
1314 ohci->next_config_rom = NULL;
1315
1316 /*
1317 * Restore config_rom image and manually update
1318 * config_rom registers. Writing the header quadlet
1319 * will indicate that the config rom is ready, so we
1320 * do that last.
1321 */
1322 reg_write(ohci, OHCI1394_BusOptions,
1323 be32_to_cpu(ohci->config_rom[2]));
1324 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1325 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1326 }
1327
1328 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1329 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1330 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1331 #endif
1332
1333 spin_unlock_irqrestore(&ohci->lock, flags);
1334
1335 if (free_rom)
1336 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1337 free_rom, free_rom_bus);
1338
1339 log_selfids(ohci->node_id, generation,
1340 self_id_count, ohci->self_id_buffer);
1341
1342 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1343 self_id_count, ohci->self_id_buffer);
1344 }
1345
1346 static irqreturn_t irq_handler(int irq, void *data)
1347 {
1348 struct fw_ohci *ohci = data;
1349 u32 event, iso_event, cycle_time;
1350 int i;
1351
1352 event = reg_read(ohci, OHCI1394_IntEventClear);
1353
1354 if (!event || !~event)
1355 return IRQ_NONE;
1356
1357 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1358 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1359 log_irqs(event);
1360
1361 if (event & OHCI1394_selfIDComplete)
1362 tasklet_schedule(&ohci->bus_reset_tasklet);
1363
1364 if (event & OHCI1394_RQPkt)
1365 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1366
1367 if (event & OHCI1394_RSPkt)
1368 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1369
1370 if (event & OHCI1394_reqTxComplete)
1371 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1372
1373 if (event & OHCI1394_respTxComplete)
1374 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1375
1376 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1377 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1378
1379 while (iso_event) {
1380 i = ffs(iso_event) - 1;
1381 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1382 iso_event &= ~(1 << i);
1383 }
1384
1385 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1386 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1387
1388 while (iso_event) {
1389 i = ffs(iso_event) - 1;
1390 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1391 iso_event &= ~(1 << i);
1392 }
1393
1394 if (unlikely(event & OHCI1394_regAccessFail))
1395 fw_error("Register access failure - "
1396 "please notify linux1394-devel@lists.sf.net\n");
1397
1398 if (unlikely(event & OHCI1394_postedWriteErr))
1399 fw_error("PCI posted write error\n");
1400
1401 if (unlikely(event & OHCI1394_cycleTooLong)) {
1402 if (printk_ratelimit())
1403 fw_notify("isochronous cycle too long\n");
1404 reg_write(ohci, OHCI1394_LinkControlSet,
1405 OHCI1394_LinkControl_cycleMaster);
1406 }
1407
1408 if (event & OHCI1394_cycle64Seconds) {
1409 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1410 if ((cycle_time & 0x80000000) == 0)
1411 ohci->bus_seconds++;
1412 }
1413
1414 return IRQ_HANDLED;
1415 }
1416
1417 static int software_reset(struct fw_ohci *ohci)
1418 {
1419 int i;
1420
1421 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1422
1423 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1424 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1425 OHCI1394_HCControl_softReset) == 0)
1426 return 0;
1427 msleep(1);
1428 }
1429
1430 return -EBUSY;
1431 }
1432
1433 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1434 {
1435 struct fw_ohci *ohci = fw_ohci(card);
1436 struct pci_dev *dev = to_pci_dev(card->device);
1437 u32 lps;
1438 int i;
1439
1440 if (software_reset(ohci)) {
1441 fw_error("Failed to reset ohci card.\n");
1442 return -EBUSY;
1443 }
1444
1445 /*
1446 * Now enable LPS, which we need in order to start accessing
1447 * most of the registers. In fact, on some cards (ALI M5251),
1448 * accessing registers in the SClk domain without LPS enabled
1449 * will lock up the machine. Wait 50msec to make sure we have
1450 * full link enabled. However, with some cards (well, at least
1451 * a JMicron PCIe card), we have to try again sometimes.
1452 */
1453 reg_write(ohci, OHCI1394_HCControlSet,
1454 OHCI1394_HCControl_LPS |
1455 OHCI1394_HCControl_postedWriteEnable);
1456 flush_writes(ohci);
1457
1458 for (lps = 0, i = 0; !lps && i < 3; i++) {
1459 msleep(50);
1460 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1461 OHCI1394_HCControl_LPS;
1462 }
1463
1464 if (!lps) {
1465 fw_error("Failed to set Link Power Status\n");
1466 return -EIO;
1467 }
1468
1469 reg_write(ohci, OHCI1394_HCControlClear,
1470 OHCI1394_HCControl_noByteSwapData);
1471
1472 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1473 reg_write(ohci, OHCI1394_LinkControlClear,
1474 OHCI1394_LinkControl_rcvPhyPkt);
1475 reg_write(ohci, OHCI1394_LinkControlSet,
1476 OHCI1394_LinkControl_rcvSelfID |
1477 OHCI1394_LinkControl_cycleTimerEnable |
1478 OHCI1394_LinkControl_cycleMaster);
1479
1480 reg_write(ohci, OHCI1394_ATRetries,
1481 OHCI1394_MAX_AT_REQ_RETRIES |
1482 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1483 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1484
1485 ar_context_run(&ohci->ar_request_ctx);
1486 ar_context_run(&ohci->ar_response_ctx);
1487
1488 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1489 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1490 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1491 reg_write(ohci, OHCI1394_IntMaskSet,
1492 OHCI1394_selfIDComplete |
1493 OHCI1394_RQPkt | OHCI1394_RSPkt |
1494 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1495 OHCI1394_isochRx | OHCI1394_isochTx |
1496 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1497 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1498 OHCI1394_masterIntEnable);
1499 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1500 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1501
1502 /* Activate link_on bit and contender bit in our self ID packets.*/
1503 if (ohci_update_phy_reg(card, 4, 0,
1504 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1505 return -EIO;
1506
1507 /*
1508 * When the link is not yet enabled, the atomic config rom
1509 * update mechanism described below in ohci_set_config_rom()
1510 * is not active. We have to update ConfigRomHeader and
1511 * BusOptions manually, and the write to ConfigROMmap takes
1512 * effect immediately. We tie this to the enabling of the
1513 * link, so we have a valid config rom before enabling - the
1514 * OHCI requires that ConfigROMhdr and BusOptions have valid
1515 * values before enabling.
1516 *
1517 * However, when the ConfigROMmap is written, some controllers
1518 * always read back quadlets 0 and 2 from the config rom to
1519 * the ConfigRomHeader and BusOptions registers on bus reset.
1520 * They shouldn't do that in this initial case where the link
1521 * isn't enabled. This means we have to use the same
1522 * workaround here, setting the bus header to 0 and then write
1523 * the right values in the bus reset tasklet.
1524 */
1525
1526 if (config_rom) {
1527 ohci->next_config_rom =
1528 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1529 &ohci->next_config_rom_bus,
1530 GFP_KERNEL);
1531 if (ohci->next_config_rom == NULL)
1532 return -ENOMEM;
1533
1534 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1535 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1536 } else {
1537 /*
1538 * In the suspend case, config_rom is NULL, which
1539 * means that we just reuse the old config rom.
1540 */
1541 ohci->next_config_rom = ohci->config_rom;
1542 ohci->next_config_rom_bus = ohci->config_rom_bus;
1543 }
1544
1545 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1546 ohci->next_config_rom[0] = 0;
1547 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1548 reg_write(ohci, OHCI1394_BusOptions,
1549 be32_to_cpu(ohci->next_config_rom[2]));
1550 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1551
1552 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1553
1554 if (request_irq(dev->irq, irq_handler,
1555 IRQF_SHARED, ohci_driver_name, ohci)) {
1556 fw_error("Failed to allocate shared interrupt %d.\n",
1557 dev->irq);
1558 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1559 ohci->config_rom, ohci->config_rom_bus);
1560 return -EIO;
1561 }
1562
1563 reg_write(ohci, OHCI1394_HCControlSet,
1564 OHCI1394_HCControl_linkEnable |
1565 OHCI1394_HCControl_BIBimageValid);
1566 flush_writes(ohci);
1567
1568 /*
1569 * We are ready to go, initiate bus reset to finish the
1570 * initialization.
1571 */
1572
1573 fw_core_initiate_bus_reset(&ohci->card, 1);
1574
1575 return 0;
1576 }
1577
1578 static int
1579 ohci_set_config_rom(struct fw_card *card, u32 *config_rom, size_t length)
1580 {
1581 struct fw_ohci *ohci;
1582 unsigned long flags;
1583 int retval = -EBUSY;
1584 __be32 *next_config_rom;
1585 dma_addr_t uninitialized_var(next_config_rom_bus);
1586
1587 ohci = fw_ohci(card);
1588
1589 /*
1590 * When the OHCI controller is enabled, the config rom update
1591 * mechanism is a bit tricky, but easy enough to use. See
1592 * section 5.5.6 in the OHCI specification.
1593 *
1594 * The OHCI controller caches the new config rom address in a
1595 * shadow register (ConfigROMmapNext) and needs a bus reset
1596 * for the changes to take place. When the bus reset is
1597 * detected, the controller loads the new values for the
1598 * ConfigRomHeader and BusOptions registers from the specified
1599 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1600 * shadow register. All automatically and atomically.
1601 *
1602 * Now, there's a twist to this story. The automatic load of
1603 * ConfigRomHeader and BusOptions doesn't honor the
1604 * noByteSwapData bit, so with a be32 config rom, the
1605 * controller will load be32 values in to these registers
1606 * during the atomic update, even on litte endian
1607 * architectures. The workaround we use is to put a 0 in the
1608 * header quadlet; 0 is endian agnostic and means that the
1609 * config rom isn't ready yet. In the bus reset tasklet we
1610 * then set up the real values for the two registers.
1611 *
1612 * We use ohci->lock to avoid racing with the code that sets
1613 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1614 */
1615
1616 next_config_rom =
1617 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1618 &next_config_rom_bus, GFP_KERNEL);
1619 if (next_config_rom == NULL)
1620 return -ENOMEM;
1621
1622 spin_lock_irqsave(&ohci->lock, flags);
1623
1624 if (ohci->next_config_rom == NULL) {
1625 ohci->next_config_rom = next_config_rom;
1626 ohci->next_config_rom_bus = next_config_rom_bus;
1627
1628 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1629 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1630 length * 4);
1631
1632 ohci->next_header = config_rom[0];
1633 ohci->next_config_rom[0] = 0;
1634
1635 reg_write(ohci, OHCI1394_ConfigROMmap,
1636 ohci->next_config_rom_bus);
1637 retval = 0;
1638 }
1639
1640 spin_unlock_irqrestore(&ohci->lock, flags);
1641
1642 /*
1643 * Now initiate a bus reset to have the changes take
1644 * effect. We clean up the old config rom memory and DMA
1645 * mappings in the bus reset tasklet, since the OHCI
1646 * controller could need to access it before the bus reset
1647 * takes effect.
1648 */
1649 if (retval == 0)
1650 fw_core_initiate_bus_reset(&ohci->card, 1);
1651 else
1652 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1653 next_config_rom, next_config_rom_bus);
1654
1655 return retval;
1656 }
1657
1658 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1659 {
1660 struct fw_ohci *ohci = fw_ohci(card);
1661
1662 at_context_transmit(&ohci->at_request_ctx, packet);
1663 }
1664
1665 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1666 {
1667 struct fw_ohci *ohci = fw_ohci(card);
1668
1669 at_context_transmit(&ohci->at_response_ctx, packet);
1670 }
1671
1672 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1673 {
1674 struct fw_ohci *ohci = fw_ohci(card);
1675 struct context *ctx = &ohci->at_request_ctx;
1676 struct driver_data *driver_data = packet->driver_data;
1677 int retval = -ENOENT;
1678
1679 tasklet_disable(&ctx->tasklet);
1680
1681 if (packet->ack != 0)
1682 goto out;
1683
1684 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1685 driver_data->packet = NULL;
1686 packet->ack = RCODE_CANCELLED;
1687 packet->callback(packet, &ohci->card, packet->ack);
1688 retval = 0;
1689
1690 out:
1691 tasklet_enable(&ctx->tasklet);
1692
1693 return retval;
1694 }
1695
1696 static int
1697 ohci_enable_phys_dma(struct fw_card *card, int node_id, int generation)
1698 {
1699 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1700 return 0;
1701 #else
1702 struct fw_ohci *ohci = fw_ohci(card);
1703 unsigned long flags;
1704 int n, retval = 0;
1705
1706 /*
1707 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1708 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1709 */
1710
1711 spin_lock_irqsave(&ohci->lock, flags);
1712
1713 if (ohci->generation != generation) {
1714 retval = -ESTALE;
1715 goto out;
1716 }
1717
1718 /*
1719 * Note, if the node ID contains a non-local bus ID, physical DMA is
1720 * enabled for _all_ nodes on remote buses.
1721 */
1722
1723 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1724 if (n < 32)
1725 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1726 else
1727 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1728
1729 flush_writes(ohci);
1730 out:
1731 spin_unlock_irqrestore(&ohci->lock, flags);
1732 return retval;
1733 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1734 }
1735
1736 static u64
1737 ohci_get_bus_time(struct fw_card *card)
1738 {
1739 struct fw_ohci *ohci = fw_ohci(card);
1740 u32 cycle_time;
1741 u64 bus_time;
1742
1743 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1744 bus_time = ((u64) ohci->bus_seconds << 32) | cycle_time;
1745
1746 return bus_time;
1747 }
1748
1749 static int handle_ir_dualbuffer_packet(struct context *context,
1750 struct descriptor *d,
1751 struct descriptor *last)
1752 {
1753 struct iso_context *ctx =
1754 container_of(context, struct iso_context, context);
1755 struct db_descriptor *db = (struct db_descriptor *) d;
1756 __le32 *ir_header;
1757 size_t header_length;
1758 void *p, *end;
1759 int i;
1760
1761 if (db->first_res_count != 0 && db->second_res_count != 0) {
1762 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1763 /* This descriptor isn't done yet, stop iteration. */
1764 return 0;
1765 }
1766 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1767 }
1768
1769 header_length = le16_to_cpu(db->first_req_count) -
1770 le16_to_cpu(db->first_res_count);
1771
1772 i = ctx->header_length;
1773 p = db + 1;
1774 end = p + header_length;
1775 while (p < end && i + ctx->base.header_size <= PAGE_SIZE) {
1776 /*
1777 * The iso header is byteswapped to little endian by
1778 * the controller, but the remaining header quadlets
1779 * are big endian. We want to present all the headers
1780 * as big endian, so we have to swap the first
1781 * quadlet.
1782 */
1783 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1784 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1785 i += ctx->base.header_size;
1786 ctx->excess_bytes +=
1787 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1788 p += ctx->base.header_size + 4;
1789 }
1790 ctx->header_length = i;
1791
1792 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1793 le16_to_cpu(db->second_res_count);
1794
1795 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1796 ir_header = (__le32 *) (db + 1);
1797 ctx->base.callback(&ctx->base,
1798 le32_to_cpu(ir_header[0]) & 0xffff,
1799 ctx->header_length, ctx->header,
1800 ctx->base.callback_data);
1801 ctx->header_length = 0;
1802 }
1803
1804 return 1;
1805 }
1806
1807 static int handle_ir_packet_per_buffer(struct context *context,
1808 struct descriptor *d,
1809 struct descriptor *last)
1810 {
1811 struct iso_context *ctx =
1812 container_of(context, struct iso_context, context);
1813 struct descriptor *pd;
1814 __le32 *ir_header;
1815 void *p;
1816 int i;
1817
1818 for (pd = d; pd <= last; pd++) {
1819 if (pd->transfer_status)
1820 break;
1821 }
1822 if (pd > last)
1823 /* Descriptor(s) not done yet, stop iteration */
1824 return 0;
1825
1826 i = ctx->header_length;
1827 p = last + 1;
1828
1829 if (ctx->base.header_size > 0 &&
1830 i + ctx->base.header_size <= PAGE_SIZE) {
1831 /*
1832 * The iso header is byteswapped to little endian by
1833 * the controller, but the remaining header quadlets
1834 * are big endian. We want to present all the headers
1835 * as big endian, so we have to swap the first quadlet.
1836 */
1837 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1838 memcpy(ctx->header + i + 4, p + 8, ctx->base.header_size - 4);
1839 ctx->header_length += ctx->base.header_size;
1840 }
1841
1842 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1843 ir_header = (__le32 *) p;
1844 ctx->base.callback(&ctx->base,
1845 le32_to_cpu(ir_header[0]) & 0xffff,
1846 ctx->header_length, ctx->header,
1847 ctx->base.callback_data);
1848 ctx->header_length = 0;
1849 }
1850
1851 return 1;
1852 }
1853
1854 static int handle_it_packet(struct context *context,
1855 struct descriptor *d,
1856 struct descriptor *last)
1857 {
1858 struct iso_context *ctx =
1859 container_of(context, struct iso_context, context);
1860
1861 if (last->transfer_status == 0)
1862 /* This descriptor isn't done yet, stop iteration. */
1863 return 0;
1864
1865 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS)
1866 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1867 0, NULL, ctx->base.callback_data);
1868
1869 return 1;
1870 }
1871
1872 static struct fw_iso_context *
1873 ohci_allocate_iso_context(struct fw_card *card, int type, size_t header_size)
1874 {
1875 struct fw_ohci *ohci = fw_ohci(card);
1876 struct iso_context *ctx, *list;
1877 descriptor_callback_t callback;
1878 u32 *mask, regs;
1879 unsigned long flags;
1880 int index, retval = -ENOMEM;
1881
1882 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1883 mask = &ohci->it_context_mask;
1884 list = ohci->it_context_list;
1885 callback = handle_it_packet;
1886 } else {
1887 mask = &ohci->ir_context_mask;
1888 list = ohci->ir_context_list;
1889 if (ohci->use_dualbuffer)
1890 callback = handle_ir_dualbuffer_packet;
1891 else
1892 callback = handle_ir_packet_per_buffer;
1893 }
1894
1895 spin_lock_irqsave(&ohci->lock, flags);
1896 index = ffs(*mask) - 1;
1897 if (index >= 0)
1898 *mask &= ~(1 << index);
1899 spin_unlock_irqrestore(&ohci->lock, flags);
1900
1901 if (index < 0)
1902 return ERR_PTR(-EBUSY);
1903
1904 if (type == FW_ISO_CONTEXT_TRANSMIT)
1905 regs = OHCI1394_IsoXmitContextBase(index);
1906 else
1907 regs = OHCI1394_IsoRcvContextBase(index);
1908
1909 ctx = &list[index];
1910 memset(ctx, 0, sizeof(*ctx));
1911 ctx->header_length = 0;
1912 ctx->header = (void *) __get_free_page(GFP_KERNEL);
1913 if (ctx->header == NULL)
1914 goto out;
1915
1916 retval = context_init(&ctx->context, ohci, regs, callback);
1917 if (retval < 0)
1918 goto out_with_header;
1919
1920 return &ctx->base;
1921
1922 out_with_header:
1923 free_page((unsigned long)ctx->header);
1924 out:
1925 spin_lock_irqsave(&ohci->lock, flags);
1926 *mask |= 1 << index;
1927 spin_unlock_irqrestore(&ohci->lock, flags);
1928
1929 return ERR_PTR(retval);
1930 }
1931
1932 static int ohci_start_iso(struct fw_iso_context *base,
1933 s32 cycle, u32 sync, u32 tags)
1934 {
1935 struct iso_context *ctx = container_of(base, struct iso_context, base);
1936 struct fw_ohci *ohci = ctx->context.ohci;
1937 u32 control, match;
1938 int index;
1939
1940 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1941 index = ctx - ohci->it_context_list;
1942 match = 0;
1943 if (cycle >= 0)
1944 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
1945 (cycle & 0x7fff) << 16;
1946
1947 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
1948 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
1949 context_run(&ctx->context, match);
1950 } else {
1951 index = ctx - ohci->ir_context_list;
1952 control = IR_CONTEXT_ISOCH_HEADER;
1953 if (ohci->use_dualbuffer)
1954 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
1955 match = (tags << 28) | (sync << 8) | ctx->base.channel;
1956 if (cycle >= 0) {
1957 match |= (cycle & 0x07fff) << 12;
1958 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
1959 }
1960
1961 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
1962 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
1963 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
1964 context_run(&ctx->context, control);
1965 }
1966
1967 return 0;
1968 }
1969
1970 static int ohci_stop_iso(struct fw_iso_context *base)
1971 {
1972 struct fw_ohci *ohci = fw_ohci(base->card);
1973 struct iso_context *ctx = container_of(base, struct iso_context, base);
1974 int index;
1975
1976 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
1977 index = ctx - ohci->it_context_list;
1978 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
1979 } else {
1980 index = ctx - ohci->ir_context_list;
1981 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
1982 }
1983 flush_writes(ohci);
1984 context_stop(&ctx->context);
1985
1986 return 0;
1987 }
1988
1989 static void ohci_free_iso_context(struct fw_iso_context *base)
1990 {
1991 struct fw_ohci *ohci = fw_ohci(base->card);
1992 struct iso_context *ctx = container_of(base, struct iso_context, base);
1993 unsigned long flags;
1994 int index;
1995
1996 ohci_stop_iso(base);
1997 context_release(&ctx->context);
1998 free_page((unsigned long)ctx->header);
1999
2000 spin_lock_irqsave(&ohci->lock, flags);
2001
2002 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2003 index = ctx - ohci->it_context_list;
2004 ohci->it_context_mask |= 1 << index;
2005 } else {
2006 index = ctx - ohci->ir_context_list;
2007 ohci->ir_context_mask |= 1 << index;
2008 }
2009
2010 spin_unlock_irqrestore(&ohci->lock, flags);
2011 }
2012
2013 static int
2014 ohci_queue_iso_transmit(struct fw_iso_context *base,
2015 struct fw_iso_packet *packet,
2016 struct fw_iso_buffer *buffer,
2017 unsigned long payload)
2018 {
2019 struct iso_context *ctx = container_of(base, struct iso_context, base);
2020 struct descriptor *d, *last, *pd;
2021 struct fw_iso_packet *p;
2022 __le32 *header;
2023 dma_addr_t d_bus, page_bus;
2024 u32 z, header_z, payload_z, irq;
2025 u32 payload_index, payload_end_index, next_page_index;
2026 int page, end_page, i, length, offset;
2027
2028 /*
2029 * FIXME: Cycle lost behavior should be configurable: lose
2030 * packet, retransmit or terminate..
2031 */
2032
2033 p = packet;
2034 payload_index = payload;
2035
2036 if (p->skip)
2037 z = 1;
2038 else
2039 z = 2;
2040 if (p->header_length > 0)
2041 z++;
2042
2043 /* Determine the first page the payload isn't contained in. */
2044 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2045 if (p->payload_length > 0)
2046 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2047 else
2048 payload_z = 0;
2049
2050 z += payload_z;
2051
2052 /* Get header size in number of descriptors. */
2053 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2054
2055 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2056 if (d == NULL)
2057 return -ENOMEM;
2058
2059 if (!p->skip) {
2060 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2061 d[0].req_count = cpu_to_le16(8);
2062
2063 header = (__le32 *) &d[1];
2064 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2065 IT_HEADER_TAG(p->tag) |
2066 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2067 IT_HEADER_CHANNEL(ctx->base.channel) |
2068 IT_HEADER_SPEED(ctx->base.speed));
2069 header[1] =
2070 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2071 p->payload_length));
2072 }
2073
2074 if (p->header_length > 0) {
2075 d[2].req_count = cpu_to_le16(p->header_length);
2076 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2077 memcpy(&d[z], p->header, p->header_length);
2078 }
2079
2080 pd = d + z - payload_z;
2081 payload_end_index = payload_index + p->payload_length;
2082 for (i = 0; i < payload_z; i++) {
2083 page = payload_index >> PAGE_SHIFT;
2084 offset = payload_index & ~PAGE_MASK;
2085 next_page_index = (page + 1) << PAGE_SHIFT;
2086 length =
2087 min(next_page_index, payload_end_index) - payload_index;
2088 pd[i].req_count = cpu_to_le16(length);
2089
2090 page_bus = page_private(buffer->pages[page]);
2091 pd[i].data_address = cpu_to_le32(page_bus + offset);
2092
2093 payload_index += length;
2094 }
2095
2096 if (p->interrupt)
2097 irq = DESCRIPTOR_IRQ_ALWAYS;
2098 else
2099 irq = DESCRIPTOR_NO_IRQ;
2100
2101 last = z == 2 ? d : d + z - 1;
2102 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2103 DESCRIPTOR_STATUS |
2104 DESCRIPTOR_BRANCH_ALWAYS |
2105 irq);
2106
2107 context_append(&ctx->context, d, z, header_z);
2108
2109 return 0;
2110 }
2111
2112 static int
2113 ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2114 struct fw_iso_packet *packet,
2115 struct fw_iso_buffer *buffer,
2116 unsigned long payload)
2117 {
2118 struct iso_context *ctx = container_of(base, struct iso_context, base);
2119 struct db_descriptor *db = NULL;
2120 struct descriptor *d;
2121 struct fw_iso_packet *p;
2122 dma_addr_t d_bus, page_bus;
2123 u32 z, header_z, length, rest;
2124 int page, offset, packet_count, header_size;
2125
2126 /*
2127 * FIXME: Cycle lost behavior should be configurable: lose
2128 * packet, retransmit or terminate..
2129 */
2130
2131 p = packet;
2132 z = 2;
2133
2134 /*
2135 * The OHCI controller puts the status word in the header
2136 * buffer too, so we need 4 extra bytes per packet.
2137 */
2138 packet_count = p->header_length / ctx->base.header_size;
2139 header_size = packet_count * (ctx->base.header_size + 4);
2140
2141 /* Get header size in number of descriptors. */
2142 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2143 page = payload >> PAGE_SHIFT;
2144 offset = payload & ~PAGE_MASK;
2145 rest = p->payload_length;
2146
2147 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2148 while (rest > 0) {
2149 d = context_get_descriptors(&ctx->context,
2150 z + header_z, &d_bus);
2151 if (d == NULL)
2152 return -ENOMEM;
2153
2154 db = (struct db_descriptor *) d;
2155 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2156 DESCRIPTOR_BRANCH_ALWAYS);
2157 db->first_size = cpu_to_le16(ctx->base.header_size + 4);
2158 if (p->skip && rest == p->payload_length) {
2159 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2160 db->first_req_count = db->first_size;
2161 } else {
2162 db->first_req_count = cpu_to_le16(header_size);
2163 }
2164 db->first_res_count = db->first_req_count;
2165 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2166
2167 if (p->skip && rest == p->payload_length)
2168 length = 4;
2169 else if (offset + rest < PAGE_SIZE)
2170 length = rest;
2171 else
2172 length = PAGE_SIZE - offset;
2173
2174 db->second_req_count = cpu_to_le16(length);
2175 db->second_res_count = db->second_req_count;
2176 page_bus = page_private(buffer->pages[page]);
2177 db->second_buffer = cpu_to_le32(page_bus + offset);
2178
2179 if (p->interrupt && length == rest)
2180 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2181
2182 context_append(&ctx->context, d, z, header_z);
2183 offset = (offset + length) & ~PAGE_MASK;
2184 rest -= length;
2185 if (offset == 0)
2186 page++;
2187 }
2188
2189 return 0;
2190 }
2191
2192 static int
2193 ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2194 struct fw_iso_packet *packet,
2195 struct fw_iso_buffer *buffer,
2196 unsigned long payload)
2197 {
2198 struct iso_context *ctx = container_of(base, struct iso_context, base);
2199 struct descriptor *d = NULL, *pd = NULL;
2200 struct fw_iso_packet *p = packet;
2201 dma_addr_t d_bus, page_bus;
2202 u32 z, header_z, rest;
2203 int i, j, length;
2204 int page, offset, packet_count, header_size, payload_per_buffer;
2205
2206 /*
2207 * The OHCI controller puts the status word in the
2208 * buffer too, so we need 4 extra bytes per packet.
2209 */
2210 packet_count = p->header_length / ctx->base.header_size;
2211 header_size = ctx->base.header_size + 4;
2212
2213 /* Get header size in number of descriptors. */
2214 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2215 page = payload >> PAGE_SHIFT;
2216 offset = payload & ~PAGE_MASK;
2217 payload_per_buffer = p->payload_length / packet_count;
2218
2219 for (i = 0; i < packet_count; i++) {
2220 /* d points to the header descriptor */
2221 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2222 d = context_get_descriptors(&ctx->context,
2223 z + header_z, &d_bus);
2224 if (d == NULL)
2225 return -ENOMEM;
2226
2227 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2228 DESCRIPTOR_INPUT_MORE);
2229 if (p->skip && i == 0)
2230 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2231 d->req_count = cpu_to_le16(header_size);
2232 d->res_count = d->req_count;
2233 d->transfer_status = 0;
2234 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2235
2236 rest = payload_per_buffer;
2237 for (j = 1; j < z; j++) {
2238 pd = d + j;
2239 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2240 DESCRIPTOR_INPUT_MORE);
2241
2242 if (offset + rest < PAGE_SIZE)
2243 length = rest;
2244 else
2245 length = PAGE_SIZE - offset;
2246 pd->req_count = cpu_to_le16(length);
2247 pd->res_count = pd->req_count;
2248 pd->transfer_status = 0;
2249
2250 page_bus = page_private(buffer->pages[page]);
2251 pd->data_address = cpu_to_le32(page_bus + offset);
2252
2253 offset = (offset + length) & ~PAGE_MASK;
2254 rest -= length;
2255 if (offset == 0)
2256 page++;
2257 }
2258 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2259 DESCRIPTOR_INPUT_LAST |
2260 DESCRIPTOR_BRANCH_ALWAYS);
2261 if (p->interrupt && i == packet_count - 1)
2262 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2263
2264 context_append(&ctx->context, d, z, header_z);
2265 }
2266
2267 return 0;
2268 }
2269
2270 static int
2271 ohci_queue_iso(struct fw_iso_context *base,
2272 struct fw_iso_packet *packet,
2273 struct fw_iso_buffer *buffer,
2274 unsigned long payload)
2275 {
2276 struct iso_context *ctx = container_of(base, struct iso_context, base);
2277 unsigned long flags;
2278 int retval;
2279
2280 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2281 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2282 retval = ohci_queue_iso_transmit(base, packet, buffer, payload);
2283 else if (ctx->context.ohci->use_dualbuffer)
2284 retval = ohci_queue_iso_receive_dualbuffer(base, packet,
2285 buffer, payload);
2286 else
2287 retval = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2288 buffer,
2289 payload);
2290 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2291
2292 return retval;
2293 }
2294
2295 static const struct fw_card_driver ohci_driver = {
2296 .enable = ohci_enable,
2297 .update_phy_reg = ohci_update_phy_reg,
2298 .set_config_rom = ohci_set_config_rom,
2299 .send_request = ohci_send_request,
2300 .send_response = ohci_send_response,
2301 .cancel_packet = ohci_cancel_packet,
2302 .enable_phys_dma = ohci_enable_phys_dma,
2303 .get_bus_time = ohci_get_bus_time,
2304
2305 .allocate_iso_context = ohci_allocate_iso_context,
2306 .free_iso_context = ohci_free_iso_context,
2307 .queue_iso = ohci_queue_iso,
2308 .start_iso = ohci_start_iso,
2309 .stop_iso = ohci_stop_iso,
2310 };
2311
2312 #ifdef CONFIG_PPC_PMAC
2313 static void ohci_pmac_on(struct pci_dev *dev)
2314 {
2315 if (machine_is(powermac)) {
2316 struct device_node *ofn = pci_device_to_OF_node(dev);
2317
2318 if (ofn) {
2319 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2320 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2321 }
2322 }
2323 }
2324
2325 static void ohci_pmac_off(struct pci_dev *dev)
2326 {
2327 if (machine_is(powermac)) {
2328 struct device_node *ofn = pci_device_to_OF_node(dev);
2329
2330 if (ofn) {
2331 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2332 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2333 }
2334 }
2335 }
2336 #else
2337 #define ohci_pmac_on(dev)
2338 #define ohci_pmac_off(dev)
2339 #endif /* CONFIG_PPC_PMAC */
2340
2341 static int __devinit
2342 pci_probe(struct pci_dev *dev, const struct pci_device_id *ent)
2343 {
2344 struct fw_ohci *ohci;
2345 u32 bus_options, max_receive, link_speed, version;
2346 u64 guid;
2347 int err;
2348 size_t size;
2349
2350 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2351 if (ohci == NULL) {
2352 fw_error("Could not malloc fw_ohci data.\n");
2353 return -ENOMEM;
2354 }
2355
2356 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2357
2358 ohci_pmac_on(dev);
2359
2360 err = pci_enable_device(dev);
2361 if (err) {
2362 fw_error("Failed to enable OHCI hardware.\n");
2363 goto fail_free;
2364 }
2365
2366 pci_set_master(dev);
2367 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2368 pci_set_drvdata(dev, ohci);
2369
2370 spin_lock_init(&ohci->lock);
2371
2372 tasklet_init(&ohci->bus_reset_tasklet,
2373 bus_reset_tasklet, (unsigned long)ohci);
2374
2375 err = pci_request_region(dev, 0, ohci_driver_name);
2376 if (err) {
2377 fw_error("MMIO resource unavailable\n");
2378 goto fail_disable;
2379 }
2380
2381 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2382 if (ohci->registers == NULL) {
2383 fw_error("Failed to remap registers\n");
2384 err = -ENXIO;
2385 goto fail_iomem;
2386 }
2387
2388 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2389 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2390
2391 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2392 #if !defined(CONFIG_X86_32)
2393 /* dual-buffer mode is broken with descriptor addresses above 2G */
2394 if (dev->vendor == PCI_VENDOR_ID_TI &&
2395 dev->device == PCI_DEVICE_ID_TI_TSB43AB22)
2396 ohci->use_dualbuffer = false;
2397 #endif
2398
2399 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2400 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2401 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2402 #endif
2403 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2404
2405 ar_context_init(&ohci->ar_request_ctx, ohci,
2406 OHCI1394_AsReqRcvContextControlSet);
2407
2408 ar_context_init(&ohci->ar_response_ctx, ohci,
2409 OHCI1394_AsRspRcvContextControlSet);
2410
2411 context_init(&ohci->at_request_ctx, ohci,
2412 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2413
2414 context_init(&ohci->at_response_ctx, ohci,
2415 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2416
2417 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2418 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2419 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2420 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2421 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2422
2423 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2424 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2425 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2426 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2427 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2428
2429 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2430 fw_error("Out of memory for it/ir contexts.\n");
2431 err = -ENOMEM;
2432 goto fail_registers;
2433 }
2434
2435 /* self-id dma buffer allocation */
2436 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2437 SELF_ID_BUF_SIZE,
2438 &ohci->self_id_bus,
2439 GFP_KERNEL);
2440 if (ohci->self_id_cpu == NULL) {
2441 fw_error("Out of memory for self ID buffer.\n");
2442 err = -ENOMEM;
2443 goto fail_registers;
2444 }
2445
2446 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2447 max_receive = (bus_options >> 12) & 0xf;
2448 link_speed = bus_options & 0x7;
2449 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2450 reg_read(ohci, OHCI1394_GUIDLo);
2451
2452 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2453 if (err < 0)
2454 goto fail_self_id;
2455
2456 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2457 dev->dev.bus_id, version >> 16, version & 0xff);
2458 return 0;
2459
2460 fail_self_id:
2461 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2462 ohci->self_id_cpu, ohci->self_id_bus);
2463 fail_registers:
2464 kfree(ohci->it_context_list);
2465 kfree(ohci->ir_context_list);
2466 pci_iounmap(dev, ohci->registers);
2467 fail_iomem:
2468 pci_release_region(dev, 0);
2469 fail_disable:
2470 pci_disable_device(dev);
2471 fail_free:
2472 kfree(&ohci->card);
2473 ohci_pmac_off(dev);
2474
2475 return err;
2476 }
2477
2478 static void pci_remove(struct pci_dev *dev)
2479 {
2480 struct fw_ohci *ohci;
2481
2482 ohci = pci_get_drvdata(dev);
2483 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2484 flush_writes(ohci);
2485 fw_core_remove_card(&ohci->card);
2486
2487 /*
2488 * FIXME: Fail all pending packets here, now that the upper
2489 * layers can't queue any more.
2490 */
2491
2492 software_reset(ohci);
2493 free_irq(dev->irq, ohci);
2494 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2495 ohci->self_id_cpu, ohci->self_id_bus);
2496 kfree(ohci->it_context_list);
2497 kfree(ohci->ir_context_list);
2498 pci_iounmap(dev, ohci->registers);
2499 pci_release_region(dev, 0);
2500 pci_disable_device(dev);
2501 kfree(&ohci->card);
2502 ohci_pmac_off(dev);
2503
2504 fw_notify("Removed fw-ohci device.\n");
2505 }
2506
2507 #ifdef CONFIG_PM
2508 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2509 {
2510 struct fw_ohci *ohci = pci_get_drvdata(dev);
2511 int err;
2512
2513 software_reset(ohci);
2514 free_irq(dev->irq, ohci);
2515 err = pci_save_state(dev);
2516 if (err) {
2517 fw_error("pci_save_state failed\n");
2518 return err;
2519 }
2520 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2521 if (err)
2522 fw_error("pci_set_power_state failed with %d\n", err);
2523 ohci_pmac_off(dev);
2524
2525 return 0;
2526 }
2527
2528 static int pci_resume(struct pci_dev *dev)
2529 {
2530 struct fw_ohci *ohci = pci_get_drvdata(dev);
2531 int err;
2532
2533 ohci_pmac_on(dev);
2534 pci_set_power_state(dev, PCI_D0);
2535 pci_restore_state(dev);
2536 err = pci_enable_device(dev);
2537 if (err) {
2538 fw_error("pci_enable_device failed\n");
2539 return err;
2540 }
2541
2542 return ohci_enable(&ohci->card, NULL, 0);
2543 }
2544 #endif
2545
2546 static struct pci_device_id pci_table[] = {
2547 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2548 { }
2549 };
2550
2551 MODULE_DEVICE_TABLE(pci, pci_table);
2552
2553 static struct pci_driver fw_ohci_pci_driver = {
2554 .name = ohci_driver_name,
2555 .id_table = pci_table,
2556 .probe = pci_probe,
2557 .remove = pci_remove,
2558 #ifdef CONFIG_PM
2559 .resume = pci_resume,
2560 .suspend = pci_suspend,
2561 #endif
2562 };
2563
2564 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2565 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2566 MODULE_LICENSE("GPL");
2567
2568 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2569 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2570 MODULE_ALIAS("ohci1394");
2571 #endif
2572
2573 static int __init fw_ohci_init(void)
2574 {
2575 return pci_register_driver(&fw_ohci_pci_driver);
2576 }
2577
2578 static void __exit fw_ohci_cleanup(void)
2579 {
2580 pci_unregister_driver(&fw_ohci_pci_driver);
2581 }
2582
2583 module_init(fw_ohci_init);
2584 module_exit(fw_ohci_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree