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ath9k_hw: fix calculated runtime tx power limit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_def.c
blob85057e074bfce3782498b273d859601758c7781d
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9002_phy.h"
20
21 static void ath9k_get_txgain_index(struct ath_hw *ah,
22 struct ath9k_channel *chan,
23 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
24 u8 *calChans, u16 availPiers, u8 *pwr, u8 *pcdacIdx)
25 {
26 u8 pcdac, i = 0;
27 u16 idxL = 0, idxR = 0, numPiers;
28 bool match;
29 struct chan_centers centers;
30
31 ath9k_hw_get_channel_centers(ah, chan, &centers);
32
33 for (numPiers = 0; numPiers < availPiers; numPiers++)
34 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
35 break;
36
37 match = ath9k_hw_get_lower_upper_index(
38 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
39 calChans, numPiers, &idxL, &idxR);
40 if (match) {
41 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
42 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
43 } else {
44 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
45 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
46 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
47 }
48
49 while (pcdac > ah->originalGain[i] &&
50 i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
51 i++;
52
53 *pcdacIdx = i;
54 }
55
56 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
57 u32 initTxGain,
58 int txPower,
59 u8 *pPDADCValues)
60 {
61 u32 i;
62 u32 offset;
63
64 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
65 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
66 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
67 AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
68
69 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
70 AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
71
72 offset = txPower;
73 for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
74 if (i < offset)
75 pPDADCValues[i] = 0x0;
76 else
77 pPDADCValues[i] = 0xFF;
78 }
79
80 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
81 {
82 return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
83 }
84
85 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
86 {
87 return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
88 }
89
90 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
91
92 static bool __ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
93 {
94 struct ath_common *common = ath9k_hw_common(ah);
95 u16 *eep_data = (u16 *)&ah->eeprom.def;
96 int addr, ar5416_eep_start_loc = 0x100;
97
98 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
99 if (!ath9k_hw_nvram_read(common, addr + ar5416_eep_start_loc,
100 eep_data)) {
101 ath_err(ath9k_hw_common(ah),
102 "Unable to read eeprom region\n");
103 return false;
104 }
105 eep_data++;
106 }
107 return true;
108 }
109
110 static bool __ath9k_hw_usb_def_fill_eeprom(struct ath_hw *ah)
111 {
112 u16 *eep_data = (u16 *)&ah->eeprom.def;
113
114 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
115 0x100, SIZE_EEPROM_DEF);
116 return true;
117 }
118
119 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
120 {
121 struct ath_common *common = ath9k_hw_common(ah);
122
123 if (!ath9k_hw_use_flash(ah)) {
124 ath_dbg(common, ATH_DBG_EEPROM,
125 "Reading from EEPROM, not flash\n");
126 }
127
128 if (common->bus_ops->ath_bus_type == ATH_USB)
129 return __ath9k_hw_usb_def_fill_eeprom(ah);
130 else
131 return __ath9k_hw_def_fill_eeprom(ah);
132 }
133
134 #undef SIZE_EEPROM_DEF
135
136 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
137 {
138 struct ar5416_eeprom_def *eep =
139 (struct ar5416_eeprom_def *) &ah->eeprom.def;
140 struct ath_common *common = ath9k_hw_common(ah);
141 u16 *eepdata, temp, magic, magic2;
142 u32 sum = 0, el;
143 bool need_swap = false;
144 int i, addr, size;
145
146 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
147 ath_err(common, "Reading Magic # failed\n");
148 return false;
149 }
150
151 if (!ath9k_hw_use_flash(ah)) {
152 ath_dbg(common, ATH_DBG_EEPROM,
153 "Read Magic = 0x%04X\n", magic);
154
155 if (magic != AR5416_EEPROM_MAGIC) {
156 magic2 = swab16(magic);
157
158 if (magic2 == AR5416_EEPROM_MAGIC) {
159 size = sizeof(struct ar5416_eeprom_def);
160 need_swap = true;
161 eepdata = (u16 *) (&ah->eeprom);
162
163 for (addr = 0; addr < size / sizeof(u16); addr++) {
164 temp = swab16(*eepdata);
165 *eepdata = temp;
166 eepdata++;
167 }
168 } else {
169 ath_err(common,
170 "Invalid EEPROM Magic. Endianness mismatch.\n");
171 return -EINVAL;
172 }
173 }
174 }
175
176 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
177 need_swap ? "True" : "False");
178
179 if (need_swap)
180 el = swab16(ah->eeprom.def.baseEepHeader.length);
181 else
182 el = ah->eeprom.def.baseEepHeader.length;
183
184 if (el > sizeof(struct ar5416_eeprom_def))
185 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
186 else
187 el = el / sizeof(u16);
188
189 eepdata = (u16 *)(&ah->eeprom);
190
191 for (i = 0; i < el; i++)
192 sum ^= *eepdata++;
193
194 if (need_swap) {
195 u32 integer, j;
196 u16 word;
197
198 ath_dbg(common, ATH_DBG_EEPROM,
199 "EEPROM Endianness is not native.. Changing.\n");
200
201 word = swab16(eep->baseEepHeader.length);
202 eep->baseEepHeader.length = word;
203
204 word = swab16(eep->baseEepHeader.checksum);
205 eep->baseEepHeader.checksum = word;
206
207 word = swab16(eep->baseEepHeader.version);
208 eep->baseEepHeader.version = word;
209
210 word = swab16(eep->baseEepHeader.regDmn[0]);
211 eep->baseEepHeader.regDmn[0] = word;
212
213 word = swab16(eep->baseEepHeader.regDmn[1]);
214 eep->baseEepHeader.regDmn[1] = word;
215
216 word = swab16(eep->baseEepHeader.rfSilent);
217 eep->baseEepHeader.rfSilent = word;
218
219 word = swab16(eep->baseEepHeader.blueToothOptions);
220 eep->baseEepHeader.blueToothOptions = word;
221
222 word = swab16(eep->baseEepHeader.deviceCap);
223 eep->baseEepHeader.deviceCap = word;
224
225 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
226 struct modal_eep_header *pModal =
227 &eep->modalHeader[j];
228 integer = swab32(pModal->antCtrlCommon);
229 pModal->antCtrlCommon = integer;
230
231 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
232 integer = swab32(pModal->antCtrlChain[i]);
233 pModal->antCtrlChain[i] = integer;
234 }
235 for (i = 0; i < 3; i++) {
236 word = swab16(pModal->xpaBiasLvlFreq[i]);
237 pModal->xpaBiasLvlFreq[i] = word;
238 }
239
240 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
241 word = swab16(pModal->spurChans[i].spurChan);
242 pModal->spurChans[i].spurChan = word;
243 }
244 }
245 }
246
247 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
248 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
249 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
250 sum, ah->eep_ops->get_eeprom_ver(ah));
251 return -EINVAL;
252 }
253
254 /* Enable fixup for AR_AN_TOP2 if necessary */
255 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
256 ((eep->baseEepHeader.version & 0xff) > 0x0a) &&
257 (eep->baseEepHeader.pwdclkind == 0))
258 ah->need_an_top2_fixup = 1;
259
260 if ((common->bus_ops->ath_bus_type == ATH_USB) &&
261 (AR_SREV_9280(ah)))
262 eep->modalHeader[0].xpaBiasLvl = 0;
263
264 return 0;
265 }
266
267 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
268 enum eeprom_param param)
269 {
270 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
271 struct modal_eep_header *pModal = eep->modalHeader;
272 struct base_eep_header *pBase = &eep->baseEepHeader;
273
274 switch (param) {
275 case EEP_NFTHRESH_5:
276 return pModal[0].noiseFloorThreshCh[0];
277 case EEP_NFTHRESH_2:
278 return pModal[1].noiseFloorThreshCh[0];
279 case EEP_MAC_LSW:
280 return get_unaligned_be16(pBase->macAddr);
281 case EEP_MAC_MID:
282 return get_unaligned_be16(pBase->macAddr + 2);
283 case EEP_MAC_MSW:
284 return get_unaligned_be16(pBase->macAddr + 4);
285 case EEP_REG_0:
286 return pBase->regDmn[0];
287 case EEP_REG_1:
288 return pBase->regDmn[1];
289 case EEP_OP_CAP:
290 return pBase->deviceCap;
291 case EEP_OP_MODE:
292 return pBase->opCapFlags;
293 case EEP_RF_SILENT:
294 return pBase->rfSilent;
295 case EEP_OB_5:
296 return pModal[0].ob;
297 case EEP_DB_5:
298 return pModal[0].db;
299 case EEP_OB_2:
300 return pModal[1].ob;
301 case EEP_DB_2:
302 return pModal[1].db;
303 case EEP_MINOR_REV:
304 return AR5416_VER_MASK;
305 case EEP_TX_MASK:
306 return pBase->txMask;
307 case EEP_RX_MASK:
308 return pBase->rxMask;
309 case EEP_FSTCLK_5G:
310 return pBase->fastClk5g;
311 case EEP_RXGAIN_TYPE:
312 return pBase->rxGainType;
313 case EEP_TXGAIN_TYPE:
314 return pBase->txGainType;
315 case EEP_OL_PWRCTRL:
316 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
317 return pBase->openLoopPwrCntl ? true : false;
318 else
319 return false;
320 case EEP_RC_CHAIN_MASK:
321 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
322 return pBase->rcChainMask;
323 else
324 return 0;
325 case EEP_DAC_HPWR_5G:
326 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
327 return pBase->dacHiPwrMode_5G;
328 else
329 return 0;
330 case EEP_FRAC_N_5G:
331 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
332 return pBase->frac_n_5g;
333 else
334 return 0;
335 case EEP_PWR_TABLE_OFFSET:
336 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_21)
337 return pBase->pwr_table_offset;
338 else
339 return AR5416_PWR_TABLE_OFFSET_DB;
340 default:
341 return 0;
342 }
343 }
344
345 static void ath9k_hw_def_set_gain(struct ath_hw *ah,
346 struct modal_eep_header *pModal,
347 struct ar5416_eeprom_def *eep,
348 u8 txRxAttenLocal, int regChainOffset, int i)
349 {
350 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
351 txRxAttenLocal = pModal->txRxAttenCh[i];
352
353 if (AR_SREV_9280_20_OR_LATER(ah)) {
354 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
355 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
356 pModal->bswMargin[i]);
357 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
358 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
359 pModal->bswAtten[i]);
360 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
361 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
362 pModal->xatten2Margin[i]);
363 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
364 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
365 pModal->xatten2Db[i]);
366 } else {
367 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
368 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
369 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
370 | SM(pModal-> bswMargin[i],
371 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
372 REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
373 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
374 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
375 | SM(pModal->bswAtten[i],
376 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
377 }
378 }
379
380 if (AR_SREV_9280_20_OR_LATER(ah)) {
381 REG_RMW_FIELD(ah,
382 AR_PHY_RXGAIN + regChainOffset,
383 AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
384 REG_RMW_FIELD(ah,
385 AR_PHY_RXGAIN + regChainOffset,
386 AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[i]);
387 } else {
388 REG_WRITE(ah,
389 AR_PHY_RXGAIN + regChainOffset,
390 (REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) &
391 ~AR_PHY_RXGAIN_TXRX_ATTEN)
392 | SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN));
393 REG_WRITE(ah,
394 AR_PHY_GAIN_2GHZ + regChainOffset,
395 (REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) &
396 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
397 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
398 }
399 }
400
401 static void ath9k_hw_def_set_board_values(struct ath_hw *ah,
402 struct ath9k_channel *chan)
403 {
404 struct modal_eep_header *pModal;
405 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
406 int i, regChainOffset;
407 u8 txRxAttenLocal;
408
409 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
410 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
411
412 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon & 0xffff);
413
414 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
415 if (AR_SREV_9280(ah)) {
416 if (i >= 2)
417 break;
418 }
419
420 if (AR_SREV_5416_20_OR_LATER(ah) &&
421 (ah->rxchainmask == 5 || ah->txchainmask == 5) && (i != 0))
422 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
423 else
424 regChainOffset = i * 0x1000;
425
426 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
427 pModal->antCtrlChain[i]);
428
429 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
430 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
431 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
432 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
433 SM(pModal->iqCalICh[i],
434 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
435 SM(pModal->iqCalQCh[i],
436 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
437
438 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah))
439 ath9k_hw_def_set_gain(ah, pModal, eep, txRxAttenLocal,
440 regChainOffset, i);
441 }
442
443 if (AR_SREV_9280_20_OR_LATER(ah)) {
444 if (IS_CHAN_2GHZ(chan)) {
445 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
446 AR_AN_RF2G1_CH0_OB,
447 AR_AN_RF2G1_CH0_OB_S,
448 pModal->ob);
449 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
450 AR_AN_RF2G1_CH0_DB,
451 AR_AN_RF2G1_CH0_DB_S,
452 pModal->db);
453 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
454 AR_AN_RF2G1_CH1_OB,
455 AR_AN_RF2G1_CH1_OB_S,
456 pModal->ob_ch1);
457 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
458 AR_AN_RF2G1_CH1_DB,
459 AR_AN_RF2G1_CH1_DB_S,
460 pModal->db_ch1);
461 } else {
462 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
463 AR_AN_RF5G1_CH0_OB5,
464 AR_AN_RF5G1_CH0_OB5_S,
465 pModal->ob);
466 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
467 AR_AN_RF5G1_CH0_DB5,
468 AR_AN_RF5G1_CH0_DB5_S,
469 pModal->db);
470 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
471 AR_AN_RF5G1_CH1_OB5,
472 AR_AN_RF5G1_CH1_OB5_S,
473 pModal->ob_ch1);
474 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
475 AR_AN_RF5G1_CH1_DB5,
476 AR_AN_RF5G1_CH1_DB5_S,
477 pModal->db_ch1);
478 }
479 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
480 AR_AN_TOP2_XPABIAS_LVL,
481 AR_AN_TOP2_XPABIAS_LVL_S,
482 pModal->xpaBiasLvl);
483 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
484 AR_AN_TOP2_LOCALBIAS,
485 AR_AN_TOP2_LOCALBIAS_S,
486 !!(pModal->lna_ctl &
487 LNA_CTL_LOCAL_BIAS));
488 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
489 !!(pModal->lna_ctl & LNA_CTL_FORCE_XPA));
490 }
491
492 REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
493 pModal->switchSettling);
494 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
495 pModal->adcDesiredSize);
496
497 if (!AR_SREV_9280_20_OR_LATER(ah))
498 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
499 AR_PHY_DESIRED_SZ_PGA,
500 pModal->pgaDesiredSize);
501
502 REG_WRITE(ah, AR_PHY_RF_CTL4,
503 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
504 | SM(pModal->txEndToXpaOff,
505 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
506 | SM(pModal->txFrameToXpaOn,
507 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
508 | SM(pModal->txFrameToXpaOn,
509 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
510
511 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
512 pModal->txEndToRxOn);
513
514 if (AR_SREV_9280_20_OR_LATER(ah)) {
515 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
516 pModal->thresh62);
517 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
518 AR_PHY_EXT_CCA0_THRESH62,
519 pModal->thresh62);
520 } else {
521 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
522 pModal->thresh62);
523 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
524 AR_PHY_EXT_CCA_THRESH62,
525 pModal->thresh62);
526 }
527
528 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
529 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
530 AR_PHY_TX_END_DATA_START,
531 pModal->txFrameToDataStart);
532 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
533 pModal->txFrameToPaOn);
534 }
535
536 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
537 if (IS_CHAN_HT40(chan))
538 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
539 AR_PHY_SETTLING_SWITCH,
540 pModal->swSettleHt40);
541 }
542
543 if (AR_SREV_9280_20_OR_LATER(ah) &&
544 AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
545 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
546 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
547 pModal->miscBits);
548
549
550 if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
551 if (IS_CHAN_2GHZ(chan))
552 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
553 eep->baseEepHeader.dacLpMode);
554 else if (eep->baseEepHeader.dacHiPwrMode_5G)
555 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
556 else
557 REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
558 eep->baseEepHeader.dacLpMode);
559
560 udelay(100);
561
562 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
563 pModal->miscBits >> 2);
564
565 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
566 AR_PHY_TX_DESIRED_SCALE_CCK,
567 eep->baseEepHeader.desiredScaleCCK);
568 }
569 }
570
571 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
572 struct ath9k_channel *chan)
573 {
574 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
575 struct modal_eep_header *pModal;
576 struct ar5416_eeprom_def *eep = &ah->eeprom.def;
577 u8 biaslevel;
578
579 if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
580 return;
581
582 if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
583 return;
584
585 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
586
587 if (pModal->xpaBiasLvl != 0xff) {
588 biaslevel = pModal->xpaBiasLvl;
589 } else {
590 u16 resetFreqBin, freqBin, freqCount = 0;
591 struct chan_centers centers;
592
593 ath9k_hw_get_channel_centers(ah, chan, &centers);
594
595 resetFreqBin = FREQ2FBIN(centers.synth_center,
596 IS_CHAN_2GHZ(chan));
597 freqBin = XPA_LVL_FREQ(0) & 0xff;
598 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
599
600 freqCount++;
601
602 while (freqCount < 3) {
603 if (XPA_LVL_FREQ(freqCount) == 0x0)
604 break;
605
606 freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
607 if (resetFreqBin >= freqBin)
608 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
609 else
610 break;
611 freqCount++;
612 }
613 }
614
615 if (IS_CHAN_2GHZ(chan)) {
616 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
617 7, 1) & (~0x18)) | biaslevel << 3;
618 } else {
619 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
620 6, 1) & (~0xc0)) | biaslevel << 6;
621 }
622 #undef XPA_LVL_FREQ
623 }
624
625 static int16_t ath9k_change_gain_boundary_setting(struct ath_hw *ah,
626 u16 *gb,
627 u16 numXpdGain,
628 u16 pdGainOverlap_t2,
629 int8_t pwr_table_offset,
630 int16_t *diff)
631
632 {
633 u16 k;
634
635 /* Prior to writing the boundaries or the pdadc vs. power table
636 * into the chip registers the default starting point on the pdadc
637 * vs. power table needs to be checked and the curve boundaries
638 * adjusted accordingly
639 */
640 if (AR_SREV_9280_20_OR_LATER(ah)) {
641 u16 gb_limit;
642
643 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
644 /* get the difference in dB */
645 *diff = (u16)(pwr_table_offset - AR5416_PWR_TABLE_OFFSET_DB);
646 /* get the number of half dB steps */
647 *diff *= 2;
648 /* change the original gain boundary settings
649 * by the number of half dB steps
650 */
651 for (k = 0; k < numXpdGain; k++)
652 gb[k] = (u16)(gb[k] - *diff);
653 }
654 /* Because of a hardware limitation, ensure the gain boundary
655 * is not larger than (63 - overlap)
656 */
657 gb_limit = (u16)(MAX_RATE_POWER - pdGainOverlap_t2);
658
659 for (k = 0; k < numXpdGain; k++)
660 gb[k] = (u16)min(gb_limit, gb[k]);
661 }
662
663 return *diff;
664 }
665
666 static void ath9k_adjust_pdadc_values(struct ath_hw *ah,
667 int8_t pwr_table_offset,
668 int16_t diff,
669 u8 *pdadcValues)
670 {
671 #define NUM_PDADC(diff) (AR5416_NUM_PDADC_VALUES - diff)
672 u16 k;
673
674 /* If this is a board that has a pwrTableOffset that differs from
675 * the default AR5416_PWR_TABLE_OFFSET_DB then the start of the
676 * pdadc vs pwr table needs to be adjusted prior to writing to the
677 * chip.
678 */
679 if (AR_SREV_9280_20_OR_LATER(ah)) {
680 if (AR5416_PWR_TABLE_OFFSET_DB != pwr_table_offset) {
681 /* shift the table to start at the new offset */
682 for (k = 0; k < (u16)NUM_PDADC(diff); k++ ) {
683 pdadcValues[k] = pdadcValues[k + diff];
684 }
685
686 /* fill the back of the table */
687 for (k = (u16)NUM_PDADC(diff); k < NUM_PDADC(0); k++) {
688 pdadcValues[k] = pdadcValues[NUM_PDADC(diff)];
689 }
690 }
691 }
692 #undef NUM_PDADC
693 }
694
695 static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
696 struct ath9k_channel *chan)
697 {
698 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
699 #define SM_PDGAIN_B(x, y) \
700 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
701 struct ath_common *common = ath9k_hw_common(ah);
702 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
703 struct cal_data_per_freq *pRawDataset;
704 u8 *pCalBChans = NULL;
705 u16 pdGainOverlap_t2;
706 static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
707 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
708 u16 numPiers, i, j;
709 int16_t diff = 0;
710 u16 numXpdGain, xpdMask;
711 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
712 u32 reg32, regOffset, regChainOffset;
713 int16_t modalIdx;
714 int8_t pwr_table_offset;
715
716 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
717 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
718
719 pwr_table_offset = ah->eep_ops->get_eeprom(ah, EEP_PWR_TABLE_OFFSET);
720
721 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
722 AR5416_EEP_MINOR_VER_2) {
723 pdGainOverlap_t2 =
724 pEepData->modalHeader[modalIdx].pdGainOverlap;
725 } else {
726 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
727 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
728 }
729
730 if (IS_CHAN_2GHZ(chan)) {
731 pCalBChans = pEepData->calFreqPier2G;
732 numPiers = AR5416_NUM_2G_CAL_PIERS;
733 } else {
734 pCalBChans = pEepData->calFreqPier5G;
735 numPiers = AR5416_NUM_5G_CAL_PIERS;
736 }
737
738 if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
739 pRawDataset = pEepData->calPierData2G[0];
740 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
741 pRawDataset)->vpdPdg[0][0];
742 }
743
744 numXpdGain = 0;
745
746 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
747 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
748 if (numXpdGain >= AR5416_NUM_PD_GAINS)
749 break;
750 xpdGainValues[numXpdGain] =
751 (u16)(AR5416_PD_GAINS_IN_MASK - i);
752 numXpdGain++;
753 }
754 }
755
756 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
757 (numXpdGain - 1) & 0x3);
758 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
759 xpdGainValues[0]);
760 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
761 xpdGainValues[1]);
762 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
763 xpdGainValues[2]);
764
765 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
766 if (AR_SREV_5416_20_OR_LATER(ah) &&
767 (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
768 (i != 0)) {
769 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
770 } else
771 regChainOffset = i * 0x1000;
772
773 if (pEepData->baseEepHeader.txMask & (1 << i)) {
774 if (IS_CHAN_2GHZ(chan))
775 pRawDataset = pEepData->calPierData2G[i];
776 else
777 pRawDataset = pEepData->calPierData5G[i];
778
779
780 if (OLC_FOR_AR9280_20_LATER) {
781 u8 pcdacIdx;
782 u8 txPower;
783
784 ath9k_get_txgain_index(ah, chan,
785 (struct calDataPerFreqOpLoop *)pRawDataset,
786 pCalBChans, numPiers, &txPower, &pcdacIdx);
787 ath9k_olc_get_pdadcs(ah, pcdacIdx,
788 txPower/2, pdadcValues);
789 } else {
790 ath9k_hw_get_gain_boundaries_pdadcs(ah,
791 chan, pRawDataset,
792 pCalBChans, numPiers,
793 pdGainOverlap_t2,
794 gainBoundaries,
795 pdadcValues,
796 numXpdGain);
797 }
798
799 diff = ath9k_change_gain_boundary_setting(ah,
800 gainBoundaries,
801 numXpdGain,
802 pdGainOverlap_t2,
803 pwr_table_offset,
804 &diff);
805
806 ENABLE_REGWRITE_BUFFER(ah);
807
808 if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
809 if (OLC_FOR_AR9280_20_LATER) {
810 REG_WRITE(ah,
811 AR_PHY_TPCRG5 + regChainOffset,
812 SM(0x6,
813 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
814 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
815 SM_PD_GAIN(3) | SM_PD_GAIN(4));
816 } else {
817 REG_WRITE(ah,
818 AR_PHY_TPCRG5 + regChainOffset,
819 SM(pdGainOverlap_t2,
820 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
821 SM_PDGAIN_B(0, 1) |
822 SM_PDGAIN_B(1, 2) |
823 SM_PDGAIN_B(2, 3) |
824 SM_PDGAIN_B(3, 4));
825 }
826 }
827
828
829 ath9k_adjust_pdadc_values(ah, pwr_table_offset,
830 diff, pdadcValues);
831
832 regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
833 for (j = 0; j < 32; j++) {
834 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
835 REG_WRITE(ah, regOffset, reg32);
836
837 ath_dbg(common, ATH_DBG_EEPROM,
838 "PDADC (%d,%4x): %4.4x %8.8x\n",
839 i, regChainOffset, regOffset,
840 reg32);
841 ath_dbg(common, ATH_DBG_EEPROM,
842 "PDADC: Chain %d | PDADC %3d "
843 "Value %3d | PDADC %3d Value %3d | "
844 "PDADC %3d Value %3d | PDADC %3d "
845 "Value %3d |\n",
846 i, 4 * j, pdadcValues[4 * j],
847 4 * j + 1, pdadcValues[4 * j + 1],
848 4 * j + 2, pdadcValues[4 * j + 2],
849 4 * j + 3, pdadcValues[4 * j + 3]);
850
851 regOffset += 4;
852 }
853 REGWRITE_BUFFER_FLUSH(ah);
854 }
855 }
856
857 #undef SM_PD_GAIN
858 #undef SM_PDGAIN_B
859 }
860
861 static void ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
862 struct ath9k_channel *chan,
863 int16_t *ratesArray,
864 u16 cfgCtl,
865 u16 AntennaReduction,
866 u16 twiceMaxRegulatoryPower,
867 u16 powerLimit)
868 {
869 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
870 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 9 /* 10*log10(3)*2 */
871
872 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
873 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
874 u16 twiceMaxEdgePower = MAX_RATE_POWER;
875 static const u16 tpScaleReductionTable[5] =
876 { 0, 3, 6, 9, MAX_RATE_POWER };
877
878 int i;
879 int16_t twiceLargestAntenna;
880 struct cal_ctl_data *rep;
881 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
882 0, { 0, 0, 0, 0}
883 };
884 struct cal_target_power_leg targetPowerOfdmExt = {
885 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
886 0, { 0, 0, 0, 0 }
887 };
888 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
889 0, {0, 0, 0, 0}
890 };
891 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
892 static const u16 ctlModesFor11a[] = {
893 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
894 };
895 static const u16 ctlModesFor11g[] = {
896 CTL_11B, CTL_11G, CTL_2GHT20,
897 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
898 };
899 u16 numCtlModes;
900 const u16 *pCtlMode;
901 u16 ctlMode, freq;
902 struct chan_centers centers;
903 int tx_chainmask;
904 u16 twiceMinEdgePower;
905
906 tx_chainmask = ah->txchainmask;
907
908 ath9k_hw_get_channel_centers(ah, chan, &centers);
909
910 twiceLargestAntenna = max(
911 pEepData->modalHeader
912 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
913 pEepData->modalHeader
914 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
915
916 twiceLargestAntenna = max((u8)twiceLargestAntenna,
917 pEepData->modalHeader
918 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
919
920 twiceLargestAntenna = (int16_t)min(AntennaReduction -
921 twiceLargestAntenna, 0);
922
923 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
924
925 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
926 maxRegAllowedPower -=
927 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
928 }
929
930 scaledPower = min(powerLimit, maxRegAllowedPower);
931
932 switch (ar5416_get_ntxchains(tx_chainmask)) {
933 case 1:
934 break;
935 case 2:
936 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
937 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
938 else
939 scaledPower = 0;
940 break;
941 case 3:
942 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
943 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
944 else
945 scaledPower = 0;
946 break;
947 }
948
949 if (IS_CHAN_2GHZ(chan)) {
950 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
951 SUB_NUM_CTL_MODES_AT_2G_40;
952 pCtlMode = ctlModesFor11g;
953
954 ath9k_hw_get_legacy_target_powers(ah, chan,
955 pEepData->calTargetPowerCck,
956 AR5416_NUM_2G_CCK_TARGET_POWERS,
957 &targetPowerCck, 4, false);
958 ath9k_hw_get_legacy_target_powers(ah, chan,
959 pEepData->calTargetPower2G,
960 AR5416_NUM_2G_20_TARGET_POWERS,
961 &targetPowerOfdm, 4, false);
962 ath9k_hw_get_target_powers(ah, chan,
963 pEepData->calTargetPower2GHT20,
964 AR5416_NUM_2G_20_TARGET_POWERS,
965 &targetPowerHt20, 8, false);
966
967 if (IS_CHAN_HT40(chan)) {
968 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
969 ath9k_hw_get_target_powers(ah, chan,
970 pEepData->calTargetPower2GHT40,
971 AR5416_NUM_2G_40_TARGET_POWERS,
972 &targetPowerHt40, 8, true);
973 ath9k_hw_get_legacy_target_powers(ah, chan,
974 pEepData->calTargetPowerCck,
975 AR5416_NUM_2G_CCK_TARGET_POWERS,
976 &targetPowerCckExt, 4, true);
977 ath9k_hw_get_legacy_target_powers(ah, chan,
978 pEepData->calTargetPower2G,
979 AR5416_NUM_2G_20_TARGET_POWERS,
980 &targetPowerOfdmExt, 4, true);
981 }
982 } else {
983 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
984 SUB_NUM_CTL_MODES_AT_5G_40;
985 pCtlMode = ctlModesFor11a;
986
987 ath9k_hw_get_legacy_target_powers(ah, chan,
988 pEepData->calTargetPower5G,
989 AR5416_NUM_5G_20_TARGET_POWERS,
990 &targetPowerOfdm, 4, false);
991 ath9k_hw_get_target_powers(ah, chan,
992 pEepData->calTargetPower5GHT20,
993 AR5416_NUM_5G_20_TARGET_POWERS,
994 &targetPowerHt20, 8, false);
995
996 if (IS_CHAN_HT40(chan)) {
997 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
998 ath9k_hw_get_target_powers(ah, chan,
999 pEepData->calTargetPower5GHT40,
1000 AR5416_NUM_5G_40_TARGET_POWERS,
1001 &targetPowerHt40, 8, true);
1002 ath9k_hw_get_legacy_target_powers(ah, chan,
1003 pEepData->calTargetPower5G,
1004 AR5416_NUM_5G_20_TARGET_POWERS,
1005 &targetPowerOfdmExt, 4, true);
1006 }
1007 }
1008
1009 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
1010 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
1011 (pCtlMode[ctlMode] == CTL_2GHT40);
1012 if (isHt40CtlMode)
1013 freq = centers.synth_center;
1014 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
1015 freq = centers.ext_center;
1016 else
1017 freq = centers.ctl_center;
1018
1019 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
1020 ah->eep_ops->get_eeprom_rev(ah) <= 2)
1021 twiceMaxEdgePower = MAX_RATE_POWER;
1022
1023 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
1024 if ((((cfgCtl & ~CTL_MODE_M) |
1025 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1026 pEepData->ctlIndex[i]) ||
1027 (((cfgCtl & ~CTL_MODE_M) |
1028 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
1029 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
1030 rep = &(pEepData->ctlData[i]);
1031
1032 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
1033 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
1034 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
1035
1036 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
1037 twiceMaxEdgePower = min(twiceMaxEdgePower,
1038 twiceMinEdgePower);
1039 } else {
1040 twiceMaxEdgePower = twiceMinEdgePower;
1041 break;
1042 }
1043 }
1044 }
1045
1046 minCtlPower = min(twiceMaxEdgePower, scaledPower);
1047
1048 switch (pCtlMode[ctlMode]) {
1049 case CTL_11B:
1050 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
1051 targetPowerCck.tPow2x[i] =
1052 min((u16)targetPowerCck.tPow2x[i],
1053 minCtlPower);
1054 }
1055 break;
1056 case CTL_11A:
1057 case CTL_11G:
1058 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
1059 targetPowerOfdm.tPow2x[i] =
1060 min((u16)targetPowerOfdm.tPow2x[i],
1061 minCtlPower);
1062 }
1063 break;
1064 case CTL_5GHT20:
1065 case CTL_2GHT20:
1066 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
1067 targetPowerHt20.tPow2x[i] =
1068 min((u16)targetPowerHt20.tPow2x[i],
1069 minCtlPower);
1070 }
1071 break;
1072 case CTL_11B_EXT:
1073 targetPowerCckExt.tPow2x[0] = min((u16)
1074 targetPowerCckExt.tPow2x[0],
1075 minCtlPower);
1076 break;
1077 case CTL_11A_EXT:
1078 case CTL_11G_EXT:
1079 targetPowerOfdmExt.tPow2x[0] = min((u16)
1080 targetPowerOfdmExt.tPow2x[0],
1081 minCtlPower);
1082 break;
1083 case CTL_5GHT40:
1084 case CTL_2GHT40:
1085 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1086 targetPowerHt40.tPow2x[i] =
1087 min((u16)targetPowerHt40.tPow2x[i],
1088 minCtlPower);
1089 }
1090 break;
1091 default:
1092 break;
1093 }
1094 }
1095
1096 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1097 ratesArray[rate18mb] = ratesArray[rate24mb] =
1098 targetPowerOfdm.tPow2x[0];
1099 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1100 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1101 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1102 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1103
1104 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1105 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1106
1107 if (IS_CHAN_2GHZ(chan)) {
1108 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1109 ratesArray[rate2s] = ratesArray[rate2l] =
1110 targetPowerCck.tPow2x[1];
1111 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
1112 targetPowerCck.tPow2x[2];
1113 ratesArray[rate11s] = ratesArray[rate11l] =
1114 targetPowerCck.tPow2x[3];
1115 }
1116 if (IS_CHAN_HT40(chan)) {
1117 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1118 ratesArray[rateHt40_0 + i] =
1119 targetPowerHt40.tPow2x[i];
1120 }
1121 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1122 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1123 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1124 if (IS_CHAN_2GHZ(chan)) {
1125 ratesArray[rateExtCck] =
1126 targetPowerCckExt.tPow2x[0];
1127 }
1128 }
1129 }
1130
1131 static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1132 struct ath9k_channel *chan,
1133 u16 cfgCtl,
1134 u8 twiceAntennaReduction,
1135 u8 twiceMaxRegulatoryPower,
1136 u8 powerLimit, bool test)
1137 {
1138 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
1139 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1140 struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
1141 struct modal_eep_header *pModal =
1142 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
1143 int16_t ratesArray[Ar5416RateSize];
1144 u8 ht40PowerIncForPdadc = 2;
1145 int i, cck_ofdm_delta = 0;
1146
1147 memset(ratesArray, 0, sizeof(ratesArray));
1148
1149 if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1150 AR5416_EEP_MINOR_VER_2) {
1151 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1152 }
1153
1154 ath9k_hw_set_def_power_per_rate_table(ah, chan,
1155 &ratesArray[0], cfgCtl,
1156 twiceAntennaReduction,
1157 twiceMaxRegulatoryPower,
1158 powerLimit);
1159
1160 ath9k_hw_set_def_power_cal_table(ah, chan);
1161
1162 regulatory->max_power_level = 0;
1163 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1164 if (ratesArray[i] > MAX_RATE_POWER)
1165 ratesArray[i] = MAX_RATE_POWER;
1166 if (ratesArray[i] > regulatory->max_power_level)
1167 regulatory->max_power_level = ratesArray[i];
1168 }
1169
1170 switch(ar5416_get_ntxchains(ah->txchainmask)) {
1171 case 1:
1172 break;
1173 case 2:
1174 regulatory->max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
1175 break;
1176 case 3:
1177 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1178 break;
1179 default:
1180 ath_dbg(ath9k_hw_common(ah), ATH_DBG_EEPROM,
1181 "Invalid chainmask configuration\n");
1182 break;
1183 }
1184
1185 if (test)
1186 return;
1187
1188 if (AR_SREV_9280_20_OR_LATER(ah)) {
1189 for (i = 0; i < Ar5416RateSize; i++) {
1190 int8_t pwr_table_offset;
1191
1192 pwr_table_offset = ah->eep_ops->get_eeprom(ah,
1193 EEP_PWR_TABLE_OFFSET);
1194 ratesArray[i] -= pwr_table_offset * 2;
1195 }
1196 }
1197
1198 ENABLE_REGWRITE_BUFFER(ah);
1199
1200 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1201 ATH9K_POW_SM(ratesArray[rate18mb], 24)
1202 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1203 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1204 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1205 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1206 ATH9K_POW_SM(ratesArray[rate54mb], 24)
1207 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1208 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1209 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1210
1211 if (IS_CHAN_2GHZ(chan)) {
1212 if (OLC_FOR_AR9280_20_LATER) {
1213 cck_ofdm_delta = 2;
1214 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1215 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
1216 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
1217 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1218 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
1219 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1220 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
1221 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
1222 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
1223 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
1224 } else {
1225 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1226 ATH9K_POW_SM(ratesArray[rate2s], 24)
1227 | ATH9K_POW_SM(ratesArray[rate2l], 16)
1228 | ATH9K_POW_SM(ratesArray[rateXr], 8)
1229 | ATH9K_POW_SM(ratesArray[rate1l], 0));
1230 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1231 ATH9K_POW_SM(ratesArray[rate11s], 24)
1232 | ATH9K_POW_SM(ratesArray[rate11l], 16)
1233 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1234 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1235 }
1236 }
1237
1238 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1239 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1240 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1241 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1242 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1243 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1244 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1245 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1246 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1247 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1248
1249 if (IS_CHAN_HT40(chan)) {
1250 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1251 ATH9K_POW_SM(ratesArray[rateHt40_3] +
1252 ht40PowerIncForPdadc, 24)
1253 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1254 ht40PowerIncForPdadc, 16)
1255 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1256 ht40PowerIncForPdadc, 8)
1257 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1258 ht40PowerIncForPdadc, 0));
1259 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1260 ATH9K_POW_SM(ratesArray[rateHt40_7] +
1261 ht40PowerIncForPdadc, 24)
1262 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1263 ht40PowerIncForPdadc, 16)
1264 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1265 ht40PowerIncForPdadc, 8)
1266 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1267 ht40PowerIncForPdadc, 0));
1268 if (OLC_FOR_AR9280_20_LATER) {
1269 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1270 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1271 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
1272 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1273 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
1274 } else {
1275 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1276 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1277 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1278 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1279 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1280 }
1281 }
1282
1283 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
1284 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
1285 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
1286
1287 REGWRITE_BUFFER_FLUSH(ah);
1288 }
1289
1290 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1291 {
1292 #define EEP_DEF_SPURCHAN \
1293 (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
1294 struct ath_common *common = ath9k_hw_common(ah);
1295
1296 u16 spur_val = AR_NO_SPUR;
1297
1298 ath_dbg(common, ATH_DBG_ANI,
1299 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1300 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1301
1302 switch (ah->config.spurmode) {
1303 case SPUR_DISABLE:
1304 break;
1305 case SPUR_ENABLE_IOCTL:
1306 spur_val = ah->config.spurchans[i][is2GHz];
1307 ath_dbg(common, ATH_DBG_ANI,
1308 "Getting spur val from new loc. %d\n", spur_val);
1309 break;
1310 case SPUR_ENABLE_EEPROM:
1311 spur_val = EEP_DEF_SPURCHAN;
1312 break;
1313 }
1314
1315 return spur_val;
1316
1317 #undef EEP_DEF_SPURCHAN
1318 }
1319
1320 const struct eeprom_ops eep_def_ops = {
1321 .check_eeprom = ath9k_hw_def_check_eeprom,
1322 .get_eeprom = ath9k_hw_def_get_eeprom,
1323 .fill_eeprom = ath9k_hw_def_fill_eeprom,
1324 .get_eeprom_ver = ath9k_hw_def_get_eeprom_ver,
1325 .get_eeprom_rev = ath9k_hw_def_get_eeprom_rev,
1326 .set_board_values = ath9k_hw_def_set_board_values,
1327 .set_addac = ath9k_hw_def_set_addac,
1328 .set_txpower = ath9k_hw_def_set_txpower,
1329 .get_spur_channel = ath9k_hw_def_get_spur_channel
1330 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree