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ath9k_hw: fix calculated runtime tx power limit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / eeprom_9287.c
blob604312cfe8cb046a435225868428d6c84424421c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <asm/unaligned.h>
18 #include "hw.h"
19 #include "ar9002_phy.h"
20
21 #define SIZE_EEPROM_AR9287 (sizeof(struct ar9287_eeprom) / sizeof(u16))
22
23 static int ath9k_hw_ar9287_get_eeprom_ver(struct ath_hw *ah)
24 {
25 return (ah->eeprom.map9287.baseEepHeader.version >> 12) & 0xF;
26 }
27
28 static int ath9k_hw_ar9287_get_eeprom_rev(struct ath_hw *ah)
29 {
30 return (ah->eeprom.map9287.baseEepHeader.version) & 0xFFF;
31 }
32
33 static bool __ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
34 {
35 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
36 struct ath_common *common = ath9k_hw_common(ah);
37 u16 *eep_data;
38 int addr, eep_start_loc = AR9287_EEP_START_LOC;
39 eep_data = (u16 *)eep;
40
41 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
42 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc,
43 eep_data)) {
44 ath_dbg(common, ATH_DBG_EEPROM,
45 "Unable to read eeprom region\n");
46 return false;
47 }
48 eep_data++;
49 }
50
51 return true;
52 }
53
54 static bool __ath9k_hw_usb_ar9287_fill_eeprom(struct ath_hw *ah)
55 {
56 u16 *eep_data = (u16 *)&ah->eeprom.map9287;
57
58 ath9k_hw_usb_gen_fill_eeprom(ah, eep_data,
59 AR9287_HTC_EEP_START_LOC,
60 SIZE_EEPROM_AR9287);
61 return true;
62 }
63
64 static bool ath9k_hw_ar9287_fill_eeprom(struct ath_hw *ah)
65 {
66 struct ath_common *common = ath9k_hw_common(ah);
67
68 if (!ath9k_hw_use_flash(ah)) {
69 ath_dbg(common, ATH_DBG_EEPROM,
70 "Reading from EEPROM, not flash\n");
71 }
72
73 if (common->bus_ops->ath_bus_type == ATH_USB)
74 return __ath9k_hw_usb_ar9287_fill_eeprom(ah);
75 else
76 return __ath9k_hw_ar9287_fill_eeprom(ah);
77 }
78
79 static int ath9k_hw_ar9287_check_eeprom(struct ath_hw *ah)
80 {
81 u32 sum = 0, el, integer;
82 u16 temp, word, magic, magic2, *eepdata;
83 int i, addr;
84 bool need_swap = false;
85 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
86 struct ath_common *common = ath9k_hw_common(ah);
87
88 if (!ath9k_hw_use_flash(ah)) {
89 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
90 &magic)) {
91 ath_err(common, "Reading Magic # failed\n");
92 return false;
93 }
94
95 ath_dbg(common, ATH_DBG_EEPROM,
96 "Read Magic = 0x%04X\n", magic);
97
98 if (magic != AR5416_EEPROM_MAGIC) {
99 magic2 = swab16(magic);
100
101 if (magic2 == AR5416_EEPROM_MAGIC) {
102 need_swap = true;
103 eepdata = (u16 *)(&ah->eeprom);
104
105 for (addr = 0; addr < SIZE_EEPROM_AR9287; addr++) {
106 temp = swab16(*eepdata);
107 *eepdata = temp;
108 eepdata++;
109 }
110 } else {
111 ath_err(common,
112 "Invalid EEPROM Magic. Endianness mismatch.\n");
113 return -EINVAL;
114 }
115 }
116 }
117
118 ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
119 need_swap ? "True" : "False");
120
121 if (need_swap)
122 el = swab16(ah->eeprom.map9287.baseEepHeader.length);
123 else
124 el = ah->eeprom.map9287.baseEepHeader.length;
125
126 if (el > sizeof(struct ar9287_eeprom))
127 el = sizeof(struct ar9287_eeprom) / sizeof(u16);
128 else
129 el = el / sizeof(u16);
130
131 eepdata = (u16 *)(&ah->eeprom);
132
133 for (i = 0; i < el; i++)
134 sum ^= *eepdata++;
135
136 if (need_swap) {
137 word = swab16(eep->baseEepHeader.length);
138 eep->baseEepHeader.length = word;
139
140 word = swab16(eep->baseEepHeader.checksum);
141 eep->baseEepHeader.checksum = word;
142
143 word = swab16(eep->baseEepHeader.version);
144 eep->baseEepHeader.version = word;
145
146 word = swab16(eep->baseEepHeader.regDmn[0]);
147 eep->baseEepHeader.regDmn[0] = word;
148
149 word = swab16(eep->baseEepHeader.regDmn[1]);
150 eep->baseEepHeader.regDmn[1] = word;
151
152 word = swab16(eep->baseEepHeader.rfSilent);
153 eep->baseEepHeader.rfSilent = word;
154
155 word = swab16(eep->baseEepHeader.blueToothOptions);
156 eep->baseEepHeader.blueToothOptions = word;
157
158 word = swab16(eep->baseEepHeader.deviceCap);
159 eep->baseEepHeader.deviceCap = word;
160
161 integer = swab32(eep->modalHeader.antCtrlCommon);
162 eep->modalHeader.antCtrlCommon = integer;
163
164 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
165 integer = swab32(eep->modalHeader.antCtrlChain[i]);
166 eep->modalHeader.antCtrlChain[i] = integer;
167 }
168
169 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
170 word = swab16(eep->modalHeader.spurChans[i].spurChan);
171 eep->modalHeader.spurChans[i].spurChan = word;
172 }
173 }
174
175 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
176 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
177 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
178 sum, ah->eep_ops->get_eeprom_ver(ah));
179 return -EINVAL;
180 }
181
182 return 0;
183 }
184
185 static u32 ath9k_hw_ar9287_get_eeprom(struct ath_hw *ah,
186 enum eeprom_param param)
187 {
188 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
189 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
190 struct base_eep_ar9287_header *pBase = &eep->baseEepHeader;
191 u16 ver_minor;
192
193 ver_minor = pBase->version & AR9287_EEP_VER_MINOR_MASK;
194
195 switch (param) {
196 case EEP_NFTHRESH_2:
197 return pModal->noiseFloorThreshCh[0];
198 case EEP_MAC_LSW:
199 return get_unaligned_be16(pBase->macAddr);
200 case EEP_MAC_MID:
201 return get_unaligned_be16(pBase->macAddr + 2);
202 case EEP_MAC_MSW:
203 return get_unaligned_be16(pBase->macAddr + 4);
204 case EEP_REG_0:
205 return pBase->regDmn[0];
206 case EEP_REG_1:
207 return pBase->regDmn[1];
208 case EEP_OP_CAP:
209 return pBase->deviceCap;
210 case EEP_OP_MODE:
211 return pBase->opCapFlags;
212 case EEP_RF_SILENT:
213 return pBase->rfSilent;
214 case EEP_MINOR_REV:
215 return ver_minor;
216 case EEP_TX_MASK:
217 return pBase->txMask;
218 case EEP_RX_MASK:
219 return pBase->rxMask;
220 case EEP_DEV_TYPE:
221 return pBase->deviceType;
222 case EEP_OL_PWRCTRL:
223 return pBase->openLoopPwrCntl;
224 case EEP_TEMPSENSE_SLOPE:
225 if (ver_minor >= AR9287_EEP_MINOR_VER_2)
226 return pBase->tempSensSlope;
227 else
228 return 0;
229 case EEP_TEMPSENSE_SLOPE_PAL_ON:
230 if (ver_minor >= AR9287_EEP_MINOR_VER_3)
231 return pBase->tempSensSlopePalOn;
232 else
233 return 0;
234 default:
235 return 0;
236 }
237 }
238
239 static void ar9287_eeprom_get_tx_gain_index(struct ath_hw *ah,
240 struct ath9k_channel *chan,
241 struct cal_data_op_loop_ar9287 *pRawDatasetOpLoop,
242 u8 *pCalChans, u16 availPiers, int8_t *pPwr)
243 {
244 u16 idxL = 0, idxR = 0, numPiers;
245 bool match;
246 struct chan_centers centers;
247
248 ath9k_hw_get_channel_centers(ah, chan, &centers);
249
250 for (numPiers = 0; numPiers < availPiers; numPiers++) {
251 if (pCalChans[numPiers] == AR5416_BCHAN_UNUSED)
252 break;
253 }
254
255 match = ath9k_hw_get_lower_upper_index(
256 (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
257 pCalChans, numPiers, &idxL, &idxR);
258
259 if (match) {
260 *pPwr = (int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0];
261 } else {
262 *pPwr = ((int8_t) pRawDatasetOpLoop[idxL].pwrPdg[0][0] +
263 (int8_t) pRawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
264 }
265
266 }
267
268 static void ar9287_eeprom_olpc_set_pdadcs(struct ath_hw *ah,
269 int32_t txPower, u16 chain)
270 {
271 u32 tmpVal;
272 u32 a;
273
274 /* Enable OLPC for chain 0 */
275
276 tmpVal = REG_READ(ah, 0xa270);
277 tmpVal = tmpVal & 0xFCFFFFFF;
278 tmpVal = tmpVal | (0x3 << 24);
279 REG_WRITE(ah, 0xa270, tmpVal);
280
281 /* Enable OLPC for chain 1 */
282
283 tmpVal = REG_READ(ah, 0xb270);
284 tmpVal = tmpVal & 0xFCFFFFFF;
285 tmpVal = tmpVal | (0x3 << 24);
286 REG_WRITE(ah, 0xb270, tmpVal);
287
288 /* Write the OLPC ref power for chain 0 */
289
290 if (chain == 0) {
291 tmpVal = REG_READ(ah, 0xa398);
292 tmpVal = tmpVal & 0xff00ffff;
293 a = (txPower)&0xff;
294 tmpVal = tmpVal | (a << 16);
295 REG_WRITE(ah, 0xa398, tmpVal);
296 }
297
298 /* Write the OLPC ref power for chain 1 */
299
300 if (chain == 1) {
301 tmpVal = REG_READ(ah, 0xb398);
302 tmpVal = tmpVal & 0xff00ffff;
303 a = (txPower)&0xff;
304 tmpVal = tmpVal | (a << 16);
305 REG_WRITE(ah, 0xb398, tmpVal);
306 }
307 }
308
309 static void ath9k_hw_set_ar9287_power_cal_table(struct ath_hw *ah,
310 struct ath9k_channel *chan)
311 {
312 struct cal_data_per_freq_ar9287 *pRawDataset;
313 struct cal_data_op_loop_ar9287 *pRawDatasetOpenLoop;
314 u8 *pCalBChans = NULL;
315 u16 pdGainOverlap_t2;
316 u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
317 u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
318 u16 numPiers = 0, i, j;
319 u16 numXpdGain, xpdMask;
320 u16 xpdGainValues[AR5416_NUM_PD_GAINS] = {0, 0, 0, 0};
321 u32 reg32, regOffset, regChainOffset, regval;
322 int16_t diff = 0;
323 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
324
325 xpdMask = pEepData->modalHeader.xpdGain;
326
327 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
328 AR9287_EEP_MINOR_VER_2)
329 pdGainOverlap_t2 = pEepData->modalHeader.pdGainOverlap;
330 else
331 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
332 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
333
334 if (IS_CHAN_2GHZ(chan)) {
335 pCalBChans = pEepData->calFreqPier2G;
336 numPiers = AR9287_NUM_2G_CAL_PIERS;
337 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
338 pRawDatasetOpenLoop =
339 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[0];
340 ah->initPDADC = pRawDatasetOpenLoop->vpdPdg[0][0];
341 }
342 }
343
344 numXpdGain = 0;
345
346 /* Calculate the value of xpdgains from the xpdGain Mask */
347 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
348 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
349 if (numXpdGain >= AR5416_NUM_PD_GAINS)
350 break;
351 xpdGainValues[numXpdGain] =
352 (u16)(AR5416_PD_GAINS_IN_MASK-i);
353 numXpdGain++;
354 }
355 }
356
357 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
358 (numXpdGain - 1) & 0x3);
359 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
360 xpdGainValues[0]);
361 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
362 xpdGainValues[1]);
363 REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
364 xpdGainValues[2]);
365
366 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
367 regChainOffset = i * 0x1000;
368
369 if (pEepData->baseEepHeader.txMask & (1 << i)) {
370 pRawDatasetOpenLoop =
371 (struct cal_data_op_loop_ar9287 *)pEepData->calPierData2G[i];
372
373 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
374 int8_t txPower;
375 ar9287_eeprom_get_tx_gain_index(ah, chan,
376 pRawDatasetOpenLoop,
377 pCalBChans, numPiers,
378 &txPower);
379 ar9287_eeprom_olpc_set_pdadcs(ah, txPower, i);
380 } else {
381 pRawDataset =
382 (struct cal_data_per_freq_ar9287 *)
383 pEepData->calPierData2G[i];
384
385 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
386 pRawDataset,
387 pCalBChans, numPiers,
388 pdGainOverlap_t2,
389 gainBoundaries,
390 pdadcValues,
391 numXpdGain);
392 }
393
394 ENABLE_REGWRITE_BUFFER(ah);
395
396 if (i == 0) {
397 if (!ath9k_hw_ar9287_get_eeprom(ah,
398 EEP_OL_PWRCTRL)) {
399
400 regval = SM(pdGainOverlap_t2,
401 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
402 | SM(gainBoundaries[0],
403 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
404 | SM(gainBoundaries[1],
405 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
406 | SM(gainBoundaries[2],
407 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
408 | SM(gainBoundaries[3],
409 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4);
410
411 REG_WRITE(ah,
412 AR_PHY_TPCRG5 + regChainOffset,
413 regval);
414 }
415 }
416
417 if ((int32_t)AR9287_PWR_TABLE_OFFSET_DB !=
418 pEepData->baseEepHeader.pwrTableOffset) {
419 diff = (u16)(pEepData->baseEepHeader.pwrTableOffset -
420 (int32_t)AR9287_PWR_TABLE_OFFSET_DB);
421 diff *= 2;
422
423 for (j = 0; j < ((u16)AR5416_NUM_PDADC_VALUES-diff); j++)
424 pdadcValues[j] = pdadcValues[j+diff];
425
426 for (j = (u16)(AR5416_NUM_PDADC_VALUES-diff);
427 j < AR5416_NUM_PDADC_VALUES; j++)
428 pdadcValues[j] =
429 pdadcValues[AR5416_NUM_PDADC_VALUES-diff];
430 }
431
432 if (!ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
433 regOffset = AR_PHY_BASE +
434 (672 << 2) + regChainOffset;
435
436 for (j = 0; j < 32; j++) {
437 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
438
439 REG_WRITE(ah, regOffset, reg32);
440 regOffset += 4;
441 }
442 }
443 REGWRITE_BUFFER_FLUSH(ah);
444 }
445 }
446 }
447
448 static void ath9k_hw_set_ar9287_power_per_rate_table(struct ath_hw *ah,
449 struct ath9k_channel *chan,
450 int16_t *ratesArray,
451 u16 cfgCtl,
452 u16 AntennaReduction,
453 u16 twiceMaxRegulatoryPower,
454 u16 powerLimit)
455 {
456 #define CMP_CTL \
457 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
458 pEepData->ctlIndex[i])
459
460 #define CMP_NO_CTL \
461 (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
462 ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
463
464 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN 6
465 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN 10
466
467 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
468 u16 twiceMaxEdgePower = MAX_RATE_POWER;
469 static const u16 tpScaleReductionTable[5] =
470 { 0, 3, 6, 9, MAX_RATE_POWER };
471 int i;
472 int16_t twiceLargestAntenna;
473 struct cal_ctl_data_ar9287 *rep;
474 struct cal_target_power_leg targetPowerOfdm = {0, {0, 0, 0, 0} },
475 targetPowerCck = {0, {0, 0, 0, 0} };
476 struct cal_target_power_leg targetPowerOfdmExt = {0, {0, 0, 0, 0} },
477 targetPowerCckExt = {0, {0, 0, 0, 0} };
478 struct cal_target_power_ht targetPowerHt20,
479 targetPowerHt40 = {0, {0, 0, 0, 0} };
480 u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
481 static const u16 ctlModesFor11g[] = {
482 CTL_11B, CTL_11G, CTL_2GHT20,
483 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
484 };
485 u16 numCtlModes = 0;
486 const u16 *pCtlMode = NULL;
487 u16 ctlMode, freq;
488 struct chan_centers centers;
489 int tx_chainmask;
490 u16 twiceMinEdgePower;
491 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
492 tx_chainmask = ah->txchainmask;
493
494 ath9k_hw_get_channel_centers(ah, chan, &centers);
495
496 /* Compute TxPower reduction due to Antenna Gain */
497 twiceLargestAntenna = max(pEepData->modalHeader.antennaGainCh[0],
498 pEepData->modalHeader.antennaGainCh[1]);
499 twiceLargestAntenna = (int16_t)min((AntennaReduction) -
500 twiceLargestAntenna, 0);
501
502 /*
503 * scaledPower is the minimum of the user input power level
504 * and the regulatory allowed power level.
505 */
506 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
507
508 if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX)
509 maxRegAllowedPower -=
510 (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
511
512 scaledPower = min(powerLimit, maxRegAllowedPower);
513
514 /*
515 * Reduce scaled Power by number of chains active
516 * to get the per chain tx power level.
517 */
518 switch (ar5416_get_ntxchains(tx_chainmask)) {
519 case 1:
520 break;
521 case 2:
522 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
523 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
524 else
525 scaledPower = 0;
526 break;
527 case 3:
528 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
529 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
530 else
531 scaledPower = 0;
532 break;
533 }
534 scaledPower = max((u16)0, scaledPower);
535
536 /*
537 * Get TX power from EEPROM.
538 */
539 if (IS_CHAN_2GHZ(chan)) {
540 /* CTL_11B, CTL_11G, CTL_2GHT20 */
541 numCtlModes =
542 ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
543
544 pCtlMode = ctlModesFor11g;
545
546 ath9k_hw_get_legacy_target_powers(ah, chan,
547 pEepData->calTargetPowerCck,
548 AR9287_NUM_2G_CCK_TARGET_POWERS,
549 &targetPowerCck, 4, false);
550 ath9k_hw_get_legacy_target_powers(ah, chan,
551 pEepData->calTargetPower2G,
552 AR9287_NUM_2G_20_TARGET_POWERS,
553 &targetPowerOfdm, 4, false);
554 ath9k_hw_get_target_powers(ah, chan,
555 pEepData->calTargetPower2GHT20,
556 AR9287_NUM_2G_20_TARGET_POWERS,
557 &targetPowerHt20, 8, false);
558
559 if (IS_CHAN_HT40(chan)) {
560 /* All 2G CTLs */
561 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
562 ath9k_hw_get_target_powers(ah, chan,
563 pEepData->calTargetPower2GHT40,
564 AR9287_NUM_2G_40_TARGET_POWERS,
565 &targetPowerHt40, 8, true);
566 ath9k_hw_get_legacy_target_powers(ah, chan,
567 pEepData->calTargetPowerCck,
568 AR9287_NUM_2G_CCK_TARGET_POWERS,
569 &targetPowerCckExt, 4, true);
570 ath9k_hw_get_legacy_target_powers(ah, chan,
571 pEepData->calTargetPower2G,
572 AR9287_NUM_2G_20_TARGET_POWERS,
573 &targetPowerOfdmExt, 4, true);
574 }
575 }
576
577 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
578 bool isHt40CtlMode =
579 (pCtlMode[ctlMode] == CTL_2GHT40) ? true : false;
580
581 if (isHt40CtlMode)
582 freq = centers.synth_center;
583 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
584 freq = centers.ext_center;
585 else
586 freq = centers.ctl_center;
587
588 /* Walk through the CTL indices stored in EEPROM */
589 for (i = 0; (i < AR9287_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
590 struct cal_ctl_edges *pRdEdgesPower;
591
592 /*
593 * Compare test group from regulatory channel list
594 * with test mode from pCtlMode list
595 */
596 if (CMP_CTL || CMP_NO_CTL) {
597 rep = &(pEepData->ctlData[i]);
598 pRdEdgesPower =
599 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1];
600
601 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
602 pRdEdgesPower,
603 IS_CHAN_2GHZ(chan),
604 AR5416_NUM_BAND_EDGES);
605
606 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
607 twiceMaxEdgePower = min(twiceMaxEdgePower,
608 twiceMinEdgePower);
609 } else {
610 twiceMaxEdgePower = twiceMinEdgePower;
611 break;
612 }
613 }
614 }
615
616 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
617
618 /* Apply ctl mode to correct target power set */
619 switch (pCtlMode[ctlMode]) {
620 case CTL_11B:
621 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
622 targetPowerCck.tPow2x[i] =
623 (u8)min((u16)targetPowerCck.tPow2x[i],
624 minCtlPower);
625 }
626 break;
627 case CTL_11A:
628 case CTL_11G:
629 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
630 targetPowerOfdm.tPow2x[i] =
631 (u8)min((u16)targetPowerOfdm.tPow2x[i],
632 minCtlPower);
633 }
634 break;
635 case CTL_5GHT20:
636 case CTL_2GHT20:
637 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
638 targetPowerHt20.tPow2x[i] =
639 (u8)min((u16)targetPowerHt20.tPow2x[i],
640 minCtlPower);
641 }
642 break;
643 case CTL_11B_EXT:
644 targetPowerCckExt.tPow2x[0] =
645 (u8)min((u16)targetPowerCckExt.tPow2x[0],
646 minCtlPower);
647 break;
648 case CTL_11A_EXT:
649 case CTL_11G_EXT:
650 targetPowerOfdmExt.tPow2x[0] =
651 (u8)min((u16)targetPowerOfdmExt.tPow2x[0],
652 minCtlPower);
653 break;
654 case CTL_5GHT40:
655 case CTL_2GHT40:
656 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
657 targetPowerHt40.tPow2x[i] =
658 (u8)min((u16)targetPowerHt40.tPow2x[i],
659 minCtlPower);
660 }
661 break;
662 default:
663 break;
664 }
665 }
666
667 /* Now set the rates array */
668
669 ratesArray[rate6mb] =
670 ratesArray[rate9mb] =
671 ratesArray[rate12mb] =
672 ratesArray[rate18mb] =
673 ratesArray[rate24mb] = targetPowerOfdm.tPow2x[0];
674
675 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
676 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
677 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
678 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
679
680 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
681 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
682
683 if (IS_CHAN_2GHZ(chan)) {
684 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
685 ratesArray[rate2s] =
686 ratesArray[rate2l] = targetPowerCck.tPow2x[1];
687 ratesArray[rate5_5s] =
688 ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
689 ratesArray[rate11s] =
690 ratesArray[rate11l] = targetPowerCck.tPow2x[3];
691 }
692 if (IS_CHAN_HT40(chan)) {
693 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++)
694 ratesArray[rateHt40_0 + i] = targetPowerHt40.tPow2x[i];
695
696 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
697 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
698 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
699
700 if (IS_CHAN_2GHZ(chan))
701 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
702 }
703
704 #undef CMP_CTL
705 #undef CMP_NO_CTL
706 #undef REDUCE_SCALED_POWER_BY_TWO_CHAIN
707 #undef REDUCE_SCALED_POWER_BY_THREE_CHAIN
708 }
709
710 static void ath9k_hw_ar9287_set_txpower(struct ath_hw *ah,
711 struct ath9k_channel *chan, u16 cfgCtl,
712 u8 twiceAntennaReduction,
713 u8 twiceMaxRegulatoryPower,
714 u8 powerLimit, bool test)
715 {
716 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
717 struct ar9287_eeprom *pEepData = &ah->eeprom.map9287;
718 struct modal_eep_ar9287_header *pModal = &pEepData->modalHeader;
719 int16_t ratesArray[Ar5416RateSize];
720 u8 ht40PowerIncForPdadc = 2;
721 int i;
722
723 memset(ratesArray, 0, sizeof(ratesArray));
724
725 if ((pEepData->baseEepHeader.version & AR9287_EEP_VER_MINOR_MASK) >=
726 AR9287_EEP_MINOR_VER_2)
727 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
728
729 ath9k_hw_set_ar9287_power_per_rate_table(ah, chan,
730 &ratesArray[0], cfgCtl,
731 twiceAntennaReduction,
732 twiceMaxRegulatoryPower,
733 powerLimit);
734
735 ath9k_hw_set_ar9287_power_cal_table(ah, chan);
736
737 regulatory->max_power_level = 0;
738 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
739 if (ratesArray[i] > MAX_RATE_POWER)
740 ratesArray[i] = MAX_RATE_POWER;
741
742 if (ratesArray[i] > regulatory->max_power_level)
743 regulatory->max_power_level = ratesArray[i];
744 }
745
746 if (test)
747 return;
748
749 if (AR_SREV_9280_20_OR_LATER(ah)) {
750 for (i = 0; i < Ar5416RateSize; i++)
751 ratesArray[i] -= AR9287_PWR_TABLE_OFFSET_DB * 2;
752 }
753
754 ENABLE_REGWRITE_BUFFER(ah);
755
756 /* OFDM power per rate */
757 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
758 ATH9K_POW_SM(ratesArray[rate18mb], 24)
759 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
760 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
761 | ATH9K_POW_SM(ratesArray[rate6mb], 0));
762
763 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
764 ATH9K_POW_SM(ratesArray[rate54mb], 24)
765 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
766 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
767 | ATH9K_POW_SM(ratesArray[rate24mb], 0));
768
769 /* CCK power per rate */
770 if (IS_CHAN_2GHZ(chan)) {
771 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
772 ATH9K_POW_SM(ratesArray[rate2s], 24)
773 | ATH9K_POW_SM(ratesArray[rate2l], 16)
774 | ATH9K_POW_SM(ratesArray[rateXr], 8)
775 | ATH9K_POW_SM(ratesArray[rate1l], 0));
776 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
777 ATH9K_POW_SM(ratesArray[rate11s], 24)
778 | ATH9K_POW_SM(ratesArray[rate11l], 16)
779 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
780 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
781 }
782
783 /* HT20 power per rate */
784 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
785 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
786 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
787 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
788 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
789
790 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
791 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
792 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
793 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
794 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
795
796 /* HT40 power per rate */
797 if (IS_CHAN_HT40(chan)) {
798 if (ath9k_hw_ar9287_get_eeprom(ah, EEP_OL_PWRCTRL)) {
799 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
800 ATH9K_POW_SM(ratesArray[rateHt40_3], 24)
801 | ATH9K_POW_SM(ratesArray[rateHt40_2], 16)
802 | ATH9K_POW_SM(ratesArray[rateHt40_1], 8)
803 | ATH9K_POW_SM(ratesArray[rateHt40_0], 0));
804
805 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
806 ATH9K_POW_SM(ratesArray[rateHt40_7], 24)
807 | ATH9K_POW_SM(ratesArray[rateHt40_6], 16)
808 | ATH9K_POW_SM(ratesArray[rateHt40_5], 8)
809 | ATH9K_POW_SM(ratesArray[rateHt40_4], 0));
810 } else {
811 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
812 ATH9K_POW_SM(ratesArray[rateHt40_3] +
813 ht40PowerIncForPdadc, 24)
814 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
815 ht40PowerIncForPdadc, 16)
816 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
817 ht40PowerIncForPdadc, 8)
818 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
819 ht40PowerIncForPdadc, 0));
820
821 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
822 ATH9K_POW_SM(ratesArray[rateHt40_7] +
823 ht40PowerIncForPdadc, 24)
824 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
825 ht40PowerIncForPdadc, 16)
826 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
827 ht40PowerIncForPdadc, 8)
828 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
829 ht40PowerIncForPdadc, 0));
830 }
831
832 /* Dup/Ext power per rate */
833 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
834 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
835 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
836 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
837 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
838 }
839 REGWRITE_BUFFER_FLUSH(ah);
840 }
841
842 static void ath9k_hw_ar9287_set_addac(struct ath_hw *ah,
843 struct ath9k_channel *chan)
844 {
845 }
846
847 static void ath9k_hw_ar9287_set_board_values(struct ath_hw *ah,
848 struct ath9k_channel *chan)
849 {
850 struct ar9287_eeprom *eep = &ah->eeprom.map9287;
851 struct modal_eep_ar9287_header *pModal = &eep->modalHeader;
852 u32 regChainOffset, regval;
853 u8 txRxAttenLocal;
854 int i;
855
856 pModal = &eep->modalHeader;
857
858 REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
859
860 for (i = 0; i < AR9287_MAX_CHAINS; i++) {
861 regChainOffset = i * 0x1000;
862
863 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
864 pModal->antCtrlChain[i]);
865
866 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
867 (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset)
868 & ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
869 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
870 SM(pModal->iqCalICh[i],
871 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
872 SM(pModal->iqCalQCh[i],
873 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
874
875 txRxAttenLocal = pModal->txRxAttenCh[i];
876
877 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
878 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
879 pModal->bswMargin[i]);
880 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
881 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
882 pModal->bswAtten[i]);
883 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
884 AR9280_PHY_RXGAIN_TXRX_ATTEN,
885 txRxAttenLocal);
886 REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
887 AR9280_PHY_RXGAIN_TXRX_MARGIN,
888 pModal->rxTxMarginCh[i]);
889 }
890
891
892 if (IS_CHAN_HT40(chan))
893 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
894 AR_PHY_SETTLING_SWITCH, pModal->swSettleHt40);
895 else
896 REG_RMW_FIELD(ah, AR_PHY_SETTLING,
897 AR_PHY_SETTLING_SWITCH, pModal->switchSettling);
898
899 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
900 AR_PHY_DESIRED_SZ_ADC, pModal->adcDesiredSize);
901
902 REG_WRITE(ah, AR_PHY_RF_CTL4,
903 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
904 | SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
905 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)
906 | SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
907
908 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3,
909 AR_PHY_TX_END_TO_A2_RX_ON, pModal->txEndToRxOn);
910
911 REG_RMW_FIELD(ah, AR_PHY_CCA,
912 AR9280_PHY_CCA_THRESH62, pModal->thresh62);
913 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
914 AR_PHY_EXT_CCA0_THRESH62, pModal->thresh62);
915
916 regval = REG_READ(ah, AR9287_AN_RF2G3_CH0);
917 regval &= ~(AR9287_AN_RF2G3_DB1 |
918 AR9287_AN_RF2G3_DB2 |
919 AR9287_AN_RF2G3_OB_CCK |
920 AR9287_AN_RF2G3_OB_PSK |
921 AR9287_AN_RF2G3_OB_QAM |
922 AR9287_AN_RF2G3_OB_PAL_OFF);
923 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
924 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
925 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
926 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
927 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
928 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
929
930 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH0, regval);
931
932 regval = REG_READ(ah, AR9287_AN_RF2G3_CH1);
933 regval &= ~(AR9287_AN_RF2G3_DB1 |
934 AR9287_AN_RF2G3_DB2 |
935 AR9287_AN_RF2G3_OB_CCK |
936 AR9287_AN_RF2G3_OB_PSK |
937 AR9287_AN_RF2G3_OB_QAM |
938 AR9287_AN_RF2G3_OB_PAL_OFF);
939 regval |= (SM(pModal->db1, AR9287_AN_RF2G3_DB1) |
940 SM(pModal->db2, AR9287_AN_RF2G3_DB2) |
941 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) |
942 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) |
943 SM(pModal->ob_qam, AR9287_AN_RF2G3_OB_QAM) |
944 SM(pModal->ob_pal_off, AR9287_AN_RF2G3_OB_PAL_OFF));
945
946 ath9k_hw_analog_shift_regwrite(ah, AR9287_AN_RF2G3_CH1, regval);
947
948 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
949 AR_PHY_TX_END_DATA_START, pModal->txFrameToDataStart);
950 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
951 AR_PHY_TX_END_PA_ON, pModal->txFrameToPaOn);
952
953 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TOP2,
954 AR9287_AN_TOP2_XPABIAS_LVL,
955 AR9287_AN_TOP2_XPABIAS_LVL_S,
956 pModal->xpaBiasLvl);
957 }
958
959 static u16 ath9k_hw_ar9287_get_spur_channel(struct ath_hw *ah,
960 u16 i, bool is2GHz)
961 {
962 #define EEP_MAP9287_SPURCHAN \
963 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
964
965 struct ath_common *common = ath9k_hw_common(ah);
966 u16 spur_val = AR_NO_SPUR;
967
968 ath_dbg(common, ATH_DBG_ANI,
969 "Getting spur idx:%d is2Ghz:%d val:%x\n",
970 i, is2GHz, ah->config.spurchans[i][is2GHz]);
971
972 switch (ah->config.spurmode) {
973 case SPUR_DISABLE:
974 break;
975 case SPUR_ENABLE_IOCTL:
976 spur_val = ah->config.spurchans[i][is2GHz];
977 ath_dbg(common, ATH_DBG_ANI,
978 "Getting spur val from new loc. %d\n", spur_val);
979 break;
980 case SPUR_ENABLE_EEPROM:
981 spur_val = EEP_MAP9287_SPURCHAN;
982 break;
983 }
984
985 return spur_val;
986
987 #undef EEP_MAP9287_SPURCHAN
988 }
989
990 const struct eeprom_ops eep_ar9287_ops = {
991 .check_eeprom = ath9k_hw_ar9287_check_eeprom,
992 .get_eeprom = ath9k_hw_ar9287_get_eeprom,
993 .fill_eeprom = ath9k_hw_ar9287_fill_eeprom,
994 .get_eeprom_ver = ath9k_hw_ar9287_get_eeprom_ver,
995 .get_eeprom_rev = ath9k_hw_ar9287_get_eeprom_rev,
996 .set_board_values = ath9k_hw_ar9287_set_board_values,
997 .set_addac = ath9k_hw_ar9287_set_addac,
998 .set_txpower = ath9k_hw_ar9287_set_txpower,
999 .get_spur_channel = ath9k_hw_ar9287_get_spur_channel
1000 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree