2 * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Freescale DIU Frame Buffer device driver
6 * Authors: Hongjun Chen <hong-jun.chen@freescale.com>
7 * Paul Widmer <paul.widmer@freescale.com>
8 * Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
9 * York Sun <yorksun@freescale.com>
11 * Based on imxfb.c Copyright (C) 2004 S.Hauer, Pengutronix
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
20 #ifndef __FSL_DIU_FB_H__
21 #define __FSL_DIU_FB_H__
23 #include <linux/types.h>
25 struct mfb_chroma_key
{
35 struct aoi_display_offset
{
40 #define MFB_SET_CHROMA_KEY _IOW('M', 1, struct mfb_chroma_key)
41 #define MFB_SET_BRIGHTNESS _IOW('M', 3, __u8)
42 #define MFB_SET_ALPHA _IOW('M', 0, __u8)
43 #define MFB_GET_ALPHA _IOR('M', 0, __u8)
44 #define MFB_SET_AOID _IOW('M', 4, struct aoi_display_offset)
45 #define MFB_GET_AOID _IOR('M', 4, struct aoi_display_offset)
46 #define MFB_SET_PIXFMT _IOW('M', 8, __u32)
47 #define MFB_GET_PIXFMT _IOR('M', 8, __u32)
50 * The original definitions of MFB_SET_PIXFMT and MFB_GET_PIXFMT used the
51 * wrong value for 'size' field of the ioctl. The current macros above use the
52 * right size, but we still need to provide backwards compatibility, at least
55 #define MFB_SET_PIXFMT_OLD 0x80014d08
56 #define MFB_GET_PIXFMT_OLD 0x40014d08
61 * These are the fields of area descriptor(in DDR memory) for every plane
64 /* Word 0(32-bit) in DDR memory */
66 /* __u16 pixel_s:2; */
67 /* __u16 pallete:1; */
69 /* __u16 green_c:2; */
71 /* __u16 alpha_c:3; */
75 __be32 pix_fmt
; /* hard coding pixel format */
77 /* Word 1(32-bit) in DDR memory */
80 /* Word 2(32-bit) in DDR memory */
81 /* __u32 delta_xs:11; */
83 /* __u32 delta_ys:11; */
85 /* __u32 g_alpha:8; */
86 __le32 src_size_g_alpha
;
88 /* Word 3(32-bit) in DDR memory */
89 /* __u32 delta_xi:11; */
91 /* __u32 delta_yi:11; */
96 /* Word 4(32-bit) in DDR memory */
104 /* Word 5(32-bit) in DDR memory */
105 /*__u32 offset_xd:11;
112 /* Word 6(32-bit) in DDR memory */
118 /* Word 7(32-bit) in DDR memory */
125 /* Word 8(32-bit) in DDR memory */
128 /* Word 9(32-bit) in DDR memory, just for 64-bit aligned */
130 } __attribute__ ((packed
));
132 /* DIU register map */
154 } __attribute__ ((packed
));
157 * Modes of operation of DIU. The DIU supports five different modes, but
158 * the driver only supports modes 0 and 1.
160 #define MFB_MODE0 0 /* DIU off */
161 #define MFB_MODE1 1 /* All three planes output to display */
163 #endif /* __KERNEL__ */
164 #endif /* __FSL_DIU_FB_H__ */