drivers/staging/echo/mmx.h

   1 /*
   2  * mmx.h
   3  * Copyright (C) 1997-2001 H. Dietz and R. Fisher
   4  *
   5  * This file is part of FFmpeg.
   6  *
   7  * FFmpeg is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2.1 of the License, or (at your option) any later version.
  11  *
  12  * FFmpeg is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with FFmpeg; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  20  */
  21 #ifndef AVCODEC_I386MMX_H
  22 #define AVCODEC_I386MMX_H
  23
  24 /*
  25  * The type of an value that fits in an MMX register (note that long
  26  * long constant values MUST be suffixed by LL and unsigned long long
  27  * values by ULL, lest they be truncated by the compiler)
  28  */
  29
  30 union mmx_t {
  31         long long q;            /* Quadword (64-bit) value */
  32         unsigned long long uq;  /* Unsigned Quadword */
  33         int d[2];               /* 2 Doubleword (32-bit) values */
  34         unsigned int ud[2];     /* 2 Unsigned Doubleword */
  35         short w[4];             /* 4 Word (16-bit) values */
  36         unsigned short uw[4];   /* 4 Unsigned Word */
  37         char b[8];              /* 8 Byte (8-bit) values */
  38         unsigned char ub[8];    /* 8 Unsigned Byte */
  39         float s[2];             /* Single-precision (32-bit) value */
  40 };                              /* On an 8-byte (64-bit) boundary */
  41
  42 /* SSE registers */
  43 union xmm_t {
  44         char b[16];
  45 };
  46
  47 #define mmx_i2r(op, imm, reg) \
  48         __asm__ __volatile__ (#op " %0, %%" #reg \
  49                                 : /* nothing */ \
  50                                 : "i" (imm))
  51
  52 #define mmx_m2r(op, mem, reg) \
  53         __asm__ __volatile__ (#op " %0, %%" #reg \
  54                                 : /* nothing */ \
  55                                 : "m" (mem))
  56
  57 #define mmx_r2m(op, reg, mem) \
  58         __asm__ __volatile__ (#op " %%" #reg ", %0" \
  59                                 : "=m" (mem) \
  60                                 : /* nothing */)
  61
  62 #define mmx_r2r(op, regs, regd) \
  63         __asm__ __volatile__ (#op " %" #regs ", %" #regd)
  64
  65 #define emms() __asm__ __volatile__ ("emms")
  66
  67 #define movd_m2r(var, reg)      mmx_m2r(movd, var, reg)
  68 #define movd_r2m(reg, var)      mmx_r2m(movd, reg, var)
  69 #define movd_r2r(regs, regd)    mmx_r2r(movd, regs, regd)
  70
  71 #define movq_m2r(var, reg)      mmx_m2r(movq, var, reg)
  72 #define movq_r2m(reg, var)      mmx_r2m(movq, reg, var)
  73 #define movq_r2r(regs, regd)    mmx_r2r(movq, regs, regd)
  74
  75 #define packssdw_m2r(var, reg)          mmx_m2r(packssdw, var, reg)
  76 #define packssdw_r2r(regs, regd)        mmx_r2r(packssdw, regs, regd)
  77 #define packsswb_m2r(var, reg)          mmx_m2r(packsswb, var, reg)
  78 #define packsswb_r2r(regs, regd)        mmx_r2r(packsswb, regs, regd)
  79
  80 #define packuswb_m2r(var, reg)          mmx_m2r(packuswb, var, reg)
  81 #define packuswb_r2r(regs, regd)        mmx_r2r(packuswb, regs, regd)
  82
  83 #define paddb_m2r(var, reg)     mmx_m2r(paddb, var, reg)
  84 #define paddb_r2r(regs, regd)   mmx_r2r(paddb, regs, regd)
  85 #define paddd_m2r(var, reg)     mmx_m2r(paddd, var, reg)
  86 #define paddd_r2r(regs, regd)   mmx_r2r(paddd, regs, regd)
  87 #define paddw_m2r(var, reg)     mmx_m2r(paddw, var, reg)
  88 #define paddw_r2r(regs, regd)   mmx_r2r(paddw, regs, regd)
  89
  90 #define paddsb_m2r(var, reg)    mmx_m2r(paddsb, var, reg)
  91 #define paddsb_r2r(regs, regd)  mmx_r2r(paddsb, regs, regd)
  92 #define paddsw_m2r(var, reg)    mmx_m2r(paddsw, var, reg)
  93 #define paddsw_r2r(regs, regd)  mmx_r2r(paddsw, regs, regd)
  94
  95 #define paddusb_m2r(var, reg)   mmx_m2r(paddusb, var, reg)
  96 #define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
  97 #define paddusw_m2r(var, reg)   mmx_m2r(paddusw, var, reg)
  98 #define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
  99
 100 #define pand_m2r(var, reg)      mmx_m2r(pand, var, reg)
 101 #define pand_r2r(regs, regd)    mmx_r2r(pand, regs, regd)
 102
 103 #define pandn_m2r(var, reg)     mmx_m2r(pandn, var, reg)
 104 #define pandn_r2r(regs, regd)   mmx_r2r(pandn, regs, regd)
 105
 106 #define pcmpeqb_m2r(var, reg)   mmx_m2r(pcmpeqb, var, reg)
 107 #define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
 108 #define pcmpeqd_m2r(var, reg)   mmx_m2r(pcmpeqd, var, reg)
 109 #define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
 110 #define pcmpeqw_m2r(var, reg)   mmx_m2r(pcmpeqw, var, reg)
 111 #define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
 112
 113 #define pcmpgtb_m2r(var, reg)   mmx_m2r(pcmpgtb, var, reg)
 114 #define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
 115 #define pcmpgtd_m2r(var, reg)   mmx_m2r(pcmpgtd, var, reg)
 116 #define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
 117 #define pcmpgtw_m2r(var, reg)   mmx_m2r(pcmpgtw, var, reg)
 118 #define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
 119
 120 #define pmaddwd_m2r(var, reg)   mmx_m2r(pmaddwd, var, reg)
 121 #define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
 122
 123 #define pmulhw_m2r(var, reg)    mmx_m2r(pmulhw, var, reg)
 124 #define pmulhw_r2r(regs, regd)  mmx_r2r(pmulhw, regs, regd)
 125
 126 #define pmullw_m2r(var, reg)    mmx_m2r(pmullw, var, reg)
 127 #define pmullw_r2r(regs, regd)  mmx_r2r(pmullw, regs, regd)
 128
 129 #define por_m2r(var, reg)       mmx_m2r(por, var, reg)
 130 #define por_r2r(regs, regd)     mmx_r2r(por, regs, regd)
 131
 132 #define pslld_i2r(imm, reg)     mmx_i2r(pslld, imm, reg)
 133 #define pslld_m2r(var, reg)     mmx_m2r(pslld, var, reg)
 134 #define pslld_r2r(regs, regd)   mmx_r2r(pslld, regs, regd)
 135 #define psllq_i2r(imm, reg)     mmx_i2r(psllq, imm, reg)
 136 #define psllq_m2r(var, reg)     mmx_m2r(psllq, var, reg)
 137 #define psllq_r2r(regs, regd)   mmx_r2r(psllq, regs, regd)
 138 #define psllw_i2r(imm, reg)     mmx_i2r(psllw, imm, reg)
 139 #define psllw_m2r(var, reg)     mmx_m2r(psllw, var, reg)
 140 #define psllw_r2r(regs, regd)   mmx_r2r(psllw, regs, regd)
 141
 142 #define psrad_i2r(imm, reg)     mmx_i2r(psrad, imm, reg)
 143 #define psrad_m2r(var, reg)     mmx_m2r(psrad, var, reg)
 144 #define psrad_r2r(regs, regd)   mmx_r2r(psrad, regs, regd)
 145 #define psraw_i2r(imm, reg)     mmx_i2r(psraw, imm, reg)
 146 #define psraw_m2r(var, reg)     mmx_m2r(psraw, var, reg)
 147 #define psraw_r2r(regs, regd)   mmx_r2r(psraw, regs, regd)
 148
 149 #define psrld_i2r(imm, reg)     mmx_i2r(psrld, imm, reg)
 150 #define psrld_m2r(var, reg)     mmx_m2r(psrld, var, reg)
 151 #define psrld_r2r(regs, regd)   mmx_r2r(psrld, regs, regd)
 152 #define psrlq_i2r(imm, reg)     mmx_i2r(psrlq, imm, reg)
 153 #define psrlq_m2r(var, reg)     mmx_m2r(psrlq, var, reg)
 154 #define psrlq_r2r(regs, regd)   mmx_r2r(psrlq, regs, regd)
 155 #define psrlw_i2r(imm, reg)     mmx_i2r(psrlw, imm, reg)
 156 #define psrlw_m2r(var, reg)     mmx_m2r(psrlw, var, reg)
 157 #define psrlw_r2r(regs, regd)   mmx_r2r(psrlw, regs, regd)
 158
 159 #define psubb_m2r(var, reg)     mmx_m2r(psubb, var, reg)
 160 #define psubb_r2r(regs, regd)   mmx_r2r(psubb, regs, regd)
 161 #define psubd_m2r(var, reg)     mmx_m2r(psubd, var, reg)
 162 #define psubd_r2r(regs, regd)   mmx_r2r(psubd, regs, regd)
 163 #define psubw_m2r(var, reg)     mmx_m2r(psubw, var, reg)
 164 #define psubw_r2r(regs, regd)   mmx_r2r(psubw, regs, regd)
 165
 166 #define psubsb_m2r(var, reg)    mmx_m2r(psubsb, var, reg)
 167 #define psubsb_r2r(regs, regd)  mmx_r2r(psubsb, regs, regd)
 168 #define psubsw_m2r(var, reg)    mmx_m2r(psubsw, var, reg)
 169 #define psubsw_r2r(regs, regd)  mmx_r2r(psubsw, regs, regd)
 170
 171 #define psubusb_m2r(var, reg)   mmx_m2r(psubusb, var, reg)
 172 #define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
 173 #define psubusw_m2r(var, reg)   mmx_m2r(psubusw, var, reg)
 174 #define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
 175
 176 #define punpckhbw_m2r(var, reg)         mmx_m2r(punpckhbw, var, reg)
 177 #define punpckhbw_r2r(regs, regd)       mmx_r2r(punpckhbw, regs, regd)
 178 #define punpckhdq_m2r(var, reg)         mmx_m2r(punpckhdq, var, reg)
 179 #define punpckhdq_r2r(regs, regd)       mmx_r2r(punpckhdq, regs, regd)
 180 #define punpckhwd_m2r(var, reg)         mmx_m2r(punpckhwd, var, reg)
 181 #define punpckhwd_r2r(regs, regd)       mmx_r2r(punpckhwd, regs, regd)
 182
 183 #define punpcklbw_m2r(var, reg)         mmx_m2r(punpcklbw, var, reg)
 184 #define punpcklbw_r2r(regs, regd)       mmx_r2r(punpcklbw, regs, regd)
 185 #define punpckldq_m2r(var, reg)         mmx_m2r(punpckldq, var, reg)
 186 #define punpckldq_r2r(regs, regd)       mmx_r2r(punpckldq, regs, regd)
 187 #define punpcklwd_m2r(var, reg)         mmx_m2r(punpcklwd, var, reg)
 188 #define punpcklwd_r2r(regs, regd)       mmx_r2r(punpcklwd, regs, regd)
 189
 190 #define pxor_m2r(var, reg)      mmx_m2r(pxor, var, reg)
 191 #define pxor_r2r(regs, regd)    mmx_r2r(pxor, regs, regd)
 192
 193 /* 3DNOW extensions */
 194
 195 #define pavgusb_m2r(var, reg)   mmx_m2r(pavgusb, var, reg)
 196 #define pavgusb_r2r(regs, regd) mmx_r2r(pavgusb, regs, regd)
 197
 198 /* AMD MMX extensions - also available in intel SSE */
 199
 200 #define mmx_m2ri(op, mem, reg, imm) \
 201         __asm__ __volatile__ (#op " %1, %0, %%" #reg \
 202                                 : /* nothing */ \
 203                                 : "m" (mem), "i" (imm))
 204 #define mmx_r2ri(op, regs, regd, imm) \
 205         __asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
 206                                 : /* nothing */ \
 207                                 : "i" (imm))
 208
 209 #define mmx_fetch(mem, hint) \
 210         __asm__ __volatile__ ("prefetch" #hint " %0" \
 211                                 : /* nothing */ \
 212                                 : "m" (mem))
 213
 214 #define maskmovq(regs, maskreg) mmx_r2ri(maskmovq, regs, maskreg)
 215
 216 #define movntq_r2m(mmreg, var)  mmx_r2m(movntq, mmreg, var)
 217
 218 #define pavgb_m2r(var, reg)     mmx_m2r(pavgb, var, reg)
 219 #define pavgb_r2r(regs, regd)   mmx_r2r(pavgb, regs, regd)
 220 #define pavgw_m2r(var, reg)     mmx_m2r(pavgw, var, reg)
 221 #define pavgw_r2r(regs, regd)   mmx_r2r(pavgw, regs, regd)
 222
 223 #define pextrw_r2r(mmreg, reg, imm)     mmx_r2ri(pextrw, mmreg, reg, imm)
 224
 225 #define pinsrw_r2r(reg, mmreg, imm)     mmx_r2ri(pinsrw, reg, mmreg, imm)
 226
 227 #define pmaxsw_m2r(var, reg)    mmx_m2r(pmaxsw, var, reg)
 228 #define pmaxsw_r2r(regs, regd)  mmx_r2r(pmaxsw, regs, regd)
 229
 230 #define pmaxub_m2r(var, reg)    mmx_m2r(pmaxub, var, reg)
 231 #define pmaxub_r2r(regs, regd)  mmx_r2r(pmaxub, regs, regd)
 232
 233 #define pminsw_m2r(var, reg)    mmx_m2r(pminsw, var, reg)
 234 #define pminsw_r2r(regs, regd)  mmx_r2r(pminsw, regs, regd)
 235
 236 #define pminub_m2r(var, reg)    mmx_m2r(pminub, var, reg)
 237 #define pminub_r2r(regs, regd)  mmx_r2r(pminub, regs, regd)
 238
 239 #define pmovmskb(mmreg, reg) \
 240         __asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg)
 241
 242 #define pmulhuw_m2r(var, reg)   mmx_m2r(pmulhuw, var, reg)
 243 #define pmulhuw_r2r(regs, regd) mmx_r2r(pmulhuw, regs, regd)
 244
 245 #define prefetcht0(mem)         mmx_fetch(mem, t0)
 246 #define prefetcht1(mem)         mmx_fetch(mem, t1)
 247 #define prefetcht2(mem)         mmx_fetch(mem, t2)
 248 #define prefetchnta(mem)        mmx_fetch(mem, nta)
 249
 250 #define psadbw_m2r(var, reg)    mmx_m2r(psadbw, var, reg)
 251 #define psadbw_r2r(regs, regd)  mmx_r2r(psadbw, regs, regd)
 252
 253 #define pshufw_m2r(var, reg, imm)       mmx_m2ri(pshufw, var, reg, imm)
 254 #define pshufw_r2r(regs, regd, imm)     mmx_r2ri(pshufw, regs, regd, imm)
 255
 256 #define sfence() __asm__ __volatile__ ("sfence\n\t")
 257
 258 /* SSE2 */
 259 #define pshufhw_m2r(var, reg, imm)      mmx_m2ri(pshufhw, var, reg, imm)
 260 #define pshufhw_r2r(regs, regd, imm)    mmx_r2ri(pshufhw, regs, regd, imm)
 261 #define pshuflw_m2r(var, reg, imm)      mmx_m2ri(pshuflw, var, reg, imm)
 262 #define pshuflw_r2r(regs, regd, imm)    mmx_r2ri(pshuflw, regs, regd, imm)
 263
 264 #define pshufd_r2r(regs, regd, imm)     mmx_r2ri(pshufd, regs, regd, imm)
 265
 266 #define movdqa_m2r(var, reg)    mmx_m2r(movdqa, var, reg)
 267 #define movdqa_r2m(reg, var)    mmx_r2m(movdqa, reg, var)
 268 #define movdqa_r2r(regs, regd)  mmx_r2r(movdqa, regs, regd)
 269 #define movdqu_m2r(var, reg)    mmx_m2r(movdqu, var, reg)
 270 #define movdqu_r2m(reg, var)    mmx_r2m(movdqu, reg, var)
 271 #define movdqu_r2r(regs, regd)  mmx_r2r(movdqu, regs, regd)
 272
 273 #define pmullw_r2m(reg, var)    mmx_r2m(pmullw, reg, var)
 274
 275 #define pslldq_i2r(imm, reg)    mmx_i2r(pslldq, imm, reg)
 276 #define psrldq_i2r(imm, reg)    mmx_i2r(psrldq, imm, reg)
 277
 278 #define punpcklqdq_r2r(regs, regd)      mmx_r2r(punpcklqdq, regs, regd)
 279 #define punpckhqdq_r2r(regs, regd)      mmx_r2r(punpckhqdq, regs, regd)
 280
 281 #endif /* AVCODEC_I386MMX_H */