sound/arm/pxa2xx-ac97-lib.c

   1 /*
   2  * Based on sound/arm/pxa2xx-ac97.c and sound/soc/pxa/pxa2xx-ac97.c
   3  * which contain:
   4  *
   5  * Author:      Nicolas Pitre
   6  * Created:     Dec 02, 2004
   7  * Copyright:   MontaVista Software Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19
  20 #include <sound/ac97_codec.h>
  21 #include <sound/pxa2xx-lib.h>
  22
  23 #include <asm/irq.h>
  24 #include <mach/hardware.h>
  25 #include <mach/regs-ac97.h>
  26 #include <mach/pxa2xx-gpio.h>
  27 #include <mach/audio.h>
  28
  29 static DEFINE_MUTEX(car_mutex);
  30 static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  31 static volatile long gsr_bits;
  32 static struct clk *ac97_clk;
  33 static struct clk *ac97conf_clk;
  34 static int reset_gpio;
  35
  36 /*
  37  * Beware PXA27x bugs:
  38  *
  39  *   o Slot 12 read from modem space will hang controller.
  40  *   o CDONE, SDONE interrupt fails after any slot 12 IO.
  41  *
  42  * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  43  * 1 jiffy timeout if interrupt never comes).
  44  */
  45
  46 enum {
  47         RESETGPIO_FORCE_HIGH,
  48         RESETGPIO_FORCE_LOW,
  49         RESETGPIO_NORMAL_ALTFUNC
  50 };
  51
  52 /**
  53  * set_resetgpio_mode - computes and sets the AC97_RESET gpio mode on PXA
  54  * @mode: chosen action
  55  *
  56  * As the PXA27x CPUs suffer from a AC97 bug, a manual control of the reset line
  57  * must be done to insure proper work of AC97 reset line.  This function
  58  * computes the correct gpio_mode for further use by reset functions, and
  59  * applied the change through pxa_gpio_mode.
  60  */
  61 static void set_resetgpio_mode(int resetgpio_action)
  62 {
  63         int mode = 0;
  64
  65         if (reset_gpio)
  66                 switch (resetgpio_action) {
  67                 case RESETGPIO_NORMAL_ALTFUNC:
  68                         if (reset_gpio == 113)
  69                                 mode = 113 | GPIO_OUT | GPIO_DFLT_LOW;
  70                         if (reset_gpio == 95)
  71                                 mode = 95 | GPIO_ALT_FN_1_OUT;
  72                         break;
  73                 case RESETGPIO_FORCE_LOW:
  74                         mode = reset_gpio | GPIO_OUT | GPIO_DFLT_LOW;
  75                         break;
  76                 case RESETGPIO_FORCE_HIGH:
  77                         mode = reset_gpio | GPIO_OUT | GPIO_DFLT_HIGH;
  78                         break;
  79                 };
  80
  81         if (mode)
  82                 pxa_gpio_mode(mode);
  83 }
  84
  85 unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  86 {
  87         unsigned short val = -1;
  88         volatile u32 *reg_addr;
  89
  90         mutex_lock(&car_mutex);
  91
  92         /* set up primary or secondary codec space */
  93         if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
  94                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
  95         else
  96                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
  97         reg_addr += (reg >> 1);
  98
  99         /* start read access across the ac97 link */
 100         GSR = GSR_CDONE | GSR_SDONE;
 101         gsr_bits = 0;
 102         val = *reg_addr;
 103         if (reg == AC97_GPIO_STATUS)
 104                 goto out;
 105         if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
 106             !((GSR | gsr_bits) & GSR_SDONE)) {
 107                 printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
 108                                 __func__, reg, GSR | gsr_bits);
 109                 val = -1;
 110                 goto out;
 111         }
 112
 113         /* valid data now */
 114         GSR = GSR_CDONE | GSR_SDONE;
 115         gsr_bits = 0;
 116         val = *reg_addr;
 117         /* but we've just started another cycle... */
 118         wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
 119
 120 out:    mutex_unlock(&car_mutex);
 121         return val;
 122 }
 123 EXPORT_SYMBOL_GPL(pxa2xx_ac97_read);
 124
 125 void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
 126                         unsigned short val)
 127 {
 128         volatile u32 *reg_addr;
 129
 130         mutex_lock(&car_mutex);
 131
 132         /* set up primary or secondary codec space */
 133         if (cpu_is_pxa25x() && reg == AC97_GPIO_STATUS)
 134                 reg_addr = ac97->num ? &SMC_REG_BASE : &PMC_REG_BASE;
 135         else
 136                 reg_addr = ac97->num ? &SAC_REG_BASE : &PAC_REG_BASE;
 137         reg_addr += (reg >> 1);
 138
 139         GSR = GSR_CDONE | GSR_SDONE;
 140         gsr_bits = 0;
 141         *reg_addr = val;
 142         if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
 143             !((GSR | gsr_bits) & GSR_CDONE))
 144                 printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
 145                                 __func__, reg, GSR | gsr_bits);
 146
 147         mutex_unlock(&car_mutex);
 148 }
 149 EXPORT_SYMBOL_GPL(pxa2xx_ac97_write);
 150
 151 #ifdef CONFIG_PXA25x
 152 static inline void pxa_ac97_warm_pxa25x(void)
 153 {
 154         gsr_bits = 0;
 155
 156         GCR |= GCR_WARM_RST | GCR_PRIRDY_IEN | GCR_SECRDY_IEN;
 157         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
 158 }
 159
 160 static inline void pxa_ac97_cold_pxa25x(void)
 161 {
 162         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 163         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 164
 165         gsr_bits = 0;
 166
 167         GCR = GCR_COLD_RST;
 168         GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
 169         wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
 170 }
 171 #endif
 172
 173 #ifdef CONFIG_PXA27x
 174 static inline void pxa_ac97_warm_pxa27x(void)
 175 {
 176         gsr_bits = 0;
 177
 178         /* warm reset broken on Bulverde,
 179            so manually keep AC97 reset high */
 180         set_resetgpio_mode(RESETGPIO_FORCE_HIGH);
 181         udelay(10);
 182         GCR |= GCR_WARM_RST;
 183         set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
 184         udelay(500);
 185 }
 186
 187 static inline void pxa_ac97_cold_pxa27x(void)
 188 {
 189         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 190         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 191
 192         gsr_bits = 0;
 193
 194         /* PXA27x Developers Manual section 13.5.2.2.1 */
 195         clk_enable(ac97conf_clk);
 196         udelay(5);
 197         clk_disable(ac97conf_clk);
 198         GCR = GCR_COLD_RST;
 199         udelay(50);
 200 }
 201 #endif
 202
 203 #ifdef CONFIG_PXA3xx
 204 static inline void pxa_ac97_warm_pxa3xx(void)
 205 {
 206         int timeout = 100;
 207
 208         gsr_bits = 0;
 209
 210         /* Can't use interrupts */
 211         GCR |= GCR_WARM_RST;
 212         while (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)) && timeout--)
 213                 mdelay(1);
 214 }
 215
 216 static inline void pxa_ac97_cold_pxa3xx(void)
 217 {
 218         int timeout = 1000;
 219
 220         /* Hold CLKBPB for 100us */
 221         GCR = 0;
 222         GCR = GCR_CLKBPB;
 223         udelay(100);
 224         GCR = 0;
 225
 226         GCR &=  GCR_COLD_RST;  /* clear everything but nCRST */
 227         GCR &= ~GCR_COLD_RST;  /* then assert nCRST */
 228
 229         gsr_bits = 0;
 230
 231         /* Can't use interrupts on PXA3xx */
 232         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 233
 234         GCR = GCR_WARM_RST | GCR_COLD_RST;
 235         while (!(GSR & (GSR_PCR | GSR_SCR)) && timeout--)
 236                 mdelay(10);
 237 }
 238 #endif
 239
 240 bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97)
 241 {
 242         unsigned long gsr;
 243
 244 #ifdef CONFIG_PXA25x
 245         if (cpu_is_pxa25x())
 246                 pxa_ac97_warm_pxa25x();
 247         else
 248 #endif
 249 #ifdef CONFIG_PXA27x
 250         if (cpu_is_pxa27x())
 251                 pxa_ac97_warm_pxa27x();
 252         else
 253 #endif
 254 #ifdef CONFIG_PXA3xx
 255         if (cpu_is_pxa3xx())
 256                 pxa_ac97_warm_pxa3xx();
 257         else
 258 #endif
 259                 BUG();
 260         gsr = GSR | gsr_bits;
 261         if (!(gsr & (GSR_PCR | GSR_SCR))) {
 262                 printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
 263                                  __func__, gsr);
 264
 265                 return false;
 266         }
 267
 268         return true;
 269 }
 270 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_warm_reset);
 271
 272 bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97)
 273 {
 274         unsigned long gsr;
 275
 276 #ifdef CONFIG_PXA25x
 277         if (cpu_is_pxa25x())
 278                 pxa_ac97_cold_pxa25x();
 279         else
 280 #endif
 281 #ifdef CONFIG_PXA27x
 282         if (cpu_is_pxa27x())
 283                 pxa_ac97_cold_pxa27x();
 284         else
 285 #endif
 286 #ifdef CONFIG_PXA3xx
 287         if (cpu_is_pxa3xx())
 288                 pxa_ac97_cold_pxa3xx();
 289         else
 290 #endif
 291                 BUG();
 292
 293         gsr = GSR | gsr_bits;
 294         if (!(gsr & (GSR_PCR | GSR_SCR))) {
 295                 printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
 296                                  __func__, gsr);
 297
 298                 return false;
 299         }
 300
 301         return true;
 302 }
 303 EXPORT_SYMBOL_GPL(pxa2xx_ac97_try_cold_reset);
 304
 305
 306 void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97)
 307 {
 308         GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
 309         GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
 310 }
 311 EXPORT_SYMBOL_GPL(pxa2xx_ac97_finish_reset);
 312
 313 static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
 314 {
 315         long status;
 316
 317         status = GSR;
 318         if (status) {
 319                 GSR = status;
 320                 gsr_bits |= status;
 321                 wake_up(&gsr_wq);
 322
 323                 /* Although we don't use those we still need to clear them
 324                    since they tend to spuriously trigger when MMC is used
 325                    (hardware bug? go figure)... */
 326                 if (cpu_is_pxa27x()) {
 327                         MISR = MISR_EOC;
 328                         PISR = PISR_EOC;
 329                         MCSR = MCSR_EOC;
 330                 }
 331
 332                 return IRQ_HANDLED;
 333         }
 334
 335         return IRQ_NONE;
 336 }
 337
 338 #ifdef CONFIG_PM
 339 int pxa2xx_ac97_hw_suspend(void)
 340 {
 341         GCR |= GCR_ACLINK_OFF;
 342         clk_disable(ac97_clk);
 343         return 0;
 344 }
 345 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_suspend);
 346
 347 int pxa2xx_ac97_hw_resume(void)
 348 {
 349         if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
 350                 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
 351                 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
 352                 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
 353                 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
 354         }
 355         if (cpu_is_pxa27x()) {
 356                 /* Use GPIO 113 or 95 as AC97 Reset on Bulverde */
 357                 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
 358         }
 359         clk_enable(ac97_clk);
 360         return 0;
 361 }
 362 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_resume);
 363 #endif
 364
 365 int __devinit pxa2xx_ac97_hw_probe(struct platform_device *dev)
 366 {
 367         int ret;
 368         struct pxa2xx_ac97_platform_data *pdata = dev->dev.platform_data;
 369
 370         if (pdata) {
 371                 switch (pdata->reset_gpio) {
 372                 case 95:
 373                 case 113:
 374                         reset_gpio = pdata->reset_gpio;
 375                         break;
 376                 case 0:
 377                         reset_gpio = 113;
 378                         break;
 379                 case -1:
 380                         break;
 381                 default:
 382                         dev_err(&dev->dev, "Invalid reset GPIO %d\n",
 383                                 pdata->reset_gpio);
 384                 }
 385         } else {
 386                 if (cpu_is_pxa27x())
 387                         reset_gpio = 113;
 388         }
 389
 390         if (cpu_is_pxa25x() || cpu_is_pxa27x()) {
 391                 pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
 392                 pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
 393                 pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
 394                 pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
 395         }
 396
 397         if (cpu_is_pxa27x()) {
 398                 /* Use GPIO 113 as AC97 Reset on Bulverde */
 399                 set_resetgpio_mode(RESETGPIO_NORMAL_ALTFUNC);
 400                 ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
 401                 if (IS_ERR(ac97conf_clk)) {
 402                         ret = PTR_ERR(ac97conf_clk);
 403                         ac97conf_clk = NULL;
 404                         goto err_conf;
 405                 }
 406         }
 407
 408         ac97_clk = clk_get(&dev->dev, "AC97CLK");
 409         if (IS_ERR(ac97_clk)) {
 410                 ret = PTR_ERR(ac97_clk);
 411                 ac97_clk = NULL;
 412                 goto err_clk;
 413         }
 414
 415         ret = clk_enable(ac97_clk);
 416         if (ret)
 417                 goto err_clk2;
 418
 419         ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, IRQF_DISABLED, "AC97", NULL);
 420         if (ret < 0)
 421                 goto err_irq;
 422
 423         return 0;
 424
 425 err_irq:
 426         GCR |= GCR_ACLINK_OFF;
 427 err_clk2:
 428         clk_put(ac97_clk);
 429         ac97_clk = NULL;
 430 err_clk:
 431         if (ac97conf_clk) {
 432                 clk_put(ac97conf_clk);
 433                 ac97conf_clk = NULL;
 434         }
 435 err_conf:
 436         return ret;
 437 }
 438 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_probe);
 439
 440 void pxa2xx_ac97_hw_remove(struct platform_device *dev)
 441 {
 442         GCR |= GCR_ACLINK_OFF;
 443         free_irq(IRQ_AC97, NULL);
 444         if (ac97conf_clk) {
 445                 clk_put(ac97conf_clk);
 446                 ac97conf_clk = NULL;
 447         }
 448         clk_disable(ac97_clk);
 449         clk_put(ac97_clk);
 450         ac97_clk = NULL;
 451 }
 452 EXPORT_SYMBOL_GPL(pxa2xx_ac97_hw_remove);
 453
 454 MODULE_AUTHOR("Nicolas Pitre");
 455 MODULE_DESCRIPTION("Intel/Marvell PXA sound library");
 456 MODULE_LICENSE("GPL");
 457