2 * Atmel PIO2 Port Multiplexer support
4 * Copyright (C) 2004-2006 Atmel Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #include <linux/clk.h>
12 #include <linux/debugfs.h>
14 #include <linux/platform_device.h>
15 #include <linux/irq.h>
20 #include <asm/arch/portmux.h>
24 #define MAX_NR_PIO_DEVICES 8
28 const struct platform_device
*pdev
;
35 static struct pio_device pio_dev
[MAX_NR_PIO_DEVICES
];
37 static struct pio_device
*gpio_to_pio(unsigned int gpio
)
39 struct pio_device
*pio
;
43 if (index
>= MAX_NR_PIO_DEVICES
)
45 pio
= &pio_dev
[index
];
52 /* Pin multiplexing API */
54 void __init
at32_select_periph(unsigned int pin
, unsigned int periph
,
57 struct pio_device
*pio
;
58 unsigned int pin_index
= pin
& 0x1f;
59 u32 mask
= 1 << pin_index
;
61 pio
= gpio_to_pio(pin
);
63 printk("pio: invalid pin %u\n", pin
);
67 if (unlikely(test_and_set_bit(pin_index
, &pio
->pinmux_mask
))) {
68 printk("%s: pin %u is busy\n", pio
->name
, pin_index
);
72 pio_writel(pio
, PUER
, mask
);
74 pio_writel(pio
, BSR
, mask
);
76 pio_writel(pio
, ASR
, mask
);
78 pio_writel(pio
, PDR
, mask
);
79 if (!(flags
& AT32_GPIOF_PULLUP
))
80 pio_writel(pio
, PUDR
, mask
);
82 /* gpio_request NOT allowed */
83 set_bit(pin_index
, &pio
->gpio_mask
);
91 void __init
at32_select_gpio(unsigned int pin
, unsigned long flags
)
93 struct pio_device
*pio
;
94 unsigned int pin_index
= pin
& 0x1f;
95 u32 mask
= 1 << pin_index
;
97 pio
= gpio_to_pio(pin
);
99 printk("pio: invalid pin %u\n", pin
);
103 if (unlikely(test_and_set_bit(pin_index
, &pio
->pinmux_mask
))) {
104 printk("%s: pin %u is busy\n", pio
->name
, pin_index
);
108 if (flags
& AT32_GPIOF_OUTPUT
) {
109 if (flags
& AT32_GPIOF_HIGH
)
110 pio_writel(pio
, SODR
, mask
);
112 pio_writel(pio
, CODR
, mask
);
113 pio_writel(pio
, PUDR
, mask
);
114 pio_writel(pio
, OER
, mask
);
116 if (flags
& AT32_GPIOF_PULLUP
)
117 pio_writel(pio
, PUER
, mask
);
119 pio_writel(pio
, PUDR
, mask
);
120 if (flags
& AT32_GPIOF_DEGLITCH
)
121 pio_writel(pio
, IFER
, mask
);
123 pio_writel(pio
, IFDR
, mask
);
124 pio_writel(pio
, ODR
, mask
);
127 pio_writel(pio
, PER
, mask
);
129 /* gpio_request now allowed */
130 clear_bit(pin_index
, &pio
->gpio_mask
);
138 /* Reserve a pin, preventing anyone else from changing its configuration. */
139 void __init
at32_reserve_pin(unsigned int pin
)
141 struct pio_device
*pio
;
142 unsigned int pin_index
= pin
& 0x1f;
144 pio
= gpio_to_pio(pin
);
145 if (unlikely(!pio
)) {
146 printk("pio: invalid pin %u\n", pin
);
150 if (unlikely(test_and_set_bit(pin_index
, &pio
->pinmux_mask
))) {
151 printk("%s: pin %u is busy\n", pio
->name
, pin_index
);
161 /*--------------------------------------------------------------------------*/
165 int gpio_request(unsigned int gpio
, const char *label
)
167 struct pio_device
*pio
;
170 pio
= gpio_to_pio(gpio
);
175 if (test_and_set_bit(pin
, &pio
->gpio_mask
))
180 EXPORT_SYMBOL(gpio_request
);
182 void gpio_free(unsigned int gpio
)
184 struct pio_device
*pio
;
187 pio
= gpio_to_pio(gpio
);
190 "gpio: attempted to free invalid pin %u\n", gpio
);
195 if (!test_and_clear_bit(pin
, &pio
->gpio_mask
))
196 printk(KERN_ERR
"gpio: freeing free or non-gpio pin %s-%u\n",
199 EXPORT_SYMBOL(gpio_free
);
201 int gpio_direction_input(unsigned int gpio
)
203 struct pio_device
*pio
;
206 pio
= gpio_to_pio(gpio
);
211 pio_writel(pio
, ODR
, 1 << pin
);
215 EXPORT_SYMBOL(gpio_direction_input
);
217 int gpio_direction_output(unsigned int gpio
, int value
)
219 struct pio_device
*pio
;
222 pio
= gpio_to_pio(gpio
);
226 gpio_set_value(gpio
, value
);
229 pio_writel(pio
, OER
, 1 << pin
);
233 EXPORT_SYMBOL(gpio_direction_output
);
235 int gpio_get_value(unsigned int gpio
)
237 struct pio_device
*pio
= &pio_dev
[gpio
>> 5];
239 return (pio_readl(pio
, PDSR
) >> (gpio
& 0x1f)) & 1;
241 EXPORT_SYMBOL(gpio_get_value
);
243 void gpio_set_value(unsigned int gpio
, int value
)
245 struct pio_device
*pio
= &pio_dev
[gpio
>> 5];
248 mask
= 1 << (gpio
& 0x1f);
250 pio_writel(pio
, SODR
, mask
);
252 pio_writel(pio
, CODR
, mask
);
254 EXPORT_SYMBOL(gpio_set_value
);
256 /*--------------------------------------------------------------------------*/
258 /* GPIO IRQ support */
260 static void gpio_irq_mask(unsigned irq
)
262 unsigned gpio
= irq_to_gpio(irq
);
263 struct pio_device
*pio
= &pio_dev
[gpio
>> 5];
265 pio_writel(pio
, IDR
, 1 << (gpio
& 0x1f));
268 static void gpio_irq_unmask(unsigned irq
)
270 unsigned gpio
= irq_to_gpio(irq
);
271 struct pio_device
*pio
= &pio_dev
[gpio
>> 5];
273 pio_writel(pio
, IER
, 1 << (gpio
& 0x1f));
276 static int gpio_irq_type(unsigned irq
, unsigned type
)
278 if (type
!= IRQ_TYPE_EDGE_BOTH
&& type
!= IRQ_TYPE_NONE
)
284 static struct irq_chip gpio_irqchip
= {
286 .mask
= gpio_irq_mask
,
287 .unmask
= gpio_irq_unmask
,
288 .set_type
= gpio_irq_type
,
291 static void gpio_irq_handler(unsigned irq
, struct irq_desc
*desc
)
293 struct pio_device
*pio
= get_irq_chip_data(irq
);
296 gpio_irq
= (unsigned) get_irq_data(irq
);
301 /* ack pending GPIO interrupts */
302 isr
= pio_readl(pio
, ISR
) & pio_readl(pio
, IMR
);
320 gpio_irq_setup(struct pio_device
*pio
, int irq
, int gpio_irq
)
324 set_irq_chip_data(irq
, pio
);
325 set_irq_data(irq
, (void *) gpio_irq
);
327 for (i
= 0; i
< 32; i
++, gpio_irq
++) {
328 set_irq_chip_data(gpio_irq
, pio
);
329 set_irq_chip_and_handler(gpio_irq
, &gpio_irqchip
,
333 set_irq_chained_handler(irq
, gpio_irq_handler
);
336 /*--------------------------------------------------------------------------*/
338 static int __init
pio_probe(struct platform_device
*pdev
)
340 struct pio_device
*pio
= NULL
;
341 int irq
= platform_get_irq(pdev
, 0);
342 int gpio_irq_base
= GPIO_IRQ_BASE
+ pdev
->id
* 32;
344 BUG_ON(pdev
->id
>= MAX_NR_PIO_DEVICES
);
345 pio
= &pio_dev
[pdev
->id
];
348 gpio_irq_setup(pio
, irq
, gpio_irq_base
);
350 platform_set_drvdata(pdev
, pio
);
352 printk(KERN_DEBUG
"%s: base 0x%p, irq %d chains %d..%d\n",
353 pio
->name
, pio
->regs
, irq
, gpio_irq_base
, gpio_irq_base
+ 31);
358 static struct platform_driver pio_driver
= {
365 static int __init
pio_init(void)
367 return platform_driver_register(&pio_driver
);
369 postcore_initcall(pio_init
);
371 void __init
at32_init_pio(struct platform_device
*pdev
)
373 struct resource
*regs
;
374 struct pio_device
*pio
;
376 if (pdev
->id
> MAX_NR_PIO_DEVICES
) {
377 dev_err(&pdev
->dev
, "only %d PIO devices supported\n",
382 pio
= &pio_dev
[pdev
->id
];
383 snprintf(pio
->name
, sizeof(pio
->name
), "pio%d", pdev
->id
);
385 regs
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
387 dev_err(&pdev
->dev
, "no mmio resource defined\n");
391 pio
->clk
= clk_get(&pdev
->dev
, "mck");
392 if (IS_ERR(pio
->clk
))
394 * This is a fatal error, but if we continue we might
395 * be so lucky that we manage to initialize the
396 * console and display this message...
398 dev_err(&pdev
->dev
, "no mck clock defined\n");
400 clk_enable(pio
->clk
);
403 pio
->regs
= ioremap(regs
->start
, regs
->end
- regs
->start
+ 1);
406 * request_gpio() is only valid for pins that have been
407 * explicitly configured as GPIO and not previously requested
409 pio
->gpio_mask
= ~0UL;
411 /* start with irqs disabled and acked */
412 pio_writel(pio
, IDR
, ~0UL);
413 (void) pio_readl(pio
, ISR
);