1 /* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 #include <linux/module.h>
20 #include <linux/device.h>
21 #include <linux/platform_device.h>
22 #include <linux/clk.h>
23 #include <linux/slab.h>
24 #include <linux/interrupt.h>
25 #include <linux/err.h>
26 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/uaccess.h>
30 #include <linux/debugfs.h>
31 #include <linux/seq_file.h>
32 #include <linux/pm_runtime.h>
34 #include <linux/usb.h>
35 #include <linux/usb/otg.h>
36 #include <linux/usb/ulpi.h>
37 #include <linux/usb/gadget.h>
38 #include <linux/usb/hcd.h>
39 #include <linux/usb/msm_hsusb.h>
40 #include <linux/usb/msm_hsusb_hw.h>
41 #include <linux/regulator/consumer.h>
45 #define MSM_USB_BASE (motg->regs)
46 #define DRIVER_NAME "msm_otg"
48 #define ULPI_IO_TIMEOUT_USEC (10 * 1000)
50 #define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
51 #define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
52 #define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
53 #define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
55 #define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
56 #define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
57 #define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
58 #define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
60 #define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
61 #define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
63 static struct regulator
*hsusb_3p3
;
64 static struct regulator
*hsusb_1p8
;
65 static struct regulator
*hsusb_vddcx
;
67 static int msm_hsusb_init_vddcx(struct msm_otg
*motg
, int init
)
72 hsusb_vddcx
= regulator_get(motg
->otg
.dev
, "HSUSB_VDDCX");
73 if (IS_ERR(hsusb_vddcx
)) {
74 dev_err(motg
->otg
.dev
, "unable to get hsusb vddcx\n");
75 return PTR_ERR(hsusb_vddcx
);
78 ret
= regulator_set_voltage(hsusb_vddcx
,
79 USB_PHY_VDD_DIG_VOL_MIN
,
80 USB_PHY_VDD_DIG_VOL_MAX
);
82 dev_err(motg
->otg
.dev
, "unable to set the voltage "
84 regulator_put(hsusb_vddcx
);
88 ret
= regulator_enable(hsusb_vddcx
);
90 dev_err(motg
->otg
.dev
, "unable to enable hsusb vddcx\n");
91 regulator_put(hsusb_vddcx
);
94 ret
= regulator_set_voltage(hsusb_vddcx
, 0,
95 USB_PHY_VDD_DIG_VOL_MIN
);
97 dev_err(motg
->otg
.dev
, "unable to set the voltage "
101 ret
= regulator_disable(hsusb_vddcx
);
103 dev_err(motg
->otg
.dev
, "unable to disable hsusb vddcx\n");
105 regulator_put(hsusb_vddcx
);
111 static int msm_hsusb_ldo_init(struct msm_otg
*motg
, int init
)
116 hsusb_3p3
= regulator_get(motg
->otg
.dev
, "HSUSB_3p3");
117 if (IS_ERR(hsusb_3p3
)) {
118 dev_err(motg
->otg
.dev
, "unable to get hsusb 3p3\n");
119 return PTR_ERR(hsusb_3p3
);
122 rc
= regulator_set_voltage(hsusb_3p3
, USB_PHY_3P3_VOL_MIN
,
123 USB_PHY_3P3_VOL_MAX
);
125 dev_err(motg
->otg
.dev
, "unable to set voltage level "
129 rc
= regulator_enable(hsusb_3p3
);
131 dev_err(motg
->otg
.dev
, "unable to enable the hsusb 3p3\n");
134 hsusb_1p8
= regulator_get(motg
->otg
.dev
, "HSUSB_1p8");
135 if (IS_ERR(hsusb_1p8
)) {
136 dev_err(motg
->otg
.dev
, "unable to get hsusb 1p8\n");
137 rc
= PTR_ERR(hsusb_1p8
);
140 rc
= regulator_set_voltage(hsusb_1p8
, USB_PHY_1P8_VOL_MIN
,
141 USB_PHY_1P8_VOL_MAX
);
143 dev_err(motg
->otg
.dev
, "unable to set voltage level "
147 rc
= regulator_enable(hsusb_1p8
);
149 dev_err(motg
->otg
.dev
, "unable to enable the hsusb 1p8\n");
156 regulator_disable(hsusb_1p8
);
158 regulator_put(hsusb_1p8
);
160 regulator_disable(hsusb_3p3
);
162 regulator_put(hsusb_3p3
);
166 #ifdef CONFIG_PM_SLEEP
167 #define USB_PHY_SUSP_DIG_VOL 500000
168 static int msm_hsusb_config_vddcx(int high
)
170 int max_vol
= USB_PHY_VDD_DIG_VOL_MAX
;
175 min_vol
= USB_PHY_VDD_DIG_VOL_MIN
;
177 min_vol
= USB_PHY_SUSP_DIG_VOL
;
179 ret
= regulator_set_voltage(hsusb_vddcx
, min_vol
, max_vol
);
181 pr_err("%s: unable to set the voltage for regulator "
182 "HSUSB_VDDCX\n", __func__
);
186 pr_debug("%s: min_vol:%d max_vol:%d\n", __func__
, min_vol
, max_vol
);
192 static int msm_hsusb_ldo_set_mode(int on
)
196 if (!hsusb_1p8
|| IS_ERR(hsusb_1p8
)) {
197 pr_err("%s: HSUSB_1p8 is not initialized\n", __func__
);
201 if (!hsusb_3p3
|| IS_ERR(hsusb_3p3
)) {
202 pr_err("%s: HSUSB_3p3 is not initialized\n", __func__
);
207 ret
= regulator_set_optimum_mode(hsusb_1p8
,
208 USB_PHY_1P8_HPM_LOAD
);
210 pr_err("%s: Unable to set HPM of the regulator "
211 "HSUSB_1p8\n", __func__
);
214 ret
= regulator_set_optimum_mode(hsusb_3p3
,
215 USB_PHY_3P3_HPM_LOAD
);
217 pr_err("%s: Unable to set HPM of the regulator "
218 "HSUSB_3p3\n", __func__
);
219 regulator_set_optimum_mode(hsusb_1p8
,
220 USB_PHY_1P8_LPM_LOAD
);
224 ret
= regulator_set_optimum_mode(hsusb_1p8
,
225 USB_PHY_1P8_LPM_LOAD
);
227 pr_err("%s: Unable to set LPM of the regulator "
228 "HSUSB_1p8\n", __func__
);
229 ret
= regulator_set_optimum_mode(hsusb_3p3
,
230 USB_PHY_3P3_LPM_LOAD
);
232 pr_err("%s: Unable to set LPM of the regulator "
233 "HSUSB_3p3\n", __func__
);
236 pr_debug("reg (%s)\n", on
? "HPM" : "LPM");
237 return ret
< 0 ? ret
: 0;
240 static int ulpi_read(struct otg_transceiver
*otg
, u32 reg
)
242 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
245 /* initiate read operation */
246 writel(ULPI_RUN
| ULPI_READ
| ULPI_ADDR(reg
),
249 /* wait for completion */
250 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
251 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
257 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
258 dev_err(otg
->dev
, "ulpi_read: timeout %08x\n",
259 readl(USB_ULPI_VIEWPORT
));
262 return ULPI_DATA_READ(readl(USB_ULPI_VIEWPORT
));
265 static int ulpi_write(struct otg_transceiver
*otg
, u32 val
, u32 reg
)
267 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
270 /* initiate write operation */
271 writel(ULPI_RUN
| ULPI_WRITE
|
272 ULPI_ADDR(reg
) | ULPI_DATA(val
),
275 /* wait for completion */
276 while (cnt
< ULPI_IO_TIMEOUT_USEC
) {
277 if (!(readl(USB_ULPI_VIEWPORT
) & ULPI_RUN
))
283 if (cnt
>= ULPI_IO_TIMEOUT_USEC
) {
284 dev_err(otg
->dev
, "ulpi_write: timeout\n");
290 static struct otg_io_access_ops msm_otg_io_ops
= {
295 static void ulpi_init(struct msm_otg
*motg
)
297 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
298 int *seq
= pdata
->phy_init_seq
;
303 while (seq
[0] >= 0) {
304 dev_vdbg(motg
->otg
.dev
, "ulpi: write 0x%02x to 0x%02x\n",
306 ulpi_write(&motg
->otg
, seq
[0], seq
[1]);
311 static int msm_otg_link_clk_reset(struct msm_otg
*motg
, bool assert)
316 ret
= clk_reset(motg
->clk
, CLK_RESET_ASSERT
);
318 dev_err(motg
->otg
.dev
, "usb hs_clk assert failed\n");
320 ret
= clk_reset(motg
->clk
, CLK_RESET_DEASSERT
);
322 dev_err(motg
->otg
.dev
, "usb hs_clk deassert failed\n");
327 static int msm_otg_phy_clk_reset(struct msm_otg
*motg
)
331 ret
= clk_reset(motg
->phy_reset_clk
, CLK_RESET_ASSERT
);
333 dev_err(motg
->otg
.dev
, "usb phy clk assert failed\n");
336 usleep_range(10000, 12000);
337 ret
= clk_reset(motg
->phy_reset_clk
, CLK_RESET_DEASSERT
);
339 dev_err(motg
->otg
.dev
, "usb phy clk deassert failed\n");
343 static int msm_otg_phy_reset(struct msm_otg
*motg
)
349 ret
= msm_otg_link_clk_reset(motg
, 1);
352 ret
= msm_otg_phy_clk_reset(motg
);
355 ret
= msm_otg_link_clk_reset(motg
, 0);
359 val
= readl(USB_PORTSC
) & ~PORTSC_PTS_MASK
;
360 writel(val
| PORTSC_PTS_ULPI
, USB_PORTSC
);
362 for (retries
= 3; retries
> 0; retries
--) {
363 ret
= ulpi_write(&motg
->otg
, ULPI_FUNC_CTRL_SUSPENDM
,
364 ULPI_CLR(ULPI_FUNC_CTRL
));
367 ret
= msm_otg_phy_clk_reset(motg
);
374 /* This reset calibrates the phy, if the above write succeeded */
375 ret
= msm_otg_phy_clk_reset(motg
);
379 for (retries
= 3; retries
> 0; retries
--) {
380 ret
= ulpi_read(&motg
->otg
, ULPI_DEBUG
);
381 if (ret
!= -ETIMEDOUT
)
383 ret
= msm_otg_phy_clk_reset(motg
);
390 dev_info(motg
->otg
.dev
, "phy_reset: success\n");
394 #define LINK_RESET_TIMEOUT_USEC (250 * 1000)
395 static int msm_otg_reset(struct otg_transceiver
*otg
)
397 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
398 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
404 ret
= msm_otg_phy_reset(motg
);
406 dev_err(otg
->dev
, "phy_reset failed\n");
412 writel(USBCMD_RESET
, USB_USBCMD
);
413 while (cnt
< LINK_RESET_TIMEOUT_USEC
) {
414 if (!(readl(USB_USBCMD
) & USBCMD_RESET
))
419 if (cnt
>= LINK_RESET_TIMEOUT_USEC
)
422 /* select ULPI phy */
423 writel(0x80000000, USB_PORTSC
);
427 writel(0x0, USB_AHBBURST
);
428 writel(0x00, USB_AHBMODE
);
430 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
431 val
= readl(USB_OTGSC
);
432 if (pdata
->mode
== USB_OTG
) {
433 ulpi_val
= ULPI_INT_IDGRD
| ULPI_INT_SESS_VALID
;
434 val
|= OTGSC_IDIE
| OTGSC_BSVIE
;
435 } else if (pdata
->mode
== USB_PERIPHERAL
) {
436 ulpi_val
= ULPI_INT_SESS_VALID
;
439 writel(val
, USB_OTGSC
);
440 ulpi_write(otg
, ulpi_val
, ULPI_USB_INT_EN_RISE
);
441 ulpi_write(otg
, ulpi_val
, ULPI_USB_INT_EN_FALL
);
447 #define PHY_SUSPEND_TIMEOUT_USEC (500 * 1000)
448 #define PHY_RESUME_TIMEOUT_USEC (100 * 1000)
450 #ifdef CONFIG_PM_SLEEP
451 static int msm_otg_suspend(struct msm_otg
*motg
)
453 struct otg_transceiver
*otg
= &motg
->otg
;
454 struct usb_bus
*bus
= otg
->host
;
455 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
458 if (atomic_read(&motg
->in_lpm
))
461 disable_irq(motg
->irq
);
463 * Chipidea 45-nm PHY suspend sequence:
465 * Interrupt Latch Register auto-clear feature is not present
466 * in all PHY versions. Latch register is clear on read type.
467 * Clear latch register to avoid spurious wakeup from
468 * low power mode (LPM).
470 * PHY comparators are disabled when PHY enters into low power
471 * mode (LPM). Keep PHY comparators ON in LPM only when we expect
472 * VBUS/Id notifications from USB PHY. Otherwise turn off USB
473 * PHY comparators. This save significant amount of power.
475 * PLL is not turned off when PHY enters into low power mode (LPM).
476 * Disable PLL for maximum power savings.
479 if (motg
->pdata
->phy_type
== CI_45NM_INTEGRATED_PHY
) {
480 ulpi_read(otg
, 0x14);
481 if (pdata
->otg_control
== OTG_PHY_CONTROL
)
482 ulpi_write(otg
, 0x01, 0x30);
483 ulpi_write(otg
, 0x08, 0x09);
487 * PHY may take some time or even fail to enter into low power
488 * mode (LPM). Hence poll for 500 msec and reset the PHY and link
491 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
492 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
493 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
499 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
) {
500 dev_err(otg
->dev
, "Unable to suspend PHY\n");
502 enable_irq(motg
->irq
);
507 * PHY has capability to generate interrupt asynchronously in low
508 * power mode (LPM). This interrupt is level triggered. So USB IRQ
509 * line must be disabled till async interrupt enable bit is cleared
510 * in USBCMD register. Assert STP (ULPI interface STOP signal) to
511 * block data communication from PHY.
513 writel(readl(USB_USBCMD
) | ASYNC_INTR_CTRL
| ULPI_STP_CTRL
, USB_USBCMD
);
515 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
516 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
)
517 writel(readl(USB_PHY_CTRL
) | PHY_RETEN
, USB_PHY_CTRL
);
519 clk_disable(motg
->pclk
);
520 clk_disable(motg
->clk
);
522 clk_disable(motg
->core_clk
);
524 if (!IS_ERR(motg
->pclk_src
))
525 clk_disable(motg
->pclk_src
);
527 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
528 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
529 msm_hsusb_ldo_set_mode(0);
530 msm_hsusb_config_vddcx(0);
533 if (device_may_wakeup(otg
->dev
))
534 enable_irq_wake(motg
->irq
);
536 clear_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
538 atomic_set(&motg
->in_lpm
, 1);
539 enable_irq(motg
->irq
);
541 dev_info(otg
->dev
, "USB in low power mode\n");
546 static int msm_otg_resume(struct msm_otg
*motg
)
548 struct otg_transceiver
*otg
= &motg
->otg
;
549 struct usb_bus
*bus
= otg
->host
;
553 if (!atomic_read(&motg
->in_lpm
))
556 if (!IS_ERR(motg
->pclk_src
))
557 clk_enable(motg
->pclk_src
);
559 clk_enable(motg
->pclk
);
560 clk_enable(motg
->clk
);
562 clk_enable(motg
->core_clk
);
564 if (motg
->pdata
->phy_type
== SNPS_28NM_INTEGRATED_PHY
&&
565 motg
->pdata
->otg_control
== OTG_PMIC_CONTROL
) {
566 msm_hsusb_ldo_set_mode(1);
567 msm_hsusb_config_vddcx(1);
568 writel(readl(USB_PHY_CTRL
) & ~PHY_RETEN
, USB_PHY_CTRL
);
571 temp
= readl(USB_USBCMD
);
572 temp
&= ~ASYNC_INTR_CTRL
;
573 temp
&= ~ULPI_STP_CTRL
;
574 writel(temp
, USB_USBCMD
);
577 * PHY comes out of low power mode (LPM) in case of wakeup
578 * from asynchronous interrupt.
580 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
581 goto skip_phy_resume
;
583 writel(readl(USB_PORTSC
) & ~PORTSC_PHCD
, USB_PORTSC
);
584 while (cnt
< PHY_RESUME_TIMEOUT_USEC
) {
585 if (!(readl(USB_PORTSC
) & PORTSC_PHCD
))
591 if (cnt
>= PHY_RESUME_TIMEOUT_USEC
) {
593 * This is a fatal error. Reset the link and
594 * PHY. USB state can not be restored. Re-insertion
595 * of USB cable is the only way to get USB working.
597 dev_err(otg
->dev
, "Unable to resume USB."
598 "Re-plugin the cable\n");
603 if (device_may_wakeup(otg
->dev
))
604 disable_irq_wake(motg
->irq
);
606 set_bit(HCD_FLAG_HW_ACCESSIBLE
, &(bus_to_hcd(bus
))->flags
);
608 atomic_set(&motg
->in_lpm
, 0);
610 if (motg
->async_int
) {
612 pm_runtime_put(otg
->dev
);
613 enable_irq(motg
->irq
);
616 dev_info(otg
->dev
, "USB exited from low power mode\n");
622 static void msm_otg_notify_charger(struct msm_otg
*motg
, unsigned mA
)
624 if (motg
->cur_power
== mA
)
627 /* TODO: Notify PMIC about available current */
628 dev_info(motg
->otg
.dev
, "Avail curr from USB = %u\n", mA
);
629 motg
->cur_power
= mA
;
632 static int msm_otg_set_power(struct otg_transceiver
*otg
, unsigned mA
)
634 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
637 * Gadget driver uses set_power method to notify about the
638 * available current based on suspend/configured states.
640 * IDEV_CHG can be drawn irrespective of suspend/un-configured
641 * states when CDP/ACA is connected.
643 if (motg
->chg_type
== USB_SDP_CHARGER
)
644 msm_otg_notify_charger(motg
, mA
);
649 static void msm_otg_start_host(struct otg_transceiver
*otg
, int on
)
651 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
652 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
658 hcd
= bus_to_hcd(otg
->host
);
661 dev_dbg(otg
->dev
, "host on\n");
663 if (pdata
->vbus_power
)
664 pdata
->vbus_power(1);
666 * Some boards have a switch cotrolled by gpio
667 * to enable/disable internal HUB. Enable internal
668 * HUB before kicking the host.
670 if (pdata
->setup_gpio
)
671 pdata
->setup_gpio(OTG_STATE_A_HOST
);
673 usb_add_hcd(hcd
, hcd
->irq
, IRQF_SHARED
);
676 dev_dbg(otg
->dev
, "host off\n");
681 if (pdata
->setup_gpio
)
682 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
683 if (pdata
->vbus_power
)
684 pdata
->vbus_power(0);
688 static int msm_otg_set_host(struct otg_transceiver
*otg
, struct usb_bus
*host
)
690 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
694 * Fail host registration if this board can support
695 * only peripheral configuration.
697 if (motg
->pdata
->mode
== USB_PERIPHERAL
) {
698 dev_info(otg
->dev
, "Host mode is not supported\n");
703 if (otg
->state
== OTG_STATE_A_HOST
) {
704 pm_runtime_get_sync(otg
->dev
);
705 msm_otg_start_host(otg
, 0);
707 otg
->state
= OTG_STATE_UNDEFINED
;
708 schedule_work(&motg
->sm_work
);
716 hcd
= bus_to_hcd(host
);
717 hcd
->power_budget
= motg
->pdata
->power_budget
;
720 dev_dbg(otg
->dev
, "host driver registered w/ tranceiver\n");
723 * Kick the state machine work, if peripheral is not supported
724 * or peripheral is already registered with us.
726 if (motg
->pdata
->mode
== USB_HOST
|| otg
->gadget
) {
727 pm_runtime_get_sync(otg
->dev
);
728 schedule_work(&motg
->sm_work
);
734 static void msm_otg_start_peripheral(struct otg_transceiver
*otg
, int on
)
736 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
737 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
743 dev_dbg(otg
->dev
, "gadget on\n");
745 * Some boards have a switch cotrolled by gpio
746 * to enable/disable internal HUB. Disable internal
747 * HUB before kicking the gadget.
749 if (pdata
->setup_gpio
)
750 pdata
->setup_gpio(OTG_STATE_B_PERIPHERAL
);
751 usb_gadget_vbus_connect(otg
->gadget
);
753 dev_dbg(otg
->dev
, "gadget off\n");
754 usb_gadget_vbus_disconnect(otg
->gadget
);
755 if (pdata
->setup_gpio
)
756 pdata
->setup_gpio(OTG_STATE_UNDEFINED
);
761 static int msm_otg_set_peripheral(struct otg_transceiver
*otg
,
762 struct usb_gadget
*gadget
)
764 struct msm_otg
*motg
= container_of(otg
, struct msm_otg
, otg
);
767 * Fail peripheral registration if this board can support
768 * only host configuration.
770 if (motg
->pdata
->mode
== USB_HOST
) {
771 dev_info(otg
->dev
, "Peripheral mode is not supported\n");
776 if (otg
->state
== OTG_STATE_B_PERIPHERAL
) {
777 pm_runtime_get_sync(otg
->dev
);
778 msm_otg_start_peripheral(otg
, 0);
780 otg
->state
= OTG_STATE_UNDEFINED
;
781 schedule_work(&motg
->sm_work
);
788 otg
->gadget
= gadget
;
789 dev_dbg(otg
->dev
, "peripheral driver registered w/ tranceiver\n");
792 * Kick the state machine work, if host is not supported
793 * or host is already registered with us.
795 if (motg
->pdata
->mode
== USB_PERIPHERAL
|| otg
->host
) {
796 pm_runtime_get_sync(otg
->dev
);
797 schedule_work(&motg
->sm_work
);
803 static bool msm_chg_check_secondary_det(struct msm_otg
*motg
)
805 struct otg_transceiver
*otg
= &motg
->otg
;
809 switch (motg
->pdata
->phy_type
) {
810 case CI_45NM_INTEGRATED_PHY
:
811 chg_det
= ulpi_read(otg
, 0x34);
812 ret
= chg_det
& (1 << 4);
814 case SNPS_28NM_INTEGRATED_PHY
:
815 chg_det
= ulpi_read(otg
, 0x87);
824 static void msm_chg_enable_secondary_det(struct msm_otg
*motg
)
826 struct otg_transceiver
*otg
= &motg
->otg
;
829 switch (motg
->pdata
->phy_type
) {
830 case CI_45NM_INTEGRATED_PHY
:
831 chg_det
= ulpi_read(otg
, 0x34);
832 /* Turn off charger block */
833 chg_det
|= ~(1 << 1);
834 ulpi_write(otg
, chg_det
, 0x34);
836 /* control chg block via ULPI */
837 chg_det
&= ~(1 << 3);
838 ulpi_write(otg
, chg_det
, 0x34);
839 /* put it in host mode for enabling D- source */
840 chg_det
&= ~(1 << 2);
841 ulpi_write(otg
, chg_det
, 0x34);
842 /* Turn on chg detect block */
843 chg_det
&= ~(1 << 1);
844 ulpi_write(otg
, chg_det
, 0x34);
846 /* enable chg detection */
847 chg_det
&= ~(1 << 0);
848 ulpi_write(otg
, chg_det
, 0x34);
850 case SNPS_28NM_INTEGRATED_PHY
:
852 * Configure DM as current source, DP as current sink
853 * and enable battery charging comparators.
855 ulpi_write(otg
, 0x8, 0x85);
856 ulpi_write(otg
, 0x2, 0x85);
857 ulpi_write(otg
, 0x1, 0x85);
864 static bool msm_chg_check_primary_det(struct msm_otg
*motg
)
866 struct otg_transceiver
*otg
= &motg
->otg
;
870 switch (motg
->pdata
->phy_type
) {
871 case CI_45NM_INTEGRATED_PHY
:
872 chg_det
= ulpi_read(otg
, 0x34);
873 ret
= chg_det
& (1 << 4);
875 case SNPS_28NM_INTEGRATED_PHY
:
876 chg_det
= ulpi_read(otg
, 0x87);
885 static void msm_chg_enable_primary_det(struct msm_otg
*motg
)
887 struct otg_transceiver
*otg
= &motg
->otg
;
890 switch (motg
->pdata
->phy_type
) {
891 case CI_45NM_INTEGRATED_PHY
:
892 chg_det
= ulpi_read(otg
, 0x34);
893 /* enable chg detection */
894 chg_det
&= ~(1 << 0);
895 ulpi_write(otg
, chg_det
, 0x34);
897 case SNPS_28NM_INTEGRATED_PHY
:
899 * Configure DP as current source, DM as current sink
900 * and enable battery charging comparators.
902 ulpi_write(otg
, 0x2, 0x85);
903 ulpi_write(otg
, 0x1, 0x85);
910 static bool msm_chg_check_dcd(struct msm_otg
*motg
)
912 struct otg_transceiver
*otg
= &motg
->otg
;
916 switch (motg
->pdata
->phy_type
) {
917 case CI_45NM_INTEGRATED_PHY
:
918 line_state
= ulpi_read(otg
, 0x15);
919 ret
= !(line_state
& 1);
921 case SNPS_28NM_INTEGRATED_PHY
:
922 line_state
= ulpi_read(otg
, 0x87);
923 ret
= line_state
& 2;
931 static void msm_chg_disable_dcd(struct msm_otg
*motg
)
933 struct otg_transceiver
*otg
= &motg
->otg
;
936 switch (motg
->pdata
->phy_type
) {
937 case CI_45NM_INTEGRATED_PHY
:
938 chg_det
= ulpi_read(otg
, 0x34);
939 chg_det
&= ~(1 << 5);
940 ulpi_write(otg
, chg_det
, 0x34);
942 case SNPS_28NM_INTEGRATED_PHY
:
943 ulpi_write(otg
, 0x10, 0x86);
950 static void msm_chg_enable_dcd(struct msm_otg
*motg
)
952 struct otg_transceiver
*otg
= &motg
->otg
;
955 switch (motg
->pdata
->phy_type
) {
956 case CI_45NM_INTEGRATED_PHY
:
957 chg_det
= ulpi_read(otg
, 0x34);
958 /* Turn on D+ current source */
960 ulpi_write(otg
, chg_det
, 0x34);
962 case SNPS_28NM_INTEGRATED_PHY
:
963 /* Data contact detection enable */
964 ulpi_write(otg
, 0x10, 0x85);
971 static void msm_chg_block_on(struct msm_otg
*motg
)
973 struct otg_transceiver
*otg
= &motg
->otg
;
974 u32 func_ctrl
, chg_det
;
976 /* put the controller in non-driving mode */
977 func_ctrl
= ulpi_read(otg
, ULPI_FUNC_CTRL
);
978 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
979 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NONDRIVING
;
980 ulpi_write(otg
, func_ctrl
, ULPI_FUNC_CTRL
);
982 switch (motg
->pdata
->phy_type
) {
983 case CI_45NM_INTEGRATED_PHY
:
984 chg_det
= ulpi_read(otg
, 0x34);
985 /* control chg block via ULPI */
986 chg_det
&= ~(1 << 3);
987 ulpi_write(otg
, chg_det
, 0x34);
988 /* Turn on chg detect block */
989 chg_det
&= ~(1 << 1);
990 ulpi_write(otg
, chg_det
, 0x34);
993 case SNPS_28NM_INTEGRATED_PHY
:
994 /* Clear charger detecting control bits */
995 ulpi_write(otg
, 0x3F, 0x86);
996 /* Clear alt interrupt latch and enable bits */
997 ulpi_write(otg
, 0x1F, 0x92);
998 ulpi_write(otg
, 0x1F, 0x95);
1006 static void msm_chg_block_off(struct msm_otg
*motg
)
1008 struct otg_transceiver
*otg
= &motg
->otg
;
1009 u32 func_ctrl
, chg_det
;
1011 switch (motg
->pdata
->phy_type
) {
1012 case CI_45NM_INTEGRATED_PHY
:
1013 chg_det
= ulpi_read(otg
, 0x34);
1014 /* Turn off charger block */
1015 chg_det
|= ~(1 << 1);
1016 ulpi_write(otg
, chg_det
, 0x34);
1018 case SNPS_28NM_INTEGRATED_PHY
:
1019 /* Clear charger detecting control bits */
1020 ulpi_write(otg
, 0x3F, 0x86);
1021 /* Clear alt interrupt latch and enable bits */
1022 ulpi_write(otg
, 0x1F, 0x92);
1023 ulpi_write(otg
, 0x1F, 0x95);
1029 /* put the controller in normal mode */
1030 func_ctrl
= ulpi_read(otg
, ULPI_FUNC_CTRL
);
1031 func_ctrl
&= ~ULPI_FUNC_CTRL_OPMODE_MASK
;
1032 func_ctrl
|= ULPI_FUNC_CTRL_OPMODE_NORMAL
;
1033 ulpi_write(otg
, func_ctrl
, ULPI_FUNC_CTRL
);
1036 #define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
1037 #define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
1038 #define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
1039 #define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
1040 static void msm_chg_detect_work(struct work_struct
*w
)
1042 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, chg_work
.work
);
1043 struct otg_transceiver
*otg
= &motg
->otg
;
1044 bool is_dcd
, tmout
, vout
;
1045 unsigned long delay
;
1047 dev_dbg(otg
->dev
, "chg detection work\n");
1048 switch (motg
->chg_state
) {
1049 case USB_CHG_STATE_UNDEFINED
:
1050 pm_runtime_get_sync(otg
->dev
);
1051 msm_chg_block_on(motg
);
1052 msm_chg_enable_dcd(motg
);
1053 motg
->chg_state
= USB_CHG_STATE_WAIT_FOR_DCD
;
1054 motg
->dcd_retries
= 0;
1055 delay
= MSM_CHG_DCD_POLL_TIME
;
1057 case USB_CHG_STATE_WAIT_FOR_DCD
:
1058 is_dcd
= msm_chg_check_dcd(motg
);
1059 tmout
= ++motg
->dcd_retries
== MSM_CHG_DCD_MAX_RETRIES
;
1060 if (is_dcd
|| tmout
) {
1061 msm_chg_disable_dcd(motg
);
1062 msm_chg_enable_primary_det(motg
);
1063 delay
= MSM_CHG_PRIMARY_DET_TIME
;
1064 motg
->chg_state
= USB_CHG_STATE_DCD_DONE
;
1066 delay
= MSM_CHG_DCD_POLL_TIME
;
1069 case USB_CHG_STATE_DCD_DONE
:
1070 vout
= msm_chg_check_primary_det(motg
);
1072 msm_chg_enable_secondary_det(motg
);
1073 delay
= MSM_CHG_SECONDARY_DET_TIME
;
1074 motg
->chg_state
= USB_CHG_STATE_PRIMARY_DONE
;
1076 motg
->chg_type
= USB_SDP_CHARGER
;
1077 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1081 case USB_CHG_STATE_PRIMARY_DONE
:
1082 vout
= msm_chg_check_secondary_det(motg
);
1084 motg
->chg_type
= USB_DCP_CHARGER
;
1086 motg
->chg_type
= USB_CDP_CHARGER
;
1087 motg
->chg_state
= USB_CHG_STATE_SECONDARY_DONE
;
1089 case USB_CHG_STATE_SECONDARY_DONE
:
1090 motg
->chg_state
= USB_CHG_STATE_DETECTED
;
1091 case USB_CHG_STATE_DETECTED
:
1092 msm_chg_block_off(motg
);
1093 dev_dbg(otg
->dev
, "charger = %d\n", motg
->chg_type
);
1094 schedule_work(&motg
->sm_work
);
1100 schedule_delayed_work(&motg
->chg_work
, delay
);
1104 * We support OTG, Peripheral only and Host only configurations. In case
1105 * of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
1106 * via Id pin status or user request (debugfs). Id/BSV interrupts are not
1107 * enabled when switch is controlled by user and default mode is supplied
1108 * by board file, which can be changed by userspace later.
1110 static void msm_otg_init_sm(struct msm_otg
*motg
)
1112 struct msm_otg_platform_data
*pdata
= motg
->pdata
;
1113 u32 otgsc
= readl(USB_OTGSC
);
1115 switch (pdata
->mode
) {
1117 if (pdata
->otg_control
== OTG_PHY_CONTROL
) {
1118 if (otgsc
& OTGSC_ID
)
1119 set_bit(ID
, &motg
->inputs
);
1121 clear_bit(ID
, &motg
->inputs
);
1123 if (otgsc
& OTGSC_BSV
)
1124 set_bit(B_SESS_VLD
, &motg
->inputs
);
1126 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1127 } else if (pdata
->otg_control
== OTG_USER_CONTROL
) {
1128 if (pdata
->default_mode
== USB_HOST
) {
1129 clear_bit(ID
, &motg
->inputs
);
1130 } else if (pdata
->default_mode
== USB_PERIPHERAL
) {
1131 set_bit(ID
, &motg
->inputs
);
1132 set_bit(B_SESS_VLD
, &motg
->inputs
);
1134 set_bit(ID
, &motg
->inputs
);
1135 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1140 clear_bit(ID
, &motg
->inputs
);
1142 case USB_PERIPHERAL
:
1143 set_bit(ID
, &motg
->inputs
);
1144 if (otgsc
& OTGSC_BSV
)
1145 set_bit(B_SESS_VLD
, &motg
->inputs
);
1147 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1154 static void msm_otg_sm_work(struct work_struct
*w
)
1156 struct msm_otg
*motg
= container_of(w
, struct msm_otg
, sm_work
);
1157 struct otg_transceiver
*otg
= &motg
->otg
;
1159 switch (otg
->state
) {
1160 case OTG_STATE_UNDEFINED
:
1161 dev_dbg(otg
->dev
, "OTG_STATE_UNDEFINED state\n");
1163 msm_otg_init_sm(motg
);
1164 otg
->state
= OTG_STATE_B_IDLE
;
1166 case OTG_STATE_B_IDLE
:
1167 dev_dbg(otg
->dev
, "OTG_STATE_B_IDLE state\n");
1168 if (!test_bit(ID
, &motg
->inputs
) && otg
->host
) {
1169 /* disable BSV bit */
1170 writel(readl(USB_OTGSC
) & ~OTGSC_BSVIE
, USB_OTGSC
);
1171 msm_otg_start_host(otg
, 1);
1172 otg
->state
= OTG_STATE_A_HOST
;
1173 } else if (test_bit(B_SESS_VLD
, &motg
->inputs
)) {
1174 switch (motg
->chg_state
) {
1175 case USB_CHG_STATE_UNDEFINED
:
1176 msm_chg_detect_work(&motg
->chg_work
.work
);
1178 case USB_CHG_STATE_DETECTED
:
1179 switch (motg
->chg_type
) {
1180 case USB_DCP_CHARGER
:
1181 msm_otg_notify_charger(motg
,
1184 case USB_CDP_CHARGER
:
1185 msm_otg_notify_charger(motg
,
1187 msm_otg_start_peripheral(otg
, 1);
1188 otg
->state
= OTG_STATE_B_PERIPHERAL
;
1190 case USB_SDP_CHARGER
:
1191 msm_otg_notify_charger(motg
, IUNIT
);
1192 msm_otg_start_peripheral(otg
, 1);
1193 otg
->state
= OTG_STATE_B_PERIPHERAL
;
1204 * If charger detection work is pending, decrement
1205 * the pm usage counter to balance with the one that
1206 * is incremented in charger detection work.
1208 if (cancel_delayed_work_sync(&motg
->chg_work
)) {
1209 pm_runtime_put_sync(otg
->dev
);
1212 msm_otg_notify_charger(motg
, 0);
1213 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1214 motg
->chg_type
= USB_INVALID_CHARGER
;
1216 pm_runtime_put_sync(otg
->dev
);
1218 case OTG_STATE_B_PERIPHERAL
:
1219 dev_dbg(otg
->dev
, "OTG_STATE_B_PERIPHERAL state\n");
1220 if (!test_bit(B_SESS_VLD
, &motg
->inputs
) ||
1221 !test_bit(ID
, &motg
->inputs
)) {
1222 msm_otg_notify_charger(motg
, 0);
1223 msm_otg_start_peripheral(otg
, 0);
1224 motg
->chg_state
= USB_CHG_STATE_UNDEFINED
;
1225 motg
->chg_type
= USB_INVALID_CHARGER
;
1226 otg
->state
= OTG_STATE_B_IDLE
;
1231 case OTG_STATE_A_HOST
:
1232 dev_dbg(otg
->dev
, "OTG_STATE_A_HOST state\n");
1233 if (test_bit(ID
, &motg
->inputs
)) {
1234 msm_otg_start_host(otg
, 0);
1235 otg
->state
= OTG_STATE_B_IDLE
;
1245 static irqreturn_t
msm_otg_irq(int irq
, void *data
)
1247 struct msm_otg
*motg
= data
;
1248 struct otg_transceiver
*otg
= &motg
->otg
;
1251 if (atomic_read(&motg
->in_lpm
)) {
1252 disable_irq_nosync(irq
);
1253 motg
->async_int
= 1;
1254 pm_runtime_get(otg
->dev
);
1258 otgsc
= readl(USB_OTGSC
);
1259 if (!(otgsc
& (OTGSC_IDIS
| OTGSC_BSVIS
)))
1262 if ((otgsc
& OTGSC_IDIS
) && (otgsc
& OTGSC_IDIE
)) {
1263 if (otgsc
& OTGSC_ID
)
1264 set_bit(ID
, &motg
->inputs
);
1266 clear_bit(ID
, &motg
->inputs
);
1267 dev_dbg(otg
->dev
, "ID set/clear\n");
1268 pm_runtime_get_noresume(otg
->dev
);
1269 } else if ((otgsc
& OTGSC_BSVIS
) && (otgsc
& OTGSC_BSVIE
)) {
1270 if (otgsc
& OTGSC_BSV
)
1271 set_bit(B_SESS_VLD
, &motg
->inputs
);
1273 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1274 dev_dbg(otg
->dev
, "BSV set/clear\n");
1275 pm_runtime_get_noresume(otg
->dev
);
1278 writel(otgsc
, USB_OTGSC
);
1279 schedule_work(&motg
->sm_work
);
1283 static int msm_otg_mode_show(struct seq_file
*s
, void *unused
)
1285 struct msm_otg
*motg
= s
->private;
1286 struct otg_transceiver
*otg
= &motg
->otg
;
1288 switch (otg
->state
) {
1289 case OTG_STATE_A_HOST
:
1290 seq_printf(s
, "host\n");
1292 case OTG_STATE_B_PERIPHERAL
:
1293 seq_printf(s
, "peripheral\n");
1296 seq_printf(s
, "none\n");
1303 static int msm_otg_mode_open(struct inode
*inode
, struct file
*file
)
1305 return single_open(file
, msm_otg_mode_show
, inode
->i_private
);
1308 static ssize_t
msm_otg_mode_write(struct file
*file
, const char __user
*ubuf
,
1309 size_t count
, loff_t
*ppos
)
1311 struct seq_file
*s
= file
->private_data
;
1312 struct msm_otg
*motg
= s
->private;
1314 struct otg_transceiver
*otg
= &motg
->otg
;
1316 enum usb_mode_type req_mode
;
1318 memset(buf
, 0x00, sizeof(buf
));
1320 if (copy_from_user(&buf
, ubuf
, min_t(size_t, sizeof(buf
) - 1, count
))) {
1325 if (!strncmp(buf
, "host", 4)) {
1326 req_mode
= USB_HOST
;
1327 } else if (!strncmp(buf
, "peripheral", 10)) {
1328 req_mode
= USB_PERIPHERAL
;
1329 } else if (!strncmp(buf
, "none", 4)) {
1330 req_mode
= USB_NONE
;
1338 switch (otg
->state
) {
1339 case OTG_STATE_A_HOST
:
1340 case OTG_STATE_B_PERIPHERAL
:
1341 set_bit(ID
, &motg
->inputs
);
1342 clear_bit(B_SESS_VLD
, &motg
->inputs
);
1348 case USB_PERIPHERAL
:
1349 switch (otg
->state
) {
1350 case OTG_STATE_B_IDLE
:
1351 case OTG_STATE_A_HOST
:
1352 set_bit(ID
, &motg
->inputs
);
1353 set_bit(B_SESS_VLD
, &motg
->inputs
);
1360 switch (otg
->state
) {
1361 case OTG_STATE_B_IDLE
:
1362 case OTG_STATE_B_PERIPHERAL
:
1363 clear_bit(ID
, &motg
->inputs
);
1373 pm_runtime_get_sync(otg
->dev
);
1374 schedule_work(&motg
->sm_work
);
1379 const struct file_operations msm_otg_mode_fops
= {
1380 .open
= msm_otg_mode_open
,
1382 .write
= msm_otg_mode_write
,
1383 .llseek
= seq_lseek
,
1384 .release
= single_release
,
1387 static struct dentry
*msm_otg_dbg_root
;
1388 static struct dentry
*msm_otg_dbg_mode
;
1390 static int msm_otg_debugfs_init(struct msm_otg
*motg
)
1392 msm_otg_dbg_root
= debugfs_create_dir("msm_otg", NULL
);
1394 if (!msm_otg_dbg_root
|| IS_ERR(msm_otg_dbg_root
))
1397 msm_otg_dbg_mode
= debugfs_create_file("mode", S_IRUGO
| S_IWUSR
,
1398 msm_otg_dbg_root
, motg
, &msm_otg_mode_fops
);
1399 if (!msm_otg_dbg_mode
) {
1400 debugfs_remove(msm_otg_dbg_root
);
1401 msm_otg_dbg_root
= NULL
;
1408 static void msm_otg_debugfs_cleanup(void)
1410 debugfs_remove(msm_otg_dbg_mode
);
1411 debugfs_remove(msm_otg_dbg_root
);
1414 static int __init
msm_otg_probe(struct platform_device
*pdev
)
1417 struct resource
*res
;
1418 struct msm_otg
*motg
;
1419 struct otg_transceiver
*otg
;
1421 dev_info(&pdev
->dev
, "msm_otg probe\n");
1422 if (!pdev
->dev
.platform_data
) {
1423 dev_err(&pdev
->dev
, "No platform data given. Bailing out\n");
1427 motg
= kzalloc(sizeof(struct msm_otg
), GFP_KERNEL
);
1429 dev_err(&pdev
->dev
, "unable to allocate msm_otg\n");
1433 motg
->pdata
= pdev
->dev
.platform_data
;
1435 otg
->dev
= &pdev
->dev
;
1437 motg
->phy_reset_clk
= clk_get(&pdev
->dev
, "usb_phy_clk");
1438 if (IS_ERR(motg
->phy_reset_clk
)) {
1439 dev_err(&pdev
->dev
, "failed to get usb_phy_clk\n");
1440 ret
= PTR_ERR(motg
->phy_reset_clk
);
1444 motg
->clk
= clk_get(&pdev
->dev
, "usb_hs_clk");
1445 if (IS_ERR(motg
->clk
)) {
1446 dev_err(&pdev
->dev
, "failed to get usb_hs_clk\n");
1447 ret
= PTR_ERR(motg
->clk
);
1448 goto put_phy_reset_clk
;
1450 clk_set_rate(motg
->clk
, 60000000);
1453 * If USB Core is running its protocol engine based on CORE CLK,
1454 * CORE CLK must be running at >55Mhz for correct HSUSB
1455 * operation and USB core cannot tolerate frequency changes on
1456 * CORE CLK. For such USB cores, vote for maximum clk frequency
1459 if (motg
->pdata
->pclk_src_name
) {
1460 motg
->pclk_src
= clk_get(&pdev
->dev
,
1461 motg
->pdata
->pclk_src_name
);
1462 if (IS_ERR(motg
->pclk_src
))
1464 clk_set_rate(motg
->pclk_src
, INT_MAX
);
1465 clk_enable(motg
->pclk_src
);
1467 motg
->pclk_src
= ERR_PTR(-ENOENT
);
1470 motg
->pclk
= clk_get(&pdev
->dev
, "usb_hs_pclk");
1471 if (IS_ERR(motg
->pclk
)) {
1472 dev_err(&pdev
->dev
, "failed to get usb_hs_pclk\n");
1473 ret
= PTR_ERR(motg
->pclk
);
1478 * USB core clock is not present on all MSM chips. This
1479 * clock is introduced to remove the dependency on AXI
1482 motg
->core_clk
= clk_get(&pdev
->dev
, "usb_hs_core_clk");
1483 if (IS_ERR(motg
->core_clk
))
1484 motg
->core_clk
= NULL
;
1486 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1488 dev_err(&pdev
->dev
, "failed to get platform resource mem\n");
1493 motg
->regs
= ioremap(res
->start
, resource_size(res
));
1495 dev_err(&pdev
->dev
, "ioremap failed\n");
1499 dev_info(&pdev
->dev
, "OTG regs = %p\n", motg
->regs
);
1501 motg
->irq
= platform_get_irq(pdev
, 0);
1503 dev_err(&pdev
->dev
, "platform_get_irq failed\n");
1508 clk_enable(motg
->clk
);
1509 clk_enable(motg
->pclk
);
1511 ret
= msm_hsusb_init_vddcx(motg
, 1);
1513 dev_err(&pdev
->dev
, "hsusb vddcx configuration failed\n");
1517 ret
= msm_hsusb_ldo_init(motg
, 1);
1519 dev_err(&pdev
->dev
, "hsusb vreg configuration failed\n");
1522 ret
= msm_hsusb_ldo_set_mode(1);
1524 dev_err(&pdev
->dev
, "hsusb vreg enable failed\n");
1529 clk_enable(motg
->core_clk
);
1531 writel(0, USB_USBINTR
);
1532 writel(0, USB_OTGSC
);
1534 INIT_WORK(&motg
->sm_work
, msm_otg_sm_work
);
1535 INIT_DELAYED_WORK(&motg
->chg_work
, msm_chg_detect_work
);
1536 ret
= request_irq(motg
->irq
, msm_otg_irq
, IRQF_SHARED
,
1539 dev_err(&pdev
->dev
, "request irq failed\n");
1543 otg
->init
= msm_otg_reset
;
1544 otg
->set_host
= msm_otg_set_host
;
1545 otg
->set_peripheral
= msm_otg_set_peripheral
;
1546 otg
->set_power
= msm_otg_set_power
;
1548 otg
->io_ops
= &msm_otg_io_ops
;
1550 ret
= otg_set_transceiver(&motg
->otg
);
1552 dev_err(&pdev
->dev
, "otg_set_transceiver failed\n");
1556 platform_set_drvdata(pdev
, motg
);
1557 device_init_wakeup(&pdev
->dev
, 1);
1559 if (motg
->pdata
->mode
== USB_OTG
&&
1560 motg
->pdata
->otg_control
== OTG_USER_CONTROL
) {
1561 ret
= msm_otg_debugfs_init(motg
);
1563 dev_dbg(&pdev
->dev
, "mode debugfs file is"
1567 pm_runtime_set_active(&pdev
->dev
);
1568 pm_runtime_enable(&pdev
->dev
);
1572 free_irq(motg
->irq
, motg
);
1574 clk_disable(motg
->pclk
);
1575 clk_disable(motg
->clk
);
1577 msm_hsusb_ldo_init(motg
, 0);
1579 msm_hsusb_init_vddcx(motg
, 0);
1581 iounmap(motg
->regs
);
1584 clk_put(motg
->core_clk
);
1585 clk_put(motg
->pclk
);
1587 if (!IS_ERR(motg
->pclk_src
)) {
1588 clk_disable(motg
->pclk_src
);
1589 clk_put(motg
->pclk_src
);
1594 clk_put(motg
->phy_reset_clk
);
1600 static int __devexit
msm_otg_remove(struct platform_device
*pdev
)
1602 struct msm_otg
*motg
= platform_get_drvdata(pdev
);
1603 struct otg_transceiver
*otg
= &motg
->otg
;
1606 if (otg
->host
|| otg
->gadget
)
1609 msm_otg_debugfs_cleanup();
1610 cancel_delayed_work_sync(&motg
->chg_work
);
1611 cancel_work_sync(&motg
->sm_work
);
1613 pm_runtime_resume(&pdev
->dev
);
1615 device_init_wakeup(&pdev
->dev
, 0);
1616 pm_runtime_disable(&pdev
->dev
);
1618 otg_set_transceiver(NULL
);
1619 free_irq(motg
->irq
, motg
);
1622 * Put PHY in low power mode.
1624 ulpi_read(otg
, 0x14);
1625 ulpi_write(otg
, 0x08, 0x09);
1627 writel(readl(USB_PORTSC
) | PORTSC_PHCD
, USB_PORTSC
);
1628 while (cnt
< PHY_SUSPEND_TIMEOUT_USEC
) {
1629 if (readl(USB_PORTSC
) & PORTSC_PHCD
)
1634 if (cnt
>= PHY_SUSPEND_TIMEOUT_USEC
)
1635 dev_err(otg
->dev
, "Unable to suspend PHY\n");
1637 clk_disable(motg
->pclk
);
1638 clk_disable(motg
->clk
);
1640 clk_disable(motg
->core_clk
);
1641 if (!IS_ERR(motg
->pclk_src
)) {
1642 clk_disable(motg
->pclk_src
);
1643 clk_put(motg
->pclk_src
);
1645 msm_hsusb_ldo_init(motg
, 0);
1647 iounmap(motg
->regs
);
1648 pm_runtime_set_suspended(&pdev
->dev
);
1650 clk_put(motg
->phy_reset_clk
);
1651 clk_put(motg
->pclk
);
1654 clk_put(motg
->core_clk
);
1661 #ifdef CONFIG_PM_RUNTIME
1662 static int msm_otg_runtime_idle(struct device
*dev
)
1664 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1665 struct otg_transceiver
*otg
= &motg
->otg
;
1667 dev_dbg(dev
, "OTG runtime idle\n");
1670 * It is observed some times that a spurious interrupt
1671 * comes when PHY is put into LPM immediately after PHY reset.
1672 * This 1 sec delay also prevents entering into LPM immediately
1673 * after asynchronous interrupt.
1675 if (otg
->state
!= OTG_STATE_UNDEFINED
)
1676 pm_schedule_suspend(dev
, 1000);
1681 static int msm_otg_runtime_suspend(struct device
*dev
)
1683 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1685 dev_dbg(dev
, "OTG runtime suspend\n");
1686 return msm_otg_suspend(motg
);
1689 static int msm_otg_runtime_resume(struct device
*dev
)
1691 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1693 dev_dbg(dev
, "OTG runtime resume\n");
1694 return msm_otg_resume(motg
);
1698 #ifdef CONFIG_PM_SLEEP
1699 static int msm_otg_pm_suspend(struct device
*dev
)
1701 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1703 dev_dbg(dev
, "OTG PM suspend\n");
1704 return msm_otg_suspend(motg
);
1707 static int msm_otg_pm_resume(struct device
*dev
)
1709 struct msm_otg
*motg
= dev_get_drvdata(dev
);
1712 dev_dbg(dev
, "OTG PM resume\n");
1714 ret
= msm_otg_resume(motg
);
1719 * Runtime PM Documentation recommends bringing the
1720 * device to full powered state upon resume.
1722 pm_runtime_disable(dev
);
1723 pm_runtime_set_active(dev
);
1724 pm_runtime_enable(dev
);
1731 static const struct dev_pm_ops msm_otg_dev_pm_ops
= {
1732 SET_SYSTEM_SLEEP_PM_OPS(msm_otg_pm_suspend
, msm_otg_pm_resume
)
1733 SET_RUNTIME_PM_OPS(msm_otg_runtime_suspend
, msm_otg_runtime_resume
,
1734 msm_otg_runtime_idle
)
1738 static struct platform_driver msm_otg_driver
= {
1739 .remove
= __devexit_p(msm_otg_remove
),
1741 .name
= DRIVER_NAME
,
1742 .owner
= THIS_MODULE
,
1744 .pm
= &msm_otg_dev_pm_ops
,
1749 static int __init
msm_otg_init(void)
1751 return platform_driver_probe(&msm_otg_driver
, msm_otg_probe
);
1754 static void __exit
msm_otg_exit(void)
1756 platform_driver_unregister(&msm_otg_driver
);
1759 module_init(msm_otg_init
);
1760 module_exit(msm_otg_exit
);
1762 MODULE_LICENSE("GPL v2");
1763 MODULE_DESCRIPTION("MSM USB transceiver driver");