arch/ppc/syslib/mpc52xx_pci.h

   1 /*
   2  * PCI Include file the Freescale MPC52xx embedded cpu chips
   3  *
   4  *
   5  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
   6  *
   7  * Inspired from code written by Dale Farnsworth <dfarnsworth@mvista.com>
   8  * for the 2.4 kernel.
   9  *
  10  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  11  * Copyright (C) 2003 MontaVista, Software, Inc.
  12  *
  13  * This file is licensed under the terms of the GNU General Public License
  14  * version 2. This program is licensed "as is" without any warranty of any
  15  * kind, whether express or implied.
  16  */
  17
  18 #ifndef __SYSLIB_MPC52xx_PCI_H__
  19 #define __SYSLIB_MPC52xx_PCI_H__
  20
  21 /* ======================================================================== */
  22 /* PCI windows config                                                       */
  23 /* ======================================================================== */
  24
  25 /*
  26  * Master windows : MPC52xx -> PCI
  27  *
  28  *  0x80000000 -> 0x9FFFFFFF       PCI Mem prefetchable          IW0BTAR
  29  *  0xA0000000 -> 0xAFFFFFFF       PCI Mem                       IW1BTAR
  30  *  0xB0000000 -> 0xB0FFFFFF       PCI IO                        IW2BTAR
  31  *
  32  * Slave windows  : PCI -> MPC52xx
  33  *
  34  *  0xF0000000 -> 0xF003FFFF       MPC52xx MBAR                  TBATR0
  35  *  0x00000000 -> 0x3FFFFFFF       MPC52xx local memory          TBATR1
  36  */
  37
  38 #define MPC52xx_PCI_MEM_OFFSET  0x00000000      /* Offset for MEM MMIO */
  39
  40 #define MPC52xx_PCI_MEM_START   0x80000000
  41 #define MPC52xx_PCI_MEM_SIZE    0x20000000
  42 #define MPC52xx_PCI_MEM_STOP    (MPC52xx_PCI_MEM_START+MPC52xx_PCI_MEM_SIZE-1)
  43
  44 #define MPC52xx_PCI_MMIO_START  0xa0000000
  45 #define MPC52xx_PCI_MMIO_SIZE   0x10000000
  46 #define MPC52xx_PCI_MMIO_STOP   (MPC52xx_PCI_MMIO_START+MPC52xx_PCI_MMIO_SIZE-1)
  47
  48 #define MPC52xx_PCI_IO_BASE     0xb0000000
  49
  50 #define MPC52xx_PCI_IO_START    0x00000000
  51 #define MPC52xx_PCI_IO_SIZE     0x01000000
  52 #define MPC52xx_PCI_IO_STOP     (MPC52xx_PCI_IO_START+MPC52xx_PCI_IO_SIZE-1)
  53
  54
  55 #define MPC52xx_PCI_TARGET_IO   MPC52xx_MBAR
  56 #define MPC52xx_PCI_TARGET_MEM  0x00000000
  57
  58
  59 /* ======================================================================== */
  60 /* Structures mapping & Defines for PCI Unit                                */
  61 /* ======================================================================== */
  62
  63 #define MPC52xx_PCI_GSCR_BM             0x40000000
  64 #define MPC52xx_PCI_GSCR_PE             0x20000000
  65 #define MPC52xx_PCI_GSCR_SE             0x10000000
  66 #define MPC52xx_PCI_GSCR_XLB2PCI_MASK   0x07000000
  67 #define MPC52xx_PCI_GSCR_XLB2PCI_SHIFT  24
  68 #define MPC52xx_PCI_GSCR_IPG2PCI_MASK   0x00070000
  69 #define MPC52xx_PCI_GSCR_IPG2PCI_SHIFT  16
  70 #define MPC52xx_PCI_GSCR_BME            0x00004000
  71 #define MPC52xx_PCI_GSCR_PEE            0x00002000
  72 #define MPC52xx_PCI_GSCR_SEE            0x00001000
  73 #define MPC52xx_PCI_GSCR_PR             0x00000001
  74
  75
  76 #define MPC52xx_PCI_IWBTAR_TRANSLATION(proc_ad,pci_ad,size)       \
  77                 ( ( (proc_ad) & 0xff000000 )                    | \
  78                   ( (((size) - 1) >> 8) & 0x00ff0000 )          | \
  79                   ( ((pci_ad) >> 16) & 0x0000ff00 ) )
  80
  81 #define MPC52xx_PCI_IWCR_PACK(win0,win1,win2)   (((win0) << 24) | \
  82                                                  ((win1) << 16) | \
  83                                                  ((win2) <<  8))
  84
  85 #define MPC52xx_PCI_IWCR_DISABLE        0x0
  86 #define MPC52xx_PCI_IWCR_ENABLE         0x1
  87 #define MPC52xx_PCI_IWCR_READ           0x0
  88 #define MPC52xx_PCI_IWCR_READ_LINE      0x2
  89 #define MPC52xx_PCI_IWCR_READ_MULTI     0x4
  90 #define MPC52xx_PCI_IWCR_MEM            0x0
  91 #define MPC52xx_PCI_IWCR_IO             0x8
  92
  93 #define MPC52xx_PCI_TCR_P               0x01000000
  94 #define MPC52xx_PCI_TCR_LD              0x00010000
  95
  96 #define MPC52xx_PCI_TBATR_DISABLE       0x0
  97 #define MPC52xx_PCI_TBATR_ENABLE        0x1
  98
  99
 100 #ifndef __ASSEMBLY__
 101
 102 struct mpc52xx_pci {
 103         u32     idr;            /* PCI + 0x00 */
 104         u32     scr;            /* PCI + 0x04 */
 105         u32     ccrir;          /* PCI + 0x08 */
 106         u32     cr1;            /* PCI + 0x0C */
 107         u32     bar0;           /* PCI + 0x10 */
 108         u32     bar1;           /* PCI + 0x14 */
 109         u8      reserved1[16];  /* PCI + 0x18 */
 110         u32     ccpr;           /* PCI + 0x28 */
 111         u32     sid;            /* PCI + 0x2C */
 112         u32     erbar;          /* PCI + 0x30 */
 113         u32     cpr;            /* PCI + 0x34 */
 114         u8      reserved2[4];   /* PCI + 0x38 */
 115         u32     cr2;            /* PCI + 0x3C */
 116         u8      reserved3[32];  /* PCI + 0x40 */
 117         u32     gscr;           /* PCI + 0x60 */
 118         u32     tbatr0;         /* PCI + 0x64 */
 119         u32     tbatr1;         /* PCI + 0x68 */
 120         u32     tcr;            /* PCI + 0x6C */
 121         u32     iw0btar;        /* PCI + 0x70 */
 122         u32     iw1btar;        /* PCI + 0x74 */
 123         u32     iw2btar;        /* PCI + 0x78 */
 124         u8      reserved4[4];   /* PCI + 0x7C */
 125         u32     iwcr;           /* PCI + 0x80 */
 126         u32     icr;            /* PCI + 0x84 */
 127         u32     isr;            /* PCI + 0x88 */
 128         u32     arb;            /* PCI + 0x8C */
 129         u8      reserved5[104]; /* PCI + 0x90 */
 130         u32     car;            /* PCI + 0xF8 */
 131         u8      reserved6[4];   /* PCI + 0xFC */
 132 };
 133
 134 #endif  /* __ASSEMBLY__ */
 135
 136
 137 #endif  /* __SYSLIB_MPC52xx_PCI_H__ */