drivers/staging/msm/mdp4_overlay_lcdc.c

   1 /* Copyright (c) 2008-2009, Code Aurora Forum. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  *
  12  * You should have received a copy of the GNU General Public License
  13  * along with this program; if not, write to the Free Software
  14  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  15  * 02110-1301, USA.
  16  */
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/sched.h>
  21 #include <linux/time.h>
  22 #include <linux/init.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/hrtimer.h>
  25 #include <linux/delay.h>
  26 #include <mach/hardware.h>
  27 #include <linux/io.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/mach-types.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/spinlock.h>
  33
  34 #include <linux/fb.h>
  35
  36 #include "mdp.h"
  37 #include "msm_fb.h"
  38 #include "mdp4.h"
  39
  40 #ifdef CONFIG_FB_MSM_MDP40
  41 #define LCDC_BASE       0xC0000
  42 #else
  43 #define LCDC_BASE       0xE0000
  44 #endif
  45
  46 int first_pixel_start_x;
  47 int first_pixel_start_y;
  48
  49 static struct mdp4_overlay_pipe *lcdc_pipe;
  50
  51 int mdp_lcdc_on(struct platform_device *pdev)
  52 {
  53         int lcdc_width;
  54         int lcdc_height;
  55         int lcdc_bpp;
  56         int lcdc_border_clr;
  57         int lcdc_underflow_clr;
  58         int lcdc_hsync_skew;
  59
  60         int hsync_period;
  61         int hsync_ctrl;
  62         int vsync_period;
  63         int display_hctl;
  64         int display_v_start;
  65         int display_v_end;
  66         int active_hctl;
  67         int active_h_start;
  68         int active_h_end;
  69         int active_v_start;
  70         int active_v_end;
  71         int ctrl_polarity;
  72         int h_back_porch;
  73         int h_front_porch;
  74         int v_back_porch;
  75         int v_front_porch;
  76         int hsync_pulse_width;
  77         int vsync_pulse_width;
  78         int hsync_polarity;
  79         int vsync_polarity;
  80         int data_en_polarity;
  81         int hsync_start_x;
  82         int hsync_end_x;
  83         uint8 *buf;
  84         int bpp, ptype;
  85         uint32 format;
  86         struct fb_info *fbi;
  87         struct fb_var_screeninfo *var;
  88         struct msm_fb_data_type *mfd;
  89         struct mdp4_overlay_pipe *pipe;
  90         int ret;
  91
  92         mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);
  93
  94         if (!mfd)
  95                 return -ENODEV;
  96
  97         if (mfd->key != MFD_KEY)
  98                 return -EINVAL;
  99
 100         fbi = mfd->fbi;
 101         var = &fbi->var;
 102
 103         /* MDP cmd block enable */
 104         mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
 105
 106         bpp = fbi->var.bits_per_pixel / 8;
 107         buf = (uint8 *) fbi->fix.smem_start;
 108         buf += fbi->var.xoffset * bpp +
 109                 fbi->var.yoffset * fbi->fix.line_length;
 110
 111         if (bpp == 2)
 112                 format = MDP_RGB_565;
 113         else if (bpp == 3)
 114                 format = MDP_RGB_888;
 115         else
 116                 format = MDP_ARGB_8888;
 117
 118
 119         if (lcdc_pipe == NULL) {
 120                 ptype = mdp4_overlay_format2type(format);
 121                 pipe = mdp4_overlay_pipe_alloc();
 122                 pipe->pipe_type = ptype;
 123                 /* use RGB1 pipe */
 124                 pipe->pipe_num  = OVERLAY_PIPE_RGB1;
 125                 pipe->mixer_stage  = MDP4_MIXER_STAGE_BASE;
 126                 pipe->mixer_num  = MDP4_MIXER0;
 127                 pipe->src_format = format;
 128                 mdp4_overlay_format2pipe(pipe);
 129
 130                 lcdc_pipe = pipe; /* keep it */
 131         } else {
 132                 pipe = lcdc_pipe;
 133         }
 134
 135         pipe->src_height = fbi->var.yres;
 136         pipe->src_width = fbi->var.xres;
 137         pipe->src_h = fbi->var.yres;
 138         pipe->src_w = fbi->var.xres;
 139         pipe->src_y = 0;
 140         pipe->src_x = 0;
 141         pipe->srcp0_addr = (uint32) buf;
 142         pipe->srcp0_ystride = fbi->fix.line_length;
 143
 144         mdp4_overlay_dmap_xy(pipe);
 145         mdp4_overlay_dmap_cfg(mfd, 1);
 146
 147         mdp4_overlay_rgb_setup(pipe);
 148
 149         mdp4_mixer_stage_up(pipe);
 150
 151         mdp4_overlayproc_cfg(pipe);
 152
 153         /*
 154          * LCDC timing setting
 155          */
 156         h_back_porch = var->left_margin;
 157         h_front_porch = var->right_margin;
 158         v_back_porch = var->upper_margin;
 159         v_front_porch = var->lower_margin;
 160         hsync_pulse_width = var->hsync_len;
 161         vsync_pulse_width = var->vsync_len;
 162         lcdc_border_clr = mfd->panel_info.lcdc.border_clr;
 163         lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
 164         lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
 165
 166         lcdc_width = mfd->panel_info.xres;
 167         lcdc_height = mfd->panel_info.yres;
 168         lcdc_bpp = mfd->panel_info.bpp;
 169
 170         hsync_period =
 171             hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;
 172         hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
 173         hsync_start_x = hsync_pulse_width + h_back_porch;
 174         hsync_end_x = hsync_period - h_front_porch - 1;
 175         display_hctl = (hsync_end_x << 16) | hsync_start_x;
 176
 177         vsync_period =
 178             (vsync_pulse_width + v_back_porch + lcdc_height +
 179              v_front_porch) * hsync_period;
 180         display_v_start =
 181             (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew;
 182         display_v_end =
 183             vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1;
 184
 185         if (lcdc_width != var->xres) {
 186                 active_h_start = hsync_start_x + first_pixel_start_x;
 187                 active_h_end = active_h_start + var->xres - 1;
 188                 active_hctl =
 189                     ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
 190         } else {
 191                 active_hctl = 0;
 192         }
 193
 194         if (lcdc_height != var->yres) {
 195                 active_v_start =
 196                     display_v_start + first_pixel_start_y * hsync_period;
 197                 active_v_end = active_v_start + (var->yres) * hsync_period - 1;
 198                 active_v_start |= ACTIVE_START_Y_EN;
 199         } else {
 200                 active_v_start = 0;
 201                 active_v_end = 0;
 202         }
 203
 204
 205 #ifdef CONFIG_FB_MSM_MDP40
 206         hsync_polarity = 1;
 207         vsync_polarity = 1;
 208         lcdc_underflow_clr |= 0x80000000;       /* enable recovery */
 209 #else
 210         hsync_polarity = 0;
 211         vsync_polarity = 0;
 212 #endif
 213         data_en_polarity = 0;
 214
 215         ctrl_polarity =
 216             (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);
 217
 218         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x4, hsync_ctrl);
 219         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x8, vsync_period);
 220         MDP_OUTP(MDP_BASE + LCDC_BASE + 0xc, vsync_pulse_width * hsync_period);
 221         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x10, display_hctl);
 222         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x14, display_v_start);
 223         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x18, display_v_end);
 224         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x28, lcdc_border_clr);
 225         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x2c, lcdc_underflow_clr);
 226         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x30, lcdc_hsync_skew);
 227         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x38, ctrl_polarity);
 228         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x1c, active_hctl);
 229         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x20, active_v_start);
 230         MDP_OUTP(MDP_BASE + LCDC_BASE + 0x24, active_v_end);
 231
 232         ret = panel_next_on(pdev);
 233         if (ret == 0) {
 234                 /* enable LCDC block */
 235                 MDP_OUTP(MDP_BASE + LCDC_BASE, 1);
 236                 mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
 237         }
 238         /* MDP cmd block disable */
 239         mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
 240
 241         return ret;
 242 }
 243
 244 int mdp_lcdc_off(struct platform_device *pdev)
 245 {
 246         int ret = 0;
 247         struct mdp4_overlay_pipe *pipe;
 248
 249         /* MDP cmd block enable */
 250         mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
 251         MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
 252         /* MDP cmd block disable */
 253         mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
 254         mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
 255
 256         ret = panel_next_off(pdev);
 257
 258         /* delay to make sure the last frame finishes */
 259         mdelay(100);
 260
 261         /* dis-engage rgb0 from mixer */
 262         pipe = lcdc_pipe;
 263         mdp4_mixer_stage_down(pipe);
 264
 265         return ret;
 266 }
 267
 268 /*
 269  * mdp4_overlay0_done_lcdc: called from isr
 270  */
 271 void mdp4_overlay0_done_lcdc()
 272 {
 273         complete(&lcdc_pipe->comp);
 274 }
 275
 276 void mdp4_lcdc_overlay(struct msm_fb_data_type *mfd)
 277 {
 278         struct fb_info *fbi = mfd->fbi;
 279         uint8 *buf;
 280         int bpp;
 281         unsigned long flag;
 282         struct mdp4_overlay_pipe *pipe;
 283
 284         if (!mfd->panel_power_on)
 285                 return;
 286
 287         /* no need to power on cmd block since it's lcdc mode */
 288         bpp = fbi->var.bits_per_pixel / 8;
 289         buf = (uint8 *) fbi->fix.smem_start;
 290         buf += fbi->var.xoffset * bpp +
 291                 fbi->var.yoffset * fbi->fix.line_length;
 292
 293         mutex_lock(&mfd->dma->ov_mutex);
 294
 295         pipe = lcdc_pipe;
 296         pipe->srcp0_addr = (uint32) buf;
 297         mdp4_overlay_rgb_setup(pipe);
 298         mdp4_overlay_reg_flush(pipe, 1); /* rgb1 and mixer0 */
 299
 300         /* enable irq */
 301         spin_lock_irqsave(&mdp_spin_lock, flag);
 302         mdp_enable_irq(MDP_OVERLAY0_TERM);
 303         INIT_COMPLETION(lcdc_pipe->comp);
 304         mfd->dma->waiting = TRUE;
 305         outp32(MDP_INTR_CLEAR, INTR_OVERLAY0_DONE);
 306         mdp_intr_mask |= INTR_OVERLAY0_DONE;
 307         outp32(MDP_INTR_ENABLE, mdp_intr_mask);
 308         spin_unlock_irqrestore(&mdp_spin_lock, flag);
 309         wait_for_completion_killable(&lcdc_pipe->comp);
 310         mdp_disable_irq(MDP_OVERLAY0_TERM);
 311
 312         mutex_unlock(&mfd->dma->ov_mutex);
 313 }