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ixgbe: cleanup short msleep's (<20ms) to use usleep_range
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ixgbe / ixgbe_82599.c
blobe39380ca996c546fe32ecf6023a3c484be54fdec
1 /*******************************************************************************
2
3 Intel 10 Gigabit PCI Express Linux driver
4 Copyright(c) 1999 - 2011 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26 *******************************************************************************/
27
28 #include <linux/pci.h>
29 #include <linux/delay.h>
30 #include <linux/sched.h>
31
32 #include "ixgbe.h"
33 #include "ixgbe_phy.h"
34 #include "ixgbe_mbx.h"
35
36 #define IXGBE_82599_MAX_TX_QUEUES 128
37 #define IXGBE_82599_MAX_RX_QUEUES 128
38 #define IXGBE_82599_RAR_ENTRIES 128
39 #define IXGBE_82599_MC_TBL_SIZE 128
40 #define IXGBE_82599_VFT_TBL_SIZE 128
41
42 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
43 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
44 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
46 ixgbe_link_speed speed,
47 bool autoneg,
48 bool autoneg_wait_to_complete);
49 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
50 ixgbe_link_speed speed,
51 bool autoneg,
52 bool autoneg_wait_to_complete);
53 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
57 bool autoneg,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
61 bool autoneg,
62 bool autoneg_wait_to_complete);
63 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
64 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
65
66 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
67 {
68 struct ixgbe_mac_info *mac = &hw->mac;
69
70 /* enable the laser control functions for SFP+ fiber */
71 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
72 mac->ops.disable_tx_laser =
73 &ixgbe_disable_tx_laser_multispeed_fiber;
74 mac->ops.enable_tx_laser =
75 &ixgbe_enable_tx_laser_multispeed_fiber;
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
77 } else {
78 mac->ops.disable_tx_laser = NULL;
79 mac->ops.enable_tx_laser = NULL;
80 mac->ops.flap_tx_laser = NULL;
81 }
82
83 if (hw->phy.multispeed_fiber) {
84 /* Set up dual speed SFP+ support */
85 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
86 } else {
87 if ((mac->ops.get_media_type(hw) ==
88 ixgbe_media_type_backplane) &&
89 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
90 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
91 !ixgbe_verify_lesm_fw_enabled_82599(hw))
92 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
93 else
94 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
95 }
96 }
97
98 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
99 {
100 s32 ret_val = 0;
101 u32 reg_anlp1 = 0;
102 u32 i = 0;
103 u16 list_offset, data_offset, data_value;
104
105 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
106 ixgbe_init_mac_link_ops_82599(hw);
107
108 hw->phy.ops.reset = NULL;
109
110 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
111 &data_offset);
112
113 if (ret_val != 0)
114 goto setup_sfp_out;
115
116 /* PHY config will finish before releasing the semaphore */
117 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
118 IXGBE_GSSR_MAC_CSR_SM);
119 if (ret_val != 0) {
120 ret_val = IXGBE_ERR_SWFW_SYNC;
121 goto setup_sfp_out;
122 }
123
124 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
125 while (data_value != 0xffff) {
126 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
127 IXGBE_WRITE_FLUSH(hw);
128 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
129 }
130
131 /* Release the semaphore */
132 ixgbe_release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
133 /*
134 * Delay obtaining semaphore again to allow FW access,
135 * semaphore_delay is in ms usleep_range needs us.
136 */
137 usleep_range(hw->eeprom.semaphore_delay * 1000,
138 hw->eeprom.semaphore_delay * 2000);
139
140 /* Now restart DSP by setting Restart_AN and clearing LMS */
141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
142 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
143 IXGBE_AUTOC_AN_RESTART));
144
145 /* Wait for AN to leave state 0 */
146 for (i = 0; i < 10; i++) {
147 usleep_range(4000, 8000);
148 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
149 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
150 break;
151 }
152 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
153 hw_dbg(hw, "sfp module setup not complete\n");
154 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
155 goto setup_sfp_out;
156 }
157
158 /* Restart DSP by setting Restart_AN and return to SFI mode */
159 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
160 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
161 IXGBE_AUTOC_AN_RESTART));
162 }
163
164 setup_sfp_out:
165 return ret_val;
166 }
167
168 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
169 {
170 struct ixgbe_mac_info *mac = &hw->mac;
171
172 ixgbe_init_mac_link_ops_82599(hw);
173
174 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
175 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
176 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
177 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
178 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
179 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
180
181 return 0;
182 }
183
184 /**
185 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
186 * @hw: pointer to hardware structure
187 *
188 * Initialize any function pointers that were not able to be
189 * set during get_invariants because the PHY/SFP type was
190 * not known. Perform the SFP init if necessary.
191 *
192 **/
193 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
194 {
195 struct ixgbe_mac_info *mac = &hw->mac;
196 struct ixgbe_phy_info *phy = &hw->phy;
197 s32 ret_val = 0;
198
199 /* Identify the PHY or SFP module */
200 ret_val = phy->ops.identify(hw);
201
202 /* Setup function pointers based on detected SFP module and speeds */
203 ixgbe_init_mac_link_ops_82599(hw);
204
205 /* If copper media, overwrite with copper function pointers */
206 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
207 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
208 mac->ops.get_link_capabilities =
209 &ixgbe_get_copper_link_capabilities_generic;
210 }
211
212 /* Set necessary function pointers based on phy type */
213 switch (hw->phy.type) {
214 case ixgbe_phy_tn:
215 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
216 phy->ops.get_firmware_version =
217 &ixgbe_get_phy_firmware_version_tnx;
218 break;
219 case ixgbe_phy_aq:
220 phy->ops.get_firmware_version =
221 &ixgbe_get_phy_firmware_version_generic;
222 break;
223 default:
224 break;
225 }
226
227 return ret_val;
228 }
229
230 /**
231 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
232 * @hw: pointer to hardware structure
233 * @speed: pointer to link speed
234 * @negotiation: true when autoneg or autotry is enabled
235 *
236 * Determines the link capabilities by reading the AUTOC register.
237 **/
238 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
239 ixgbe_link_speed *speed,
240 bool *negotiation)
241 {
242 s32 status = 0;
243 u32 autoc = 0;
244
245 /* Determine 1G link capabilities off of SFP+ type */
246 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
247 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
248 *speed = IXGBE_LINK_SPEED_1GB_FULL;
249 *negotiation = true;
250 goto out;
251 }
252
253 /*
254 * Determine link capabilities based on the stored value of AUTOC,
255 * which represents EEPROM defaults. If AUTOC value has not been
256 * stored, use the current register value.
257 */
258 if (hw->mac.orig_link_settings_stored)
259 autoc = hw->mac.orig_autoc;
260 else
261 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
262
263 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
264 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
265 *speed = IXGBE_LINK_SPEED_1GB_FULL;
266 *negotiation = false;
267 break;
268
269 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
270 *speed = IXGBE_LINK_SPEED_10GB_FULL;
271 *negotiation = false;
272 break;
273
274 case IXGBE_AUTOC_LMS_1G_AN:
275 *speed = IXGBE_LINK_SPEED_1GB_FULL;
276 *negotiation = true;
277 break;
278
279 case IXGBE_AUTOC_LMS_10G_SERIAL:
280 *speed = IXGBE_LINK_SPEED_10GB_FULL;
281 *negotiation = false;
282 break;
283
284 case IXGBE_AUTOC_LMS_KX4_KX_KR:
285 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
286 *speed = IXGBE_LINK_SPEED_UNKNOWN;
287 if (autoc & IXGBE_AUTOC_KR_SUPP)
288 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
289 if (autoc & IXGBE_AUTOC_KX4_SUPP)
290 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
291 if (autoc & IXGBE_AUTOC_KX_SUPP)
292 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
293 *negotiation = true;
294 break;
295
296 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
297 *speed = IXGBE_LINK_SPEED_100_FULL;
298 if (autoc & IXGBE_AUTOC_KR_SUPP)
299 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
300 if (autoc & IXGBE_AUTOC_KX4_SUPP)
301 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
302 if (autoc & IXGBE_AUTOC_KX_SUPP)
303 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
304 *negotiation = true;
305 break;
306
307 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
308 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
309 *negotiation = false;
310 break;
311
312 default:
313 status = IXGBE_ERR_LINK_SETUP;
314 goto out;
315 break;
316 }
317
318 if (hw->phy.multispeed_fiber) {
319 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
320 IXGBE_LINK_SPEED_1GB_FULL;
321 *negotiation = true;
322 }
323
324 out:
325 return status;
326 }
327
328 /**
329 * ixgbe_get_media_type_82599 - Get media type
330 * @hw: pointer to hardware structure
331 *
332 * Returns the media type (fiber, copper, backplane)
333 **/
334 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
335 {
336 enum ixgbe_media_type media_type;
337
338 /* Detect if there is a copper PHY attached. */
339 switch (hw->phy.type) {
340 case ixgbe_phy_cu_unknown:
341 case ixgbe_phy_tn:
342 case ixgbe_phy_aq:
343 media_type = ixgbe_media_type_copper;
344 goto out;
345 default:
346 break;
347 }
348
349 switch (hw->device_id) {
350 case IXGBE_DEV_ID_82599_KX4:
351 case IXGBE_DEV_ID_82599_KX4_MEZZ:
352 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
353 case IXGBE_DEV_ID_82599_KR:
354 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
355 case IXGBE_DEV_ID_82599_XAUI_LOM:
356 /* Default device ID is mezzanine card KX/KX4 */
357 media_type = ixgbe_media_type_backplane;
358 break;
359 case IXGBE_DEV_ID_82599_SFP:
360 case IXGBE_DEV_ID_82599_SFP_FCOE:
361 case IXGBE_DEV_ID_82599_SFP_EM:
362 media_type = ixgbe_media_type_fiber;
363 break;
364 case IXGBE_DEV_ID_82599_CX4:
365 media_type = ixgbe_media_type_cx4;
366 break;
367 case IXGBE_DEV_ID_82599_T3_LOM:
368 media_type = ixgbe_media_type_copper;
369 break;
370 default:
371 media_type = ixgbe_media_type_unknown;
372 break;
373 }
374 out:
375 return media_type;
376 }
377
378 /**
379 * ixgbe_start_mac_link_82599 - Setup MAC link settings
380 * @hw: pointer to hardware structure
381 * @autoneg_wait_to_complete: true when waiting for completion is needed
382 *
383 * Configures link settings based on values in the ixgbe_hw struct.
384 * Restarts the link. Performs autonegotiation if needed.
385 **/
386 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
387 bool autoneg_wait_to_complete)
388 {
389 u32 autoc_reg;
390 u32 links_reg;
391 u32 i;
392 s32 status = 0;
393
394 /* Restart link */
395 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
396 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
397 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
398
399 /* Only poll for autoneg to complete if specified to do so */
400 if (autoneg_wait_to_complete) {
401 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
402 IXGBE_AUTOC_LMS_KX4_KX_KR ||
403 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
404 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
405 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
406 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
407 links_reg = 0; /* Just in case Autoneg time = 0 */
408 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
409 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
410 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
411 break;
412 msleep(100);
413 }
414 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
415 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
416 hw_dbg(hw, "Autoneg did not complete.\n");
417 }
418 }
419 }
420
421 /* Add delay to filter out noises during initial link setup */
422 msleep(50);
423
424 return status;
425 }
426
427 /**
428 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
429 * @hw: pointer to hardware structure
430 *
431 * The base drivers may require better control over SFP+ module
432 * PHY states. This includes selectively shutting down the Tx
433 * laser on the PHY, effectively halting physical link.
434 **/
435 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
436 {
437 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
438
439 /* Disable tx laser; allow 100us to go dark per spec */
440 esdp_reg |= IXGBE_ESDP_SDP3;
441 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
442 IXGBE_WRITE_FLUSH(hw);
443 udelay(100);
444 }
445
446 /**
447 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
448 * @hw: pointer to hardware structure
449 *
450 * The base drivers may require better control over SFP+ module
451 * PHY states. This includes selectively turning on the Tx
452 * laser on the PHY, effectively starting physical link.
453 **/
454 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
455 {
456 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
457
458 /* Enable tx laser; allow 100ms to light up */
459 esdp_reg &= ~IXGBE_ESDP_SDP3;
460 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
461 IXGBE_WRITE_FLUSH(hw);
462 msleep(100);
463 }
464
465 /**
466 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
467 * @hw: pointer to hardware structure
468 *
469 * When the driver changes the link speeds that it can support,
470 * it sets autotry_restart to true to indicate that we need to
471 * initiate a new autotry session with the link partner. To do
472 * so, we set the speed then disable and re-enable the tx laser, to
473 * alert the link partner that it also needs to restart autotry on its
474 * end. This is consistent with true clause 37 autoneg, which also
475 * involves a loss of signal.
476 **/
477 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
478 {
479 if (hw->mac.autotry_restart) {
480 ixgbe_disable_tx_laser_multispeed_fiber(hw);
481 ixgbe_enable_tx_laser_multispeed_fiber(hw);
482 hw->mac.autotry_restart = false;
483 }
484 }
485
486 /**
487 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
488 * @hw: pointer to hardware structure
489 * @speed: new link speed
490 * @autoneg: true if autonegotiation enabled
491 * @autoneg_wait_to_complete: true when waiting for completion is needed
492 *
493 * Set the link speed in the AUTOC register and restarts link.
494 **/
495 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
496 ixgbe_link_speed speed,
497 bool autoneg,
498 bool autoneg_wait_to_complete)
499 {
500 s32 status = 0;
501 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
502 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
503 u32 speedcnt = 0;
504 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
505 u32 i = 0;
506 bool link_up = false;
507 bool negotiation;
508
509 /* Mask off requested but non-supported speeds */
510 status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
511 &negotiation);
512 if (status != 0)
513 return status;
514
515 speed &= link_speed;
516
517 /*
518 * Try each speed one by one, highest priority first. We do this in
519 * software because 10gb fiber doesn't support speed autonegotiation.
520 */
521 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
522 speedcnt++;
523 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
524
525 /* If we already have link at this speed, just jump out */
526 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
527 false);
528 if (status != 0)
529 return status;
530
531 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
532 goto out;
533
534 /* Set the module link speed */
535 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
536 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
537 IXGBE_WRITE_FLUSH(hw);
538
539 /* Allow module to change analog characteristics (1G->10G) */
540 msleep(40);
541
542 status = ixgbe_setup_mac_link_82599(hw,
543 IXGBE_LINK_SPEED_10GB_FULL,
544 autoneg,
545 autoneg_wait_to_complete);
546 if (status != 0)
547 return status;
548
549 /* Flap the tx laser if it has not already been done */
550 hw->mac.ops.flap_tx_laser(hw);
551
552 /*
553 * Wait for the controller to acquire link. Per IEEE 802.3ap,
554 * Section 73.10.2, we may have to wait up to 500ms if KR is
555 * attempted. 82599 uses the same timing for 10g SFI.
556 */
557 for (i = 0; i < 5; i++) {
558 /* Wait for the link partner to also set speed */
559 msleep(100);
560
561 /* If we have link, just jump out */
562 status = hw->mac.ops.check_link(hw, &link_speed,
563 &link_up, false);
564 if (status != 0)
565 return status;
566
567 if (link_up)
568 goto out;
569 }
570 }
571
572 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
573 speedcnt++;
574 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
575 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
576
577 /* If we already have link at this speed, just jump out */
578 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
579 false);
580 if (status != 0)
581 return status;
582
583 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
584 goto out;
585
586 /* Set the module link speed */
587 esdp_reg &= ~IXGBE_ESDP_SDP5;
588 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
589 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
590 IXGBE_WRITE_FLUSH(hw);
591
592 /* Allow module to change analog characteristics (10G->1G) */
593 msleep(40);
594
595 status = ixgbe_setup_mac_link_82599(hw,
596 IXGBE_LINK_SPEED_1GB_FULL,
597 autoneg,
598 autoneg_wait_to_complete);
599 if (status != 0)
600 return status;
601
602 /* Flap the tx laser if it has not already been done */
603 hw->mac.ops.flap_tx_laser(hw);
604
605 /* Wait for the link partner to also set speed */
606 msleep(100);
607
608 /* If we have link, just jump out */
609 status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
610 false);
611 if (status != 0)
612 return status;
613
614 if (link_up)
615 goto out;
616 }
617
618 /*
619 * We didn't get link. Configure back to the highest speed we tried,
620 * (if there was more than one). We call ourselves back with just the
621 * single highest speed that the user requested.
622 */
623 if (speedcnt > 1)
624 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
625 highest_link_speed,
626 autoneg,
627 autoneg_wait_to_complete);
628
629 out:
630 /* Set autoneg_advertised value based on input link speed */
631 hw->phy.autoneg_advertised = 0;
632
633 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
634 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
635
636 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
637 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
638
639 return status;
640 }
641
642 /**
643 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
644 * @hw: pointer to hardware structure
645 * @speed: new link speed
646 * @autoneg: true if autonegotiation enabled
647 * @autoneg_wait_to_complete: true when waiting for completion is needed
648 *
649 * Implements the Intel SmartSpeed algorithm.
650 **/
651 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
652 ixgbe_link_speed speed, bool autoneg,
653 bool autoneg_wait_to_complete)
654 {
655 s32 status = 0;
656 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
657 s32 i, j;
658 bool link_up = false;
659 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
660
661 /* Set autoneg_advertised value based on input link speed */
662 hw->phy.autoneg_advertised = 0;
663
664 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
665 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
666
667 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
668 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
669
670 if (speed & IXGBE_LINK_SPEED_100_FULL)
671 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
672
673 /*
674 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
675 * autoneg advertisement if link is unable to be established at the
676 * highest negotiated rate. This can sometimes happen due to integrity
677 * issues with the physical media connection.
678 */
679
680 /* First, try to get link with full advertisement */
681 hw->phy.smart_speed_active = false;
682 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
683 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
684 autoneg_wait_to_complete);
685 if (status != 0)
686 goto out;
687
688 /*
689 * Wait for the controller to acquire link. Per IEEE 802.3ap,
690 * Section 73.10.2, we may have to wait up to 500ms if KR is
691 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
692 * Table 9 in the AN MAS.
693 */
694 for (i = 0; i < 5; i++) {
695 mdelay(100);
696
697 /* If we have link, just jump out */
698 status = hw->mac.ops.check_link(hw, &link_speed,
699 &link_up, false);
700 if (status != 0)
701 goto out;
702
703 if (link_up)
704 goto out;
705 }
706 }
707
708 /*
709 * We didn't get link. If we advertised KR plus one of KX4/KX
710 * (or BX4/BX), then disable KR and try again.
711 */
712 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
713 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
714 goto out;
715
716 /* Turn SmartSpeed on to disable KR support */
717 hw->phy.smart_speed_active = true;
718 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
719 autoneg_wait_to_complete);
720 if (status != 0)
721 goto out;
722
723 /*
724 * Wait for the controller to acquire link. 600ms will allow for
725 * the AN link_fail_inhibit_timer as well for multiple cycles of
726 * parallel detect, both 10g and 1g. This allows for the maximum
727 * connect attempts as defined in the AN MAS table 73-7.
728 */
729 for (i = 0; i < 6; i++) {
730 mdelay(100);
731
732 /* If we have link, just jump out */
733 status = hw->mac.ops.check_link(hw, &link_speed,
734 &link_up, false);
735 if (status != 0)
736 goto out;
737
738 if (link_up)
739 goto out;
740 }
741
742 /* We didn't get link. Turn SmartSpeed back off. */
743 hw->phy.smart_speed_active = false;
744 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
745 autoneg_wait_to_complete);
746
747 out:
748 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
749 hw_dbg(hw, "Smartspeed has downgraded the link speed from "
750 "the maximum advertised\n");
751 return status;
752 }
753
754 /**
755 * ixgbe_setup_mac_link_82599 - Set MAC link speed
756 * @hw: pointer to hardware structure
757 * @speed: new link speed
758 * @autoneg: true if autonegotiation enabled
759 * @autoneg_wait_to_complete: true when waiting for completion is needed
760 *
761 * Set the link speed in the AUTOC register and restarts link.
762 **/
763 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
764 ixgbe_link_speed speed, bool autoneg,
765 bool autoneg_wait_to_complete)
766 {
767 s32 status = 0;
768 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
769 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
770 u32 start_autoc = autoc;
771 u32 orig_autoc = 0;
772 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
773 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
774 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
775 u32 links_reg;
776 u32 i;
777 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
778
779 /* Check to see if speed passed in is supported. */
780 hw->mac.ops.get_link_capabilities(hw, &link_capabilities, &autoneg);
781 if (status != 0)
782 goto out;
783
784 speed &= link_capabilities;
785
786 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
787 status = IXGBE_ERR_LINK_SETUP;
788 goto out;
789 }
790
791 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
792 if (hw->mac.orig_link_settings_stored)
793 orig_autoc = hw->mac.orig_autoc;
794 else
795 orig_autoc = autoc;
796
797 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
798 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
799 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
800 /* Set KX4/KX/KR support according to speed requested */
801 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
802 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
803 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
804 autoc |= IXGBE_AUTOC_KX4_SUPP;
805 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
806 (hw->phy.smart_speed_active == false))
807 autoc |= IXGBE_AUTOC_KR_SUPP;
808 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
809 autoc |= IXGBE_AUTOC_KX_SUPP;
810 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
811 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
812 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
813 /* Switch from 1G SFI to 10G SFI if requested */
814 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
815 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
816 autoc &= ~IXGBE_AUTOC_LMS_MASK;
817 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
818 }
819 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
820 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
821 /* Switch from 10G SFI to 1G SFI if requested */
822 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
823 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
824 autoc &= ~IXGBE_AUTOC_LMS_MASK;
825 if (autoneg)
826 autoc |= IXGBE_AUTOC_LMS_1G_AN;
827 else
828 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
829 }
830 }
831
832 if (autoc != start_autoc) {
833 /* Restart link */
834 autoc |= IXGBE_AUTOC_AN_RESTART;
835 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
836
837 /* Only poll for autoneg to complete if specified to do so */
838 if (autoneg_wait_to_complete) {
839 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
840 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
841 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
842 links_reg = 0; /*Just in case Autoneg time=0*/
843 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
844 links_reg =
845 IXGBE_READ_REG(hw, IXGBE_LINKS);
846 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
847 break;
848 msleep(100);
849 }
850 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
851 status =
852 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
853 hw_dbg(hw, "Autoneg did not "
854 "complete.\n");
855 }
856 }
857 }
858
859 /* Add delay to filter out noises during initial link setup */
860 msleep(50);
861 }
862
863 out:
864 return status;
865 }
866
867 /**
868 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
869 * @hw: pointer to hardware structure
870 * @speed: new link speed
871 * @autoneg: true if autonegotiation enabled
872 * @autoneg_wait_to_complete: true if waiting is needed to complete
873 *
874 * Restarts link on PHY and MAC based on settings passed in.
875 **/
876 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
877 ixgbe_link_speed speed,
878 bool autoneg,
879 bool autoneg_wait_to_complete)
880 {
881 s32 status;
882
883 /* Setup the PHY according to input speed */
884 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
885 autoneg_wait_to_complete);
886 /* Set up MAC */
887 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
888
889 return status;
890 }
891
892 /**
893 * ixgbe_reset_hw_82599 - Perform hardware reset
894 * @hw: pointer to hardware structure
895 *
896 * Resets the hardware by resetting the transmit and receive units, masks
897 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
898 * reset.
899 **/
900 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
901 {
902 s32 status = 0;
903 u32 ctrl;
904 u32 i;
905 u32 autoc;
906 u32 autoc2;
907
908 /* Call adapter stop to disable tx/rx and clear interrupts */
909 hw->mac.ops.stop_adapter(hw);
910
911 /* PHY ops must be identified and initialized prior to reset */
912
913 /* Identify PHY and related function pointers */
914 status = hw->phy.ops.init(hw);
915
916 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
917 goto reset_hw_out;
918
919 /* Setup SFP module if there is one present. */
920 if (hw->phy.sfp_setup_needed) {
921 status = hw->mac.ops.setup_sfp(hw);
922 hw->phy.sfp_setup_needed = false;
923 }
924
925 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
926 goto reset_hw_out;
927
928 /* Reset PHY */
929 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
930 hw->phy.ops.reset(hw);
931
932 /*
933 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
934 * access and verify no pending requests before reset
935 */
936 ixgbe_disable_pcie_master(hw);
937
938 mac_reset_top:
939 /*
940 * Issue global reset to the MAC. This needs to be a SW reset.
941 * If link reset is used, it might reset the MAC when mng is using it
942 */
943 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
944 IXGBE_WRITE_REG(hw, IXGBE_CTRL, (ctrl | IXGBE_CTRL_RST));
945 IXGBE_WRITE_FLUSH(hw);
946
947 /* Poll for reset bit to self-clear indicating reset is complete */
948 for (i = 0; i < 10; i++) {
949 udelay(1);
950 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
951 if (!(ctrl & IXGBE_CTRL_RST))
952 break;
953 }
954 if (ctrl & IXGBE_CTRL_RST) {
955 status = IXGBE_ERR_RESET_FAILED;
956 hw_dbg(hw, "Reset polling failed to complete.\n");
957 }
958
959 /*
960 * Double resets are required for recovery from certain error
961 * conditions. Between resets, it is necessary to stall to allow time
962 * for any pending HW events to complete. We use 1usec since that is
963 * what is needed for ixgbe_disable_pcie_master(). The second reset
964 * then clears out any effects of those events.
965 */
966 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
967 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
968 udelay(1);
969 goto mac_reset_top;
970 }
971
972 msleep(50);
973
974 /*
975 * Store the original AUTOC/AUTOC2 values if they have not been
976 * stored off yet. Otherwise restore the stored original
977 * values since the reset operation sets back to defaults.
978 */
979 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
980 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
981 if (hw->mac.orig_link_settings_stored == false) {
982 hw->mac.orig_autoc = autoc;
983 hw->mac.orig_autoc2 = autoc2;
984 hw->mac.orig_link_settings_stored = true;
985 } else {
986 if (autoc != hw->mac.orig_autoc)
987 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
988 IXGBE_AUTOC_AN_RESTART));
989
990 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
991 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
992 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
993 autoc2 |= (hw->mac.orig_autoc2 &
994 IXGBE_AUTOC2_UPPER_MASK);
995 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
996 }
997 }
998
999 /* Store the permanent mac address */
1000 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1001
1002 /*
1003 * Store MAC address from RAR0, clear receive address registers, and
1004 * clear the multicast table. Also reset num_rar_entries to 128,
1005 * since we modify this value when programming the SAN MAC address.
1006 */
1007 hw->mac.num_rar_entries = 128;
1008 hw->mac.ops.init_rx_addrs(hw);
1009
1010 /* Store the permanent SAN mac address */
1011 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1012
1013 /* Add the SAN MAC address to the RAR only if it's a valid address */
1014 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1015 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1016 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1017
1018 /* Reserve the last RAR for the SAN MAC address */
1019 hw->mac.num_rar_entries--;
1020 }
1021
1022 /* Store the alternative WWNN/WWPN prefix */
1023 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1024 &hw->mac.wwpn_prefix);
1025
1026 reset_hw_out:
1027 return status;
1028 }
1029
1030 /**
1031 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1032 * @hw: pointer to hardware structure
1033 **/
1034 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1035 {
1036 int i;
1037 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1038 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1039
1040 /*
1041 * Before starting reinitialization process,
1042 * FDIRCMD.CMD must be zero.
1043 */
1044 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1045 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1046 IXGBE_FDIRCMD_CMD_MASK))
1047 break;
1048 udelay(10);
1049 }
1050 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1051 hw_dbg(hw, "Flow Director previous command isn't complete, "
1052 "aborting table re-initialization.\n");
1053 return IXGBE_ERR_FDIR_REINIT_FAILED;
1054 }
1055
1056 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1057 IXGBE_WRITE_FLUSH(hw);
1058 /*
1059 * 82599 adapters flow director init flow cannot be restarted,
1060 * Workaround 82599 silicon errata by performing the following steps
1061 * before re-writing the FDIRCTRL control register with the same value.
1062 * - write 1 to bit 8 of FDIRCMD register &
1063 * - write 0 to bit 8 of FDIRCMD register
1064 */
1065 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1066 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1067 IXGBE_FDIRCMD_CLEARHT));
1068 IXGBE_WRITE_FLUSH(hw);
1069 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1070 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1071 ~IXGBE_FDIRCMD_CLEARHT));
1072 IXGBE_WRITE_FLUSH(hw);
1073 /*
1074 * Clear FDIR Hash register to clear any leftover hashes
1075 * waiting to be programmed.
1076 */
1077 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1078 IXGBE_WRITE_FLUSH(hw);
1079
1080 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1081 IXGBE_WRITE_FLUSH(hw);
1082
1083 /* Poll init-done after we write FDIRCTRL register */
1084 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1085 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1086 IXGBE_FDIRCTRL_INIT_DONE)
1087 break;
1088 udelay(10);
1089 }
1090 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1091 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1092 return IXGBE_ERR_FDIR_REINIT_FAILED;
1093 }
1094
1095 /* Clear FDIR statistics registers (read to clear) */
1096 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1097 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1098 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1099 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1100 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1101
1102 return 0;
1103 }
1104
1105 /**
1106 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1107 * @hw: pointer to hardware structure
1108 * @pballoc: which mode to allocate filters with
1109 **/
1110 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 pballoc)
1111 {
1112 u32 fdirctrl = 0;
1113 u32 pbsize;
1114 int i;
1115
1116 /*
1117 * Before enabling Flow Director, the Rx Packet Buffer size
1118 * must be reduced. The new value is the current size minus
1119 * flow director memory usage size.
1120 */
1121 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1122 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1123 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1124
1125 /*
1126 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1127 * initialized to zero for non DCB mode otherwise actual total RX PB
1128 * would be bigger than programmed and filter space would run into
1129 * the PB 0 region.
1130 */
1131 for (i = 1; i < 8; i++)
1132 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1133
1134 /* Send interrupt when 64 filters are left */
1135 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1136
1137 /* Set the maximum length per hash bucket to 0xA filters */
1138 fdirctrl |= 0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT;
1139
1140 switch (pballoc) {
1141 case IXGBE_FDIR_PBALLOC_64K:
1142 /* 8k - 1 signature filters */
1143 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1144 break;
1145 case IXGBE_FDIR_PBALLOC_128K:
1146 /* 16k - 1 signature filters */
1147 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1148 break;
1149 case IXGBE_FDIR_PBALLOC_256K:
1150 /* 32k - 1 signature filters */
1151 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1152 break;
1153 default:
1154 /* bad value */
1155 return IXGBE_ERR_CONFIG;
1156 };
1157
1158 /* Move the flexible bytes to use the ethertype - shift 6 words */
1159 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1160
1161
1162 /* Prime the keys for hashing */
1163 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1164 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1165
1166 /*
1167 * Poll init-done after we write the register. Estimated times:
1168 * 10G: PBALLOC = 11b, timing is 60us
1169 * 1G: PBALLOC = 11b, timing is 600us
1170 * 100M: PBALLOC = 11b, timing is 6ms
1171 *
1172 * Multiple these timings by 4 if under full Rx load
1173 *
1174 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1175 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1176 * this might not finish in our poll time, but we can live with that
1177 * for now.
1178 */
1179 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1180 IXGBE_WRITE_FLUSH(hw);
1181 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1182 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1183 IXGBE_FDIRCTRL_INIT_DONE)
1184 break;
1185 usleep_range(1000, 2000);
1186 }
1187 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1188 hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
1189
1190 return 0;
1191 }
1192
1193 /**
1194 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1195 * @hw: pointer to hardware structure
1196 * @pballoc: which mode to allocate filters with
1197 **/
1198 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 pballoc)
1199 {
1200 u32 fdirctrl = 0;
1201 u32 pbsize;
1202 int i;
1203
1204 /*
1205 * Before enabling Flow Director, the Rx Packet Buffer size
1206 * must be reduced. The new value is the current size minus
1207 * flow director memory usage size.
1208 */
1209 pbsize = (1 << (IXGBE_FDIR_PBALLOC_SIZE_SHIFT + pballoc));
1210 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
1211 (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
1212
1213 /*
1214 * The defaults in the HW for RX PB 1-7 are not zero and so should be
1215 * initialized to zero for non DCB mode otherwise actual total RX PB
1216 * would be bigger than programmed and filter space would run into
1217 * the PB 0 region.
1218 */
1219 for (i = 1; i < 8; i++)
1220 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
1221
1222 /* Send interrupt when 64 filters are left */
1223 fdirctrl |= 4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT;
1224
1225 /* Initialize the drop queue to Rx queue 127 */
1226 fdirctrl |= (127 << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
1227
1228 switch (pballoc) {
1229 case IXGBE_FDIR_PBALLOC_64K:
1230 /* 2k - 1 perfect filters */
1231 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
1232 break;
1233 case IXGBE_FDIR_PBALLOC_128K:
1234 /* 4k - 1 perfect filters */
1235 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
1236 break;
1237 case IXGBE_FDIR_PBALLOC_256K:
1238 /* 8k - 1 perfect filters */
1239 fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
1240 break;
1241 default:
1242 /* bad value */
1243 return IXGBE_ERR_CONFIG;
1244 };
1245
1246 /* Turn perfect match filtering on */
1247 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
1248 fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
1249
1250 /* Move the flexible bytes to use the ethertype - shift 6 words */
1251 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT);
1252
1253 /* Prime the keys for hashing */
1254 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1255 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1256
1257 /*
1258 * Poll init-done after we write the register. Estimated times:
1259 * 10G: PBALLOC = 11b, timing is 60us
1260 * 1G: PBALLOC = 11b, timing is 600us
1261 * 100M: PBALLOC = 11b, timing is 6ms
1262 *
1263 * Multiple these timings by 4 if under full Rx load
1264 *
1265 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1266 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1267 * this might not finish in our poll time, but we can live with that
1268 * for now.
1269 */
1270
1271 /* Set the maximum length per hash bucket to 0xA filters */
1272 fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT);
1273
1274 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1275 IXGBE_WRITE_FLUSH(hw);
1276 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1277 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1278 IXGBE_FDIRCTRL_INIT_DONE)
1279 break;
1280 usleep_range(1000, 2000);
1281 }
1282 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1283 hw_dbg(hw, "Flow Director Perfect poll time exceeded!\n");
1284
1285 return 0;
1286 }
1287
1288
1289 /**
1290 * ixgbe_atr_compute_hash_82599 - Compute the hashes for SW ATR
1291 * @stream: input bitstream to compute the hash on
1292 * @key: 32-bit hash key
1293 **/
1294 static u32 ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
1295 u32 key)
1296 {
1297 /*
1298 * The algorithm is as follows:
1299 * Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
1300 * where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
1301 * and A[n] x B[n] is bitwise AND between same length strings
1302 *
1303 * K[n] is 16 bits, defined as:
1304 * for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
1305 * for n modulo 32 < 15, K[n] =
1306 * K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
1307 *
1308 * S[n] is 16 bits, defined as:
1309 * for n >= 15, S[n] = S[n:n - 15]
1310 * for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
1311 *
1312 * To simplify for programming, the algorithm is implemented
1313 * in software this way:
1314 *
1315 * key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
1316 *
1317 * for (i = 0; i < 352; i+=32)
1318 * hi_hash_dword[31:0] ^= Stream[(i+31):i];
1319 *
1320 * lo_hash_dword[15:0] ^= Stream[15:0];
1321 * lo_hash_dword[15:0] ^= hi_hash_dword[31:16];
1322 * lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
1323 *
1324 * hi_hash_dword[31:0] ^= Stream[351:320];
1325 *
1326 * if(key[0])
1327 * hash[15:0] ^= Stream[15:0];
1328 *
1329 * for (i = 0; i < 16; i++) {
1330 * if (key[i])
1331 * hash[15:0] ^= lo_hash_dword[(i+15):i];
1332 * if (key[i + 16])
1333 * hash[15:0] ^= hi_hash_dword[(i+15):i];
1334 * }
1335 *
1336 */
1337 __be32 common_hash_dword = 0;
1338 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1339 u32 hash_result = 0;
1340 u8 i;
1341
1342 /* record the flow_vm_vlan bits as they are a key part to the hash */
1343 flow_vm_vlan = ntohl(atr_input->dword_stream[0]);
1344
1345 /* generate common hash dword */
1346 for (i = 10; i; i -= 2)
1347 common_hash_dword ^= atr_input->dword_stream[i] ^
1348 atr_input->dword_stream[i - 1];
1349
1350 hi_hash_dword = ntohl(common_hash_dword);
1351
1352 /* low dword is word swapped version of common */
1353 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1354
1355 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1356 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1357
1358 /* Process bits 0 and 16 */
1359 if (key & 0x0001) hash_result ^= lo_hash_dword;
1360 if (key & 0x00010000) hash_result ^= hi_hash_dword;
1361
1362 /*
1363 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1364 * delay this because bit 0 of the stream should not be processed
1365 * so we do not add the vlan until after bit 0 was processed
1366 */
1367 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1368
1369
1370 /* process the remaining 30 bits in the key 2 bits at a time */
1371 for (i = 15; i; i-- ) {
1372 if (key & (0x0001 << i)) hash_result ^= lo_hash_dword >> i;
1373 if (key & (0x00010000 << i)) hash_result ^= hi_hash_dword >> i;
1374 }
1375
1376 return hash_result & IXGBE_ATR_HASH_MASK;
1377 }
1378
1379 /*
1380 * These defines allow us to quickly generate all of the necessary instructions
1381 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1382 * for values 0 through 15
1383 */
1384 #define IXGBE_ATR_COMMON_HASH_KEY \
1385 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1386 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1387 do { \
1388 u32 n = (_n); \
1389 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1390 common_hash ^= lo_hash_dword >> n; \
1391 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1392 bucket_hash ^= lo_hash_dword >> n; \
1393 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1394 sig_hash ^= lo_hash_dword << (16 - n); \
1395 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1396 common_hash ^= hi_hash_dword >> n; \
1397 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1398 bucket_hash ^= hi_hash_dword >> n; \
1399 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1400 sig_hash ^= hi_hash_dword << (16 - n); \
1401 } while (0);
1402
1403 /**
1404 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1405 * @stream: input bitstream to compute the hash on
1406 *
1407 * This function is almost identical to the function above but contains
1408 * several optomizations such as unwinding all of the loops, letting the
1409 * compiler work out all of the conditional ifs since the keys are static
1410 * defines, and computing two keys at once since the hashed dword stream
1411 * will be the same for both keys.
1412 **/
1413 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1414 union ixgbe_atr_hash_dword common)
1415 {
1416 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1417 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1418
1419 /* record the flow_vm_vlan bits as they are a key part to the hash */
1420 flow_vm_vlan = ntohl(input.dword);
1421
1422 /* generate common hash dword */
1423 hi_hash_dword = ntohl(common.dword);
1424
1425 /* low dword is word swapped version of common */
1426 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1427
1428 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1429 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1430
1431 /* Process bits 0 and 16 */
1432 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1433
1434 /*
1435 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1436 * delay this because bit 0 of the stream should not be processed
1437 * so we do not add the vlan until after bit 0 was processed
1438 */
1439 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1440
1441 /* Process remaining 30 bit of the key */
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1456 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1457
1458 /* combine common_hash result with signature and bucket hashes */
1459 bucket_hash ^= common_hash;
1460 bucket_hash &= IXGBE_ATR_HASH_MASK;
1461
1462 sig_hash ^= common_hash << 16;
1463 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1464
1465 /* return completed signature hash */
1466 return sig_hash ^ bucket_hash;
1467 }
1468
1469 /**
1470 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1471 * @hw: pointer to hardware structure
1472 * @input: unique input dword
1473 * @common: compressed common input dword
1474 * @queue: queue index to direct traffic to
1475 **/
1476 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1477 union ixgbe_atr_hash_dword input,
1478 union ixgbe_atr_hash_dword common,
1479 u8 queue)
1480 {
1481 u64 fdirhashcmd;
1482 u32 fdircmd;
1483
1484 /*
1485 * Get the flow_type in order to program FDIRCMD properly
1486 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1487 */
1488 switch (input.formatted.flow_type) {
1489 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1490 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1491 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1492 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1493 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1494 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1495 break;
1496 default:
1497 hw_dbg(hw, " Error on flow type input\n");
1498 return IXGBE_ERR_CONFIG;
1499 }
1500
1501 /* configure FDIRCMD register */
1502 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1503 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1504 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1505 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1506
1507 /*
1508 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1509 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1510 */
1511 fdirhashcmd = (u64)fdircmd << 32;
1512 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1513
1514 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1515
1516 hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1517
1518 return 0;
1519 }
1520
1521 /**
1522 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1523 * @input_mask: mask to be bit swapped
1524 *
1525 * The source and destination port masks for flow director are bit swapped
1526 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1527 * generate a correctly swapped value we need to bit swap the mask and that
1528 * is what is accomplished by this function.
1529 **/
1530 static u32 ixgbe_get_fdirtcpm_82599(struct ixgbe_atr_input_masks *input_masks)
1531 {
1532 u32 mask = ntohs(input_masks->dst_port_mask);
1533 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1534 mask |= ntohs(input_masks->src_port_mask);
1535 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1536 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1537 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1538 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1539 }
1540
1541 /*
1542 * These two macros are meant to address the fact that we have registers
1543 * that are either all or in part big-endian. As a result on big-endian
1544 * systems we will end up byte swapping the value to little-endian before
1545 * it is byte swapped again and written to the hardware in the original
1546 * big-endian format.
1547 */
1548 #define IXGBE_STORE_AS_BE32(_value) \
1549 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1550 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1551
1552 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1553 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
1554
1555 #define IXGBE_STORE_AS_BE16(_value) \
1556 (((u16)(_value) >> 8) | ((u16)(_value) << 8))
1557
1558 /**
1559 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1560 * @hw: pointer to hardware structure
1561 * @input: input bitstream
1562 * @input_masks: bitwise masks for relevant fields
1563 * @soft_id: software index into the silicon hash tables for filter storage
1564 * @queue: queue index to direct traffic to
1565 *
1566 * Note that the caller to this function must lock before calling, since the
1567 * hardware writes must be protected from one another.
1568 **/
1569 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1570 union ixgbe_atr_input *input,
1571 struct ixgbe_atr_input_masks *input_masks,
1572 u16 soft_id, u8 queue)
1573 {
1574 u32 fdirhash;
1575 u32 fdircmd;
1576 u32 fdirport, fdirtcpm;
1577 u32 fdirvlan;
1578 /* start with VLAN, flex bytes, VM pool, and IPv6 destination masked */
1579 u32 fdirm = IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP | IXGBE_FDIRM_FLEX |
1580 IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6;
1581
1582 /*
1583 * Check flow_type formatting, and bail out before we touch the hardware
1584 * if there's a configuration issue
1585 */
1586 switch (input->formatted.flow_type) {
1587 case IXGBE_ATR_FLOW_TYPE_IPV4:
1588 /* use the L4 protocol mask for raw IPv4/IPv6 traffic */
1589 fdirm |= IXGBE_FDIRM_L4P;
1590 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1591 if (input_masks->dst_port_mask || input_masks->src_port_mask) {
1592 hw_dbg(hw, " Error on src/dst port mask\n");
1593 return IXGBE_ERR_CONFIG;
1594 }
1595 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1596 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1597 break;
1598 default:
1599 hw_dbg(hw, " Error on flow type input\n");
1600 return IXGBE_ERR_CONFIG;
1601 }
1602
1603 /*
1604 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1605 * are zero, then assume a full mask for that field. Also assume that
1606 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1607 * cannot be masked out in this implementation.
1608 *
1609 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1610 * point in time.
1611 */
1612
1613 /* Program FDIRM */
1614 switch (ntohs(input_masks->vlan_id_mask) & 0xEFFF) {
1615 case 0xEFFF:
1616 /* Unmask VLAN ID - bit 0 and fall through to unmask prio */
1617 fdirm &= ~IXGBE_FDIRM_VLANID;
1618 case 0xE000:
1619 /* Unmask VLAN prio - bit 1 */
1620 fdirm &= ~IXGBE_FDIRM_VLANP;
1621 break;
1622 case 0x0FFF:
1623 /* Unmask VLAN ID - bit 0 */
1624 fdirm &= ~IXGBE_FDIRM_VLANID;
1625 break;
1626 case 0x0000:
1627 /* do nothing, vlans already masked */
1628 break;
1629 default:
1630 hw_dbg(hw, " Error on VLAN mask\n");
1631 return IXGBE_ERR_CONFIG;
1632 }
1633
1634 if (input_masks->flex_mask & 0xFFFF) {
1635 if ((input_masks->flex_mask & 0xFFFF) != 0xFFFF) {
1636 hw_dbg(hw, " Error on flexible byte mask\n");
1637 return IXGBE_ERR_CONFIG;
1638 }
1639 /* Unmask Flex Bytes - bit 4 */
1640 fdirm &= ~IXGBE_FDIRM_FLEX;
1641 }
1642
1643 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1644 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1645
1646 /* store the TCP/UDP port masks, bit reversed from port layout */
1647 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_masks);
1648
1649 /* write both the same so that UDP and TCP use the same mask */
1650 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1651 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1652
1653 /* store source and destination IP masks (big-enian) */
1654 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1655 ~input_masks->src_ip_mask[0]);
1656 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1657 ~input_masks->dst_ip_mask[0]);
1658
1659 /* Apply masks to input data */
1660 input->formatted.vlan_id &= input_masks->vlan_id_mask;
1661 input->formatted.flex_bytes &= input_masks->flex_mask;
1662 input->formatted.src_port &= input_masks->src_port_mask;
1663 input->formatted.dst_port &= input_masks->dst_port_mask;
1664 input->formatted.src_ip[0] &= input_masks->src_ip_mask[0];
1665 input->formatted.dst_ip[0] &= input_masks->dst_ip_mask[0];
1666
1667 /* record vlan (little-endian) and flex_bytes(big-endian) */
1668 fdirvlan =
1669 IXGBE_STORE_AS_BE16(ntohs(input->formatted.flex_bytes));
1670 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1671 fdirvlan |= ntohs(input->formatted.vlan_id);
1672 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1673
1674 /* record source and destination port (little-endian)*/
1675 fdirport = ntohs(input->formatted.dst_port);
1676 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1677 fdirport |= ntohs(input->formatted.src_port);
1678 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1679
1680 /* record the first 32 bits of the destination address (big-endian) */
1681 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1682
1683 /* record the source address (big-endian) */
1684 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1685
1686 /* configure FDIRCMD register */
1687 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1688 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1689 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1690 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1691
1692 /* we only want the bucket hash so drop the upper 16 bits */
1693 fdirhash = ixgbe_atr_compute_hash_82599(input,
1694 IXGBE_ATR_BUCKET_HASH_KEY);
1695 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1696
1697 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1698 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1699
1700 return 0;
1701 }
1702
1703 /**
1704 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1705 * @hw: pointer to hardware structure
1706 * @reg: analog register to read
1707 * @val: read value
1708 *
1709 * Performs read operation to Omer analog register specified.
1710 **/
1711 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1712 {
1713 u32 core_ctl;
1714
1715 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1716 (reg << 8));
1717 IXGBE_WRITE_FLUSH(hw);
1718 udelay(10);
1719 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1720 *val = (u8)core_ctl;
1721
1722 return 0;
1723 }
1724
1725 /**
1726 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1727 * @hw: pointer to hardware structure
1728 * @reg: atlas register to write
1729 * @val: value to write
1730 *
1731 * Performs write operation to Omer analog register specified.
1732 **/
1733 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1734 {
1735 u32 core_ctl;
1736
1737 core_ctl = (reg << 8) | val;
1738 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1739 IXGBE_WRITE_FLUSH(hw);
1740 udelay(10);
1741
1742 return 0;
1743 }
1744
1745 /**
1746 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1747 * @hw: pointer to hardware structure
1748 *
1749 * Starts the hardware using the generic start_hw function
1750 * and the generation start_hw function.
1751 * Then performs revision-specific operations, if any.
1752 **/
1753 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1754 {
1755 s32 ret_val = 0;
1756
1757 ret_val = ixgbe_start_hw_generic(hw);
1758 if (ret_val != 0)
1759 goto out;
1760
1761 ret_val = ixgbe_start_hw_gen2(hw);
1762 if (ret_val != 0)
1763 goto out;
1764
1765 /* We need to run link autotry after the driver loads */
1766 hw->mac.autotry_restart = true;
1767
1768 if (ret_val == 0)
1769 ret_val = ixgbe_verify_fw_version_82599(hw);
1770 out:
1771 return ret_val;
1772 }
1773
1774 /**
1775 * ixgbe_identify_phy_82599 - Get physical layer module
1776 * @hw: pointer to hardware structure
1777 *
1778 * Determines the physical layer module found on the current adapter.
1779 * If PHY already detected, maintains current PHY type in hw struct,
1780 * otherwise executes the PHY detection routine.
1781 **/
1782 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1783 {
1784 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1785
1786 /* Detect PHY if not unknown - returns success if already detected. */
1787 status = ixgbe_identify_phy_generic(hw);
1788 if (status != 0) {
1789 /* 82599 10GBASE-T requires an external PHY */
1790 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1791 goto out;
1792 else
1793 status = ixgbe_identify_sfp_module_generic(hw);
1794 }
1795
1796 /* Set PHY type none if no PHY detected */
1797 if (hw->phy.type == ixgbe_phy_unknown) {
1798 hw->phy.type = ixgbe_phy_none;
1799 status = 0;
1800 }
1801
1802 /* Return error if SFP module has been detected but is not supported */
1803 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1804 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1805
1806 out:
1807 return status;
1808 }
1809
1810 /**
1811 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1812 * @hw: pointer to hardware structure
1813 *
1814 * Determines physical layer capabilities of the current configuration.
1815 **/
1816 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1817 {
1818 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1819 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1820 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1821 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1822 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1823 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1824 u16 ext_ability = 0;
1825 u8 comp_codes_10g = 0;
1826 u8 comp_codes_1g = 0;
1827
1828 hw->phy.ops.identify(hw);
1829
1830 switch (hw->phy.type) {
1831 case ixgbe_phy_tn:
1832 case ixgbe_phy_aq:
1833 case ixgbe_phy_cu_unknown:
1834 hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
1835 &ext_ability);
1836 if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
1837 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1838 if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
1839 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1840 if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
1841 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1842 goto out;
1843 default:
1844 break;
1845 }
1846
1847 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1848 case IXGBE_AUTOC_LMS_1G_AN:
1849 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1850 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1851 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1852 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1853 goto out;
1854 } else
1855 /* SFI mode so read SFP module */
1856 goto sfp_check;
1857 break;
1858 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1859 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
1860 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1861 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
1862 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1863 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
1864 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
1865 goto out;
1866 break;
1867 case IXGBE_AUTOC_LMS_10G_SERIAL:
1868 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
1869 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1870 goto out;
1871 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
1872 goto sfp_check;
1873 break;
1874 case IXGBE_AUTOC_LMS_KX4_KX_KR:
1875 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
1876 if (autoc & IXGBE_AUTOC_KX_SUPP)
1877 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1878 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1879 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1880 if (autoc & IXGBE_AUTOC_KR_SUPP)
1881 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
1882 goto out;
1883 break;
1884 default:
1885 goto out;
1886 break;
1887 }
1888
1889 sfp_check:
1890 /* SFP check must be done last since DA modules are sometimes used to
1891 * test KR mode - we need to id KR mode correctly before SFP module.
1892 * Call identify_sfp because the pluggable module may have changed */
1893 hw->phy.ops.identify_sfp(hw);
1894 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1895 goto out;
1896
1897 switch (hw->phy.type) {
1898 case ixgbe_phy_sfp_passive_tyco:
1899 case ixgbe_phy_sfp_passive_unknown:
1900 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1901 break;
1902 case ixgbe_phy_sfp_ftl_active:
1903 case ixgbe_phy_sfp_active_unknown:
1904 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1905 break;
1906 case ixgbe_phy_sfp_avago:
1907 case ixgbe_phy_sfp_ftl:
1908 case ixgbe_phy_sfp_intel:
1909 case ixgbe_phy_sfp_unknown:
1910 hw->phy.ops.read_i2c_eeprom(hw,
1911 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1912 hw->phy.ops.read_i2c_eeprom(hw,
1913 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1914 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1915 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1916 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1917 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1918 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1919 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1920 break;
1921 default:
1922 break;
1923 }
1924
1925 out:
1926 return physical_layer;
1927 }
1928
1929 /**
1930 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
1931 * @hw: pointer to hardware structure
1932 * @regval: register value to write to RXCTRL
1933 *
1934 * Enables the Rx DMA unit for 82599
1935 **/
1936 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
1937 {
1938 #define IXGBE_MAX_SECRX_POLL 30
1939 int i;
1940 int secrxreg;
1941
1942 /*
1943 * Workaround for 82599 silicon errata when enabling the Rx datapath.
1944 * If traffic is incoming before we enable the Rx unit, it could hang
1945 * the Rx DMA unit. Therefore, make sure the security engine is
1946 * completely disabled prior to enabling the Rx unit.
1947 */
1948 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1949 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
1950 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1951 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
1952 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
1953 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
1954 break;
1955 else
1956 /* Use interrupt-safe sleep just in case */
1957 udelay(10);
1958 }
1959
1960 /* For informational purposes only */
1961 if (i >= IXGBE_MAX_SECRX_POLL)
1962 hw_dbg(hw, "Rx unit being enabled before security "
1963 "path fully disabled. Continuing with init.\n");
1964
1965 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
1966 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
1967 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
1968 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
1969 IXGBE_WRITE_FLUSH(hw);
1970
1971 return 0;
1972 }
1973
1974 /**
1975 * ixgbe_get_device_caps_82599 - Get additional device capabilities
1976 * @hw: pointer to hardware structure
1977 * @device_caps: the EEPROM word with the extra device capabilities
1978 *
1979 * This function will read the EEPROM location for the device capabilities,
1980 * and return the word through device_caps.
1981 **/
1982 static s32 ixgbe_get_device_caps_82599(struct ixgbe_hw *hw, u16 *device_caps)
1983 {
1984 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
1985
1986 return 0;
1987 }
1988
1989 /**
1990 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
1991 * @hw: pointer to hardware structure
1992 *
1993 * Verifies that installed the firmware version is 0.6 or higher
1994 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
1995 *
1996 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
1997 * if the FW version is not supported.
1998 **/
1999 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2000 {
2001 s32 status = IXGBE_ERR_EEPROM_VERSION;
2002 u16 fw_offset, fw_ptp_cfg_offset;
2003 u16 fw_version = 0;
2004
2005 /* firmware check is only necessary for SFI devices */
2006 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2007 status = 0;
2008 goto fw_version_out;
2009 }
2010
2011 /* get the offset to the Firmware Module block */
2012 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2013
2014 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2015 goto fw_version_out;
2016
2017 /* get the offset to the Pass Through Patch Configuration block */
2018 hw->eeprom.ops.read(hw, (fw_offset +
2019 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2020 &fw_ptp_cfg_offset);
2021
2022 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2023 goto fw_version_out;
2024
2025 /* get the firmware version */
2026 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2027 IXGBE_FW_PATCH_VERSION_4),
2028 &fw_version);
2029
2030 if (fw_version > 0x5)
2031 status = 0;
2032
2033 fw_version_out:
2034 return status;
2035 }
2036
2037 /**
2038 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2039 * @hw: pointer to hardware structure
2040 *
2041 * Returns true if the LESM FW module is present and enabled. Otherwise
2042 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2043 **/
2044 static bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2045 {
2046 bool lesm_enabled = false;
2047 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2048 s32 status;
2049
2050 /* get the offset to the Firmware Module block */
2051 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2052
2053 if ((status != 0) ||
2054 (fw_offset == 0) || (fw_offset == 0xFFFF))
2055 goto out;
2056
2057 /* get the offset to the LESM Parameters block */
2058 status = hw->eeprom.ops.read(hw, (fw_offset +
2059 IXGBE_FW_LESM_PARAMETERS_PTR),
2060 &fw_lesm_param_offset);
2061
2062 if ((status != 0) ||
2063 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2064 goto out;
2065
2066 /* get the lesm state word */
2067 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2068 IXGBE_FW_LESM_STATE_1),
2069 &fw_lesm_state);
2070
2071 if ((status == 0) &&
2072 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2073 lesm_enabled = true;
2074
2075 out:
2076 return lesm_enabled;
2077 }
2078
2079 static struct ixgbe_mac_operations mac_ops_82599 = {
2080 .init_hw = &ixgbe_init_hw_generic,
2081 .reset_hw = &ixgbe_reset_hw_82599,
2082 .start_hw = &ixgbe_start_hw_82599,
2083 .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
2084 .get_media_type = &ixgbe_get_media_type_82599,
2085 .get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
2086 .enable_rx_dma = &ixgbe_enable_rx_dma_82599,
2087 .get_mac_addr = &ixgbe_get_mac_addr_generic,
2088 .get_san_mac_addr = &ixgbe_get_san_mac_addr_generic,
2089 .get_device_caps = &ixgbe_get_device_caps_82599,
2090 .get_wwn_prefix = &ixgbe_get_wwn_prefix_generic,
2091 .stop_adapter = &ixgbe_stop_adapter_generic,
2092 .get_bus_info = &ixgbe_get_bus_info_generic,
2093 .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie,
2094 .read_analog_reg8 = &ixgbe_read_analog_reg8_82599,
2095 .write_analog_reg8 = &ixgbe_write_analog_reg8_82599,
2096 .setup_link = &ixgbe_setup_mac_link_82599,
2097 .check_link = &ixgbe_check_mac_link_generic,
2098 .get_link_capabilities = &ixgbe_get_link_capabilities_82599,
2099 .led_on = &ixgbe_led_on_generic,
2100 .led_off = &ixgbe_led_off_generic,
2101 .blink_led_start = &ixgbe_blink_led_start_generic,
2102 .blink_led_stop = &ixgbe_blink_led_stop_generic,
2103 .set_rar = &ixgbe_set_rar_generic,
2104 .clear_rar = &ixgbe_clear_rar_generic,
2105 .set_vmdq = &ixgbe_set_vmdq_generic,
2106 .clear_vmdq = &ixgbe_clear_vmdq_generic,
2107 .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
2108 .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
2109 .enable_mc = &ixgbe_enable_mc_generic,
2110 .disable_mc = &ixgbe_disable_mc_generic,
2111 .clear_vfta = &ixgbe_clear_vfta_generic,
2112 .set_vfta = &ixgbe_set_vfta_generic,
2113 .fc_enable = &ixgbe_fc_enable_generic,
2114 .init_uta_tables = &ixgbe_init_uta_tables_generic,
2115 .setup_sfp = &ixgbe_setup_sfp_modules_82599,
2116 .set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing,
2117 .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
2118 .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
2119 .release_swfw_sync = &ixgbe_release_swfw_sync,
2120
2121 };
2122
2123 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
2124 .init_params = &ixgbe_init_eeprom_params_generic,
2125 .read = &ixgbe_read_eerd_generic,
2126 .write = &ixgbe_write_eeprom_generic,
2127 .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
2128 .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
2129 .update_checksum = &ixgbe_update_eeprom_checksum_generic,
2130 };
2131
2132 static struct ixgbe_phy_operations phy_ops_82599 = {
2133 .identify = &ixgbe_identify_phy_82599,
2134 .identify_sfp = &ixgbe_identify_sfp_module_generic,
2135 .init = &ixgbe_init_phy_ops_82599,
2136 .reset = &ixgbe_reset_phy_generic,
2137 .read_reg = &ixgbe_read_phy_reg_generic,
2138 .write_reg = &ixgbe_write_phy_reg_generic,
2139 .setup_link = &ixgbe_setup_phy_link_generic,
2140 .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
2141 .read_i2c_byte = &ixgbe_read_i2c_byte_generic,
2142 .write_i2c_byte = &ixgbe_write_i2c_byte_generic,
2143 .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic,
2144 .write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic,
2145 .check_overtemp = &ixgbe_tn_check_overtemp,
2146 };
2147
2148 struct ixgbe_info ixgbe_82599_info = {
2149 .mac = ixgbe_mac_82599EB,
2150 .get_invariants = &ixgbe_get_invariants_82599,
2151 .mac_ops = &mac_ops_82599,
2152 .eeprom_ops = &eeprom_ops_82599,
2153 .phy_ops = &phy_ops_82599,
2154 .mbx_ops = &mbx_ops_generic,
2155 };
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree