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ath9k: use hw->conf on ath_setcurmode()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath9k / main.c
blob699d248efc4c641ce394149223a766d14cc63362
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include "core.h"
19 #include "reg.h"
20 #include "hw.h"
21
22 #define ATH_PCI_VERSION "0.1"
23
24 static char *dev_info = "ath9k";
25
26 MODULE_AUTHOR("Atheros Communications");
27 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
28 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
29 MODULE_LICENSE("Dual BSD/GPL");
30
31 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
32 { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI */
33 { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
34 { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI */
35 { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI */
36 { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
37 { PCI_VDEVICE(ATHEROS, 0x002B) }, /* PCI-E */
38 { 0 }
39 };
40
41 static void ath_detach(struct ath_softc *sc);
42
43 /* return bus cachesize in 4B word units */
44
45 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
46 {
47 u8 u8tmp;
48
49 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
50 *csz = (int)u8tmp;
51
52 /*
53 * This check was put in to avoid "unplesant" consequences if
54 * the bootrom has not fully initialized all PCI devices.
55 * Sometimes the cache line size register is not set
56 */
57
58 if (*csz == 0)
59 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
60 }
61
62 static void ath_setcurmode(struct ath_softc *sc, struct ieee80211_conf *conf)
63 {
64 /*
65 * All protection frames are transmited at 2Mb/s for
66 * 11g, otherwise at 1Mb/s.
67 * XXX select protection rate index from rate table.
68 */
69 sc->sc_protrix = 0;
70 switch (conf->channel->band) {
71 case IEEE80211_BAND_2GHZ:
72 if (conf_is_ht20(conf))
73 sc->cur_rate_table =
74 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
75 else if (conf_is_ht40_minus(conf))
76 sc->cur_rate_table =
77 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
78 else if (conf_is_ht40_plus(conf))
79 sc->cur_rate_table =
80 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
81 else {
82 sc->sc_protrix = 1;
83 sc->cur_rate_table =
84 sc->hw_rate_table[ATH9K_MODE_11G];
85 }
86 break;
87 case IEEE80211_BAND_5GHZ:
88 if (conf_is_ht20(conf))
89 sc->cur_rate_table =
90 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
91 else if (conf_is_ht40_minus(conf))
92 sc->cur_rate_table =
93 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
94 else if (conf_is_ht40_plus(conf))
95 sc->cur_rate_table =
96 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
97 else
98 sc->cur_rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
99 break;
100 default:
101 break;
102 }
103 }
104
105 static void ath_update_txpow(struct ath_softc *sc)
106 {
107 struct ath_hal *ah = sc->sc_ah;
108 u32 txpow;
109
110 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
111 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
112 /* read back in case value is clamped */
113 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
114 sc->sc_curtxpow = txpow;
115 }
116 }
117
118 static u8 parse_mpdudensity(u8 mpdudensity)
119 {
120 /*
121 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
122 * 0 for no restriction
123 * 1 for 1/4 us
124 * 2 for 1/2 us
125 * 3 for 1 us
126 * 4 for 2 us
127 * 5 for 4 us
128 * 6 for 8 us
129 * 7 for 16 us
130 */
131 switch (mpdudensity) {
132 case 0:
133 return 0;
134 case 1:
135 case 2:
136 case 3:
137 /* Our lower layer calculations limit our precision to
138 1 microsecond */
139 return 1;
140 case 4:
141 return 2;
142 case 5:
143 return 4;
144 case 6:
145 return 8;
146 case 7:
147 return 16;
148 default:
149 return 0;
150 }
151 }
152
153 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
154 {
155 struct ath_rate_table *rate_table = NULL;
156 struct ieee80211_supported_band *sband;
157 struct ieee80211_rate *rate;
158 int i, maxrates;
159
160 switch (band) {
161 case IEEE80211_BAND_2GHZ:
162 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
163 break;
164 case IEEE80211_BAND_5GHZ:
165 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
166 break;
167 default:
168 break;
169 }
170
171 if (rate_table == NULL)
172 return;
173
174 sband = &sc->sbands[band];
175 rate = sc->rates[band];
176
177 if (rate_table->rate_cnt > ATH_RATE_MAX)
178 maxrates = ATH_RATE_MAX;
179 else
180 maxrates = rate_table->rate_cnt;
181
182 for (i = 0; i < maxrates; i++) {
183 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
184 rate[i].hw_value = rate_table->info[i].ratecode;
185 sband->n_bitrates++;
186 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
187 rate[i].bitrate / 10, rate[i].hw_value);
188 }
189 }
190
191 static int ath_setup_channels(struct ath_softc *sc)
192 {
193 struct ath_hal *ah = sc->sc_ah;
194 int nchan, i, a = 0, b = 0;
195 u8 regclassids[ATH_REGCLASSIDS_MAX];
196 u32 nregclass = 0;
197 struct ieee80211_supported_band *band_2ghz;
198 struct ieee80211_supported_band *band_5ghz;
199 struct ieee80211_channel *chan_2ghz;
200 struct ieee80211_channel *chan_5ghz;
201 struct ath9k_channel *c;
202
203 /* Fill in ah->ah_channels */
204 if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
205 regclassids, ATH_REGCLASSIDS_MAX,
206 &nregclass, CTRY_DEFAULT, false, 1)) {
207 u32 rd = ah->ah_currentRD;
208 DPRINTF(sc, ATH_DBG_FATAL,
209 "Unable to collect channel list; "
210 "regdomain likely %u country code %u\n",
211 rd, CTRY_DEFAULT);
212 return -EINVAL;
213 }
214
215 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
216 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
217 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
218 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
219
220 for (i = 0; i < nchan; i++) {
221 c = &ah->ah_channels[i];
222 if (IS_CHAN_2GHZ(c)) {
223 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
224 chan_2ghz[a].center_freq = c->channel;
225 chan_2ghz[a].max_power = c->maxTxPower;
226
227 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
228 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
229 if (c->channelFlags & CHANNEL_PASSIVE)
230 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
231
232 band_2ghz->n_channels = ++a;
233
234 DPRINTF(sc, ATH_DBG_CONFIG, "2MHz channel: %d, "
235 "channelFlags: 0x%x\n",
236 c->channel, c->channelFlags);
237 } else if (IS_CHAN_5GHZ(c)) {
238 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
239 chan_5ghz[b].center_freq = c->channel;
240 chan_5ghz[b].max_power = c->maxTxPower;
241
242 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
243 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
244 if (c->channelFlags & CHANNEL_PASSIVE)
245 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
246
247 band_5ghz->n_channels = ++b;
248
249 DPRINTF(sc, ATH_DBG_CONFIG, "5MHz channel: %d, "
250 "channelFlags: 0x%x\n",
251 c->channel, c->channelFlags);
252 }
253 }
254
255 return 0;
256 }
257
258 /*
259 * Set/change channels. If the channel is really being changed, it's done
260 * by reseting the chip. To accomplish this we must first cleanup any pending
261 * DMA, then restart stuff.
262 */
263 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
264 {
265 struct ath_hal *ah = sc->sc_ah;
266 bool fastcc = true, stopped;
267 struct ieee80211_hw *hw = sc->hw;
268
269 if (sc->sc_flags & SC_OP_INVALID)
270 return -EIO;
271
272 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
273 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
274 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
275 (sc->sc_flags & SC_OP_FULL_RESET)) {
276 int status;
277 /*
278 * This is only performed if the channel settings have
279 * actually changed.
280 *
281 * To switch channels clear any pending DMA operations;
282 * wait long enough for the RX fifo to drain, reset the
283 * hardware at the new frequency, and then re-enable
284 * the relevant bits of the h/w.
285 */
286 ath9k_hw_set_interrupts(ah, 0);
287 ath_draintxq(sc, false);
288 stopped = ath_stoprecv(sc);
289
290 /* XXX: do not flush receive queue here. We don't want
291 * to flush data frames already in queue because of
292 * changing channel. */
293
294 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
295 fastcc = false;
296
297 DPRINTF(sc, ATH_DBG_CONFIG,
298 "(%u MHz) -> (%u MHz), cflags:%x, chanwidth: %d\n",
299 sc->sc_ah->ah_curchan->channel,
300 hchan->channel, hchan->channelFlags, sc->tx_chan_width);
301
302 spin_lock_bh(&sc->sc_resetlock);
303 if (!ath9k_hw_reset(ah, hchan, sc->tx_chan_width,
304 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
305 sc->sc_ht_extprotspacing, fastcc, &status)) {
306 DPRINTF(sc, ATH_DBG_FATAL,
307 "Unable to reset channel %u (%uMhz) "
308 "flags 0x%x hal status %u\n",
309 ath9k_hw_mhz2ieee(ah, hchan->channel,
310 hchan->channelFlags),
311 hchan->channel, hchan->channelFlags, status);
312 spin_unlock_bh(&sc->sc_resetlock);
313 return -EIO;
314 }
315 spin_unlock_bh(&sc->sc_resetlock);
316
317 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
318 sc->sc_flags &= ~SC_OP_FULL_RESET;
319
320 if (ath_startrecv(sc) != 0) {
321 DPRINTF(sc, ATH_DBG_FATAL,
322 "Unable to restart recv logic\n");
323 return -EIO;
324 }
325
326 ath_setcurmode(sc, &hw->conf);
327 ath_update_txpow(sc);
328 ath9k_hw_set_interrupts(ah, sc->sc_imask);
329 }
330 return 0;
331 }
332
333 /*
334 * This routine performs the periodic noise floor calibration function
335 * that is used to adjust and optimize the chip performance. This
336 * takes environmental changes (location, temperature) into account.
337 * When the task is complete, it reschedules itself depending on the
338 * appropriate interval that was calculated.
339 */
340 static void ath_ani_calibrate(unsigned long data)
341 {
342 struct ath_softc *sc;
343 struct ath_hal *ah;
344 bool longcal = false;
345 bool shortcal = false;
346 bool aniflag = false;
347 unsigned int timestamp = jiffies_to_msecs(jiffies);
348 u32 cal_interval;
349
350 sc = (struct ath_softc *)data;
351 ah = sc->sc_ah;
352
353 /*
354 * don't calibrate when we're scanning.
355 * we are most likely not on our home channel.
356 */
357 if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
358 return;
359
360 /* Long calibration runs independently of short calibration. */
361 if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
362 longcal = true;
363 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
364 sc->sc_ani.sc_longcal_timer = timestamp;
365 }
366
367 /* Short calibration applies only while sc_caldone is false */
368 if (!sc->sc_ani.sc_caldone) {
369 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
370 ATH_SHORT_CALINTERVAL) {
371 shortcal = true;
372 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
373 sc->sc_ani.sc_shortcal_timer = timestamp;
374 sc->sc_ani.sc_resetcal_timer = timestamp;
375 }
376 } else {
377 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
378 ATH_RESTART_CALINTERVAL) {
379 ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
380 &sc->sc_ani.sc_caldone);
381 if (sc->sc_ani.sc_caldone)
382 sc->sc_ani.sc_resetcal_timer = timestamp;
383 }
384 }
385
386 /* Verify whether we must check ANI */
387 if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
388 ATH_ANI_POLLINTERVAL) {
389 aniflag = true;
390 sc->sc_ani.sc_checkani_timer = timestamp;
391 }
392
393 /* Skip all processing if there's nothing to do. */
394 if (longcal || shortcal || aniflag) {
395 /* Call ANI routine if necessary */
396 if (aniflag)
397 ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
398 ah->ah_curchan);
399
400 /* Perform calibration if necessary */
401 if (longcal || shortcal) {
402 bool iscaldone = false;
403
404 if (ath9k_hw_calibrate(ah, ah->ah_curchan,
405 sc->sc_rx_chainmask, longcal,
406 &iscaldone)) {
407 if (longcal)
408 sc->sc_ani.sc_noise_floor =
409 ath9k_hw_getchan_noise(ah,
410 ah->ah_curchan);
411
412 DPRINTF(sc, ATH_DBG_ANI,
413 "calibrate chan %u/%x nf: %d\n",
414 ah->ah_curchan->channel,
415 ah->ah_curchan->channelFlags,
416 sc->sc_ani.sc_noise_floor);
417 } else {
418 DPRINTF(sc, ATH_DBG_ANY,
419 "calibrate chan %u/%x failed\n",
420 ah->ah_curchan->channel,
421 ah->ah_curchan->channelFlags);
422 }
423 sc->sc_ani.sc_caldone = iscaldone;
424 }
425 }
426
427 /*
428 * Set timer interval based on previous results.
429 * The interval must be the shortest necessary to satisfy ANI,
430 * short calibration and long calibration.
431 */
432 cal_interval = ATH_LONG_CALINTERVAL;
433 if (sc->sc_ah->ah_config.enable_ani)
434 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
435 if (!sc->sc_ani.sc_caldone)
436 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
437
438 mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
439 }
440
441 /*
442 * Update tx/rx chainmask. For legacy association,
443 * hard code chainmask to 1x1, for 11n association, use
444 * the chainmask configuration.
445 */
446 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
447 {
448 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
449 if (is_ht) {
450 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
451 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
452 } else {
453 sc->sc_tx_chainmask = 1;
454 sc->sc_rx_chainmask = 1;
455 }
456
457 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
458 sc->sc_tx_chainmask, sc->sc_rx_chainmask);
459 }
460
461 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
462 {
463 struct ath_node *an;
464
465 an = (struct ath_node *)sta->drv_priv;
466
467 if (sc->sc_flags & SC_OP_TXAGGR)
468 ath_tx_node_init(sc, an);
469
470 an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
471 sta->ht_cap.ampdu_factor);
472 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
473 }
474
475 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
476 {
477 struct ath_node *an = (struct ath_node *)sta->drv_priv;
478
479 if (sc->sc_flags & SC_OP_TXAGGR)
480 ath_tx_node_cleanup(sc, an);
481 }
482
483 static void ath9k_tasklet(unsigned long data)
484 {
485 struct ath_softc *sc = (struct ath_softc *)data;
486 u32 status = sc->sc_intrstatus;
487
488 if (status & ATH9K_INT_FATAL) {
489 /* need a chip reset */
490 ath_reset(sc, false);
491 return;
492 } else {
493
494 if (status &
495 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
496 spin_lock_bh(&sc->rx.rxflushlock);
497 ath_rx_tasklet(sc, 0);
498 spin_unlock_bh(&sc->rx.rxflushlock);
499 }
500 /* XXX: optimize this */
501 if (status & ATH9K_INT_TX)
502 ath_tx_tasklet(sc);
503 }
504
505 /* re-enable hardware interrupt */
506 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
507 }
508
509 static irqreturn_t ath_isr(int irq, void *dev)
510 {
511 struct ath_softc *sc = dev;
512 struct ath_hal *ah = sc->sc_ah;
513 enum ath9k_int status;
514 bool sched = false;
515
516 do {
517 if (sc->sc_flags & SC_OP_INVALID) {
518 /*
519 * The hardware is not ready/present, don't
520 * touch anything. Note this can happen early
521 * on if the IRQ is shared.
522 */
523 return IRQ_NONE;
524 }
525 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
526 return IRQ_NONE;
527 }
528
529 /*
530 * Figure out the reason(s) for the interrupt. Note
531 * that the hal returns a pseudo-ISR that may include
532 * bits we haven't explicitly enabled so we mask the
533 * value to insure we only process bits we requested.
534 */
535 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
536
537 status &= sc->sc_imask; /* discard unasked-for bits */
538
539 /*
540 * If there are no status bits set, then this interrupt was not
541 * for me (should have been caught above).
542 */
543 if (!status)
544 return IRQ_NONE;
545
546 sc->sc_intrstatus = status;
547
548 if (status & ATH9K_INT_FATAL) {
549 /* need a chip reset */
550 sched = true;
551 } else if (status & ATH9K_INT_RXORN) {
552 /* need a chip reset */
553 sched = true;
554 } else {
555 if (status & ATH9K_INT_SWBA) {
556 /* schedule a tasklet for beacon handling */
557 tasklet_schedule(&sc->bcon_tasklet);
558 }
559 if (status & ATH9K_INT_RXEOL) {
560 /*
561 * NB: the hardware should re-read the link when
562 * RXE bit is written, but it doesn't work
563 * at least on older hardware revs.
564 */
565 sched = true;
566 }
567
568 if (status & ATH9K_INT_TXURN)
569 /* bump tx trigger level */
570 ath9k_hw_updatetxtriglevel(ah, true);
571 /* XXX: optimize this */
572 if (status & ATH9K_INT_RX)
573 sched = true;
574 if (status & ATH9K_INT_TX)
575 sched = true;
576 if (status & ATH9K_INT_BMISS)
577 sched = true;
578 /* carrier sense timeout */
579 if (status & ATH9K_INT_CST)
580 sched = true;
581 if (status & ATH9K_INT_MIB) {
582 /*
583 * Disable interrupts until we service the MIB
584 * interrupt; otherwise it will continue to
585 * fire.
586 */
587 ath9k_hw_set_interrupts(ah, 0);
588 /*
589 * Let the hal handle the event. We assume
590 * it will clear whatever condition caused
591 * the interrupt.
592 */
593 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
594 ath9k_hw_set_interrupts(ah, sc->sc_imask);
595 }
596 if (status & ATH9K_INT_TIM_TIMER) {
597 if (!(ah->ah_caps.hw_caps &
598 ATH9K_HW_CAP_AUTOSLEEP)) {
599 /* Clear RxAbort bit so that we can
600 * receive frames */
601 ath9k_hw_setrxabort(ah, 0);
602 sched = true;
603 }
604 }
605 }
606 } while (0);
607
608 ath_debug_stat_interrupt(sc, status);
609
610 if (sched) {
611 /* turn off every interrupt except SWBA */
612 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
613 tasklet_schedule(&sc->intr_tq);
614 }
615
616 return IRQ_HANDLED;
617 }
618
619 static int ath_get_channel(struct ath_softc *sc,
620 struct ieee80211_channel *chan)
621 {
622 int i;
623
624 for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
625 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
626 return i;
627 }
628
629 return -1;
630 }
631
632 static u32 ath_get_extchanmode(struct ath_softc *sc,
633 struct ieee80211_channel *chan,
634 enum nl80211_channel_type channel_type)
635 {
636 u32 chanmode = 0;
637
638 switch (chan->band) {
639 case IEEE80211_BAND_2GHZ:
640 switch(channel_type) {
641 case NL80211_CHAN_NO_HT:
642 case NL80211_CHAN_HT20:
643 chanmode = CHANNEL_G_HT20;
644 break;
645 case NL80211_CHAN_HT40PLUS:
646 chanmode = CHANNEL_G_HT40PLUS;
647 break;
648 case NL80211_CHAN_HT40MINUS:
649 chanmode = CHANNEL_G_HT40MINUS;
650 break;
651 }
652 break;
653 case IEEE80211_BAND_5GHZ:
654 switch(channel_type) {
655 case NL80211_CHAN_NO_HT:
656 case NL80211_CHAN_HT20:
657 chanmode = CHANNEL_A_HT20;
658 break;
659 case NL80211_CHAN_HT40PLUS:
660 chanmode = CHANNEL_A_HT40PLUS;
661 break;
662 case NL80211_CHAN_HT40MINUS:
663 chanmode = CHANNEL_A_HT40MINUS;
664 break;
665 }
666 break;
667 default:
668 break;
669 }
670
671 return chanmode;
672 }
673
674 static int ath_keyset(struct ath_softc *sc, u16 keyix,
675 struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
676 {
677 bool status;
678
679 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
680 keyix, hk, mac, false);
681
682 return status != false;
683 }
684
685 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
686 struct ath9k_keyval *hk,
687 const u8 *addr)
688 {
689 const u8 *key_rxmic;
690 const u8 *key_txmic;
691
692 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
693 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
694
695 if (addr == NULL) {
696 /* Group key installation */
697 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
698 return ath_keyset(sc, keyix, hk, addr);
699 }
700 if (!sc->sc_splitmic) {
701 /*
702 * data key goes at first index,
703 * the hal handles the MIC keys at index+64.
704 */
705 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
706 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
707 return ath_keyset(sc, keyix, hk, addr);
708 }
709 /*
710 * TX key goes at first index, RX key at +32.
711 * The hal handles the MIC keys at index+64.
712 */
713 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
714 if (!ath_keyset(sc, keyix, hk, NULL)) {
715 /* Txmic entry failed. No need to proceed further */
716 DPRINTF(sc, ATH_DBG_KEYCACHE,
717 "Setting TX MIC Key Failed\n");
718 return 0;
719 }
720
721 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
722 /* XXX delete tx key on failure? */
723 return ath_keyset(sc, keyix + 32, hk, addr);
724 }
725
726 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
727 {
728 int i;
729
730 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
731 if (test_bit(i, sc->sc_keymap) ||
732 test_bit(i + 64, sc->sc_keymap))
733 continue; /* At least one part of TKIP key allocated */
734 if (sc->sc_splitmic &&
735 (test_bit(i + 32, sc->sc_keymap) ||
736 test_bit(i + 64 + 32, sc->sc_keymap)))
737 continue; /* At least one part of TKIP key allocated */
738
739 /* Found a free slot for a TKIP key */
740 return i;
741 }
742 return -1;
743 }
744
745 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
746 {
747 int i;
748
749 /* First, try to find slots that would not be available for TKIP. */
750 if (sc->sc_splitmic) {
751 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 4; i++) {
752 if (!test_bit(i, sc->sc_keymap) &&
753 (test_bit(i + 32, sc->sc_keymap) ||
754 test_bit(i + 64, sc->sc_keymap) ||
755 test_bit(i + 64 + 32, sc->sc_keymap)))
756 return i;
757 if (!test_bit(i + 32, sc->sc_keymap) &&
758 (test_bit(i, sc->sc_keymap) ||
759 test_bit(i + 64, sc->sc_keymap) ||
760 test_bit(i + 64 + 32, sc->sc_keymap)))
761 return i + 32;
762 if (!test_bit(i + 64, sc->sc_keymap) &&
763 (test_bit(i , sc->sc_keymap) ||
764 test_bit(i + 32, sc->sc_keymap) ||
765 test_bit(i + 64 + 32, sc->sc_keymap)))
766 return i + 64;
767 if (!test_bit(i + 64 + 32, sc->sc_keymap) &&
768 (test_bit(i, sc->sc_keymap) ||
769 test_bit(i + 32, sc->sc_keymap) ||
770 test_bit(i + 64, sc->sc_keymap)))
771 return i + 64 + 32;
772 }
773 } else {
774 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax / 2; i++) {
775 if (!test_bit(i, sc->sc_keymap) &&
776 test_bit(i + 64, sc->sc_keymap))
777 return i;
778 if (test_bit(i, sc->sc_keymap) &&
779 !test_bit(i + 64, sc->sc_keymap))
780 return i + 64;
781 }
782 }
783
784 /* No partially used TKIP slots, pick any available slot */
785 for (i = IEEE80211_WEP_NKID; i < sc->sc_keymax; i++) {
786 /* Do not allow slots that could be needed for TKIP group keys
787 * to be used. This limitation could be removed if we know that
788 * TKIP will not be used. */
789 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
790 continue;
791 if (sc->sc_splitmic) {
792 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
793 continue;
794 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
795 continue;
796 }
797
798 if (!test_bit(i, sc->sc_keymap))
799 return i; /* Found a free slot for a key */
800 }
801
802 /* No free slot found */
803 return -1;
804 }
805
806 static int ath_key_config(struct ath_softc *sc,
807 const u8 *addr,
808 struct ieee80211_key_conf *key)
809 {
810 struct ath9k_keyval hk;
811 const u8 *mac = NULL;
812 int ret = 0;
813 int idx;
814
815 memset(&hk, 0, sizeof(hk));
816
817 switch (key->alg) {
818 case ALG_WEP:
819 hk.kv_type = ATH9K_CIPHER_WEP;
820 break;
821 case ALG_TKIP:
822 hk.kv_type = ATH9K_CIPHER_TKIP;
823 break;
824 case ALG_CCMP:
825 hk.kv_type = ATH9K_CIPHER_AES_CCM;
826 break;
827 default:
828 return -EINVAL;
829 }
830
831 hk.kv_len = key->keylen;
832 memcpy(hk.kv_val, key->key, key->keylen);
833
834 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
835 /* For now, use the default keys for broadcast keys. This may
836 * need to change with virtual interfaces. */
837 idx = key->keyidx;
838 } else if (key->keyidx) {
839 struct ieee80211_vif *vif;
840
841 mac = addr;
842 vif = sc->sc_vaps[0];
843 if (vif->type != NL80211_IFTYPE_AP) {
844 /* Only keyidx 0 should be used with unicast key, but
845 * allow this for client mode for now. */
846 idx = key->keyidx;
847 } else
848 return -EIO;
849 } else {
850 mac = addr;
851 if (key->alg == ALG_TKIP)
852 idx = ath_reserve_key_cache_slot_tkip(sc);
853 else
854 idx = ath_reserve_key_cache_slot(sc);
855 if (idx < 0)
856 return -EIO; /* no free key cache entries */
857 }
858
859 if (key->alg == ALG_TKIP)
860 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
861 else
862 ret = ath_keyset(sc, idx, &hk, mac);
863
864 if (!ret)
865 return -EIO;
866
867 set_bit(idx, sc->sc_keymap);
868 if (key->alg == ALG_TKIP) {
869 set_bit(idx + 64, sc->sc_keymap);
870 if (sc->sc_splitmic) {
871 set_bit(idx + 32, sc->sc_keymap);
872 set_bit(idx + 64 + 32, sc->sc_keymap);
873 }
874 }
875
876 return idx;
877 }
878
879 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
880 {
881 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
882 if (key->hw_key_idx < IEEE80211_WEP_NKID)
883 return;
884
885 clear_bit(key->hw_key_idx, sc->sc_keymap);
886 if (key->alg != ALG_TKIP)
887 return;
888
889 clear_bit(key->hw_key_idx + 64, sc->sc_keymap);
890 if (sc->sc_splitmic) {
891 clear_bit(key->hw_key_idx + 32, sc->sc_keymap);
892 clear_bit(key->hw_key_idx + 64 + 32, sc->sc_keymap);
893 }
894 }
895
896 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
897 {
898 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3 /* 2 ^ 16 */
899 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6 /* 8 usec */
900
901 ht_info->ht_supported = true;
902 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
903 IEEE80211_HT_CAP_SM_PS |
904 IEEE80211_HT_CAP_SGI_40 |
905 IEEE80211_HT_CAP_DSSSCCK40;
906
907 ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
908 ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
909 /* set up supported mcs set */
910 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
911 ht_info->mcs.rx_mask[0] = 0xff;
912 ht_info->mcs.rx_mask[1] = 0xff;
913 ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
914 }
915
916 static void ath9k_bss_assoc_info(struct ath_softc *sc,
917 struct ieee80211_vif *vif,
918 struct ieee80211_bss_conf *bss_conf)
919 {
920 struct ath_vap *avp = (void *)vif->drv_priv;
921
922 if (bss_conf->assoc) {
923 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
924 bss_conf->aid, sc->sc_curbssid);
925
926 /* New association, store aid */
927 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
928 sc->sc_curaid = bss_conf->aid;
929 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
930 sc->sc_curaid);
931 }
932
933 /* Configure the beacon */
934 ath_beacon_config(sc, 0);
935 sc->sc_flags |= SC_OP_BEACONS;
936
937 /* Reset rssi stats */
938 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
939 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
940 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
941 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
942
943 /* Start ANI */
944 mod_timer(&sc->sc_ani.timer,
945 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
946
947 } else {
948 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
949 sc->sc_curaid = 0;
950 }
951 }
952
953 /********************************/
954 /* LED functions */
955 /********************************/
956
957 static void ath_led_brightness(struct led_classdev *led_cdev,
958 enum led_brightness brightness)
959 {
960 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
961 struct ath_softc *sc = led->sc;
962
963 switch (brightness) {
964 case LED_OFF:
965 if (led->led_type == ATH_LED_ASSOC ||
966 led->led_type == ATH_LED_RADIO)
967 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
968 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
969 (led->led_type == ATH_LED_RADIO) ? 1 :
970 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
971 break;
972 case LED_FULL:
973 if (led->led_type == ATH_LED_ASSOC)
974 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
975 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
976 break;
977 default:
978 break;
979 }
980 }
981
982 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
983 char *trigger)
984 {
985 int ret;
986
987 led->sc = sc;
988 led->led_cdev.name = led->name;
989 led->led_cdev.default_trigger = trigger;
990 led->led_cdev.brightness_set = ath_led_brightness;
991
992 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
993 if (ret)
994 DPRINTF(sc, ATH_DBG_FATAL,
995 "Failed to register led:%s", led->name);
996 else
997 led->registered = 1;
998 return ret;
999 }
1000
1001 static void ath_unregister_led(struct ath_led *led)
1002 {
1003 if (led->registered) {
1004 led_classdev_unregister(&led->led_cdev);
1005 led->registered = 0;
1006 }
1007 }
1008
1009 static void ath_deinit_leds(struct ath_softc *sc)
1010 {
1011 ath_unregister_led(&sc->assoc_led);
1012 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1013 ath_unregister_led(&sc->tx_led);
1014 ath_unregister_led(&sc->rx_led);
1015 ath_unregister_led(&sc->radio_led);
1016 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1017 }
1018
1019 static void ath_init_leds(struct ath_softc *sc)
1020 {
1021 char *trigger;
1022 int ret;
1023
1024 /* Configure gpio 1 for output */
1025 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1026 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1027 /* LED off, active low */
1028 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1029
1030 trigger = ieee80211_get_radio_led_name(sc->hw);
1031 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1032 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
1033 ret = ath_register_led(sc, &sc->radio_led, trigger);
1034 sc->radio_led.led_type = ATH_LED_RADIO;
1035 if (ret)
1036 goto fail;
1037
1038 trigger = ieee80211_get_assoc_led_name(sc->hw);
1039 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1040 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1041 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1042 sc->assoc_led.led_type = ATH_LED_ASSOC;
1043 if (ret)
1044 goto fail;
1045
1046 trigger = ieee80211_get_tx_led_name(sc->hw);
1047 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1048 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1049 ret = ath_register_led(sc, &sc->tx_led, trigger);
1050 sc->tx_led.led_type = ATH_LED_TX;
1051 if (ret)
1052 goto fail;
1053
1054 trigger = ieee80211_get_rx_led_name(sc->hw);
1055 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1056 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1057 ret = ath_register_led(sc, &sc->rx_led, trigger);
1058 sc->rx_led.led_type = ATH_LED_RX;
1059 if (ret)
1060 goto fail;
1061
1062 return;
1063
1064 fail:
1065 ath_deinit_leds(sc);
1066 }
1067
1068 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1069
1070 /*******************/
1071 /* Rfkill */
1072 /*******************/
1073
1074 static void ath_radio_enable(struct ath_softc *sc)
1075 {
1076 struct ath_hal *ah = sc->sc_ah;
1077 int status;
1078
1079 spin_lock_bh(&sc->sc_resetlock);
1080 if (!ath9k_hw_reset(ah, ah->ah_curchan,
1081 sc->tx_chan_width,
1082 sc->sc_tx_chainmask,
1083 sc->sc_rx_chainmask,
1084 sc->sc_ht_extprotspacing,
1085 false, &status)) {
1086 DPRINTF(sc, ATH_DBG_FATAL,
1087 "Unable to reset channel %u (%uMhz) "
1088 "flags 0x%x hal status %u\n",
1089 ath9k_hw_mhz2ieee(ah,
1090 ah->ah_curchan->channel,
1091 ah->ah_curchan->channelFlags),
1092 ah->ah_curchan->channel,
1093 ah->ah_curchan->channelFlags, status);
1094 }
1095 spin_unlock_bh(&sc->sc_resetlock);
1096
1097 ath_update_txpow(sc);
1098 if (ath_startrecv(sc) != 0) {
1099 DPRINTF(sc, ATH_DBG_FATAL,
1100 "Unable to restart recv logic\n");
1101 return;
1102 }
1103
1104 if (sc->sc_flags & SC_OP_BEACONS)
1105 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1106
1107 /* Re-Enable interrupts */
1108 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1109
1110 /* Enable LED */
1111 ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1112 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1113 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1114
1115 ieee80211_wake_queues(sc->hw);
1116 }
1117
1118 static void ath_radio_disable(struct ath_softc *sc)
1119 {
1120 struct ath_hal *ah = sc->sc_ah;
1121 int status;
1122
1123
1124 ieee80211_stop_queues(sc->hw);
1125
1126 /* Disable LED */
1127 ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1128 ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1129
1130 /* Disable interrupts */
1131 ath9k_hw_set_interrupts(ah, 0);
1132
1133 ath_draintxq(sc, false); /* clear pending tx frames */
1134 ath_stoprecv(sc); /* turn off frame recv */
1135 ath_flushrecv(sc); /* flush recv queue */
1136
1137 spin_lock_bh(&sc->sc_resetlock);
1138 if (!ath9k_hw_reset(ah, ah->ah_curchan,
1139 sc->tx_chan_width,
1140 sc->sc_tx_chainmask,
1141 sc->sc_rx_chainmask,
1142 sc->sc_ht_extprotspacing,
1143 false, &status)) {
1144 DPRINTF(sc, ATH_DBG_FATAL,
1145 "Unable to reset channel %u (%uMhz) "
1146 "flags 0x%x hal status %u\n",
1147 ath9k_hw_mhz2ieee(ah,
1148 ah->ah_curchan->channel,
1149 ah->ah_curchan->channelFlags),
1150 ah->ah_curchan->channel,
1151 ah->ah_curchan->channelFlags, status);
1152 }
1153 spin_unlock_bh(&sc->sc_resetlock);
1154
1155 ath9k_hw_phy_disable(ah);
1156 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1157 }
1158
1159 static bool ath_is_rfkill_set(struct ath_softc *sc)
1160 {
1161 struct ath_hal *ah = sc->sc_ah;
1162
1163 return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1164 ah->ah_rfkill_polarity;
1165 }
1166
1167 /* h/w rfkill poll function */
1168 static void ath_rfkill_poll(struct work_struct *work)
1169 {
1170 struct ath_softc *sc = container_of(work, struct ath_softc,
1171 rf_kill.rfkill_poll.work);
1172 bool radio_on;
1173
1174 if (sc->sc_flags & SC_OP_INVALID)
1175 return;
1176
1177 radio_on = !ath_is_rfkill_set(sc);
1178
1179 /*
1180 * enable/disable radio only when there is a
1181 * state change in RF switch
1182 */
1183 if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1184 enum rfkill_state state;
1185
1186 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1187 state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1188 : RFKILL_STATE_HARD_BLOCKED;
1189 } else if (radio_on) {
1190 ath_radio_enable(sc);
1191 state = RFKILL_STATE_UNBLOCKED;
1192 } else {
1193 ath_radio_disable(sc);
1194 state = RFKILL_STATE_HARD_BLOCKED;
1195 }
1196
1197 if (state == RFKILL_STATE_HARD_BLOCKED)
1198 sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1199 else
1200 sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1201
1202 rfkill_force_state(sc->rf_kill.rfkill, state);
1203 }
1204
1205 queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1206 msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1207 }
1208
1209 /* s/w rfkill handler */
1210 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1211 {
1212 struct ath_softc *sc = data;
1213
1214 switch (state) {
1215 case RFKILL_STATE_SOFT_BLOCKED:
1216 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1217 SC_OP_RFKILL_SW_BLOCKED)))
1218 ath_radio_disable(sc);
1219 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1220 return 0;
1221 case RFKILL_STATE_UNBLOCKED:
1222 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1223 sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1224 if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1225 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1226 "radio as it is disabled by h/w\n");
1227 return -EPERM;
1228 }
1229 ath_radio_enable(sc);
1230 }
1231 return 0;
1232 default:
1233 return -EINVAL;
1234 }
1235 }
1236
1237 /* Init s/w rfkill */
1238 static int ath_init_sw_rfkill(struct ath_softc *sc)
1239 {
1240 sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1241 RFKILL_TYPE_WLAN);
1242 if (!sc->rf_kill.rfkill) {
1243 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1244 return -ENOMEM;
1245 }
1246
1247 snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1248 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1249 sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1250 sc->rf_kill.rfkill->data = sc;
1251 sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1252 sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1253 sc->rf_kill.rfkill->user_claim_unsupported = 1;
1254
1255 return 0;
1256 }
1257
1258 /* Deinitialize rfkill */
1259 static void ath_deinit_rfkill(struct ath_softc *sc)
1260 {
1261 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1262 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1263
1264 if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1265 rfkill_unregister(sc->rf_kill.rfkill);
1266 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1267 sc->rf_kill.rfkill = NULL;
1268 }
1269 }
1270
1271 static int ath_start_rfkill_poll(struct ath_softc *sc)
1272 {
1273 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1274 queue_delayed_work(sc->hw->workqueue,
1275 &sc->rf_kill.rfkill_poll, 0);
1276
1277 if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1278 if (rfkill_register(sc->rf_kill.rfkill)) {
1279 DPRINTF(sc, ATH_DBG_FATAL,
1280 "Unable to register rfkill\n");
1281 rfkill_free(sc->rf_kill.rfkill);
1282
1283 /* Deinitialize the device */
1284 ath_detach(sc);
1285 if (sc->pdev->irq)
1286 free_irq(sc->pdev->irq, sc);
1287 pci_iounmap(sc->pdev, sc->mem);
1288 pci_release_region(sc->pdev, 0);
1289 pci_disable_device(sc->pdev);
1290 ieee80211_free_hw(sc->hw);
1291 return -EIO;
1292 } else {
1293 sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1294 }
1295 }
1296
1297 return 0;
1298 }
1299 #endif /* CONFIG_RFKILL */
1300
1301 static void ath_detach(struct ath_softc *sc)
1302 {
1303 struct ieee80211_hw *hw = sc->hw;
1304 int i = 0;
1305
1306 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1307
1308 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1309 ath_deinit_rfkill(sc);
1310 #endif
1311 ath_deinit_leds(sc);
1312
1313 ieee80211_unregister_hw(hw);
1314 ath_rx_cleanup(sc);
1315 ath_tx_cleanup(sc);
1316
1317 tasklet_kill(&sc->intr_tq);
1318 tasklet_kill(&sc->bcon_tasklet);
1319
1320 if (!(sc->sc_flags & SC_OP_INVALID))
1321 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1322
1323 /* cleanup tx queues */
1324 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1325 if (ATH_TXQ_SETUP(sc, i))
1326 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1327
1328 ath9k_hw_detach(sc->sc_ah);
1329 ath9k_exit_debug(sc);
1330 }
1331
1332 static int ath_init(u16 devid, struct ath_softc *sc)
1333 {
1334 struct ath_hal *ah = NULL;
1335 int status;
1336 int error = 0, i;
1337 int csz = 0;
1338
1339 /* XXX: hardware will not be ready until ath_open() being called */
1340 sc->sc_flags |= SC_OP_INVALID;
1341
1342 if (ath9k_init_debug(sc) < 0)
1343 printk(KERN_ERR "Unable to create debugfs files\n");
1344
1345 spin_lock_init(&sc->sc_resetlock);
1346 mutex_init(&sc->mutex);
1347 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1348 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1349 (unsigned long)sc);
1350
1351 /*
1352 * Cache line size is used to size and align various
1353 * structures used to communicate with the hardware.
1354 */
1355 bus_read_cachesize(sc, &csz);
1356 /* XXX assert csz is non-zero */
1357 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1358
1359 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1360 if (ah == NULL) {
1361 DPRINTF(sc, ATH_DBG_FATAL,
1362 "Unable to attach hardware; HAL status %u\n", status);
1363 error = -ENXIO;
1364 goto bad;
1365 }
1366 sc->sc_ah = ah;
1367
1368 /* Get the hardware key cache size. */
1369 sc->sc_keymax = ah->ah_caps.keycache_size;
1370 if (sc->sc_keymax > ATH_KEYMAX) {
1371 DPRINTF(sc, ATH_DBG_KEYCACHE,
1372 "Warning, using only %u entries in %u key cache\n",
1373 ATH_KEYMAX, sc->sc_keymax);
1374 sc->sc_keymax = ATH_KEYMAX;
1375 }
1376
1377 /*
1378 * Reset the key cache since some parts do not
1379 * reset the contents on initial power up.
1380 */
1381 for (i = 0; i < sc->sc_keymax; i++)
1382 ath9k_hw_keyreset(ah, (u16) i);
1383
1384 /* Collect the channel list using the default country code */
1385
1386 error = ath_setup_channels(sc);
1387 if (error)
1388 goto bad;
1389
1390 /* default to MONITOR mode */
1391 sc->sc_ah->ah_opmode = NL80211_IFTYPE_MONITOR;
1392
1393
1394 /* Setup rate tables */
1395
1396 ath_rate_attach(sc);
1397 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1398 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1399
1400 /*
1401 * Allocate hardware transmit queues: one queue for
1402 * beacon frames and one data queue for each QoS
1403 * priority. Note that the hal handles reseting
1404 * these queues at the needed time.
1405 */
1406 sc->beacon.beaconq = ath_beaconq_setup(ah);
1407 if (sc->beacon.beaconq == -1) {
1408 DPRINTF(sc, ATH_DBG_FATAL,
1409 "Unable to setup a beacon xmit queue\n");
1410 error = -EIO;
1411 goto bad2;
1412 }
1413 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1414 if (sc->beacon.cabq == NULL) {
1415 DPRINTF(sc, ATH_DBG_FATAL,
1416 "Unable to setup CAB xmit queue\n");
1417 error = -EIO;
1418 goto bad2;
1419 }
1420
1421 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1422 ath_cabq_update(sc);
1423
1424 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1425 sc->tx.hwq_map[i] = -1;
1426
1427 /* Setup data queues */
1428 /* NB: ensure BK queue is the lowest priority h/w queue */
1429 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1430 DPRINTF(sc, ATH_DBG_FATAL,
1431 "Unable to setup xmit queue for BK traffic\n");
1432 error = -EIO;
1433 goto bad2;
1434 }
1435
1436 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1437 DPRINTF(sc, ATH_DBG_FATAL,
1438 "Unable to setup xmit queue for BE traffic\n");
1439 error = -EIO;
1440 goto bad2;
1441 }
1442 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1443 DPRINTF(sc, ATH_DBG_FATAL,
1444 "Unable to setup xmit queue for VI traffic\n");
1445 error = -EIO;
1446 goto bad2;
1447 }
1448 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1449 DPRINTF(sc, ATH_DBG_FATAL,
1450 "Unable to setup xmit queue for VO traffic\n");
1451 error = -EIO;
1452 goto bad2;
1453 }
1454
1455 /* Initializes the noise floor to a reasonable default value.
1456 * Later on this will be updated during ANI processing. */
1457
1458 sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1459 setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1460
1461 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1462 ATH9K_CIPHER_TKIP, NULL)) {
1463 /*
1464 * Whether we should enable h/w TKIP MIC.
1465 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1466 * report WMM capable, so it's always safe to turn on
1467 * TKIP MIC in this case.
1468 */
1469 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1470 0, 1, NULL);
1471 }
1472
1473 /*
1474 * Check whether the separate key cache entries
1475 * are required to handle both tx+rx MIC keys.
1476 * With split mic keys the number of stations is limited
1477 * to 27 otherwise 59.
1478 */
1479 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1480 ATH9K_CIPHER_TKIP, NULL)
1481 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1482 ATH9K_CIPHER_MIC, NULL)
1483 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1484 0, NULL))
1485 sc->sc_splitmic = 1;
1486
1487 /* turn on mcast key search if possible */
1488 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1489 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1490 1, NULL);
1491
1492 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1493 sc->sc_config.txpowlimit_override = 0;
1494
1495 /* 11n Capabilities */
1496 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1497 sc->sc_flags |= SC_OP_TXAGGR;
1498 sc->sc_flags |= SC_OP_RXAGGR;
1499 }
1500
1501 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1502 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1503
1504 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1505 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1506
1507 ath9k_hw_getmac(ah, sc->sc_myaddr);
1508 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1509 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1510 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1511 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1512 }
1513
1514 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1515
1516 /* initialize beacon slots */
1517 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1518 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1519
1520 /* save MISC configurations */
1521 sc->sc_config.swBeaconProcess = 1;
1522
1523 /* setup channels and rates */
1524
1525 sc->sbands[IEEE80211_BAND_2GHZ].channels =
1526 sc->channels[IEEE80211_BAND_2GHZ];
1527 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1528 sc->rates[IEEE80211_BAND_2GHZ];
1529 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1530
1531 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1532 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1533 sc->channels[IEEE80211_BAND_5GHZ];
1534 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1535 sc->rates[IEEE80211_BAND_5GHZ];
1536 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1537 }
1538
1539 return 0;
1540 bad2:
1541 /* cleanup tx queues */
1542 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1543 if (ATH_TXQ_SETUP(sc, i))
1544 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1545 bad:
1546 if (ah)
1547 ath9k_hw_detach(ah);
1548
1549 return error;
1550 }
1551
1552 static int ath_attach(u16 devid, struct ath_softc *sc)
1553 {
1554 struct ieee80211_hw *hw = sc->hw;
1555 int error = 0;
1556
1557 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1558
1559 error = ath_init(devid, sc);
1560 if (error != 0)
1561 return error;
1562
1563 /* get mac address from hardware and set in mac80211 */
1564
1565 SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1566
1567 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1568 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1569 IEEE80211_HW_SIGNAL_DBM |
1570 IEEE80211_HW_AMPDU_AGGREGATION;
1571
1572 hw->wiphy->interface_modes =
1573 BIT(NL80211_IFTYPE_AP) |
1574 BIT(NL80211_IFTYPE_STATION) |
1575 BIT(NL80211_IFTYPE_ADHOC);
1576
1577 hw->queues = 4;
1578 hw->max_rates = 4;
1579 hw->max_rate_tries = ATH_11N_TXMAXTRY;
1580 hw->sta_data_size = sizeof(struct ath_node);
1581 hw->vif_data_size = sizeof(struct ath_vap);
1582
1583 hw->rate_control_algorithm = "ath9k_rate_control";
1584
1585 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1586 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1587 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588 setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1589 }
1590
1591 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1592 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1593 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1594 &sc->sbands[IEEE80211_BAND_5GHZ];
1595
1596 /* initialize tx/rx engine */
1597 error = ath_tx_init(sc, ATH_TXBUF);
1598 if (error != 0)
1599 goto detach;
1600
1601 error = ath_rx_init(sc, ATH_RXBUF);
1602 if (error != 0)
1603 goto detach;
1604
1605 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1606 /* Initialze h/w Rfkill */
1607 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1608 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1609
1610 /* Initialize s/w rfkill */
1611 if (ath_init_sw_rfkill(sc))
1612 goto detach;
1613 #endif
1614
1615 error = ieee80211_register_hw(hw);
1616
1617 /* Initialize LED control */
1618 ath_init_leds(sc);
1619
1620 return 0;
1621 detach:
1622 ath_detach(sc);
1623 return error;
1624 }
1625
1626 int ath_reset(struct ath_softc *sc, bool retry_tx)
1627 {
1628 struct ath_hal *ah = sc->sc_ah;
1629 struct ieee80211_hw *hw = sc->hw;
1630 int status;
1631 int error = 0;
1632
1633 ath9k_hw_set_interrupts(ah, 0);
1634 ath_draintxq(sc, retry_tx);
1635 ath_stoprecv(sc);
1636 ath_flushrecv(sc);
1637
1638 spin_lock_bh(&sc->sc_resetlock);
1639 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1640 sc->tx_chan_width,
1641 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1642 sc->sc_ht_extprotspacing, false, &status)) {
1643 DPRINTF(sc, ATH_DBG_FATAL,
1644 "Unable to reset hardware; hal status %u\n", status);
1645 error = -EIO;
1646 }
1647 spin_unlock_bh(&sc->sc_resetlock);
1648
1649 if (ath_startrecv(sc) != 0)
1650 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1651
1652 /*
1653 * We may be doing a reset in response to a request
1654 * that changes the channel so update any state that
1655 * might change as a result.
1656 */
1657 ath_setcurmode(sc, &hw->conf);
1658
1659 ath_update_txpow(sc);
1660
1661 if (sc->sc_flags & SC_OP_BEACONS)
1662 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
1663
1664 ath9k_hw_set_interrupts(ah, sc->sc_imask);
1665
1666 if (retry_tx) {
1667 int i;
1668 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1669 if (ATH_TXQ_SETUP(sc, i)) {
1670 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1671 ath_txq_schedule(sc, &sc->tx.txq[i]);
1672 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1673 }
1674 }
1675 }
1676
1677 return error;
1678 }
1679
1680 /*
1681 * This function will allocate both the DMA descriptor structure, and the
1682 * buffers it contains. These are used to contain the descriptors used
1683 * by the system.
1684 */
1685 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1686 struct list_head *head, const char *name,
1687 int nbuf, int ndesc)
1688 {
1689 #define DS2PHYS(_dd, _ds) \
1690 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1691 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1692 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1693
1694 struct ath_desc *ds;
1695 struct ath_buf *bf;
1696 int i, bsize, error;
1697
1698 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1699 name, nbuf, ndesc);
1700
1701 /* ath_desc must be a multiple of DWORDs */
1702 if ((sizeof(struct ath_desc) % 4) != 0) {
1703 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1704 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1705 error = -ENOMEM;
1706 goto fail;
1707 }
1708
1709 dd->dd_name = name;
1710 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1711
1712 /*
1713 * Need additional DMA memory because we can't use
1714 * descriptors that cross the 4K page boundary. Assume
1715 * one skipped descriptor per 4K page.
1716 */
1717 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1718 u32 ndesc_skipped =
1719 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1720 u32 dma_len;
1721
1722 while (ndesc_skipped) {
1723 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1724 dd->dd_desc_len += dma_len;
1725
1726 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1727 };
1728 }
1729
1730 /* allocate descriptors */
1731 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1732 dd->dd_desc_len,
1733 &dd->dd_desc_paddr);
1734 if (dd->dd_desc == NULL) {
1735 error = -ENOMEM;
1736 goto fail;
1737 }
1738 ds = dd->dd_desc;
1739 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1740 dd->dd_name, ds, (u32) dd->dd_desc_len,
1741 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1742
1743 /* allocate buffers */
1744 bsize = sizeof(struct ath_buf) * nbuf;
1745 bf = kmalloc(bsize, GFP_KERNEL);
1746 if (bf == NULL) {
1747 error = -ENOMEM;
1748 goto fail2;
1749 }
1750 memset(bf, 0, bsize);
1751 dd->dd_bufptr = bf;
1752
1753 INIT_LIST_HEAD(head);
1754 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1755 bf->bf_desc = ds;
1756 bf->bf_daddr = DS2PHYS(dd, ds);
1757
1758 if (!(sc->sc_ah->ah_caps.hw_caps &
1759 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1760 /*
1761 * Skip descriptor addresses which can cause 4KB
1762 * boundary crossing (addr + length) with a 32 dword
1763 * descriptor fetch.
1764 */
1765 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1766 ASSERT((caddr_t) bf->bf_desc <
1767 ((caddr_t) dd->dd_desc +
1768 dd->dd_desc_len));
1769
1770 ds += ndesc;
1771 bf->bf_desc = ds;
1772 bf->bf_daddr = DS2PHYS(dd, ds);
1773 }
1774 }
1775 list_add_tail(&bf->list, head);
1776 }
1777 return 0;
1778 fail2:
1779 pci_free_consistent(sc->pdev,
1780 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1781 fail:
1782 memset(dd, 0, sizeof(*dd));
1783 return error;
1784 #undef ATH_DESC_4KB_BOUND_CHECK
1785 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1786 #undef DS2PHYS
1787 }
1788
1789 void ath_descdma_cleanup(struct ath_softc *sc,
1790 struct ath_descdma *dd,
1791 struct list_head *head)
1792 {
1793 pci_free_consistent(sc->pdev,
1794 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1795
1796 INIT_LIST_HEAD(head);
1797 kfree(dd->dd_bufptr);
1798 memset(dd, 0, sizeof(*dd));
1799 }
1800
1801 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1802 {
1803 int qnum;
1804
1805 switch (queue) {
1806 case 0:
1807 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1808 break;
1809 case 1:
1810 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1811 break;
1812 case 2:
1813 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1814 break;
1815 case 3:
1816 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1817 break;
1818 default:
1819 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1820 break;
1821 }
1822
1823 return qnum;
1824 }
1825
1826 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1827 {
1828 int qnum;
1829
1830 switch (queue) {
1831 case ATH9K_WME_AC_VO:
1832 qnum = 0;
1833 break;
1834 case ATH9K_WME_AC_VI:
1835 qnum = 1;
1836 break;
1837 case ATH9K_WME_AC_BE:
1838 qnum = 2;
1839 break;
1840 case ATH9K_WME_AC_BK:
1841 qnum = 3;
1842 break;
1843 default:
1844 qnum = -1;
1845 break;
1846 }
1847
1848 return qnum;
1849 }
1850
1851 /**********************/
1852 /* mac80211 callbacks */
1853 /**********************/
1854
1855 static int ath9k_start(struct ieee80211_hw *hw)
1856 {
1857 struct ath_softc *sc = hw->priv;
1858 struct ieee80211_channel *curchan = hw->conf.channel;
1859 struct ath9k_channel *init_channel;
1860 int error = 0, pos, status;
1861
1862 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1863 "initial channel: %d MHz\n", curchan->center_freq);
1864
1865 /* setup initial channel */
1866
1867 pos = ath_get_channel(sc, curchan);
1868 if (pos == -1) {
1869 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n", curchan->center_freq);
1870 error = -EINVAL;
1871 goto error;
1872 }
1873
1874 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1875 sc->sc_ah->ah_channels[pos].chanmode =
1876 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1877 init_channel = &sc->sc_ah->ah_channels[pos];
1878
1879 /* Reset SERDES registers */
1880 ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1881
1882 /*
1883 * The basic interface to setting the hardware in a good
1884 * state is ``reset''. On return the hardware is known to
1885 * be powered up and with interrupts disabled. This must
1886 * be followed by initialization of the appropriate bits
1887 * and then setup of the interrupt mask.
1888 */
1889 spin_lock_bh(&sc->sc_resetlock);
1890 if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1891 sc->tx_chan_width,
1892 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1893 sc->sc_ht_extprotspacing, false, &status)) {
1894 DPRINTF(sc, ATH_DBG_FATAL,
1895 "Unable to reset hardware; hal status %u "
1896 "(freq %u flags 0x%x)\n", status,
1897 init_channel->channel, init_channel->channelFlags);
1898 error = -EIO;
1899 spin_unlock_bh(&sc->sc_resetlock);
1900 goto error;
1901 }
1902 spin_unlock_bh(&sc->sc_resetlock);
1903
1904 /*
1905 * This is needed only to setup initial state
1906 * but it's best done after a reset.
1907 */
1908 ath_update_txpow(sc);
1909
1910 /*
1911 * Setup the hardware after reset:
1912 * The receive engine is set going.
1913 * Frame transmit is handled entirely
1914 * in the frame output path; there's nothing to do
1915 * here except setup the interrupt mask.
1916 */
1917 if (ath_startrecv(sc) != 0) {
1918 DPRINTF(sc, ATH_DBG_FATAL,
1919 "Unable to start recv logic\n");
1920 error = -EIO;
1921 goto error;
1922 }
1923
1924 /* Setup our intr mask. */
1925 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1926 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1927 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1928
1929 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1930 sc->sc_imask |= ATH9K_INT_GTT;
1931
1932 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1933 sc->sc_imask |= ATH9K_INT_CST;
1934
1935 /*
1936 * Enable MIB interrupts when there are hardware phy counters.
1937 * Note we only do this (at the moment) for station mode.
1938 */
1939 if (ath9k_hw_phycounters(sc->sc_ah) &&
1940 ((sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) ||
1941 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC)))
1942 sc->sc_imask |= ATH9K_INT_MIB;
1943 /*
1944 * Some hardware processes the TIM IE and fires an
1945 * interrupt when the TIM bit is set. For hardware
1946 * that does, if not overridden by configuration,
1947 * enable the TIM interrupt when operating as station.
1948 */
1949 if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1950 (sc->sc_ah->ah_opmode == NL80211_IFTYPE_STATION) &&
1951 !sc->sc_config.swBeaconProcess)
1952 sc->sc_imask |= ATH9K_INT_TIM;
1953
1954 ath_setcurmode(sc, &hw->conf);
1955
1956 sc->sc_flags &= ~SC_OP_INVALID;
1957
1958 /* Disable BMISS interrupt when we're not associated */
1959 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1960 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1961
1962 ieee80211_wake_queues(sc->hw);
1963
1964 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1965 error = ath_start_rfkill_poll(sc);
1966 #endif
1967
1968 error:
1969 return error;
1970 }
1971
1972 static int ath9k_tx(struct ieee80211_hw *hw,
1973 struct sk_buff *skb)
1974 {
1975 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1976 struct ath_softc *sc = hw->priv;
1977 struct ath_tx_control txctl;
1978 int hdrlen, padsize;
1979
1980 memset(&txctl, 0, sizeof(struct ath_tx_control));
1981
1982 /*
1983 * As a temporary workaround, assign seq# here; this will likely need
1984 * to be cleaned up to work better with Beacon transmission and virtual
1985 * BSSes.
1986 */
1987 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1988 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1989 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1990 sc->tx.seq_no += 0x10;
1991 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1992 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1993 }
1994
1995 /* Add the padding after the header if this is not already done */
1996 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1997 if (hdrlen & 3) {
1998 padsize = hdrlen % 4;
1999 if (skb_headroom(skb) < padsize)
2000 return -1;
2001 skb_push(skb, padsize);
2002 memmove(skb->data, skb->data + padsize, hdrlen);
2003 }
2004
2005 /* Check if a tx queue is available */
2006
2007 txctl.txq = ath_test_get_txq(sc, skb);
2008 if (!txctl.txq)
2009 goto exit;
2010
2011 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2012
2013 if (ath_tx_start(sc, skb, &txctl) != 0) {
2014 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2015 goto exit;
2016 }
2017
2018 return 0;
2019 exit:
2020 dev_kfree_skb_any(skb);
2021 return 0;
2022 }
2023
2024 static void ath9k_stop(struct ieee80211_hw *hw)
2025 {
2026 struct ath_softc *sc = hw->priv;
2027
2028 if (sc->sc_flags & SC_OP_INVALID) {
2029 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2030 return;
2031 }
2032
2033 DPRINTF(sc, ATH_DBG_CONFIG, "Cleaning up\n");
2034
2035 ieee80211_stop_queues(sc->hw);
2036
2037 /* make sure h/w will not generate any interrupt
2038 * before setting the invalid flag. */
2039 ath9k_hw_set_interrupts(sc->sc_ah, 0);
2040
2041 if (!(sc->sc_flags & SC_OP_INVALID)) {
2042 ath_draintxq(sc, false);
2043 ath_stoprecv(sc);
2044 ath9k_hw_phy_disable(sc->sc_ah);
2045 } else
2046 sc->rx.rxlink = NULL;
2047
2048 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2049 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2050 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2051 #endif
2052 /* disable HAL and put h/w to sleep */
2053 ath9k_hw_disable(sc->sc_ah);
2054 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2055
2056 sc->sc_flags |= SC_OP_INVALID;
2057
2058 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2059 }
2060
2061 static int ath9k_add_interface(struct ieee80211_hw *hw,
2062 struct ieee80211_if_init_conf *conf)
2063 {
2064 struct ath_softc *sc = hw->priv;
2065 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2066 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2067
2068 /* Support only vap for now */
2069
2070 if (sc->sc_nvaps)
2071 return -ENOBUFS;
2072
2073 switch (conf->type) {
2074 case NL80211_IFTYPE_STATION:
2075 ic_opmode = NL80211_IFTYPE_STATION;
2076 break;
2077 case NL80211_IFTYPE_ADHOC:
2078 ic_opmode = NL80211_IFTYPE_ADHOC;
2079 break;
2080 case NL80211_IFTYPE_AP:
2081 ic_opmode = NL80211_IFTYPE_AP;
2082 break;
2083 default:
2084 DPRINTF(sc, ATH_DBG_FATAL,
2085 "Interface type %d not yet supported\n", conf->type);
2086 return -EOPNOTSUPP;
2087 }
2088
2089 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VAP of type: %d\n", ic_opmode);
2090
2091 /* Set the VAP opmode */
2092 avp->av_opmode = ic_opmode;
2093 avp->av_bslot = -1;
2094
2095 if (ic_opmode == NL80211_IFTYPE_AP)
2096 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2097
2098 sc->sc_vaps[0] = conf->vif;
2099 sc->sc_nvaps++;
2100
2101 /* Set the device opmode */
2102 sc->sc_ah->ah_opmode = ic_opmode;
2103
2104 if (conf->type == NL80211_IFTYPE_AP) {
2105 /* TODO: is this a suitable place to start ANI for AP mode? */
2106 /* Start ANI */
2107 mod_timer(&sc->sc_ani.timer,
2108 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2109 }
2110
2111 return 0;
2112 }
2113
2114 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2115 struct ieee80211_if_init_conf *conf)
2116 {
2117 struct ath_softc *sc = hw->priv;
2118 struct ath_vap *avp = (void *)conf->vif->drv_priv;
2119
2120 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2121
2122 /* Stop ANI */
2123 del_timer_sync(&sc->sc_ani.timer);
2124
2125 /* Reclaim beacon resources */
2126 if (sc->sc_ah->ah_opmode == NL80211_IFTYPE_AP ||
2127 sc->sc_ah->ah_opmode == NL80211_IFTYPE_ADHOC) {
2128 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2129 ath_beacon_return(sc, avp);
2130 }
2131
2132 sc->sc_flags &= ~SC_OP_BEACONS;
2133
2134 sc->sc_vaps[0] = NULL;
2135 sc->sc_nvaps--;
2136 }
2137
2138 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2139 {
2140 struct ath_softc *sc = hw->priv;
2141 struct ieee80211_conf *conf = &hw->conf;
2142
2143 mutex_lock(&sc->mutex);
2144 if (changed & (IEEE80211_CONF_CHANGE_CHANNEL |
2145 IEEE80211_CONF_CHANGE_HT)) {
2146 struct ieee80211_channel *curchan = hw->conf.channel;
2147 int pos;
2148
2149 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2150 curchan->center_freq);
2151
2152 pos = ath_get_channel(sc, curchan);
2153 if (pos == -1) {
2154 DPRINTF(sc, ATH_DBG_FATAL, "Invalid channel: %d\n",
2155 curchan->center_freq);
2156 mutex_unlock(&sc->mutex);
2157 return -EINVAL;
2158 }
2159
2160 sc->tx_chan_width = ATH9K_HT_MACMODE_20;
2161 sc->sc_ah->ah_channels[pos].chanmode =
2162 (curchan->band == IEEE80211_BAND_2GHZ) ?
2163 CHANNEL_G : CHANNEL_A;
2164
2165 if (conf->ht.enabled) {
2166 if (conf->ht.channel_type == NL80211_CHAN_HT40PLUS ||
2167 conf->ht.channel_type == NL80211_CHAN_HT40MINUS)
2168 sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
2169
2170 sc->sc_ah->ah_channels[pos].chanmode =
2171 ath_get_extchanmode(sc, curchan,
2172 conf->ht.channel_type);
2173 }
2174
2175 ath_update_chainmask(sc, conf->ht.enabled);
2176
2177 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0) {
2178 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2179 mutex_unlock(&sc->mutex);
2180 return -EINVAL;
2181 }
2182 }
2183
2184 if (changed & IEEE80211_CONF_CHANGE_POWER)
2185 sc->sc_config.txpowlimit = 2 * conf->power_level;
2186
2187 mutex_unlock(&sc->mutex);
2188 return 0;
2189 }
2190
2191 static int ath9k_config_interface(struct ieee80211_hw *hw,
2192 struct ieee80211_vif *vif,
2193 struct ieee80211_if_conf *conf)
2194 {
2195 struct ath_softc *sc = hw->priv;
2196 struct ath_hal *ah = sc->sc_ah;
2197 struct ath_vap *avp = (void *)vif->drv_priv;
2198 u32 rfilt = 0;
2199 int error, i;
2200
2201 /* TODO: Need to decide which hw opmode to use for multi-interface
2202 * cases */
2203 if (vif->type == NL80211_IFTYPE_AP &&
2204 ah->ah_opmode != NL80211_IFTYPE_AP) {
2205 ah->ah_opmode = NL80211_IFTYPE_STATION;
2206 ath9k_hw_setopmode(ah);
2207 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2208 /* Request full reset to get hw opmode changed properly */
2209 sc->sc_flags |= SC_OP_FULL_RESET;
2210 }
2211
2212 if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2213 !is_zero_ether_addr(conf->bssid)) {
2214 switch (vif->type) {
2215 case NL80211_IFTYPE_STATION:
2216 case NL80211_IFTYPE_ADHOC:
2217 /* Set BSSID */
2218 memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2219 sc->sc_curaid = 0;
2220 ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2221 sc->sc_curaid);
2222
2223 /* Set aggregation protection mode parameters */
2224 sc->sc_config.ath_aggr_prot = 0;
2225
2226 DPRINTF(sc, ATH_DBG_CONFIG,
2227 "RX filter 0x%x bssid %pM aid 0x%x\n",
2228 rfilt, sc->sc_curbssid, sc->sc_curaid);
2229
2230 /* need to reconfigure the beacon */
2231 sc->sc_flags &= ~SC_OP_BEACONS ;
2232
2233 break;
2234 default:
2235 break;
2236 }
2237 }
2238
2239 if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2240 ((vif->type == NL80211_IFTYPE_ADHOC) ||
2241 (vif->type == NL80211_IFTYPE_AP))) {
2242 /*
2243 * Allocate and setup the beacon frame.
2244 *
2245 * Stop any previous beacon DMA. This may be
2246 * necessary, for example, when an ibss merge
2247 * causes reconfiguration; we may be called
2248 * with beacon transmission active.
2249 */
2250 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2251
2252 error = ath_beacon_alloc(sc, 0);
2253 if (error != 0)
2254 return error;
2255
2256 ath_beacon_sync(sc, 0);
2257 }
2258
2259 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2260 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2261 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2262 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2263 ath9k_hw_keysetmac(sc->sc_ah,
2264 (u16)i,
2265 sc->sc_curbssid);
2266 }
2267
2268 /* Only legacy IBSS for now */
2269 if (vif->type == NL80211_IFTYPE_ADHOC)
2270 ath_update_chainmask(sc, 0);
2271
2272 return 0;
2273 }
2274
2275 #define SUPPORTED_FILTERS \
2276 (FIF_PROMISC_IN_BSS | \
2277 FIF_ALLMULTI | \
2278 FIF_CONTROL | \
2279 FIF_OTHER_BSS | \
2280 FIF_BCN_PRBRESP_PROMISC | \
2281 FIF_FCSFAIL)
2282
2283 /* FIXME: sc->sc_full_reset ? */
2284 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2285 unsigned int changed_flags,
2286 unsigned int *total_flags,
2287 int mc_count,
2288 struct dev_mc_list *mclist)
2289 {
2290 struct ath_softc *sc = hw->priv;
2291 u32 rfilt;
2292
2293 changed_flags &= SUPPORTED_FILTERS;
2294 *total_flags &= SUPPORTED_FILTERS;
2295
2296 sc->rx.rxfilter = *total_flags;
2297 rfilt = ath_calcrxfilter(sc);
2298 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2299
2300 if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2301 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2302 ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2303 }
2304
2305 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2306 }
2307
2308 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2309 struct ieee80211_vif *vif,
2310 enum sta_notify_cmd cmd,
2311 struct ieee80211_sta *sta)
2312 {
2313 struct ath_softc *sc = hw->priv;
2314
2315 switch (cmd) {
2316 case STA_NOTIFY_ADD:
2317 ath_node_attach(sc, sta);
2318 break;
2319 case STA_NOTIFY_REMOVE:
2320 ath_node_detach(sc, sta);
2321 break;
2322 default:
2323 break;
2324 }
2325 }
2326
2327 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2328 u16 queue,
2329 const struct ieee80211_tx_queue_params *params)
2330 {
2331 struct ath_softc *sc = hw->priv;
2332 struct ath9k_tx_queue_info qi;
2333 int ret = 0, qnum;
2334
2335 if (queue >= WME_NUM_AC)
2336 return 0;
2337
2338 qi.tqi_aifs = params->aifs;
2339 qi.tqi_cwmin = params->cw_min;
2340 qi.tqi_cwmax = params->cw_max;
2341 qi.tqi_burstTime = params->txop;
2342 qnum = ath_get_hal_qnum(queue, sc);
2343
2344 DPRINTF(sc, ATH_DBG_CONFIG,
2345 "Configure tx [queue/halq] [%d/%d], "
2346 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2347 queue, qnum, params->aifs, params->cw_min,
2348 params->cw_max, params->txop);
2349
2350 ret = ath_txq_update(sc, qnum, &qi);
2351 if (ret)
2352 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2353
2354 return ret;
2355 }
2356
2357 static int ath9k_set_key(struct ieee80211_hw *hw,
2358 enum set_key_cmd cmd,
2359 const u8 *local_addr,
2360 const u8 *addr,
2361 struct ieee80211_key_conf *key)
2362 {
2363 struct ath_softc *sc = hw->priv;
2364 int ret = 0;
2365
2366 DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2367
2368 switch (cmd) {
2369 case SET_KEY:
2370 ret = ath_key_config(sc, addr, key);
2371 if (ret >= 0) {
2372 key->hw_key_idx = ret;
2373 /* push IV and Michael MIC generation to stack */
2374 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2375 if (key->alg == ALG_TKIP)
2376 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2377 ret = 0;
2378 }
2379 break;
2380 case DISABLE_KEY:
2381 ath_key_delete(sc, key);
2382 break;
2383 default:
2384 ret = -EINVAL;
2385 }
2386
2387 return ret;
2388 }
2389
2390 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2391 struct ieee80211_vif *vif,
2392 struct ieee80211_bss_conf *bss_conf,
2393 u32 changed)
2394 {
2395 struct ath_softc *sc = hw->priv;
2396
2397 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2398 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2399 bss_conf->use_short_preamble);
2400 if (bss_conf->use_short_preamble)
2401 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2402 else
2403 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2404 }
2405
2406 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2407 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2408 bss_conf->use_cts_prot);
2409 if (bss_conf->use_cts_prot &&
2410 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2411 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2412 else
2413 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2414 }
2415
2416 if (changed & BSS_CHANGED_ASSOC) {
2417 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2418 bss_conf->assoc);
2419 ath9k_bss_assoc_info(sc, vif, bss_conf);
2420 }
2421 }
2422
2423 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2424 {
2425 u64 tsf;
2426 struct ath_softc *sc = hw->priv;
2427 struct ath_hal *ah = sc->sc_ah;
2428
2429 tsf = ath9k_hw_gettsf64(ah);
2430
2431 return tsf;
2432 }
2433
2434 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2435 {
2436 struct ath_softc *sc = hw->priv;
2437 struct ath_hal *ah = sc->sc_ah;
2438
2439 ath9k_hw_reset_tsf(ah);
2440 }
2441
2442 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2443 enum ieee80211_ampdu_mlme_action action,
2444 struct ieee80211_sta *sta,
2445 u16 tid, u16 *ssn)
2446 {
2447 struct ath_softc *sc = hw->priv;
2448 int ret = 0;
2449
2450 switch (action) {
2451 case IEEE80211_AMPDU_RX_START:
2452 if (!(sc->sc_flags & SC_OP_RXAGGR))
2453 ret = -ENOTSUPP;
2454 break;
2455 case IEEE80211_AMPDU_RX_STOP:
2456 break;
2457 case IEEE80211_AMPDU_TX_START:
2458 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2459 if (ret < 0)
2460 DPRINTF(sc, ATH_DBG_FATAL,
2461 "Unable to start TX aggregation\n");
2462 else
2463 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2464 break;
2465 case IEEE80211_AMPDU_TX_STOP:
2466 ret = ath_tx_aggr_stop(sc, sta, tid);
2467 if (ret < 0)
2468 DPRINTF(sc, ATH_DBG_FATAL,
2469 "Unable to stop TX aggregation\n");
2470
2471 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2472 break;
2473 case IEEE80211_AMPDU_TX_RESUME:
2474 ath_tx_aggr_resume(sc, sta, tid);
2475 break;
2476 default:
2477 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2478 }
2479
2480 return ret;
2481 }
2482
2483 static struct ieee80211_ops ath9k_ops = {
2484 .tx = ath9k_tx,
2485 .start = ath9k_start,
2486 .stop = ath9k_stop,
2487 .add_interface = ath9k_add_interface,
2488 .remove_interface = ath9k_remove_interface,
2489 .config = ath9k_config,
2490 .config_interface = ath9k_config_interface,
2491 .configure_filter = ath9k_configure_filter,
2492 .sta_notify = ath9k_sta_notify,
2493 .conf_tx = ath9k_conf_tx,
2494 .bss_info_changed = ath9k_bss_info_changed,
2495 .set_key = ath9k_set_key,
2496 .get_tsf = ath9k_get_tsf,
2497 .reset_tsf = ath9k_reset_tsf,
2498 .ampdu_action = ath9k_ampdu_action,
2499 };
2500
2501 static struct {
2502 u32 version;
2503 const char * name;
2504 } ath_mac_bb_names[] = {
2505 { AR_SREV_VERSION_5416_PCI, "5416" },
2506 { AR_SREV_VERSION_5416_PCIE, "5418" },
2507 { AR_SREV_VERSION_9100, "9100" },
2508 { AR_SREV_VERSION_9160, "9160" },
2509 { AR_SREV_VERSION_9280, "9280" },
2510 { AR_SREV_VERSION_9285, "9285" }
2511 };
2512
2513 static struct {
2514 u16 version;
2515 const char * name;
2516 } ath_rf_names[] = {
2517 { 0, "5133" },
2518 { AR_RAD5133_SREV_MAJOR, "5133" },
2519 { AR_RAD5122_SREV_MAJOR, "5122" },
2520 { AR_RAD2133_SREV_MAJOR, "2133" },
2521 { AR_RAD2122_SREV_MAJOR, "2122" }
2522 };
2523
2524 /*
2525 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2526 */
2527 static const char *
2528 ath_mac_bb_name(u32 mac_bb_version)
2529 {
2530 int i;
2531
2532 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2533 if (ath_mac_bb_names[i].version == mac_bb_version) {
2534 return ath_mac_bb_names[i].name;
2535 }
2536 }
2537
2538 return "????";
2539 }
2540
2541 /*
2542 * Return the RF name. "????" is returned if the RF is unknown.
2543 */
2544 static const char *
2545 ath_rf_name(u16 rf_version)
2546 {
2547 int i;
2548
2549 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2550 if (ath_rf_names[i].version == rf_version) {
2551 return ath_rf_names[i].name;
2552 }
2553 }
2554
2555 return "????";
2556 }
2557
2558 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2559 {
2560 void __iomem *mem;
2561 struct ath_softc *sc;
2562 struct ieee80211_hw *hw;
2563 u8 csz;
2564 u32 val;
2565 int ret = 0;
2566 struct ath_hal *ah;
2567
2568 if (pci_enable_device(pdev))
2569 return -EIO;
2570
2571 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2572
2573 if (ret) {
2574 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2575 goto bad;
2576 }
2577
2578 ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2579
2580 if (ret) {
2581 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2582 "DMA enable failed\n");
2583 goto bad;
2584 }
2585
2586 /*
2587 * Cache line size is used to size and align various
2588 * structures used to communicate with the hardware.
2589 */
2590 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2591 if (csz == 0) {
2592 /*
2593 * Linux 2.4.18 (at least) writes the cache line size
2594 * register as a 16-bit wide register which is wrong.
2595 * We must have this setup properly for rx buffer
2596 * DMA to work so force a reasonable value here if it
2597 * comes up zero.
2598 */
2599 csz = L1_CACHE_BYTES / sizeof(u32);
2600 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2601 }
2602 /*
2603 * The default setting of latency timer yields poor results,
2604 * set it to the value used by other systems. It may be worth
2605 * tweaking this setting more.
2606 */
2607 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2608
2609 pci_set_master(pdev);
2610
2611 /*
2612 * Disable the RETRY_TIMEOUT register (0x41) to keep
2613 * PCI Tx retries from interfering with C3 CPU state.
2614 */
2615 pci_read_config_dword(pdev, 0x40, &val);
2616 if ((val & 0x0000ff00) != 0)
2617 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2618
2619 ret = pci_request_region(pdev, 0, "ath9k");
2620 if (ret) {
2621 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2622 ret = -ENODEV;
2623 goto bad;
2624 }
2625
2626 mem = pci_iomap(pdev, 0, 0);
2627 if (!mem) {
2628 printk(KERN_ERR "PCI memory map error\n") ;
2629 ret = -EIO;
2630 goto bad1;
2631 }
2632
2633 hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2634 if (hw == NULL) {
2635 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2636 goto bad2;
2637 }
2638
2639 SET_IEEE80211_DEV(hw, &pdev->dev);
2640 pci_set_drvdata(pdev, hw);
2641
2642 sc = hw->priv;
2643 sc->hw = hw;
2644 sc->pdev = pdev;
2645 sc->mem = mem;
2646
2647 if (ath_attach(id->device, sc) != 0) {
2648 ret = -ENODEV;
2649 goto bad3;
2650 }
2651
2652 /* setup interrupt service routine */
2653
2654 if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2655 printk(KERN_ERR "%s: request_irq failed\n",
2656 wiphy_name(hw->wiphy));
2657 ret = -EIO;
2658 goto bad4;
2659 }
2660
2661 ah = sc->sc_ah;
2662 printk(KERN_INFO
2663 "%s: Atheros AR%s MAC/BB Rev:%x "
2664 "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2665 wiphy_name(hw->wiphy),
2666 ath_mac_bb_name(ah->ah_macVersion),
2667 ah->ah_macRev,
2668 ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2669 ah->ah_phyRev,
2670 (unsigned long)mem, pdev->irq);
2671
2672 return 0;
2673 bad4:
2674 ath_detach(sc);
2675 bad3:
2676 ieee80211_free_hw(hw);
2677 bad2:
2678 pci_iounmap(pdev, mem);
2679 bad1:
2680 pci_release_region(pdev, 0);
2681 bad:
2682 pci_disable_device(pdev);
2683 return ret;
2684 }
2685
2686 static void ath_pci_remove(struct pci_dev *pdev)
2687 {
2688 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2689 struct ath_softc *sc = hw->priv;
2690
2691 ath_detach(sc);
2692 if (pdev->irq)
2693 free_irq(pdev->irq, sc);
2694 pci_iounmap(pdev, sc->mem);
2695 pci_release_region(pdev, 0);
2696 pci_disable_device(pdev);
2697 ieee80211_free_hw(hw);
2698 }
2699
2700 #ifdef CONFIG_PM
2701
2702 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2703 {
2704 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2705 struct ath_softc *sc = hw->priv;
2706
2707 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2708
2709 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2710 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2711 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2712 #endif
2713
2714 pci_save_state(pdev);
2715 pci_disable_device(pdev);
2716 pci_set_power_state(pdev, 3);
2717
2718 return 0;
2719 }
2720
2721 static int ath_pci_resume(struct pci_dev *pdev)
2722 {
2723 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2724 struct ath_softc *sc = hw->priv;
2725 u32 val;
2726 int err;
2727
2728 err = pci_enable_device(pdev);
2729 if (err)
2730 return err;
2731 pci_restore_state(pdev);
2732 /*
2733 * Suspend/Resume resets the PCI configuration space, so we have to
2734 * re-disable the RETRY_TIMEOUT register (0x41) to keep
2735 * PCI Tx retries from interfering with C3 CPU state
2736 */
2737 pci_read_config_dword(pdev, 0x40, &val);
2738 if ((val & 0x0000ff00) != 0)
2739 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2740
2741 /* Enable LED */
2742 ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2743 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2744 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2745
2746 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2747 /*
2748 * check the h/w rfkill state on resume
2749 * and start the rfkill poll timer
2750 */
2751 if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2752 queue_delayed_work(sc->hw->workqueue,
2753 &sc->rf_kill.rfkill_poll, 0);
2754 #endif
2755
2756 return 0;
2757 }
2758
2759 #endif /* CONFIG_PM */
2760
2761 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2762
2763 static struct pci_driver ath_pci_driver = {
2764 .name = "ath9k",
2765 .id_table = ath_pci_id_table,
2766 .probe = ath_pci_probe,
2767 .remove = ath_pci_remove,
2768 #ifdef CONFIG_PM
2769 .suspend = ath_pci_suspend,
2770 .resume = ath_pci_resume,
2771 #endif /* CONFIG_PM */
2772 };
2773
2774 static int __init init_ath_pci(void)
2775 {
2776 int error;
2777
2778 printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2779
2780 /* Register rate control algorithm */
2781 error = ath_rate_control_register();
2782 if (error != 0) {
2783 printk(KERN_ERR
2784 "Unable to register rate control algorithm: %d\n",
2785 error);
2786 ath_rate_control_unregister();
2787 return error;
2788 }
2789
2790 if (pci_register_driver(&ath_pci_driver) < 0) {
2791 printk(KERN_ERR
2792 "ath_pci: No devices found, driver not installed.\n");
2793 ath_rate_control_unregister();
2794 pci_unregister_driver(&ath_pci_driver);
2795 return -ENODEV;
2796 }
2797
2798 return 0;
2799 }
2800 module_init(init_ath_pci);
2801
2802 static void __exit exit_ath_pci(void)
2803 {
2804 ath_rate_control_unregister();
2805 pci_unregister_driver(&ath_pci_driver);
2806 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2807 }
2808 module_exit(exit_ath_pci);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree