1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object
{
87 struct page
**page_list
;
88 drm_dma_handle_t
*handle
;
89 struct drm_gem_object
*cur_obj
;
92 typedef struct _drm_i915_ring_buffer
{
99 struct drm_gem_object
*ring_obj
;
100 } drm_i915_ring_buffer_t
;
103 struct mem_block
*next
;
104 struct mem_block
*prev
;
107 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header
;
111 struct opregion_acpi
;
112 struct opregion_swsci
;
113 struct opregion_asle
;
115 struct intel_opregion
{
116 struct opregion_header
*header
;
117 struct opregion_acpi
*acpi
;
118 struct opregion_swsci
*swsci
;
119 struct opregion_asle
*asle
;
123 struct drm_i915_master_private
{
124 drm_local_map_t
*sarea
;
125 struct _drm_i915_sarea
*sarea_priv
;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg
{
130 struct drm_gem_object
*obj
;
133 struct sdvo_device_mapping
{
140 struct drm_i915_error_state
{
156 struct drm_i915_display_funcs
{
157 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
158 bool (*fbc_enabled
)(struct drm_crtc
*crtc
);
159 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
160 void (*disable_fbc
)(struct drm_device
*dev
);
161 int (*get_display_clock_speed
)(struct drm_device
*dev
);
162 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
163 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
164 int planeb_clock
, int sr_hdisplay
, int pixel_size
);
165 /* clock updates for mode set */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
173 struct intel_overlay
;
175 typedef struct drm_i915_private
{
176 struct drm_device
*dev
;
182 struct pci_dev
*bridge_dev
;
183 drm_i915_ring_buffer_t ring
;
185 drm_dma_handle_t
*status_page_dmah
;
186 void *hw_status_page
;
187 dma_addr_t dma_status_page
;
189 unsigned int status_gfx_addr
;
190 drm_local_map_t hws_map
;
191 struct drm_gem_object
*hws_obj
;
192 struct drm_gem_object
*pwrctx
;
194 struct resource mch_res
;
202 wait_queue_head_t irq_queue
;
203 atomic_t irq_received
;
204 /** Protects user_irq_refcount and irq_mask_reg */
205 spinlock_t user_irq_lock
;
206 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
207 int user_irq_refcount
;
209 /** Cached value of IMR to avoid reads in updating the bitfield */
212 /** splitted irq regs for graphics and display engine on IGDNG,
213 irq_mask_reg is still used for display irq. */
215 u32 gt_irq_enable_reg
;
216 u32 de_irq_enable_reg
;
218 u32 hotplug_supported_mask
;
219 struct work_struct hotplug_work
;
221 int tex_lru_log_granularity
;
222 int allow_batchbuffer
;
223 struct mem_block
*agp_heap
;
224 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
227 /* For hangcheck timer */
228 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
229 struct timer_list hangcheck_timer
;
233 bool cursor_needs_physical
;
237 unsigned long cfb_size
;
238 unsigned long cfb_pitch
;
244 struct intel_opregion opregion
;
247 struct intel_overlay
*overlay
;
250 int backlight_duty_cycle
; /* restore backlight to this value */
251 bool panel_wants_dither
;
252 struct drm_display_mode
*panel_fixed_mode
;
253 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
254 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
256 /* Feature bits from the VBIOS */
257 unsigned int int_tv_support
:1;
258 unsigned int lvds_dither
:1;
259 unsigned int lvds_vbt
:1;
260 unsigned int int_crt_support
:1;
261 unsigned int lvds_use_ssc
:1;
262 unsigned int edp_support
:1;
265 struct notifier_block lid_notifier
;
267 int crt_ddc_bus
; /* -1 = unknown, else GPIO to use for CRT DDC */
268 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
269 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
270 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
272 unsigned int fsb_freq
, mem_freq
;
274 spinlock_t error_lock
;
275 struct drm_i915_error_state
*first_error
;
276 struct work_struct error_work
;
277 struct workqueue_struct
*wq
;
279 /* Display functions */
280 struct drm_i915_display_funcs display
;
288 u32 saveRENDERSTANDBY
;
306 u32 saveTRANS_HTOTAL_A
;
307 u32 saveTRANS_HBLANK_A
;
308 u32 saveTRANS_HSYNC_A
;
309 u32 saveTRANS_VTOTAL_A
;
310 u32 saveTRANS_VBLANK_A
;
311 u32 saveTRANS_VSYNC_A
;
319 u32 savePFIT_PGM_RATIOS
;
320 u32 saveBLC_HIST_CTL
;
322 u32 saveBLC_PWM_CTL2
;
323 u32 saveBLC_CPU_PWM_CTL
;
324 u32 saveBLC_CPU_PWM_CTL2
;
336 u32 saveTRANS_HTOTAL_B
;
337 u32 saveTRANS_HBLANK_B
;
338 u32 saveTRANS_HSYNC_B
;
339 u32 saveTRANS_VTOTAL_B
;
340 u32 saveTRANS_VBLANK_B
;
341 u32 saveTRANS_VSYNC_B
;
355 u32 savePP_ON_DELAYS
;
356 u32 savePP_OFF_DELAYS
;
364 u32 savePFIT_CONTROL
;
365 u32 save_palette_a
[256];
366 u32 save_palette_b
[256];
367 u32 saveDPFC_CB_BASE
;
368 u32 saveFBC_CFB_BASE
;
371 u32 saveFBC_CONTROL2
;
381 u32 saveCACHE_MODE_0
;
383 u32 saveDSPCLK_GATE_D
;
384 u32 saveMI_ARB_STATE
;
395 uint64_t saveFENCE
[16];
406 u32 savePIPEA_GMCH_DATA_M
;
407 u32 savePIPEB_GMCH_DATA_M
;
408 u32 savePIPEA_GMCH_DATA_N
;
409 u32 savePIPEB_GMCH_DATA_N
;
410 u32 savePIPEA_DP_LINK_M
;
411 u32 savePIPEB_DP_LINK_M
;
412 u32 savePIPEA_DP_LINK_N
;
413 u32 savePIPEB_DP_LINK_N
;
426 struct drm_mm gtt_space
;
428 struct io_mapping
*gtt_mapping
;
432 * Membership on list of all loaded devices, used to evict
433 * inactive buffers under memory pressure.
435 * Modifications should only be done whilst holding the
436 * shrink_list_lock spinlock.
438 struct list_head shrink_list
;
441 * List of objects currently involved in rendering from the
444 * Includes buffers having the contents of their GPU caches
445 * flushed, not necessarily primitives. last_rendering_seqno
446 * represents when the rendering involved will be completed.
448 * A reference is held on the buffer while on this list.
450 spinlock_t active_list_lock
;
451 struct list_head active_list
;
454 * List of objects which are not in the ringbuffer but which
455 * still have a write_domain which needs to be flushed before
458 * last_rendering_seqno is 0 while an object is in this list.
460 * A reference is held on the buffer while on this list.
462 struct list_head flushing_list
;
465 * LRU list of objects which are not in the ringbuffer and
466 * are ready to unbind, but are still in the GTT.
468 * last_rendering_seqno is 0 while an object is in this list.
470 * A reference is not held on the buffer while on this list,
471 * as merely being GTT-bound shouldn't prevent its being
472 * freed, and we'll pull it off the list in the free path.
474 struct list_head inactive_list
;
476 /** LRU list of objects with fence regs on them. */
477 struct list_head fence_list
;
480 * List of breadcrumbs associated with GPU requests currently
483 struct list_head request_list
;
486 * We leave the user IRQ off as much as possible,
487 * but this means that requests will finish and never
488 * be retired once the system goes idle. Set a timer to
489 * fire periodically while the ring is running. When it
490 * fires, go retire requests.
492 struct delayed_work retire_work
;
494 uint32_t next_gem_seqno
;
497 * Waiting sequence number, if any
499 uint32_t waiting_gem_seqno
;
502 * Last seq seen at irq time
504 uint32_t irq_gem_seqno
;
507 * Flag if the X Server, and thus DRM, is not currently in
508 * control of the device.
510 * This is set between LeaveVT and EnterVT. It needs to be
511 * replaced with a semaphore. It also needs to be
512 * transitioned away from for kernel modesetting.
517 * Flag if the hardware appears to be wedged.
519 * This is set when attempts to idle the device timeout.
520 * It prevents command submission from occuring and makes
521 * every pending request fail
525 /** Bit 6 swizzling required for X tiling */
526 uint32_t bit_6_swizzle_x
;
527 /** Bit 6 swizzling required for Y tiling */
528 uint32_t bit_6_swizzle_y
;
530 /* storage for physical objects */
531 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
533 struct sdvo_device_mapping sdvo_mappings
[2];
534 /* indicate whether the LVDS_BORDER should be enabled or not */
535 unsigned int lvds_border_bits
;
537 /* Reclocking support */
538 bool render_reclock_avail
;
539 bool lvds_downclock_avail
;
540 struct work_struct idle_work
;
541 struct timer_list idle_timer
;
544 } drm_i915_private_t
;
546 /** driver private structure attached to each drm_gem_object */
547 struct drm_i915_gem_object
{
548 struct drm_gem_object
*obj
;
550 /** Current space allocated to this object in the GTT, if any. */
551 struct drm_mm_node
*gtt_space
;
553 /** This object's place on the active/flushing/inactive lists */
554 struct list_head list
;
556 /** This object's place on the fenced object LRU */
557 struct list_head fence_list
;
560 * This is set if the object is on the active or flushing lists
561 * (has pending rendering), and is not set if it's on inactive (ready
567 * This is set if the object has been written to since last bound
572 /** AGP memory structure for our GTT binding. */
573 DRM_AGP_MEM
*agp_mem
;
579 * Current offset of the object in GTT space.
581 * This is the same as gtt_space->start
586 * Fake offset for use by mmap(2)
588 uint64_t mmap_offset
;
591 * Fence register bits (if any) for this object. Will be set
592 * as needed when mapped into the GTT.
593 * Protected by dev->struct_mutex.
597 /** How many users have pinned this object in GTT space */
600 /** Breadcrumb of last rendering to the buffer. */
601 uint32_t last_rendering_seqno
;
603 /** Current tiling mode for the object. */
604 uint32_t tiling_mode
;
607 /** Record of address bit 17 of each page at last unbind. */
610 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
614 * If present, while GEM_DOMAIN_CPU is in the read domain this array
615 * flags which individual pages are valid.
617 uint8_t *page_cpu_valid
;
619 /** User space pin count and filp owning the pin */
620 uint32_t user_pin_count
;
621 struct drm_file
*pin_filp
;
623 /** for phy allocated objects */
624 struct drm_i915_gem_phys_object
*phys_obj
;
627 * Used for checking the object doesn't appear more than once
628 * in an execbuffer object list.
633 * Advice: are the backing pages purgeable?
639 * Request queue structure.
641 * The request queue allows us to note sequence numbers that have been emitted
642 * and may be associated with active buffers to be retired.
644 * By keeping this list, we can avoid having to do questionable
645 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
646 * an emission time with seqnos for tracking how far ahead of the GPU we are.
648 struct drm_i915_gem_request
{
649 /** GEM sequence number associated with this request. */
652 /** Time at which this request was emitted, in jiffies. */
653 unsigned long emitted_jiffies
;
655 /** global list entry for this request */
656 struct list_head list
;
658 /** file_priv list entry for this request */
659 struct list_head client_list
;
662 struct drm_i915_file_private
{
664 struct list_head request_list
;
668 enum intel_chip_family
{
675 extern struct drm_ioctl_desc i915_ioctls
[];
676 extern int i915_max_ioctl
;
677 extern unsigned int i915_fbpercrtc
;
678 extern unsigned int i915_powersave
;
680 extern void i915_save_display(struct drm_device
*dev
);
681 extern void i915_restore_display(struct drm_device
*dev
);
682 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
683 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
686 extern void i915_kernel_lost_context(struct drm_device
* dev
);
687 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
688 extern int i915_driver_unload(struct drm_device
*);
689 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
690 extern void i915_driver_lastclose(struct drm_device
* dev
);
691 extern void i915_driver_preclose(struct drm_device
*dev
,
692 struct drm_file
*file_priv
);
693 extern void i915_driver_postclose(struct drm_device
*dev
,
694 struct drm_file
*file_priv
);
695 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
696 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
698 extern int i915_emit_box(struct drm_device
*dev
,
699 struct drm_clip_rect
*boxes
,
700 int i
, int DR1
, int DR4
);
701 extern int i965_reset(struct drm_device
*dev
, u8 flags
);
704 void i915_hangcheck_elapsed(unsigned long data
);
705 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
706 struct drm_file
*file_priv
);
707 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
708 struct drm_file
*file_priv
);
709 void i915_user_irq_get(struct drm_device
*dev
);
710 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
711 void i915_user_irq_put(struct drm_device
*dev
);
712 extern void i915_enable_interrupt (struct drm_device
*dev
);
714 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
715 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
716 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
717 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
718 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
719 struct drm_file
*file_priv
);
720 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
721 struct drm_file
*file_priv
);
722 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
723 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
724 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
725 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
726 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
727 struct drm_file
*file_priv
);
728 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
731 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
734 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
738 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
739 struct drm_file
*file_priv
);
740 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
741 struct drm_file
*file_priv
);
742 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
743 struct drm_file
*file_priv
);
744 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
745 struct drm_file
*file_priv
);
746 extern void i915_mem_takedown(struct mem_block
**heap
);
747 extern void i915_mem_release(struct drm_device
* dev
,
748 struct drm_file
*file_priv
, struct mem_block
*heap
);
750 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
751 struct drm_file
*file_priv
);
752 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
753 struct drm_file
*file_priv
);
754 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
755 struct drm_file
*file_priv
);
756 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
757 struct drm_file
*file_priv
);
758 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
759 struct drm_file
*file_priv
);
760 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
761 struct drm_file
*file_priv
);
762 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
763 struct drm_file
*file_priv
);
764 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
765 struct drm_file
*file_priv
);
766 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
767 struct drm_file
*file_priv
);
768 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
769 struct drm_file
*file_priv
);
770 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
771 struct drm_file
*file_priv
);
772 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
773 struct drm_file
*file_priv
);
774 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
775 struct drm_file
*file_priv
);
776 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
777 struct drm_file
*file_priv
);
778 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
779 struct drm_file
*file_priv
);
780 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
781 struct drm_file
*file_priv
);
782 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
783 struct drm_file
*file_priv
);
784 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
785 struct drm_file
*file_priv
);
786 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
787 struct drm_file
*file_priv
);
788 void i915_gem_load(struct drm_device
*dev
);
789 int i915_gem_init_object(struct drm_gem_object
*obj
);
790 void i915_gem_free_object(struct drm_gem_object
*obj
);
791 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
792 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
793 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
794 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
795 void i915_gem_lastclose(struct drm_device
*dev
);
796 uint32_t i915_get_gem_seqno(struct drm_device
*dev
);
797 bool i915_seqno_passed(uint32_t seq1
, uint32_t seq2
);
798 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
);
799 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
);
800 void i915_gem_retire_requests(struct drm_device
*dev
);
801 void i915_gem_retire_work_handler(struct work_struct
*work
);
802 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
803 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
804 uint32_t read_domains
,
805 uint32_t write_domain
);
806 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
807 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
808 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
810 int i915_gem_idle(struct drm_device
*dev
);
811 int i915_lp_ring_sync(struct drm_device
*dev
);
812 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
813 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
815 int i915_gem_attach_phys_object(struct drm_device
*dev
,
816 struct drm_gem_object
*obj
, int id
);
817 void i915_gem_detach_phys_object(struct drm_device
*dev
,
818 struct drm_gem_object
*obj
);
819 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
820 int i915_gem_object_get_pages(struct drm_gem_object
*obj
);
821 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
822 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
824 void i915_gem_shrinker_init(void);
825 void i915_gem_shrinker_exit(void);
827 /* i915_gem_tiling.c */
828 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
829 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
830 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
832 /* i915_gem_debug.c */
833 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
834 const char *where
, uint32_t mark
);
836 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
838 #define i915_verify_inactive(dev, file, line)
840 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
841 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
842 const char *where
, uint32_t mark
);
843 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
846 int i915_debugfs_init(struct drm_minor
*minor
);
847 void i915_debugfs_cleanup(struct drm_minor
*minor
);
850 extern int i915_save_state(struct drm_device
*dev
);
851 extern int i915_restore_state(struct drm_device
*dev
);
854 extern int i915_save_state(struct drm_device
*dev
);
855 extern int i915_restore_state(struct drm_device
*dev
);
858 /* i915_opregion.c */
859 extern int intel_opregion_init(struct drm_device
*dev
, int resume
);
860 extern void intel_opregion_free(struct drm_device
*dev
, int suspend
);
861 extern void opregion_asle_intr(struct drm_device
*dev
);
862 extern void opregion_enable_asle(struct drm_device
*dev
);
864 static inline int intel_opregion_init(struct drm_device
*dev
, int resume
) { return 0; }
865 static inline void intel_opregion_free(struct drm_device
*dev
, int suspend
) { return; }
866 static inline void opregion_asle_intr(struct drm_device
*dev
) { return; }
867 static inline void opregion_enable_asle(struct drm_device
*dev
) { return; }
871 extern void intel_modeset_init(struct drm_device
*dev
);
872 extern void intel_modeset_cleanup(struct drm_device
*dev
);
873 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
874 extern void i8xx_disable_fbc(struct drm_device
*dev
);
875 extern void g4x_disable_fbc(struct drm_device
*dev
);
878 * Lock test for when it's just for synchronization of ring access.
880 * In that case, we don't need to do it when GEM is initialized as nobody else
881 * has access to the ring.
883 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
884 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
885 LOCK_TEST_WITH_RETURN(dev, file_priv); \
888 #define I915_READ(reg) readl(dev_priv->regs + (reg))
889 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
890 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
891 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
892 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
893 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
894 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
895 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
896 #define POSTING_READ(reg) (void)I915_READ(reg)
898 #define I915_VERBOSE 0
900 #define RING_LOCALS volatile unsigned int *ring_virt__;
902 #define BEGIN_LP_RING(n) do { \
903 int bytes__ = 4*(n); \
904 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
905 /* a wrap must occur between instructions so pad beforehand */ \
906 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
907 i915_wrap_ring(dev); \
908 if (unlikely (dev_priv->ring.space < bytes__)) \
909 i915_wait_ring(dev, bytes__, __func__); \
910 ring_virt__ = (unsigned int *) \
911 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
912 dev_priv->ring.tail += bytes__; \
913 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
914 dev_priv->ring.space -= bytes__; \
917 #define OUT_RING(n) do { \
918 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
919 *ring_virt__++ = (n); \
922 #define ADVANCE_LP_RING() do { \
924 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
925 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
929 * Reads a dword out of the status page, which is written to from the command
930 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
933 * The following dwords have a reserved meaning:
934 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
935 * 0x04: ring 0 head pointer
936 * 0x05: ring 1 head pointer (915-class)
937 * 0x06: ring 2 head pointer (915-class)
938 * 0x10-0x1b: Context status DWords (GM45)
939 * 0x1f: Last written status offset. (GM45)
941 * The area from dword 0x20 to 0x3ff is available for driver usage.
943 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
944 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
945 #define I915_GEM_HWS_INDEX 0x20
946 #define I915_BREADCRUMB_INDEX 0x21
948 extern int i915_wrap_ring(struct drm_device
* dev
);
949 extern int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
);
951 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
952 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
953 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
954 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
956 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
957 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
958 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
959 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
960 (dev)->pci_device == 0x27AE)
961 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
962 (dev)->pci_device == 0x2982 || \
963 (dev)->pci_device == 0x2992 || \
964 (dev)->pci_device == 0x29A2 || \
965 (dev)->pci_device == 0x2A02 || \
966 (dev)->pci_device == 0x2A12 || \
967 (dev)->pci_device == 0x2A42 || \
968 (dev)->pci_device == 0x2E02 || \
969 (dev)->pci_device == 0x2E12 || \
970 (dev)->pci_device == 0x2E22 || \
971 (dev)->pci_device == 0x2E32 || \
972 (dev)->pci_device == 0x2E42 || \
973 (dev)->pci_device == 0x0042 || \
974 (dev)->pci_device == 0x0046)
976 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
977 (dev)->pci_device == 0x2A12)
979 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
981 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
982 (dev)->pci_device == 0x2E12 || \
983 (dev)->pci_device == 0x2E22 || \
984 (dev)->pci_device == 0x2E32 || \
985 (dev)->pci_device == 0x2E42 || \
988 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
989 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
990 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
992 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
993 (dev)->pci_device == 0x29B2 || \
994 (dev)->pci_device == 0x29D2 || \
997 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
998 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
999 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
1001 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1002 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1005 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1006 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1007 IS_IGD(dev) || IS_IGDNG_M(dev))
1009 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1011 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1012 * rows, which changed the alignment requirements and fence programming.
1014 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1016 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1017 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1018 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
1019 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1020 /* dsparb controlled by hw only */
1021 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1023 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
1024 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1025 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1026 (IS_I9XX(dev) || IS_GM45(dev)) && \
1029 #define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IGDNG_M(dev))
1031 #define PRIMARY_RINGBUFFER_SIZE (128*1024)