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firewire: core: integrate software-forced bus resets with bus management
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / firewire / ohci.c
blobbb6a92bc9e6a2bfc8211a877a345d18462011a45
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/bug.h>
22 #include <linux/compiler.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/firewire.h>
27 #include <linux/firewire-constants.h>
28 #include <linux/gfp.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/io.h>
32 #include <linux/kernel.h>
33 #include <linux/list.h>
34 #include <linux/mm.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/mutex.h>
38 #include <linux/pci.h>
39 #include <linux/pci_ids.h>
40 #include <linux/spinlock.h>
41 #include <linux/string.h>
42
43 #include <asm/byteorder.h>
44 #include <asm/page.h>
45 #include <asm/system.h>
46
47 #ifdef CONFIG_PPC_PMAC
48 #include <asm/pmac_feature.h>
49 #endif
50
51 #include "core.h"
52 #include "ohci.h"
53
54 #define DESCRIPTOR_OUTPUT_MORE 0
55 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
56 #define DESCRIPTOR_INPUT_MORE (2 << 12)
57 #define DESCRIPTOR_INPUT_LAST (3 << 12)
58 #define DESCRIPTOR_STATUS (1 << 11)
59 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
60 #define DESCRIPTOR_PING (1 << 7)
61 #define DESCRIPTOR_YY (1 << 6)
62 #define DESCRIPTOR_NO_IRQ (0 << 4)
63 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
64 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
65 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
66 #define DESCRIPTOR_WAIT (3 << 0)
67
68 struct descriptor {
69 __le16 req_count;
70 __le16 control;
71 __le32 data_address;
72 __le32 branch_address;
73 __le16 res_count;
74 __le16 transfer_status;
75 } __attribute__((aligned(16)));
76
77 #define CONTROL_SET(regs) (regs)
78 #define CONTROL_CLEAR(regs) ((regs) + 4)
79 #define COMMAND_PTR(regs) ((regs) + 12)
80 #define CONTEXT_MATCH(regs) ((regs) + 16)
81
82 struct ar_buffer {
83 struct descriptor descriptor;
84 struct ar_buffer *next;
85 __le32 data[0];
86 };
87
88 struct ar_context {
89 struct fw_ohci *ohci;
90 struct ar_buffer *current_buffer;
91 struct ar_buffer *last_buffer;
92 void *pointer;
93 u32 regs;
94 struct tasklet_struct tasklet;
95 };
96
97 struct context;
98
99 typedef int (*descriptor_callback_t)(struct context *ctx,
100 struct descriptor *d,
101 struct descriptor *last);
102
103 /*
104 * A buffer that contains a block of DMA-able coherent memory used for
105 * storing a portion of a DMA descriptor program.
106 */
107 struct descriptor_buffer {
108 struct list_head list;
109 dma_addr_t buffer_bus;
110 size_t buffer_size;
111 size_t used;
112 struct descriptor buffer[0];
113 };
114
115 struct context {
116 struct fw_ohci *ohci;
117 u32 regs;
118 int total_allocation;
119
120 /*
121 * List of page-sized buffers for storing DMA descriptors.
122 * Head of list contains buffers in use and tail of list contains
123 * free buffers.
124 */
125 struct list_head buffer_list;
126
127 /*
128 * Pointer to a buffer inside buffer_list that contains the tail
129 * end of the current DMA program.
130 */
131 struct descriptor_buffer *buffer_tail;
132
133 /*
134 * The descriptor containing the branch address of the first
135 * descriptor that has not yet been filled by the device.
136 */
137 struct descriptor *last;
138
139 /*
140 * The last descriptor in the DMA program. It contains the branch
141 * address that must be updated upon appending a new descriptor.
142 */
143 struct descriptor *prev;
144
145 descriptor_callback_t callback;
146
147 struct tasklet_struct tasklet;
148 };
149
150 #define IT_HEADER_SY(v) ((v) << 0)
151 #define IT_HEADER_TCODE(v) ((v) << 4)
152 #define IT_HEADER_CHANNEL(v) ((v) << 8)
153 #define IT_HEADER_TAG(v) ((v) << 14)
154 #define IT_HEADER_SPEED(v) ((v) << 16)
155 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
156
157 struct iso_context {
158 struct fw_iso_context base;
159 struct context context;
160 int excess_bytes;
161 void *header;
162 size_t header_length;
163 };
164
165 #define CONFIG_ROM_SIZE 1024
166
167 struct fw_ohci {
168 struct fw_card card;
169
170 __iomem char *registers;
171 int node_id;
172 int generation;
173 int request_generation; /* for timestamping incoming requests */
174 unsigned quirks;
175 unsigned int pri_req_max;
176 u32 bus_time;
177 bool is_root;
178 bool csr_state_setclear_abdicate;
179
180 /*
181 * Spinlock for accessing fw_ohci data. Never call out of
182 * this driver with this lock held.
183 */
184 spinlock_t lock;
185
186 struct mutex phy_reg_mutex;
187
188 struct ar_context ar_request_ctx;
189 struct ar_context ar_response_ctx;
190 struct context at_request_ctx;
191 struct context at_response_ctx;
192
193 u32 it_context_mask;
194 struct iso_context *it_context_list;
195 u64 ir_context_channels;
196 u32 ir_context_mask;
197 struct iso_context *ir_context_list;
198
199 __be32 *config_rom;
200 dma_addr_t config_rom_bus;
201 __be32 *next_config_rom;
202 dma_addr_t next_config_rom_bus;
203 __be32 next_header;
204
205 __le32 *self_id_cpu;
206 dma_addr_t self_id_bus;
207 struct tasklet_struct bus_reset_tasklet;
208
209 u32 self_id_buffer[512];
210 };
211
212 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
213 {
214 return container_of(card, struct fw_ohci, card);
215 }
216
217 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
218 #define IR_CONTEXT_BUFFER_FILL 0x80000000
219 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
220 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
221 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
222 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
223
224 #define CONTEXT_RUN 0x8000
225 #define CONTEXT_WAKE 0x1000
226 #define CONTEXT_DEAD 0x0800
227 #define CONTEXT_ACTIVE 0x0400
228
229 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
230 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
231 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
232
233 #define OHCI1394_REGISTER_SIZE 0x800
234 #define OHCI_LOOP_COUNT 500
235 #define OHCI1394_PCI_HCI_Control 0x40
236 #define SELF_ID_BUF_SIZE 0x800
237 #define OHCI_TCODE_PHY_PACKET 0x0e
238 #define OHCI_VERSION_1_1 0x010010
239
240 static char ohci_driver_name[] = KBUILD_MODNAME;
241
242 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
243 #define PCI_DEVICE_ID_TI_TSB12LV22 0x8009
244
245 #define QUIRK_CYCLE_TIMER 1
246 #define QUIRK_RESET_PACKET 2
247 #define QUIRK_BE_HEADERS 4
248 #define QUIRK_NO_1394A 8
249 #define QUIRK_NO_MSI 16
250
251 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
252 static const struct {
253 unsigned short vendor, device, flags;
254 } ohci_quirks[] = {
255 {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, QUIRK_CYCLE_TIMER |
256 QUIRK_RESET_PACKET |
257 QUIRK_NO_1394A},
258 {PCI_VENDOR_ID_TI, PCI_ANY_ID, QUIRK_RESET_PACKET},
259 {PCI_VENDOR_ID_AL, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
260 {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, QUIRK_NO_MSI},
261 {PCI_VENDOR_ID_NEC, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
262 {PCI_VENDOR_ID_VIA, PCI_ANY_ID, QUIRK_CYCLE_TIMER},
263 {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, QUIRK_BE_HEADERS},
264 };
265
266 /* This overrides anything that was found in ohci_quirks[]. */
267 static int param_quirks;
268 module_param_named(quirks, param_quirks, int, 0644);
269 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
270 ", nonatomic cycle timer = " __stringify(QUIRK_CYCLE_TIMER)
271 ", reset packet generation = " __stringify(QUIRK_RESET_PACKET)
272 ", AR/selfID endianess = " __stringify(QUIRK_BE_HEADERS)
273 ", no 1394a enhancements = " __stringify(QUIRK_NO_1394A)
274 ", disable MSI = " __stringify(QUIRK_NO_MSI)
275 ")");
276
277 #define OHCI_PARAM_DEBUG_AT_AR 1
278 #define OHCI_PARAM_DEBUG_SELFIDS 2
279 #define OHCI_PARAM_DEBUG_IRQS 4
280 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
281
282 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
283
284 static int param_debug;
285 module_param_named(debug, param_debug, int, 0644);
286 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
287 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
288 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
289 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
290 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
291 ", or a combination, or all = -1)");
292
293 static void log_irqs(u32 evt)
294 {
295 if (likely(!(param_debug &
296 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
297 return;
298
299 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
300 !(evt & OHCI1394_busReset))
301 return;
302
303 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
304 evt & OHCI1394_selfIDComplete ? " selfID" : "",
305 evt & OHCI1394_RQPkt ? " AR_req" : "",
306 evt & OHCI1394_RSPkt ? " AR_resp" : "",
307 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
308 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
309 evt & OHCI1394_isochRx ? " IR" : "",
310 evt & OHCI1394_isochTx ? " IT" : "",
311 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
312 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
313 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
314 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
315 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
316 evt & OHCI1394_busReset ? " busReset" : "",
317 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
318 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
319 OHCI1394_respTxComplete | OHCI1394_isochRx |
320 OHCI1394_isochTx | OHCI1394_postedWriteErr |
321 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
322 OHCI1394_cycleInconsistent |
323 OHCI1394_regAccessFail | OHCI1394_busReset)
324 ? " ?" : "");
325 }
326
327 static const char *speed[] = {
328 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
329 };
330 static const char *power[] = {
331 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
332 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
333 };
334 static const char port[] = { '.', '-', 'p', 'c', };
335
336 static char _p(u32 *s, int shift)
337 {
338 return port[*s >> shift & 3];
339 }
340
341 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
342 {
343 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
344 return;
345
346 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
347 self_id_count, generation, node_id);
348
349 for (; self_id_count--; ++s)
350 if ((*s & 1 << 23) == 0)
351 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
352 "%s gc=%d %s %s%s%s\n",
353 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
354 speed[*s >> 14 & 3], *s >> 16 & 63,
355 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
356 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
357 else
358 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
359 *s, *s >> 24 & 63,
360 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
361 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
362 }
363
364 static const char *evts[] = {
365 [0x00] = "evt_no_status", [0x01] = "-reserved-",
366 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
367 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
368 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
369 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
370 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
371 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
372 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
373 [0x10] = "-reserved-", [0x11] = "ack_complete",
374 [0x12] = "ack_pending ", [0x13] = "-reserved-",
375 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
376 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
377 [0x18] = "-reserved-", [0x19] = "-reserved-",
378 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
379 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
380 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
381 [0x20] = "pending/cancelled",
382 };
383 static const char *tcodes[] = {
384 [0x0] = "QW req", [0x1] = "BW req",
385 [0x2] = "W resp", [0x3] = "-reserved-",
386 [0x4] = "QR req", [0x5] = "BR req",
387 [0x6] = "QR resp", [0x7] = "BR resp",
388 [0x8] = "cycle start", [0x9] = "Lk req",
389 [0xa] = "async stream packet", [0xb] = "Lk resp",
390 [0xc] = "-reserved-", [0xd] = "-reserved-",
391 [0xe] = "link internal", [0xf] = "-reserved-",
392 };
393 static const char *phys[] = {
394 [0x0] = "phy config packet", [0x1] = "link-on packet",
395 [0x2] = "self-id packet", [0x3] = "-reserved-",
396 };
397
398 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
399 {
400 int tcode = header[0] >> 4 & 0xf;
401 char specific[12];
402
403 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
404 return;
405
406 if (unlikely(evt >= ARRAY_SIZE(evts)))
407 evt = 0x1f;
408
409 if (evt == OHCI1394_evt_bus_reset) {
410 fw_notify("A%c evt_bus_reset, generation %d\n",
411 dir, (header[2] >> 16) & 0xff);
412 return;
413 }
414
415 if (header[0] == ~header[1]) {
416 fw_notify("A%c %s, %s, %08x\n",
417 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
418 return;
419 }
420
421 switch (tcode) {
422 case 0x0: case 0x6: case 0x8:
423 snprintf(specific, sizeof(specific), " = %08x",
424 be32_to_cpu((__force __be32)header[3]));
425 break;
426 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
427 snprintf(specific, sizeof(specific), " %x,%x",
428 header[3] >> 16, header[3] & 0xffff);
429 break;
430 default:
431 specific[0] = '\0';
432 }
433
434 switch (tcode) {
435 case 0xe: case 0xa:
436 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
437 break;
438 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
439 fw_notify("A%c spd %x tl %02x, "
440 "%04x -> %04x, %s, "
441 "%s, %04x%08x%s\n",
442 dir, speed, header[0] >> 10 & 0x3f,
443 header[1] >> 16, header[0] >> 16, evts[evt],
444 tcodes[tcode], header[1] & 0xffff, header[2], specific);
445 break;
446 default:
447 fw_notify("A%c spd %x tl %02x, "
448 "%04x -> %04x, %s, "
449 "%s%s\n",
450 dir, speed, header[0] >> 10 & 0x3f,
451 header[1] >> 16, header[0] >> 16, evts[evt],
452 tcodes[tcode], specific);
453 }
454 }
455
456 #else
457
458 #define param_debug 0
459 static inline void log_irqs(u32 evt) {}
460 static inline void log_selfids(int node_id, int generation, int self_id_count, u32 *s) {}
461 static inline void log_ar_at_event(char dir, int speed, u32 *header, int evt) {}
462
463 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
464
465 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
466 {
467 writel(data, ohci->registers + offset);
468 }
469
470 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
471 {
472 return readl(ohci->registers + offset);
473 }
474
475 static inline void flush_writes(const struct fw_ohci *ohci)
476 {
477 /* Do a dummy read to flush writes. */
478 reg_read(ohci, OHCI1394_Version);
479 }
480
481 static int read_phy_reg(struct fw_ohci *ohci, int addr)
482 {
483 u32 val;
484 int i;
485
486 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
487 for (i = 0; i < 3 + 100; i++) {
488 val = reg_read(ohci, OHCI1394_PhyControl);
489 if (val & OHCI1394_PhyControl_ReadDone)
490 return OHCI1394_PhyControl_ReadData(val);
491
492 /*
493 * Try a few times without waiting. Sleeping is necessary
494 * only when the link/PHY interface is busy.
495 */
496 if (i >= 3)
497 msleep(1);
498 }
499 fw_error("failed to read phy reg\n");
500
501 return -EBUSY;
502 }
503
504 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
505 {
506 int i;
507
508 reg_write(ohci, OHCI1394_PhyControl,
509 OHCI1394_PhyControl_Write(addr, val));
510 for (i = 0; i < 3 + 100; i++) {
511 val = reg_read(ohci, OHCI1394_PhyControl);
512 if (!(val & OHCI1394_PhyControl_WritePending))
513 return 0;
514
515 if (i >= 3)
516 msleep(1);
517 }
518 fw_error("failed to write phy reg\n");
519
520 return -EBUSY;
521 }
522
523 static int update_phy_reg(struct fw_ohci *ohci, int addr,
524 int clear_bits, int set_bits)
525 {
526 int ret = read_phy_reg(ohci, addr);
527 if (ret < 0)
528 return ret;
529
530 /*
531 * The interrupt status bits are cleared by writing a one bit.
532 * Avoid clearing them unless explicitly requested in set_bits.
533 */
534 if (addr == 5)
535 clear_bits |= PHY_INT_STATUS_BITS;
536
537 return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
538 }
539
540 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
541 {
542 int ret;
543
544 ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
545 if (ret < 0)
546 return ret;
547
548 return read_phy_reg(ohci, addr);
549 }
550
551 static int ohci_read_phy_reg(struct fw_card *card, int addr)
552 {
553 struct fw_ohci *ohci = fw_ohci(card);
554 int ret;
555
556 mutex_lock(&ohci->phy_reg_mutex);
557 ret = read_phy_reg(ohci, addr);
558 mutex_unlock(&ohci->phy_reg_mutex);
559
560 return ret;
561 }
562
563 static int ohci_update_phy_reg(struct fw_card *card, int addr,
564 int clear_bits, int set_bits)
565 {
566 struct fw_ohci *ohci = fw_ohci(card);
567 int ret;
568
569 mutex_lock(&ohci->phy_reg_mutex);
570 ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
571 mutex_unlock(&ohci->phy_reg_mutex);
572
573 return ret;
574 }
575
576 static int ar_context_add_page(struct ar_context *ctx)
577 {
578 struct device *dev = ctx->ohci->card.device;
579 struct ar_buffer *ab;
580 dma_addr_t uninitialized_var(ab_bus);
581 size_t offset;
582
583 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
584 if (ab == NULL)
585 return -ENOMEM;
586
587 ab->next = NULL;
588 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
589 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
590 DESCRIPTOR_STATUS |
591 DESCRIPTOR_BRANCH_ALWAYS);
592 offset = offsetof(struct ar_buffer, data);
593 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
594 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
595 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
596 ab->descriptor.branch_address = 0;
597
598 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
599 ctx->last_buffer->next = ab;
600 ctx->last_buffer = ab;
601
602 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
603 flush_writes(ctx->ohci);
604
605 return 0;
606 }
607
608 static void ar_context_release(struct ar_context *ctx)
609 {
610 struct ar_buffer *ab, *ab_next;
611 size_t offset;
612 dma_addr_t ab_bus;
613
614 for (ab = ctx->current_buffer; ab; ab = ab_next) {
615 ab_next = ab->next;
616 offset = offsetof(struct ar_buffer, data);
617 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
618 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
619 ab, ab_bus);
620 }
621 }
622
623 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
624 #define cond_le32_to_cpu(v) \
625 (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
626 #else
627 #define cond_le32_to_cpu(v) le32_to_cpu(v)
628 #endif
629
630 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
631 {
632 struct fw_ohci *ohci = ctx->ohci;
633 struct fw_packet p;
634 u32 status, length, tcode;
635 int evt;
636
637 p.header[0] = cond_le32_to_cpu(buffer[0]);
638 p.header[1] = cond_le32_to_cpu(buffer[1]);
639 p.header[2] = cond_le32_to_cpu(buffer[2]);
640
641 tcode = (p.header[0] >> 4) & 0x0f;
642 switch (tcode) {
643 case TCODE_WRITE_QUADLET_REQUEST:
644 case TCODE_READ_QUADLET_RESPONSE:
645 p.header[3] = (__force __u32) buffer[3];
646 p.header_length = 16;
647 p.payload_length = 0;
648 break;
649
650 case TCODE_READ_BLOCK_REQUEST :
651 p.header[3] = cond_le32_to_cpu(buffer[3]);
652 p.header_length = 16;
653 p.payload_length = 0;
654 break;
655
656 case TCODE_WRITE_BLOCK_REQUEST:
657 case TCODE_READ_BLOCK_RESPONSE:
658 case TCODE_LOCK_REQUEST:
659 case TCODE_LOCK_RESPONSE:
660 p.header[3] = cond_le32_to_cpu(buffer[3]);
661 p.header_length = 16;
662 p.payload_length = p.header[3] >> 16;
663 break;
664
665 case TCODE_WRITE_RESPONSE:
666 case TCODE_READ_QUADLET_REQUEST:
667 case OHCI_TCODE_PHY_PACKET:
668 p.header_length = 12;
669 p.payload_length = 0;
670 break;
671
672 default:
673 /* FIXME: Stop context, discard everything, and restart? */
674 p.header_length = 0;
675 p.payload_length = 0;
676 }
677
678 p.payload = (void *) buffer + p.header_length;
679
680 /* FIXME: What to do about evt_* errors? */
681 length = (p.header_length + p.payload_length + 3) / 4;
682 status = cond_le32_to_cpu(buffer[length]);
683 evt = (status >> 16) & 0x1f;
684
685 p.ack = evt - 16;
686 p.speed = (status >> 21) & 0x7;
687 p.timestamp = status & 0xffff;
688 p.generation = ohci->request_generation;
689
690 log_ar_at_event('R', p.speed, p.header, evt);
691
692 /*
693 * The OHCI bus reset handler synthesizes a phy packet with
694 * the new generation number when a bus reset happens (see
695 * section 8.4.2.3). This helps us determine when a request
696 * was received and make sure we send the response in the same
697 * generation. We only need this for requests; for responses
698 * we use the unique tlabel for finding the matching
699 * request.
700 *
701 * Alas some chips sometimes emit bus reset packets with a
702 * wrong generation. We set the correct generation for these
703 * at a slightly incorrect time (in bus_reset_tasklet).
704 */
705 if (evt == OHCI1394_evt_bus_reset) {
706 if (!(ohci->quirks & QUIRK_RESET_PACKET))
707 ohci->request_generation = (p.header[2] >> 16) & 0xff;
708 } else if (ctx == &ohci->ar_request_ctx) {
709 fw_core_handle_request(&ohci->card, &p);
710 } else {
711 fw_core_handle_response(&ohci->card, &p);
712 }
713
714 return buffer + length + 1;
715 }
716
717 static void ar_context_tasklet(unsigned long data)
718 {
719 struct ar_context *ctx = (struct ar_context *)data;
720 struct fw_ohci *ohci = ctx->ohci;
721 struct ar_buffer *ab;
722 struct descriptor *d;
723 void *buffer, *end;
724
725 ab = ctx->current_buffer;
726 d = &ab->descriptor;
727
728 if (d->res_count == 0) {
729 size_t size, rest, offset;
730 dma_addr_t start_bus;
731 void *start;
732
733 /*
734 * This descriptor is finished and we may have a
735 * packet split across this and the next buffer. We
736 * reuse the page for reassembling the split packet.
737 */
738
739 offset = offsetof(struct ar_buffer, data);
740 start = buffer = ab;
741 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
742
743 ab = ab->next;
744 d = &ab->descriptor;
745 size = buffer + PAGE_SIZE - ctx->pointer;
746 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
747 memmove(buffer, ctx->pointer, size);
748 memcpy(buffer + size, ab->data, rest);
749 ctx->current_buffer = ab;
750 ctx->pointer = (void *) ab->data + rest;
751 end = buffer + size + rest;
752
753 while (buffer < end)
754 buffer = handle_ar_packet(ctx, buffer);
755
756 dma_free_coherent(ohci->card.device, PAGE_SIZE,
757 start, start_bus);
758 ar_context_add_page(ctx);
759 } else {
760 buffer = ctx->pointer;
761 ctx->pointer = end =
762 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
763
764 while (buffer < end)
765 buffer = handle_ar_packet(ctx, buffer);
766 }
767 }
768
769 static int ar_context_init(struct ar_context *ctx,
770 struct fw_ohci *ohci, u32 regs)
771 {
772 struct ar_buffer ab;
773
774 ctx->regs = regs;
775 ctx->ohci = ohci;
776 ctx->last_buffer = &ab;
777 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
778
779 ar_context_add_page(ctx);
780 ar_context_add_page(ctx);
781 ctx->current_buffer = ab.next;
782 ctx->pointer = ctx->current_buffer->data;
783
784 return 0;
785 }
786
787 static void ar_context_run(struct ar_context *ctx)
788 {
789 struct ar_buffer *ab = ctx->current_buffer;
790 dma_addr_t ab_bus;
791 size_t offset;
792
793 offset = offsetof(struct ar_buffer, data);
794 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
795
796 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
797 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
798 flush_writes(ctx->ohci);
799 }
800
801 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
802 {
803 int b, key;
804
805 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
806 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
807
808 /* figure out which descriptor the branch address goes in */
809 if (z == 2 && (b == 3 || key == 2))
810 return d;
811 else
812 return d + z - 1;
813 }
814
815 static void context_tasklet(unsigned long data)
816 {
817 struct context *ctx = (struct context *) data;
818 struct descriptor *d, *last;
819 u32 address;
820 int z;
821 struct descriptor_buffer *desc;
822
823 desc = list_entry(ctx->buffer_list.next,
824 struct descriptor_buffer, list);
825 last = ctx->last;
826 while (last->branch_address != 0) {
827 struct descriptor_buffer *old_desc = desc;
828 address = le32_to_cpu(last->branch_address);
829 z = address & 0xf;
830 address &= ~0xf;
831
832 /* If the branch address points to a buffer outside of the
833 * current buffer, advance to the next buffer. */
834 if (address < desc->buffer_bus ||
835 address >= desc->buffer_bus + desc->used)
836 desc = list_entry(desc->list.next,
837 struct descriptor_buffer, list);
838 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
839 last = find_branch_descriptor(d, z);
840
841 if (!ctx->callback(ctx, d, last))
842 break;
843
844 if (old_desc != desc) {
845 /* If we've advanced to the next buffer, move the
846 * previous buffer to the free list. */
847 unsigned long flags;
848 old_desc->used = 0;
849 spin_lock_irqsave(&ctx->ohci->lock, flags);
850 list_move_tail(&old_desc->list, &ctx->buffer_list);
851 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
852 }
853 ctx->last = last;
854 }
855 }
856
857 /*
858 * Allocate a new buffer and add it to the list of free buffers for this
859 * context. Must be called with ohci->lock held.
860 */
861 static int context_add_buffer(struct context *ctx)
862 {
863 struct descriptor_buffer *desc;
864 dma_addr_t uninitialized_var(bus_addr);
865 int offset;
866
867 /*
868 * 16MB of descriptors should be far more than enough for any DMA
869 * program. This will catch run-away userspace or DoS attacks.
870 */
871 if (ctx->total_allocation >= 16*1024*1024)
872 return -ENOMEM;
873
874 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
875 &bus_addr, GFP_ATOMIC);
876 if (!desc)
877 return -ENOMEM;
878
879 offset = (void *)&desc->buffer - (void *)desc;
880 desc->buffer_size = PAGE_SIZE - offset;
881 desc->buffer_bus = bus_addr + offset;
882 desc->used = 0;
883
884 list_add_tail(&desc->list, &ctx->buffer_list);
885 ctx->total_allocation += PAGE_SIZE;
886
887 return 0;
888 }
889
890 static int context_init(struct context *ctx, struct fw_ohci *ohci,
891 u32 regs, descriptor_callback_t callback)
892 {
893 ctx->ohci = ohci;
894 ctx->regs = regs;
895 ctx->total_allocation = 0;
896
897 INIT_LIST_HEAD(&ctx->buffer_list);
898 if (context_add_buffer(ctx) < 0)
899 return -ENOMEM;
900
901 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
902 struct descriptor_buffer, list);
903
904 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
905 ctx->callback = callback;
906
907 /*
908 * We put a dummy descriptor in the buffer that has a NULL
909 * branch address and looks like it's been sent. That way we
910 * have a descriptor to append DMA programs to.
911 */
912 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
913 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
914 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
915 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
916 ctx->last = ctx->buffer_tail->buffer;
917 ctx->prev = ctx->buffer_tail->buffer;
918
919 return 0;
920 }
921
922 static void context_release(struct context *ctx)
923 {
924 struct fw_card *card = &ctx->ohci->card;
925 struct descriptor_buffer *desc, *tmp;
926
927 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
928 dma_free_coherent(card->device, PAGE_SIZE, desc,
929 desc->buffer_bus -
930 ((void *)&desc->buffer - (void *)desc));
931 }
932
933 /* Must be called with ohci->lock held */
934 static struct descriptor *context_get_descriptors(struct context *ctx,
935 int z, dma_addr_t *d_bus)
936 {
937 struct descriptor *d = NULL;
938 struct descriptor_buffer *desc = ctx->buffer_tail;
939
940 if (z * sizeof(*d) > desc->buffer_size)
941 return NULL;
942
943 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
944 /* No room for the descriptor in this buffer, so advance to the
945 * next one. */
946
947 if (desc->list.next == &ctx->buffer_list) {
948 /* If there is no free buffer next in the list,
949 * allocate one. */
950 if (context_add_buffer(ctx) < 0)
951 return NULL;
952 }
953 desc = list_entry(desc->list.next,
954 struct descriptor_buffer, list);
955 ctx->buffer_tail = desc;
956 }
957
958 d = desc->buffer + desc->used / sizeof(*d);
959 memset(d, 0, z * sizeof(*d));
960 *d_bus = desc->buffer_bus + desc->used;
961
962 return d;
963 }
964
965 static void context_run(struct context *ctx, u32 extra)
966 {
967 struct fw_ohci *ohci = ctx->ohci;
968
969 reg_write(ohci, COMMAND_PTR(ctx->regs),
970 le32_to_cpu(ctx->last->branch_address));
971 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
972 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
973 flush_writes(ohci);
974 }
975
976 static void context_append(struct context *ctx,
977 struct descriptor *d, int z, int extra)
978 {
979 dma_addr_t d_bus;
980 struct descriptor_buffer *desc = ctx->buffer_tail;
981
982 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
983
984 desc->used += (z + extra) * sizeof(*d);
985 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
986 ctx->prev = find_branch_descriptor(d, z);
987
988 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
989 flush_writes(ctx->ohci);
990 }
991
992 static void context_stop(struct context *ctx)
993 {
994 u32 reg;
995 int i;
996
997 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
998 flush_writes(ctx->ohci);
999
1000 for (i = 0; i < 10; i++) {
1001 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1002 if ((reg & CONTEXT_ACTIVE) == 0)
1003 return;
1004
1005 mdelay(1);
1006 }
1007 fw_error("Error: DMA context still active (0x%08x)\n", reg);
1008 }
1009
1010 struct driver_data {
1011 struct fw_packet *packet;
1012 };
1013
1014 /*
1015 * This function apppends a packet to the DMA queue for transmission.
1016 * Must always be called with the ochi->lock held to ensure proper
1017 * generation handling and locking around packet queue manipulation.
1018 */
1019 static int at_context_queue_packet(struct context *ctx,
1020 struct fw_packet *packet)
1021 {
1022 struct fw_ohci *ohci = ctx->ohci;
1023 dma_addr_t d_bus, uninitialized_var(payload_bus);
1024 struct driver_data *driver_data;
1025 struct descriptor *d, *last;
1026 __le32 *header;
1027 int z, tcode;
1028 u32 reg;
1029
1030 d = context_get_descriptors(ctx, 4, &d_bus);
1031 if (d == NULL) {
1032 packet->ack = RCODE_SEND_ERROR;
1033 return -1;
1034 }
1035
1036 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1037 d[0].res_count = cpu_to_le16(packet->timestamp);
1038
1039 /*
1040 * The DMA format for asyncronous link packets is different
1041 * from the IEEE1394 layout, so shift the fields around
1042 * accordingly. If header_length is 8, it's a PHY packet, to
1043 * which we need to prepend an extra quadlet.
1044 */
1045
1046 header = (__le32 *) &d[1];
1047 switch (packet->header_length) {
1048 case 16:
1049 case 12:
1050 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1051 (packet->speed << 16));
1052 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1053 (packet->header[0] & 0xffff0000));
1054 header[2] = cpu_to_le32(packet->header[2]);
1055
1056 tcode = (packet->header[0] >> 4) & 0x0f;
1057 if (TCODE_IS_BLOCK_PACKET(tcode))
1058 header[3] = cpu_to_le32(packet->header[3]);
1059 else
1060 header[3] = (__force __le32) packet->header[3];
1061
1062 d[0].req_count = cpu_to_le16(packet->header_length);
1063 break;
1064
1065 case 8:
1066 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1067 (packet->speed << 16));
1068 header[1] = cpu_to_le32(packet->header[0]);
1069 header[2] = cpu_to_le32(packet->header[1]);
1070 d[0].req_count = cpu_to_le16(12);
1071 break;
1072
1073 case 4:
1074 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1075 (packet->speed << 16));
1076 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1077 d[0].req_count = cpu_to_le16(8);
1078 break;
1079
1080 default:
1081 /* BUG(); */
1082 packet->ack = RCODE_SEND_ERROR;
1083 return -1;
1084 }
1085
1086 driver_data = (struct driver_data *) &d[3];
1087 driver_data->packet = packet;
1088 packet->driver_data = driver_data;
1089
1090 if (packet->payload_length > 0) {
1091 payload_bus =
1092 dma_map_single(ohci->card.device, packet->payload,
1093 packet->payload_length, DMA_TO_DEVICE);
1094 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1095 packet->ack = RCODE_SEND_ERROR;
1096 return -1;
1097 }
1098 packet->payload_bus = payload_bus;
1099 packet->payload_mapped = true;
1100
1101 d[2].req_count = cpu_to_le16(packet->payload_length);
1102 d[2].data_address = cpu_to_le32(payload_bus);
1103 last = &d[2];
1104 z = 3;
1105 } else {
1106 last = &d[0];
1107 z = 2;
1108 }
1109
1110 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1111 DESCRIPTOR_IRQ_ALWAYS |
1112 DESCRIPTOR_BRANCH_ALWAYS);
1113
1114 /*
1115 * If the controller and packet generations don't match, we need to
1116 * bail out and try again. If IntEvent.busReset is set, the AT context
1117 * is halted, so appending to the context and trying to run it is
1118 * futile. Most controllers do the right thing and just flush the AT
1119 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1120 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1121 * up stalling out. So we just bail out in software and try again
1122 * later, and everyone is happy.
1123 * FIXME: Document how the locking works.
1124 */
1125 if (ohci->generation != packet->generation ||
1126 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1127 if (packet->payload_mapped)
1128 dma_unmap_single(ohci->card.device, payload_bus,
1129 packet->payload_length, DMA_TO_DEVICE);
1130 packet->ack = RCODE_GENERATION;
1131 return -1;
1132 }
1133
1134 context_append(ctx, d, z, 4 - z);
1135
1136 /* If the context isn't already running, start it up. */
1137 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1138 if ((reg & CONTEXT_RUN) == 0)
1139 context_run(ctx, 0);
1140
1141 return 0;
1142 }
1143
1144 static int handle_at_packet(struct context *context,
1145 struct descriptor *d,
1146 struct descriptor *last)
1147 {
1148 struct driver_data *driver_data;
1149 struct fw_packet *packet;
1150 struct fw_ohci *ohci = context->ohci;
1151 int evt;
1152
1153 if (last->transfer_status == 0)
1154 /* This descriptor isn't done yet, stop iteration. */
1155 return 0;
1156
1157 driver_data = (struct driver_data *) &d[3];
1158 packet = driver_data->packet;
1159 if (packet == NULL)
1160 /* This packet was cancelled, just continue. */
1161 return 1;
1162
1163 if (packet->payload_mapped)
1164 dma_unmap_single(ohci->card.device, packet->payload_bus,
1165 packet->payload_length, DMA_TO_DEVICE);
1166
1167 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1168 packet->timestamp = le16_to_cpu(last->res_count);
1169
1170 log_ar_at_event('T', packet->speed, packet->header, evt);
1171
1172 switch (evt) {
1173 case OHCI1394_evt_timeout:
1174 /* Async response transmit timed out. */
1175 packet->ack = RCODE_CANCELLED;
1176 break;
1177
1178 case OHCI1394_evt_flushed:
1179 /*
1180 * The packet was flushed should give same error as
1181 * when we try to use a stale generation count.
1182 */
1183 packet->ack = RCODE_GENERATION;
1184 break;
1185
1186 case OHCI1394_evt_missing_ack:
1187 /*
1188 * Using a valid (current) generation count, but the
1189 * node is not on the bus or not sending acks.
1190 */
1191 packet->ack = RCODE_NO_ACK;
1192 break;
1193
1194 case ACK_COMPLETE + 0x10:
1195 case ACK_PENDING + 0x10:
1196 case ACK_BUSY_X + 0x10:
1197 case ACK_BUSY_A + 0x10:
1198 case ACK_BUSY_B + 0x10:
1199 case ACK_DATA_ERROR + 0x10:
1200 case ACK_TYPE_ERROR + 0x10:
1201 packet->ack = evt - 0x10;
1202 break;
1203
1204 default:
1205 packet->ack = RCODE_SEND_ERROR;
1206 break;
1207 }
1208
1209 packet->callback(packet, &ohci->card, packet->ack);
1210
1211 return 1;
1212 }
1213
1214 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1215 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1216 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1217 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1218 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1219
1220 static void handle_local_rom(struct fw_ohci *ohci,
1221 struct fw_packet *packet, u32 csr)
1222 {
1223 struct fw_packet response;
1224 int tcode, length, i;
1225
1226 tcode = HEADER_GET_TCODE(packet->header[0]);
1227 if (TCODE_IS_BLOCK_PACKET(tcode))
1228 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1229 else
1230 length = 4;
1231
1232 i = csr - CSR_CONFIG_ROM;
1233 if (i + length > CONFIG_ROM_SIZE) {
1234 fw_fill_response(&response, packet->header,
1235 RCODE_ADDRESS_ERROR, NULL, 0);
1236 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1237 fw_fill_response(&response, packet->header,
1238 RCODE_TYPE_ERROR, NULL, 0);
1239 } else {
1240 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1241 (void *) ohci->config_rom + i, length);
1242 }
1243
1244 fw_core_handle_response(&ohci->card, &response);
1245 }
1246
1247 static void handle_local_lock(struct fw_ohci *ohci,
1248 struct fw_packet *packet, u32 csr)
1249 {
1250 struct fw_packet response;
1251 int tcode, length, ext_tcode, sel;
1252 __be32 *payload, lock_old;
1253 u32 lock_arg, lock_data;
1254
1255 tcode = HEADER_GET_TCODE(packet->header[0]);
1256 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1257 payload = packet->payload;
1258 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1259
1260 if (tcode == TCODE_LOCK_REQUEST &&
1261 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1262 lock_arg = be32_to_cpu(payload[0]);
1263 lock_data = be32_to_cpu(payload[1]);
1264 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1265 lock_arg = 0;
1266 lock_data = 0;
1267 } else {
1268 fw_fill_response(&response, packet->header,
1269 RCODE_TYPE_ERROR, NULL, 0);
1270 goto out;
1271 }
1272
1273 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1274 reg_write(ohci, OHCI1394_CSRData, lock_data);
1275 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1276 reg_write(ohci, OHCI1394_CSRControl, sel);
1277
1278 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1279 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1280 else
1281 fw_notify("swap not done yet\n");
1282
1283 fw_fill_response(&response, packet->header,
1284 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1285 out:
1286 fw_core_handle_response(&ohci->card, &response);
1287 }
1288
1289 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1290 {
1291 u64 offset;
1292 u32 csr;
1293
1294 if (ctx == &ctx->ohci->at_request_ctx) {
1295 packet->ack = ACK_PENDING;
1296 packet->callback(packet, &ctx->ohci->card, packet->ack);
1297 }
1298
1299 offset =
1300 ((unsigned long long)
1301 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1302 packet->header[2];
1303 csr = offset - CSR_REGISTER_BASE;
1304
1305 /* Handle config rom reads. */
1306 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1307 handle_local_rom(ctx->ohci, packet, csr);
1308 else switch (csr) {
1309 case CSR_BUS_MANAGER_ID:
1310 case CSR_BANDWIDTH_AVAILABLE:
1311 case CSR_CHANNELS_AVAILABLE_HI:
1312 case CSR_CHANNELS_AVAILABLE_LO:
1313 handle_local_lock(ctx->ohci, packet, csr);
1314 break;
1315 default:
1316 if (ctx == &ctx->ohci->at_request_ctx)
1317 fw_core_handle_request(&ctx->ohci->card, packet);
1318 else
1319 fw_core_handle_response(&ctx->ohci->card, packet);
1320 break;
1321 }
1322
1323 if (ctx == &ctx->ohci->at_response_ctx) {
1324 packet->ack = ACK_COMPLETE;
1325 packet->callback(packet, &ctx->ohci->card, packet->ack);
1326 }
1327 }
1328
1329 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1330 {
1331 unsigned long flags;
1332 int ret;
1333
1334 spin_lock_irqsave(&ctx->ohci->lock, flags);
1335
1336 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1337 ctx->ohci->generation == packet->generation) {
1338 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1339 handle_local_request(ctx, packet);
1340 return;
1341 }
1342
1343 ret = at_context_queue_packet(ctx, packet);
1344 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1345
1346 if (ret < 0)
1347 packet->callback(packet, &ctx->ohci->card, packet->ack);
1348
1349 }
1350
1351 static u32 cycle_timer_ticks(u32 cycle_timer)
1352 {
1353 u32 ticks;
1354
1355 ticks = cycle_timer & 0xfff;
1356 ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1357 ticks += (3072 * 8000) * (cycle_timer >> 25);
1358
1359 return ticks;
1360 }
1361
1362 /*
1363 * Some controllers exhibit one or more of the following bugs when updating the
1364 * iso cycle timer register:
1365 * - When the lowest six bits are wrapping around to zero, a read that happens
1366 * at the same time will return garbage in the lowest ten bits.
1367 * - When the cycleOffset field wraps around to zero, the cycleCount field is
1368 * not incremented for about 60 ns.
1369 * - Occasionally, the entire register reads zero.
1370 *
1371 * To catch these, we read the register three times and ensure that the
1372 * difference between each two consecutive reads is approximately the same, i.e.
1373 * less than twice the other. Furthermore, any negative difference indicates an
1374 * error. (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1375 * execute, so we have enough precision to compute the ratio of the differences.)
1376 */
1377 static u32 get_cycle_time(struct fw_ohci *ohci)
1378 {
1379 u32 c0, c1, c2;
1380 u32 t0, t1, t2;
1381 s32 diff01, diff12;
1382 int i;
1383
1384 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1385
1386 if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1387 i = 0;
1388 c1 = c2;
1389 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1390 do {
1391 c0 = c1;
1392 c1 = c2;
1393 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1394 t0 = cycle_timer_ticks(c0);
1395 t1 = cycle_timer_ticks(c1);
1396 t2 = cycle_timer_ticks(c2);
1397 diff01 = t1 - t0;
1398 diff12 = t2 - t1;
1399 } while ((diff01 <= 0 || diff12 <= 0 ||
1400 diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1401 && i++ < 20);
1402 }
1403
1404 return c2;
1405 }
1406
1407 /*
1408 * This function has to be called at least every 64 seconds. The bus_time
1409 * field stores not only the upper 25 bits of the BUS_TIME register but also
1410 * the most significant bit of the cycle timer in bit 6 so that we can detect
1411 * changes in this bit.
1412 */
1413 static u32 update_bus_time(struct fw_ohci *ohci)
1414 {
1415 u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1416
1417 if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1418 ohci->bus_time += 0x40;
1419
1420 return ohci->bus_time | cycle_time_seconds;
1421 }
1422
1423 static void bus_reset_tasklet(unsigned long data)
1424 {
1425 struct fw_ohci *ohci = (struct fw_ohci *)data;
1426 int self_id_count, i, j, reg;
1427 int generation, new_generation;
1428 unsigned long flags;
1429 void *free_rom = NULL;
1430 dma_addr_t free_rom_bus = 0;
1431 bool is_new_root;
1432
1433 reg = reg_read(ohci, OHCI1394_NodeID);
1434 if (!(reg & OHCI1394_NodeID_idValid)) {
1435 fw_notify("node ID not valid, new bus reset in progress\n");
1436 return;
1437 }
1438 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1439 fw_notify("malconfigured bus\n");
1440 return;
1441 }
1442 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1443 OHCI1394_NodeID_nodeNumber);
1444
1445 is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1446 if (!(ohci->is_root && is_new_root))
1447 reg_write(ohci, OHCI1394_LinkControlSet,
1448 OHCI1394_LinkControl_cycleMaster);
1449 ohci->is_root = is_new_root;
1450
1451 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1452 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1453 fw_notify("inconsistent self IDs\n");
1454 return;
1455 }
1456 /*
1457 * The count in the SelfIDCount register is the number of
1458 * bytes in the self ID receive buffer. Since we also receive
1459 * the inverted quadlets and a header quadlet, we shift one
1460 * bit extra to get the actual number of self IDs.
1461 */
1462 self_id_count = (reg >> 3) & 0xff;
1463 if (self_id_count == 0 || self_id_count > 252) {
1464 fw_notify("inconsistent self IDs\n");
1465 return;
1466 }
1467 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1468 rmb();
1469
1470 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1471 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1472 fw_notify("inconsistent self IDs\n");
1473 return;
1474 }
1475 ohci->self_id_buffer[j] =
1476 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1477 }
1478 rmb();
1479
1480 /*
1481 * Check the consistency of the self IDs we just read. The
1482 * problem we face is that a new bus reset can start while we
1483 * read out the self IDs from the DMA buffer. If this happens,
1484 * the DMA buffer will be overwritten with new self IDs and we
1485 * will read out inconsistent data. The OHCI specification
1486 * (section 11.2) recommends a technique similar to
1487 * linux/seqlock.h, where we remember the generation of the
1488 * self IDs in the buffer before reading them out and compare
1489 * it to the current generation after reading them out. If
1490 * the two generations match we know we have a consistent set
1491 * of self IDs.
1492 */
1493
1494 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1495 if (new_generation != generation) {
1496 fw_notify("recursive bus reset detected, "
1497 "discarding self ids\n");
1498 return;
1499 }
1500
1501 /* FIXME: Document how the locking works. */
1502 spin_lock_irqsave(&ohci->lock, flags);
1503
1504 ohci->generation = generation;
1505 context_stop(&ohci->at_request_ctx);
1506 context_stop(&ohci->at_response_ctx);
1507 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1508
1509 if (ohci->quirks & QUIRK_RESET_PACKET)
1510 ohci->request_generation = generation;
1511
1512 /*
1513 * This next bit is unrelated to the AT context stuff but we
1514 * have to do it under the spinlock also. If a new config rom
1515 * was set up before this reset, the old one is now no longer
1516 * in use and we can free it. Update the config rom pointers
1517 * to point to the current config rom and clear the
1518 * next_config_rom pointer so a new udpate can take place.
1519 */
1520
1521 if (ohci->next_config_rom != NULL) {
1522 if (ohci->next_config_rom != ohci->config_rom) {
1523 free_rom = ohci->config_rom;
1524 free_rom_bus = ohci->config_rom_bus;
1525 }
1526 ohci->config_rom = ohci->next_config_rom;
1527 ohci->config_rom_bus = ohci->next_config_rom_bus;
1528 ohci->next_config_rom = NULL;
1529
1530 /*
1531 * Restore config_rom image and manually update
1532 * config_rom registers. Writing the header quadlet
1533 * will indicate that the config rom is ready, so we
1534 * do that last.
1535 */
1536 reg_write(ohci, OHCI1394_BusOptions,
1537 be32_to_cpu(ohci->config_rom[2]));
1538 ohci->config_rom[0] = ohci->next_header;
1539 reg_write(ohci, OHCI1394_ConfigROMhdr,
1540 be32_to_cpu(ohci->next_header));
1541 }
1542
1543 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1544 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1545 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1546 #endif
1547
1548 spin_unlock_irqrestore(&ohci->lock, flags);
1549
1550 if (free_rom)
1551 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1552 free_rom, free_rom_bus);
1553
1554 log_selfids(ohci->node_id, generation,
1555 self_id_count, ohci->self_id_buffer);
1556
1557 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1558 self_id_count, ohci->self_id_buffer,
1559 ohci->csr_state_setclear_abdicate);
1560 ohci->csr_state_setclear_abdicate = false;
1561 }
1562
1563 static irqreturn_t irq_handler(int irq, void *data)
1564 {
1565 struct fw_ohci *ohci = data;
1566 u32 event, iso_event;
1567 int i;
1568
1569 event = reg_read(ohci, OHCI1394_IntEventClear);
1570
1571 if (!event || !~event)
1572 return IRQ_NONE;
1573
1574 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1575 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1576 log_irqs(event);
1577
1578 if (event & OHCI1394_selfIDComplete)
1579 tasklet_schedule(&ohci->bus_reset_tasklet);
1580
1581 if (event & OHCI1394_RQPkt)
1582 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1583
1584 if (event & OHCI1394_RSPkt)
1585 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1586
1587 if (event & OHCI1394_reqTxComplete)
1588 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1589
1590 if (event & OHCI1394_respTxComplete)
1591 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1592
1593 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1594 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1595
1596 while (iso_event) {
1597 i = ffs(iso_event) - 1;
1598 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1599 iso_event &= ~(1 << i);
1600 }
1601
1602 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1603 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1604
1605 while (iso_event) {
1606 i = ffs(iso_event) - 1;
1607 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1608 iso_event &= ~(1 << i);
1609 }
1610
1611 if (unlikely(event & OHCI1394_regAccessFail))
1612 fw_error("Register access failure - "
1613 "please notify linux1394-devel@lists.sf.net\n");
1614
1615 if (unlikely(event & OHCI1394_postedWriteErr))
1616 fw_error("PCI posted write error\n");
1617
1618 if (unlikely(event & OHCI1394_cycleTooLong)) {
1619 if (printk_ratelimit())
1620 fw_notify("isochronous cycle too long\n");
1621 reg_write(ohci, OHCI1394_LinkControlSet,
1622 OHCI1394_LinkControl_cycleMaster);
1623 }
1624
1625 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1626 /*
1627 * We need to clear this event bit in order to make
1628 * cycleMatch isochronous I/O work. In theory we should
1629 * stop active cycleMatch iso contexts now and restart
1630 * them at least two cycles later. (FIXME?)
1631 */
1632 if (printk_ratelimit())
1633 fw_notify("isochronous cycle inconsistent\n");
1634 }
1635
1636 if (event & OHCI1394_cycle64Seconds) {
1637 spin_lock(&ohci->lock);
1638 update_bus_time(ohci);
1639 spin_unlock(&ohci->lock);
1640 }
1641
1642 return IRQ_HANDLED;
1643 }
1644
1645 static int software_reset(struct fw_ohci *ohci)
1646 {
1647 int i;
1648
1649 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1650
1651 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1652 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1653 OHCI1394_HCControl_softReset) == 0)
1654 return 0;
1655 msleep(1);
1656 }
1657
1658 return -EBUSY;
1659 }
1660
1661 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
1662 {
1663 size_t size = length * 4;
1664
1665 memcpy(dest, src, size);
1666 if (size < CONFIG_ROM_SIZE)
1667 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
1668 }
1669
1670 static int configure_1394a_enhancements(struct fw_ohci *ohci)
1671 {
1672 bool enable_1394a;
1673 int ret, clear, set, offset;
1674
1675 /* Check if the driver should configure link and PHY. */
1676 if (!(reg_read(ohci, OHCI1394_HCControlSet) &
1677 OHCI1394_HCControl_programPhyEnable))
1678 return 0;
1679
1680 /* Paranoia: check whether the PHY supports 1394a, too. */
1681 enable_1394a = false;
1682 ret = read_phy_reg(ohci, 2);
1683 if (ret < 0)
1684 return ret;
1685 if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
1686 ret = read_paged_phy_reg(ohci, 1, 8);
1687 if (ret < 0)
1688 return ret;
1689 if (ret >= 1)
1690 enable_1394a = true;
1691 }
1692
1693 if (ohci->quirks & QUIRK_NO_1394A)
1694 enable_1394a = false;
1695
1696 /* Configure PHY and link consistently. */
1697 if (enable_1394a) {
1698 clear = 0;
1699 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1700 } else {
1701 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
1702 set = 0;
1703 }
1704 ret = update_phy_reg(ohci, 5, clear, set);
1705 if (ret < 0)
1706 return ret;
1707
1708 if (enable_1394a)
1709 offset = OHCI1394_HCControlSet;
1710 else
1711 offset = OHCI1394_HCControlClear;
1712 reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
1713
1714 /* Clean up: configuration has been taken care of. */
1715 reg_write(ohci, OHCI1394_HCControlClear,
1716 OHCI1394_HCControl_programPhyEnable);
1717
1718 return 0;
1719 }
1720
1721 static int ohci_enable(struct fw_card *card,
1722 const __be32 *config_rom, size_t length)
1723 {
1724 struct fw_ohci *ohci = fw_ohci(card);
1725 struct pci_dev *dev = to_pci_dev(card->device);
1726 u32 lps, seconds, version, irqs;
1727 int i, ret;
1728
1729 if (software_reset(ohci)) {
1730 fw_error("Failed to reset ohci card.\n");
1731 return -EBUSY;
1732 }
1733
1734 /*
1735 * Now enable LPS, which we need in order to start accessing
1736 * most of the registers. In fact, on some cards (ALI M5251),
1737 * accessing registers in the SClk domain without LPS enabled
1738 * will lock up the machine. Wait 50msec to make sure we have
1739 * full link enabled. However, with some cards (well, at least
1740 * a JMicron PCIe card), we have to try again sometimes.
1741 */
1742 reg_write(ohci, OHCI1394_HCControlSet,
1743 OHCI1394_HCControl_LPS |
1744 OHCI1394_HCControl_postedWriteEnable);
1745 flush_writes(ohci);
1746
1747 for (lps = 0, i = 0; !lps && i < 3; i++) {
1748 msleep(50);
1749 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1750 OHCI1394_HCControl_LPS;
1751 }
1752
1753 if (!lps) {
1754 fw_error("Failed to set Link Power Status\n");
1755 return -EIO;
1756 }
1757
1758 reg_write(ohci, OHCI1394_HCControlClear,
1759 OHCI1394_HCControl_noByteSwapData);
1760
1761 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1762 reg_write(ohci, OHCI1394_LinkControlClear,
1763 OHCI1394_LinkControl_rcvPhyPkt);
1764 reg_write(ohci, OHCI1394_LinkControlSet,
1765 OHCI1394_LinkControl_rcvSelfID |
1766 OHCI1394_LinkControl_cycleTimerEnable |
1767 OHCI1394_LinkControl_cycleMaster);
1768
1769 reg_write(ohci, OHCI1394_ATRetries,
1770 OHCI1394_MAX_AT_REQ_RETRIES |
1771 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1772 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
1773 (200 << 16));
1774
1775 seconds = lower_32_bits(get_seconds());
1776 reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
1777 ohci->bus_time = seconds & ~0x3f;
1778
1779 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
1780 if (version >= OHCI_VERSION_1_1) {
1781 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
1782 0xfffffffe);
1783 card->broadcast_channel_auto_allocated = true;
1784 }
1785
1786 /* Get implemented bits of the priority arbitration request counter. */
1787 reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
1788 ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
1789 reg_write(ohci, OHCI1394_FairnessControl, 0);
1790 card->priority_budget_implemented = ohci->pri_req_max != 0;
1791
1792 ar_context_run(&ohci->ar_request_ctx);
1793 ar_context_run(&ohci->ar_response_ctx);
1794
1795 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1796 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1797 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1798
1799 ret = configure_1394a_enhancements(ohci);
1800 if (ret < 0)
1801 return ret;
1802
1803 /* Activate link_on bit and contender bit in our self ID packets.*/
1804 ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
1805 if (ret < 0)
1806 return ret;
1807
1808 /*
1809 * When the link is not yet enabled, the atomic config rom
1810 * update mechanism described below in ohci_set_config_rom()
1811 * is not active. We have to update ConfigRomHeader and
1812 * BusOptions manually, and the write to ConfigROMmap takes
1813 * effect immediately. We tie this to the enabling of the
1814 * link, so we have a valid config rom before enabling - the
1815 * OHCI requires that ConfigROMhdr and BusOptions have valid
1816 * values before enabling.
1817 *
1818 * However, when the ConfigROMmap is written, some controllers
1819 * always read back quadlets 0 and 2 from the config rom to
1820 * the ConfigRomHeader and BusOptions registers on bus reset.
1821 * They shouldn't do that in this initial case where the link
1822 * isn't enabled. This means we have to use the same
1823 * workaround here, setting the bus header to 0 and then write
1824 * the right values in the bus reset tasklet.
1825 */
1826
1827 if (config_rom) {
1828 ohci->next_config_rom =
1829 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1830 &ohci->next_config_rom_bus,
1831 GFP_KERNEL);
1832 if (ohci->next_config_rom == NULL)
1833 return -ENOMEM;
1834
1835 copy_config_rom(ohci->next_config_rom, config_rom, length);
1836 } else {
1837 /*
1838 * In the suspend case, config_rom is NULL, which
1839 * means that we just reuse the old config rom.
1840 */
1841 ohci->next_config_rom = ohci->config_rom;
1842 ohci->next_config_rom_bus = ohci->config_rom_bus;
1843 }
1844
1845 ohci->next_header = ohci->next_config_rom[0];
1846 ohci->next_config_rom[0] = 0;
1847 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1848 reg_write(ohci, OHCI1394_BusOptions,
1849 be32_to_cpu(ohci->next_config_rom[2]));
1850 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1851
1852 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1853
1854 if (!(ohci->quirks & QUIRK_NO_MSI))
1855 pci_enable_msi(dev);
1856 if (request_irq(dev->irq, irq_handler,
1857 pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
1858 ohci_driver_name, ohci)) {
1859 fw_error("Failed to allocate interrupt %d.\n", dev->irq);
1860 pci_disable_msi(dev);
1861 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1862 ohci->config_rom, ohci->config_rom_bus);
1863 return -EIO;
1864 }
1865
1866 irqs = OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1867 OHCI1394_RQPkt | OHCI1394_RSPkt |
1868 OHCI1394_isochTx | OHCI1394_isochRx |
1869 OHCI1394_postedWriteErr |
1870 OHCI1394_selfIDComplete |
1871 OHCI1394_regAccessFail |
1872 OHCI1394_cycle64Seconds |
1873 OHCI1394_cycleInconsistent | OHCI1394_cycleTooLong |
1874 OHCI1394_masterIntEnable;
1875 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1876 irqs |= OHCI1394_busReset;
1877 reg_write(ohci, OHCI1394_IntMaskSet, irqs);
1878
1879 reg_write(ohci, OHCI1394_HCControlSet,
1880 OHCI1394_HCControl_linkEnable |
1881 OHCI1394_HCControl_BIBimageValid);
1882 flush_writes(ohci);
1883
1884 /* We are ready to go, reset bus to finish initialization. */
1885 fw_schedule_bus_reset(&ohci->card, false, true);
1886
1887 return 0;
1888 }
1889
1890 static int ohci_set_config_rom(struct fw_card *card,
1891 const __be32 *config_rom, size_t length)
1892 {
1893 struct fw_ohci *ohci;
1894 unsigned long flags;
1895 int ret = -EBUSY;
1896 __be32 *next_config_rom;
1897 dma_addr_t uninitialized_var(next_config_rom_bus);
1898
1899 ohci = fw_ohci(card);
1900
1901 /*
1902 * When the OHCI controller is enabled, the config rom update
1903 * mechanism is a bit tricky, but easy enough to use. See
1904 * section 5.5.6 in the OHCI specification.
1905 *
1906 * The OHCI controller caches the new config rom address in a
1907 * shadow register (ConfigROMmapNext) and needs a bus reset
1908 * for the changes to take place. When the bus reset is
1909 * detected, the controller loads the new values for the
1910 * ConfigRomHeader and BusOptions registers from the specified
1911 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1912 * shadow register. All automatically and atomically.
1913 *
1914 * Now, there's a twist to this story. The automatic load of
1915 * ConfigRomHeader and BusOptions doesn't honor the
1916 * noByteSwapData bit, so with a be32 config rom, the
1917 * controller will load be32 values in to these registers
1918 * during the atomic update, even on litte endian
1919 * architectures. The workaround we use is to put a 0 in the
1920 * header quadlet; 0 is endian agnostic and means that the
1921 * config rom isn't ready yet. In the bus reset tasklet we
1922 * then set up the real values for the two registers.
1923 *
1924 * We use ohci->lock to avoid racing with the code that sets
1925 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1926 */
1927
1928 next_config_rom =
1929 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1930 &next_config_rom_bus, GFP_KERNEL);
1931 if (next_config_rom == NULL)
1932 return -ENOMEM;
1933
1934 spin_lock_irqsave(&ohci->lock, flags);
1935
1936 if (ohci->next_config_rom == NULL) {
1937 ohci->next_config_rom = next_config_rom;
1938 ohci->next_config_rom_bus = next_config_rom_bus;
1939
1940 copy_config_rom(ohci->next_config_rom, config_rom, length);
1941
1942 ohci->next_header = config_rom[0];
1943 ohci->next_config_rom[0] = 0;
1944
1945 reg_write(ohci, OHCI1394_ConfigROMmap,
1946 ohci->next_config_rom_bus);
1947 ret = 0;
1948 }
1949
1950 spin_unlock_irqrestore(&ohci->lock, flags);
1951
1952 /*
1953 * Now initiate a bus reset to have the changes take
1954 * effect. We clean up the old config rom memory and DMA
1955 * mappings in the bus reset tasklet, since the OHCI
1956 * controller could need to access it before the bus reset
1957 * takes effect.
1958 */
1959 if (ret == 0)
1960 fw_schedule_bus_reset(&ohci->card, true, true);
1961 else
1962 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1963 next_config_rom, next_config_rom_bus);
1964
1965 return ret;
1966 }
1967
1968 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1969 {
1970 struct fw_ohci *ohci = fw_ohci(card);
1971
1972 at_context_transmit(&ohci->at_request_ctx, packet);
1973 }
1974
1975 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1976 {
1977 struct fw_ohci *ohci = fw_ohci(card);
1978
1979 at_context_transmit(&ohci->at_response_ctx, packet);
1980 }
1981
1982 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1983 {
1984 struct fw_ohci *ohci = fw_ohci(card);
1985 struct context *ctx = &ohci->at_request_ctx;
1986 struct driver_data *driver_data = packet->driver_data;
1987 int ret = -ENOENT;
1988
1989 tasklet_disable(&ctx->tasklet);
1990
1991 if (packet->ack != 0)
1992 goto out;
1993
1994 if (packet->payload_mapped)
1995 dma_unmap_single(ohci->card.device, packet->payload_bus,
1996 packet->payload_length, DMA_TO_DEVICE);
1997
1998 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1999 driver_data->packet = NULL;
2000 packet->ack = RCODE_CANCELLED;
2001 packet->callback(packet, &ohci->card, packet->ack);
2002 ret = 0;
2003 out:
2004 tasklet_enable(&ctx->tasklet);
2005
2006 return ret;
2007 }
2008
2009 static int ohci_enable_phys_dma(struct fw_card *card,
2010 int node_id, int generation)
2011 {
2012 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2013 return 0;
2014 #else
2015 struct fw_ohci *ohci = fw_ohci(card);
2016 unsigned long flags;
2017 int n, ret = 0;
2018
2019 /*
2020 * FIXME: Make sure this bitmask is cleared when we clear the busReset
2021 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
2022 */
2023
2024 spin_lock_irqsave(&ohci->lock, flags);
2025
2026 if (ohci->generation != generation) {
2027 ret = -ESTALE;
2028 goto out;
2029 }
2030
2031 /*
2032 * Note, if the node ID contains a non-local bus ID, physical DMA is
2033 * enabled for _all_ nodes on remote buses.
2034 */
2035
2036 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2037 if (n < 32)
2038 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2039 else
2040 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2041
2042 flush_writes(ohci);
2043 out:
2044 spin_unlock_irqrestore(&ohci->lock, flags);
2045
2046 return ret;
2047 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2048 }
2049
2050 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2051 {
2052 struct fw_ohci *ohci = fw_ohci(card);
2053 unsigned long flags;
2054 u32 value;
2055
2056 switch (csr_offset) {
2057 case CSR_STATE_CLEAR:
2058 case CSR_STATE_SET:
2059 if (ohci->is_root &&
2060 (reg_read(ohci, OHCI1394_LinkControlSet) &
2061 OHCI1394_LinkControl_cycleMaster))
2062 value = CSR_STATE_BIT_CMSTR;
2063 else
2064 value = 0;
2065 if (ohci->csr_state_setclear_abdicate)
2066 value |= CSR_STATE_BIT_ABDICATE;
2067
2068 return value;
2069
2070 case CSR_NODE_IDS:
2071 return reg_read(ohci, OHCI1394_NodeID) << 16;
2072
2073 case CSR_CYCLE_TIME:
2074 return get_cycle_time(ohci);
2075
2076 case CSR_BUS_TIME:
2077 /*
2078 * We might be called just after the cycle timer has wrapped
2079 * around but just before the cycle64Seconds handler, so we
2080 * better check here, too, if the bus time needs to be updated.
2081 */
2082 spin_lock_irqsave(&ohci->lock, flags);
2083 value = update_bus_time(ohci);
2084 spin_unlock_irqrestore(&ohci->lock, flags);
2085 return value;
2086
2087 case CSR_BUSY_TIMEOUT:
2088 value = reg_read(ohci, OHCI1394_ATRetries);
2089 return (value >> 4) & 0x0ffff00f;
2090
2091 case CSR_PRIORITY_BUDGET:
2092 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2093 (ohci->pri_req_max << 8);
2094
2095 default:
2096 WARN_ON(1);
2097 return 0;
2098 }
2099 }
2100
2101 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2102 {
2103 struct fw_ohci *ohci = fw_ohci(card);
2104 unsigned long flags;
2105
2106 switch (csr_offset) {
2107 case CSR_STATE_CLEAR:
2108 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2109 reg_write(ohci, OHCI1394_LinkControlClear,
2110 OHCI1394_LinkControl_cycleMaster);
2111 flush_writes(ohci);
2112 }
2113 if (value & CSR_STATE_BIT_ABDICATE)
2114 ohci->csr_state_setclear_abdicate = false;
2115 break;
2116
2117 case CSR_STATE_SET:
2118 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2119 reg_write(ohci, OHCI1394_LinkControlSet,
2120 OHCI1394_LinkControl_cycleMaster);
2121 flush_writes(ohci);
2122 }
2123 if (value & CSR_STATE_BIT_ABDICATE)
2124 ohci->csr_state_setclear_abdicate = true;
2125 break;
2126
2127 case CSR_NODE_IDS:
2128 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2129 flush_writes(ohci);
2130 break;
2131
2132 case CSR_CYCLE_TIME:
2133 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2134 reg_write(ohci, OHCI1394_IntEventSet,
2135 OHCI1394_cycleInconsistent);
2136 flush_writes(ohci);
2137 break;
2138
2139 case CSR_BUS_TIME:
2140 spin_lock_irqsave(&ohci->lock, flags);
2141 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2142 spin_unlock_irqrestore(&ohci->lock, flags);
2143 break;
2144
2145 case CSR_BUSY_TIMEOUT:
2146 value = (value & 0xf) | ((value & 0xf) << 4) |
2147 ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2148 reg_write(ohci, OHCI1394_ATRetries, value);
2149 flush_writes(ohci);
2150 break;
2151
2152 case CSR_PRIORITY_BUDGET:
2153 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2154 flush_writes(ohci);
2155 break;
2156
2157 default:
2158 WARN_ON(1);
2159 break;
2160 }
2161 }
2162
2163 static void copy_iso_headers(struct iso_context *ctx, void *p)
2164 {
2165 int i = ctx->header_length;
2166
2167 if (i + ctx->base.header_size > PAGE_SIZE)
2168 return;
2169
2170 /*
2171 * The iso header is byteswapped to little endian by
2172 * the controller, but the remaining header quadlets
2173 * are big endian. We want to present all the headers
2174 * as big endian, so we have to swap the first quadlet.
2175 */
2176 if (ctx->base.header_size > 0)
2177 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
2178 if (ctx->base.header_size > 4)
2179 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
2180 if (ctx->base.header_size > 8)
2181 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
2182 ctx->header_length += ctx->base.header_size;
2183 }
2184
2185 static int handle_ir_packet_per_buffer(struct context *context,
2186 struct descriptor *d,
2187 struct descriptor *last)
2188 {
2189 struct iso_context *ctx =
2190 container_of(context, struct iso_context, context);
2191 struct descriptor *pd;
2192 __le32 *ir_header;
2193 void *p;
2194
2195 for (pd = d; pd <= last; pd++) {
2196 if (pd->transfer_status)
2197 break;
2198 }
2199 if (pd > last)
2200 /* Descriptor(s) not done yet, stop iteration */
2201 return 0;
2202
2203 p = last + 1;
2204 copy_iso_headers(ctx, p);
2205
2206 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2207 ir_header = (__le32 *) p;
2208 ctx->base.callback(&ctx->base,
2209 le32_to_cpu(ir_header[0]) & 0xffff,
2210 ctx->header_length, ctx->header,
2211 ctx->base.callback_data);
2212 ctx->header_length = 0;
2213 }
2214
2215 return 1;
2216 }
2217
2218 static int handle_it_packet(struct context *context,
2219 struct descriptor *d,
2220 struct descriptor *last)
2221 {
2222 struct iso_context *ctx =
2223 container_of(context, struct iso_context, context);
2224 int i;
2225 struct descriptor *pd;
2226
2227 for (pd = d; pd <= last; pd++)
2228 if (pd->transfer_status)
2229 break;
2230 if (pd > last)
2231 /* Descriptor(s) not done yet, stop iteration */
2232 return 0;
2233
2234 i = ctx->header_length;
2235 if (i + 4 < PAGE_SIZE) {
2236 /* Present this value as big-endian to match the receive code */
2237 *(__be32 *)(ctx->header + i) = cpu_to_be32(
2238 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2239 le16_to_cpu(pd->res_count));
2240 ctx->header_length += 4;
2241 }
2242 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
2243 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
2244 ctx->header_length, ctx->header,
2245 ctx->base.callback_data);
2246 ctx->header_length = 0;
2247 }
2248 return 1;
2249 }
2250
2251 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2252 int type, int channel, size_t header_size)
2253 {
2254 struct fw_ohci *ohci = fw_ohci(card);
2255 struct iso_context *ctx, *list;
2256 descriptor_callback_t callback;
2257 u64 *channels, dont_care = ~0ULL;
2258 u32 *mask, regs;
2259 unsigned long flags;
2260 int index, ret = -ENOMEM;
2261
2262 if (type == FW_ISO_CONTEXT_TRANSMIT) {
2263 channels = &dont_care;
2264 mask = &ohci->it_context_mask;
2265 list = ohci->it_context_list;
2266 callback = handle_it_packet;
2267 } else {
2268 channels = &ohci->ir_context_channels;
2269 mask = &ohci->ir_context_mask;
2270 list = ohci->ir_context_list;
2271 callback = handle_ir_packet_per_buffer;
2272 }
2273
2274 spin_lock_irqsave(&ohci->lock, flags);
2275 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2276 if (index >= 0) {
2277 *channels &= ~(1ULL << channel);
2278 *mask &= ~(1 << index);
2279 }
2280 spin_unlock_irqrestore(&ohci->lock, flags);
2281
2282 if (index < 0)
2283 return ERR_PTR(-EBUSY);
2284
2285 if (type == FW_ISO_CONTEXT_TRANSMIT)
2286 regs = OHCI1394_IsoXmitContextBase(index);
2287 else
2288 regs = OHCI1394_IsoRcvContextBase(index);
2289
2290 ctx = &list[index];
2291 memset(ctx, 0, sizeof(*ctx));
2292 ctx->header_length = 0;
2293 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2294 if (ctx->header == NULL)
2295 goto out;
2296
2297 ret = context_init(&ctx->context, ohci, regs, callback);
2298 if (ret < 0)
2299 goto out_with_header;
2300
2301 return &ctx->base;
2302
2303 out_with_header:
2304 free_page((unsigned long)ctx->header);
2305 out:
2306 spin_lock_irqsave(&ohci->lock, flags);
2307 *mask |= 1 << index;
2308 spin_unlock_irqrestore(&ohci->lock, flags);
2309
2310 return ERR_PTR(ret);
2311 }
2312
2313 static int ohci_start_iso(struct fw_iso_context *base,
2314 s32 cycle, u32 sync, u32 tags)
2315 {
2316 struct iso_context *ctx = container_of(base, struct iso_context, base);
2317 struct fw_ohci *ohci = ctx->context.ohci;
2318 u32 control, match;
2319 int index;
2320
2321 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2322 index = ctx - ohci->it_context_list;
2323 match = 0;
2324 if (cycle >= 0)
2325 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2326 (cycle & 0x7fff) << 16;
2327
2328 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2329 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2330 context_run(&ctx->context, match);
2331 } else {
2332 index = ctx - ohci->ir_context_list;
2333 control = IR_CONTEXT_ISOCH_HEADER;
2334 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2335 if (cycle >= 0) {
2336 match |= (cycle & 0x07fff) << 12;
2337 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2338 }
2339
2340 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2341 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2342 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2343 context_run(&ctx->context, control);
2344 }
2345
2346 return 0;
2347 }
2348
2349 static int ohci_stop_iso(struct fw_iso_context *base)
2350 {
2351 struct fw_ohci *ohci = fw_ohci(base->card);
2352 struct iso_context *ctx = container_of(base, struct iso_context, base);
2353 int index;
2354
2355 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2356 index = ctx - ohci->it_context_list;
2357 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2358 } else {
2359 index = ctx - ohci->ir_context_list;
2360 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2361 }
2362 flush_writes(ohci);
2363 context_stop(&ctx->context);
2364
2365 return 0;
2366 }
2367
2368 static void ohci_free_iso_context(struct fw_iso_context *base)
2369 {
2370 struct fw_ohci *ohci = fw_ohci(base->card);
2371 struct iso_context *ctx = container_of(base, struct iso_context, base);
2372 unsigned long flags;
2373 int index;
2374
2375 ohci_stop_iso(base);
2376 context_release(&ctx->context);
2377 free_page((unsigned long)ctx->header);
2378
2379 spin_lock_irqsave(&ohci->lock, flags);
2380
2381 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2382 index = ctx - ohci->it_context_list;
2383 ohci->it_context_mask |= 1 << index;
2384 } else {
2385 index = ctx - ohci->ir_context_list;
2386 ohci->ir_context_mask |= 1 << index;
2387 ohci->ir_context_channels |= 1ULL << base->channel;
2388 }
2389
2390 spin_unlock_irqrestore(&ohci->lock, flags);
2391 }
2392
2393 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2394 struct fw_iso_packet *packet,
2395 struct fw_iso_buffer *buffer,
2396 unsigned long payload)
2397 {
2398 struct iso_context *ctx = container_of(base, struct iso_context, base);
2399 struct descriptor *d, *last, *pd;
2400 struct fw_iso_packet *p;
2401 __le32 *header;
2402 dma_addr_t d_bus, page_bus;
2403 u32 z, header_z, payload_z, irq;
2404 u32 payload_index, payload_end_index, next_page_index;
2405 int page, end_page, i, length, offset;
2406
2407 p = packet;
2408 payload_index = payload;
2409
2410 if (p->skip)
2411 z = 1;
2412 else
2413 z = 2;
2414 if (p->header_length > 0)
2415 z++;
2416
2417 /* Determine the first page the payload isn't contained in. */
2418 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2419 if (p->payload_length > 0)
2420 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2421 else
2422 payload_z = 0;
2423
2424 z += payload_z;
2425
2426 /* Get header size in number of descriptors. */
2427 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2428
2429 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2430 if (d == NULL)
2431 return -ENOMEM;
2432
2433 if (!p->skip) {
2434 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2435 d[0].req_count = cpu_to_le16(8);
2436 /*
2437 * Link the skip address to this descriptor itself. This causes
2438 * a context to skip a cycle whenever lost cycles or FIFO
2439 * overruns occur, without dropping the data. The application
2440 * should then decide whether this is an error condition or not.
2441 * FIXME: Make the context's cycle-lost behaviour configurable?
2442 */
2443 d[0].branch_address = cpu_to_le32(d_bus | z);
2444
2445 header = (__le32 *) &d[1];
2446 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2447 IT_HEADER_TAG(p->tag) |
2448 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2449 IT_HEADER_CHANNEL(ctx->base.channel) |
2450 IT_HEADER_SPEED(ctx->base.speed));
2451 header[1] =
2452 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2453 p->payload_length));
2454 }
2455
2456 if (p->header_length > 0) {
2457 d[2].req_count = cpu_to_le16(p->header_length);
2458 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2459 memcpy(&d[z], p->header, p->header_length);
2460 }
2461
2462 pd = d + z - payload_z;
2463 payload_end_index = payload_index + p->payload_length;
2464 for (i = 0; i < payload_z; i++) {
2465 page = payload_index >> PAGE_SHIFT;
2466 offset = payload_index & ~PAGE_MASK;
2467 next_page_index = (page + 1) << PAGE_SHIFT;
2468 length =
2469 min(next_page_index, payload_end_index) - payload_index;
2470 pd[i].req_count = cpu_to_le16(length);
2471
2472 page_bus = page_private(buffer->pages[page]);
2473 pd[i].data_address = cpu_to_le32(page_bus + offset);
2474
2475 payload_index += length;
2476 }
2477
2478 if (p->interrupt)
2479 irq = DESCRIPTOR_IRQ_ALWAYS;
2480 else
2481 irq = DESCRIPTOR_NO_IRQ;
2482
2483 last = z == 2 ? d : d + z - 1;
2484 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2485 DESCRIPTOR_STATUS |
2486 DESCRIPTOR_BRANCH_ALWAYS |
2487 irq);
2488
2489 context_append(&ctx->context, d, z, header_z);
2490
2491 return 0;
2492 }
2493
2494 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2495 struct fw_iso_packet *packet,
2496 struct fw_iso_buffer *buffer,
2497 unsigned long payload)
2498 {
2499 struct iso_context *ctx = container_of(base, struct iso_context, base);
2500 struct descriptor *d, *pd;
2501 struct fw_iso_packet *p = packet;
2502 dma_addr_t d_bus, page_bus;
2503 u32 z, header_z, rest;
2504 int i, j, length;
2505 int page, offset, packet_count, header_size, payload_per_buffer;
2506
2507 /*
2508 * The OHCI controller puts the isochronous header and trailer in the
2509 * buffer, so we need at least 8 bytes.
2510 */
2511 packet_count = p->header_length / ctx->base.header_size;
2512 header_size = max(ctx->base.header_size, (size_t)8);
2513
2514 /* Get header size in number of descriptors. */
2515 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2516 page = payload >> PAGE_SHIFT;
2517 offset = payload & ~PAGE_MASK;
2518 payload_per_buffer = p->payload_length / packet_count;
2519
2520 for (i = 0; i < packet_count; i++) {
2521 /* d points to the header descriptor */
2522 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2523 d = context_get_descriptors(&ctx->context,
2524 z + header_z, &d_bus);
2525 if (d == NULL)
2526 return -ENOMEM;
2527
2528 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2529 DESCRIPTOR_INPUT_MORE);
2530 if (p->skip && i == 0)
2531 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2532 d->req_count = cpu_to_le16(header_size);
2533 d->res_count = d->req_count;
2534 d->transfer_status = 0;
2535 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2536
2537 rest = payload_per_buffer;
2538 pd = d;
2539 for (j = 1; j < z; j++) {
2540 pd++;
2541 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2542 DESCRIPTOR_INPUT_MORE);
2543
2544 if (offset + rest < PAGE_SIZE)
2545 length = rest;
2546 else
2547 length = PAGE_SIZE - offset;
2548 pd->req_count = cpu_to_le16(length);
2549 pd->res_count = pd->req_count;
2550 pd->transfer_status = 0;
2551
2552 page_bus = page_private(buffer->pages[page]);
2553 pd->data_address = cpu_to_le32(page_bus + offset);
2554
2555 offset = (offset + length) & ~PAGE_MASK;
2556 rest -= length;
2557 if (offset == 0)
2558 page++;
2559 }
2560 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2561 DESCRIPTOR_INPUT_LAST |
2562 DESCRIPTOR_BRANCH_ALWAYS);
2563 if (p->interrupt && i == packet_count - 1)
2564 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2565
2566 context_append(&ctx->context, d, z, header_z);
2567 }
2568
2569 return 0;
2570 }
2571
2572 static int ohci_queue_iso(struct fw_iso_context *base,
2573 struct fw_iso_packet *packet,
2574 struct fw_iso_buffer *buffer,
2575 unsigned long payload)
2576 {
2577 struct iso_context *ctx = container_of(base, struct iso_context, base);
2578 unsigned long flags;
2579 int ret;
2580
2581 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2582 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2583 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2584 else
2585 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2586 buffer, payload);
2587 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2588
2589 return ret;
2590 }
2591
2592 static const struct fw_card_driver ohci_driver = {
2593 .enable = ohci_enable,
2594 .read_phy_reg = ohci_read_phy_reg,
2595 .update_phy_reg = ohci_update_phy_reg,
2596 .set_config_rom = ohci_set_config_rom,
2597 .send_request = ohci_send_request,
2598 .send_response = ohci_send_response,
2599 .cancel_packet = ohci_cancel_packet,
2600 .enable_phys_dma = ohci_enable_phys_dma,
2601 .read_csr = ohci_read_csr,
2602 .write_csr = ohci_write_csr,
2603
2604 .allocate_iso_context = ohci_allocate_iso_context,
2605 .free_iso_context = ohci_free_iso_context,
2606 .queue_iso = ohci_queue_iso,
2607 .start_iso = ohci_start_iso,
2608 .stop_iso = ohci_stop_iso,
2609 };
2610
2611 #ifdef CONFIG_PPC_PMAC
2612 static void pmac_ohci_on(struct pci_dev *dev)
2613 {
2614 if (machine_is(powermac)) {
2615 struct device_node *ofn = pci_device_to_OF_node(dev);
2616
2617 if (ofn) {
2618 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2619 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2620 }
2621 }
2622 }
2623
2624 static void pmac_ohci_off(struct pci_dev *dev)
2625 {
2626 if (machine_is(powermac)) {
2627 struct device_node *ofn = pci_device_to_OF_node(dev);
2628
2629 if (ofn) {
2630 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2631 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2632 }
2633 }
2634 }
2635 #else
2636 static inline void pmac_ohci_on(struct pci_dev *dev) {}
2637 static inline void pmac_ohci_off(struct pci_dev *dev) {}
2638 #endif /* CONFIG_PPC_PMAC */
2639
2640 static int __devinit pci_probe(struct pci_dev *dev,
2641 const struct pci_device_id *ent)
2642 {
2643 struct fw_ohci *ohci;
2644 u32 bus_options, max_receive, link_speed, version, link_enh;
2645 u64 guid;
2646 int i, err, n_ir, n_it;
2647 size_t size;
2648
2649 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2650 if (ohci == NULL) {
2651 err = -ENOMEM;
2652 goto fail;
2653 }
2654
2655 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2656
2657 pmac_ohci_on(dev);
2658
2659 err = pci_enable_device(dev);
2660 if (err) {
2661 fw_error("Failed to enable OHCI hardware\n");
2662 goto fail_free;
2663 }
2664
2665 pci_set_master(dev);
2666 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2667 pci_set_drvdata(dev, ohci);
2668
2669 spin_lock_init(&ohci->lock);
2670 mutex_init(&ohci->phy_reg_mutex);
2671
2672 tasklet_init(&ohci->bus_reset_tasklet,
2673 bus_reset_tasklet, (unsigned long)ohci);
2674
2675 err = pci_request_region(dev, 0, ohci_driver_name);
2676 if (err) {
2677 fw_error("MMIO resource unavailable\n");
2678 goto fail_disable;
2679 }
2680
2681 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2682 if (ohci->registers == NULL) {
2683 fw_error("Failed to remap registers\n");
2684 err = -ENXIO;
2685 goto fail_iomem;
2686 }
2687
2688 for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
2689 if (ohci_quirks[i].vendor == dev->vendor &&
2690 (ohci_quirks[i].device == dev->device ||
2691 ohci_quirks[i].device == (unsigned short)PCI_ANY_ID)) {
2692 ohci->quirks = ohci_quirks[i].flags;
2693 break;
2694 }
2695 if (param_quirks)
2696 ohci->quirks = param_quirks;
2697
2698 /* TI OHCI-Lynx and compatible: set recommended configuration bits. */
2699 if (dev->vendor == PCI_VENDOR_ID_TI) {
2700 pci_read_config_dword(dev, PCI_CFG_TI_LinkEnh, &link_enh);
2701
2702 /* adjust latency of ATx FIFO: use 1.7 KB threshold */
2703 link_enh &= ~TI_LinkEnh_atx_thresh_mask;
2704 link_enh |= TI_LinkEnh_atx_thresh_1_7K;
2705
2706 /* use priority arbitration for asynchronous responses */
2707 link_enh |= TI_LinkEnh_enab_unfair;
2708
2709 /* required for aPhyEnhanceEnable to work */
2710 link_enh |= TI_LinkEnh_enab_accel;
2711
2712 pci_write_config_dword(dev, PCI_CFG_TI_LinkEnh, link_enh);
2713 }
2714
2715 ar_context_init(&ohci->ar_request_ctx, ohci,
2716 OHCI1394_AsReqRcvContextControlSet);
2717
2718 ar_context_init(&ohci->ar_response_ctx, ohci,
2719 OHCI1394_AsRspRcvContextControlSet);
2720
2721 context_init(&ohci->at_request_ctx, ohci,
2722 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2723
2724 context_init(&ohci->at_response_ctx, ohci,
2725 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2726
2727 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2728 ohci->ir_context_channels = ~0ULL;
2729 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2730 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2731 n_ir = hweight32(ohci->ir_context_mask);
2732 size = sizeof(struct iso_context) * n_ir;
2733 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2734
2735 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2736 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2737 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2738 n_it = hweight32(ohci->it_context_mask);
2739 size = sizeof(struct iso_context) * n_it;
2740 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2741
2742 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2743 err = -ENOMEM;
2744 goto fail_contexts;
2745 }
2746
2747 /* self-id dma buffer allocation */
2748 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2749 SELF_ID_BUF_SIZE,
2750 &ohci->self_id_bus,
2751 GFP_KERNEL);
2752 if (ohci->self_id_cpu == NULL) {
2753 err = -ENOMEM;
2754 goto fail_contexts;
2755 }
2756
2757 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2758 max_receive = (bus_options >> 12) & 0xf;
2759 link_speed = bus_options & 0x7;
2760 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2761 reg_read(ohci, OHCI1394_GUIDLo);
2762
2763 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2764 if (err)
2765 goto fail_self_id;
2766
2767 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2768 fw_notify("Added fw-ohci device %s, OHCI v%x.%x, "
2769 "%d IR + %d IT contexts, quirks 0x%x\n",
2770 dev_name(&dev->dev), version >> 16, version & 0xff,
2771 n_ir, n_it, ohci->quirks);
2772
2773 return 0;
2774
2775 fail_self_id:
2776 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2777 ohci->self_id_cpu, ohci->self_id_bus);
2778 fail_contexts:
2779 kfree(ohci->ir_context_list);
2780 kfree(ohci->it_context_list);
2781 context_release(&ohci->at_response_ctx);
2782 context_release(&ohci->at_request_ctx);
2783 ar_context_release(&ohci->ar_response_ctx);
2784 ar_context_release(&ohci->ar_request_ctx);
2785 pci_iounmap(dev, ohci->registers);
2786 fail_iomem:
2787 pci_release_region(dev, 0);
2788 fail_disable:
2789 pci_disable_device(dev);
2790 fail_free:
2791 kfree(&ohci->card);
2792 pmac_ohci_off(dev);
2793 fail:
2794 if (err == -ENOMEM)
2795 fw_error("Out of memory\n");
2796
2797 return err;
2798 }
2799
2800 static void pci_remove(struct pci_dev *dev)
2801 {
2802 struct fw_ohci *ohci;
2803
2804 ohci = pci_get_drvdata(dev);
2805 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2806 flush_writes(ohci);
2807 fw_core_remove_card(&ohci->card);
2808
2809 /*
2810 * FIXME: Fail all pending packets here, now that the upper
2811 * layers can't queue any more.
2812 */
2813
2814 software_reset(ohci);
2815 free_irq(dev->irq, ohci);
2816
2817 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2818 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2819 ohci->next_config_rom, ohci->next_config_rom_bus);
2820 if (ohci->config_rom)
2821 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2822 ohci->config_rom, ohci->config_rom_bus);
2823 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2824 ohci->self_id_cpu, ohci->self_id_bus);
2825 ar_context_release(&ohci->ar_request_ctx);
2826 ar_context_release(&ohci->ar_response_ctx);
2827 context_release(&ohci->at_request_ctx);
2828 context_release(&ohci->at_response_ctx);
2829 kfree(ohci->it_context_list);
2830 kfree(ohci->ir_context_list);
2831 pci_disable_msi(dev);
2832 pci_iounmap(dev, ohci->registers);
2833 pci_release_region(dev, 0);
2834 pci_disable_device(dev);
2835 kfree(&ohci->card);
2836 pmac_ohci_off(dev);
2837
2838 fw_notify("Removed fw-ohci device.\n");
2839 }
2840
2841 #ifdef CONFIG_PM
2842 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2843 {
2844 struct fw_ohci *ohci = pci_get_drvdata(dev);
2845 int err;
2846
2847 software_reset(ohci);
2848 free_irq(dev->irq, ohci);
2849 pci_disable_msi(dev);
2850 err = pci_save_state(dev);
2851 if (err) {
2852 fw_error("pci_save_state failed\n");
2853 return err;
2854 }
2855 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2856 if (err)
2857 fw_error("pci_set_power_state failed with %d\n", err);
2858 pmac_ohci_off(dev);
2859
2860 return 0;
2861 }
2862
2863 static int pci_resume(struct pci_dev *dev)
2864 {
2865 struct fw_ohci *ohci = pci_get_drvdata(dev);
2866 int err;
2867
2868 pmac_ohci_on(dev);
2869 pci_set_power_state(dev, PCI_D0);
2870 pci_restore_state(dev);
2871 err = pci_enable_device(dev);
2872 if (err) {
2873 fw_error("pci_enable_device failed\n");
2874 return err;
2875 }
2876
2877 return ohci_enable(&ohci->card, NULL, 0);
2878 }
2879 #endif
2880
2881 static const struct pci_device_id pci_table[] = {
2882 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2883 { }
2884 };
2885
2886 MODULE_DEVICE_TABLE(pci, pci_table);
2887
2888 static struct pci_driver fw_ohci_pci_driver = {
2889 .name = ohci_driver_name,
2890 .id_table = pci_table,
2891 .probe = pci_probe,
2892 .remove = pci_remove,
2893 #ifdef CONFIG_PM
2894 .resume = pci_resume,
2895 .suspend = pci_suspend,
2896 #endif
2897 };
2898
2899 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2900 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2901 MODULE_LICENSE("GPL");
2902
2903 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2904 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2905 MODULE_ALIAS("ohci1394");
2906 #endif
2907
2908 static int __init fw_ohci_init(void)
2909 {
2910 return pci_register_driver(&fw_ohci_pci_driver);
2911 }
2912
2913 static void __exit fw_ohci_cleanup(void)
2914 {
2915 pci_unregister_driver(&fw_ohci_pci_driver);
2916 }
2917
2918 module_init(fw_ohci_init);
2919 module_exit(fw_ohci_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree