arch/arm/mach-orion5x/addr-map.c

   1 /*
   2  * arch/arm/mach-orion5x/addr-map.c
   3  *
   4  * Address map functions for Marvell Orion 5x SoCs
   5  *
   6  * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
   7  *
   8  * This file is licensed under the terms of the GNU General Public
   9  * License version 2.  This program is licensed "as is" without any
  10  * warranty of any kind, whether express or implied.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/mbus.h>
  16 #include <linux/io.h>
  17 #include <mach/hardware.h>
  18 #include "common.h"
  19
  20 /*
  21  * The Orion has fully programable address map. There's a separate address
  22  * map for each of the device _master_ interfaces, e.g. CPU, PCI, PCIe, USB,
  23  * Gigabit Ethernet, DMA/XOR engines, etc. Each interface has its own
  24  * address decode windows that allow it to access any of the Orion resources.
  25  *
  26  * CPU address decoding --
  27  * Linux assumes that it is the boot loader that already setup the access to
  28  * DDR and internal registers.
  29  * Setup access to PCI and PCIe IO/MEM space is issued by this file.
  30  * Setup access to various devices located on the device bus interface (e.g.
  31  * flashes, RTC, etc) should be issued by machine-setup.c according to
  32  * specific board population (by using orion5x_setup_*_win()).
  33  *
  34  * Non-CPU Masters address decoding --
  35  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  36  * banks only (the typical use case).
  37  * Setup access for each master to DDR is issued by platform device setup.
  38  */
  39
  40 /*
  41  * Generic Address Decode Windows bit settings
  42  */
  43 #define TARGET_DDR              0
  44 #define TARGET_DEV_BUS          1
  45 #define TARGET_PCI              3
  46 #define TARGET_PCIE             4
  47 #define ATTR_PCIE_MEM           0x59
  48 #define ATTR_PCIE_IO            0x51
  49 #define ATTR_PCIE_WA            0x79
  50 #define ATTR_PCI_MEM            0x59
  51 #define ATTR_PCI_IO             0x51
  52 #define ATTR_DEV_CS0            0x1e
  53 #define ATTR_DEV_CS1            0x1d
  54 #define ATTR_DEV_CS2            0x1b
  55 #define ATTR_DEV_BOOT           0xf
  56
  57 /*
  58  * Helpers to get DDR bank info
  59  */
  60 #define DDR_BASE_CS(n)          ORION5X_DDR_REG(0x1500 + ((n) << 3))
  61 #define DDR_SIZE_CS(n)          ORION5X_DDR_REG(0x1504 + ((n) << 3))
  62
  63 /*
  64  * CPU Address Decode Windows registers
  65  */
  66 #define CPU_WIN_CTRL(n)         ORION5X_BRIDGE_REG(0x000 | ((n) << 4))
  67 #define CPU_WIN_BASE(n)         ORION5X_BRIDGE_REG(0x004 | ((n) << 4))
  68 #define CPU_WIN_REMAP_LO(n)     ORION5X_BRIDGE_REG(0x008 | ((n) << 4))
  69 #define CPU_WIN_REMAP_HI(n)     ORION5X_BRIDGE_REG(0x00c | ((n) << 4))
  70
  71
  72 struct mbus_dram_target_info orion5x_mbus_dram_info;
  73 static int __initdata win_alloc_count;
  74
  75 static int __init orion5x_cpu_win_can_remap(int win)
  76 {
  77         u32 dev, rev;
  78
  79         orion5x_pcie_id(&dev, &rev);
  80         if ((dev == MV88F5281_DEV_ID && win < 4)
  81             || (dev == MV88F5182_DEV_ID && win < 2)
  82             || (dev == MV88F5181_DEV_ID && win < 2))
  83                 return 1;
  84
  85         return 0;
  86 }
  87
  88 static void __init setup_cpu_win(int win, u32 base, u32 size,
  89                                  u8 target, u8 attr, int remap)
  90 {
  91         if (win >= 8) {
  92                 printk(KERN_ERR "setup_cpu_win: trying to allocate "
  93                                 "window %d\n", win);
  94                 return;
  95         }
  96
  97         writel(base & 0xffff0000, CPU_WIN_BASE(win));
  98         writel(((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1,
  99                 CPU_WIN_CTRL(win));
 100
 101         if (orion5x_cpu_win_can_remap(win)) {
 102                 if (remap < 0)
 103                         remap = base;
 104
 105                 writel(remap & 0xffff0000, CPU_WIN_REMAP_LO(win));
 106                 writel(0, CPU_WIN_REMAP_HI(win));
 107         }
 108 }
 109
 110 void __init orion5x_setup_cpu_mbus_bridge(void)
 111 {
 112         int i;
 113         int cs;
 114
 115         /*
 116          * First, disable and clear windows.
 117          */
 118         for (i = 0; i < 8; i++) {
 119                 writel(0, CPU_WIN_BASE(i));
 120                 writel(0, CPU_WIN_CTRL(i));
 121                 if (orion5x_cpu_win_can_remap(i)) {
 122                         writel(0, CPU_WIN_REMAP_LO(i));
 123                         writel(0, CPU_WIN_REMAP_HI(i));
 124                 }
 125         }
 126
 127         /*
 128          * Setup windows for PCI+PCIe IO+MEM space.
 129          */
 130         setup_cpu_win(0, ORION5X_PCIE_IO_PHYS_BASE, ORION5X_PCIE_IO_SIZE,
 131                 TARGET_PCIE, ATTR_PCIE_IO, ORION5X_PCIE_IO_BUS_BASE);
 132         setup_cpu_win(1, ORION5X_PCI_IO_PHYS_BASE, ORION5X_PCI_IO_SIZE,
 133                 TARGET_PCI, ATTR_PCI_IO, ORION5X_PCI_IO_BUS_BASE);
 134         setup_cpu_win(2, ORION5X_PCIE_MEM_PHYS_BASE, ORION5X_PCIE_MEM_SIZE,
 135                 TARGET_PCIE, ATTR_PCIE_MEM, -1);
 136         setup_cpu_win(3, ORION5X_PCI_MEM_PHYS_BASE, ORION5X_PCI_MEM_SIZE,
 137                 TARGET_PCI, ATTR_PCI_MEM, -1);
 138         win_alloc_count = 4;
 139
 140         /*
 141          * Setup MBUS dram target info.
 142          */
 143         orion5x_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 144
 145         for (i = 0, cs = 0; i < 4; i++) {
 146                 u32 base = readl(DDR_BASE_CS(i));
 147                 u32 size = readl(DDR_SIZE_CS(i));
 148
 149                 /*
 150                  * Chip select enabled?
 151                  */
 152                 if (size & 1) {
 153                         struct mbus_dram_window *w;
 154
 155                         w = &orion5x_mbus_dram_info.cs[cs++];
 156                         w->cs_index = i;
 157                         w->mbus_attr = 0xf & ~(1 << i);
 158                         w->base = base & 0xffff0000;
 159                         w->size = (size | 0x0000ffff) + 1;
 160                 }
 161         }
 162         orion5x_mbus_dram_info.num_cs = cs;
 163 }
 164
 165 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
 166 {
 167         setup_cpu_win(win_alloc_count++, base, size,
 168                       TARGET_DEV_BUS, ATTR_DEV_BOOT, -1);
 169 }
 170
 171 void __init orion5x_setup_dev0_win(u32 base, u32 size)
 172 {
 173         setup_cpu_win(win_alloc_count++, base, size,
 174                       TARGET_DEV_BUS, ATTR_DEV_CS0, -1);
 175 }
 176
 177 void __init orion5x_setup_dev1_win(u32 base, u32 size)
 178 {
 179         setup_cpu_win(win_alloc_count++, base, size,
 180                       TARGET_DEV_BUS, ATTR_DEV_CS1, -1);
 181 }
 182
 183 void __init orion5x_setup_dev2_win(u32 base, u32 size)
 184 {
 185         setup_cpu_win(win_alloc_count++, base, size,
 186                       TARGET_DEV_BUS, ATTR_DEV_CS2, -1);
 187 }
 188
 189 void __init orion5x_setup_pcie_wa_win(u32 base, u32 size)
 190 {
 191         setup_cpu_win(win_alloc_count++, base, size,
 192                       TARGET_PCIE, ATTR_PCIE_WA, -1);
 193 }