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MIPS: MTX-1: Fix PCI on the MeshCube and related boards
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / r8169.c
blob17382c390b8adfc6f3199d69befad04f7d60ce75
1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/delay.h>
17 #include <linux/ethtool.h>
18 #include <linux/mii.h>
19 #include <linux/if_vlan.h>
20 #include <linux/crc32.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/tcp.h>
24 #include <linux/init.h>
25 #include <linux/dma-mapping.h>
26
27 #include <asm/system.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30
31 #define RTL8169_VERSION "2.3LK-NAPI"
32 #define MODULENAME "r8169"
33 #define PFX MODULENAME ": "
34
35 #ifdef RTL8169_DEBUG
36 #define assert(expr) \
37 if (!(expr)) { \
38 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
39 #expr,__FILE__,__func__,__LINE__); \
40 }
41 #define dprintk(fmt, args...) \
42 do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
43 #else
44 #define assert(expr) do {} while (0)
45 #define dprintk(fmt, args...) do {} while (0)
46 #endif /* RTL8169_DEBUG */
47
48 #define R8169_MSG_DEFAULT \
49 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
50
51 #define TX_BUFFS_AVAIL(tp) \
52 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
53
54 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
55 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
56 static const int multicast_filter_limit = 32;
57
58 /* MAC address length */
59 #define MAC_ADDR_LEN 6
60
61 #define MAX_READ_REQUEST_SHIFT 12
62 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
63 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
64 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
65 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
66 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
67 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
68
69 #define R8169_REGS_SIZE 256
70 #define R8169_NAPI_WEIGHT 64
71 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
72 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
73 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
74 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
75 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
76
77 #define RTL8169_TX_TIMEOUT (6*HZ)
78 #define RTL8169_PHY_TIMEOUT (10*HZ)
79
80 #define RTL_EEPROM_SIG cpu_to_le32(0x8129)
81 #define RTL_EEPROM_SIG_MASK cpu_to_le32(0xffff)
82 #define RTL_EEPROM_SIG_ADDR 0x0000
83
84 /* write/read MMIO register */
85 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
86 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
87 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
88 #define RTL_R8(reg) readb (ioaddr + (reg))
89 #define RTL_R16(reg) readw (ioaddr + (reg))
90 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
91
92 enum mac_version {
93 RTL_GIGA_MAC_NONE = 0x00,
94 RTL_GIGA_MAC_VER_01 = 0x01, // 8169
95 RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
96 RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
97 RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
98 RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
99 RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
100 RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
101 RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
102 RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
103 RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
104 RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
105 RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
106 RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
107 RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
108 RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
109 RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
110 RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
111 RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
112 RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
113 RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
114 RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
115 RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
116 RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
117 RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
118 RTL_GIGA_MAC_VER_25 = 0x19, // 8168D
119 RTL_GIGA_MAC_VER_26 = 0x1a, // 8168D
120 RTL_GIGA_MAC_VER_27 = 0x1b // 8168DP
121 };
122
123 #define _R(NAME,MAC,MASK) \
124 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
125
126 static const struct {
127 const char *name;
128 u8 mac_version;
129 u32 RxConfigMask; /* Clears the bits supported by this chip */
130 } rtl_chip_info[] = {
131 _R("RTL8169", RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
132 _R("RTL8169s", RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
133 _R("RTL8110s", RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
134 _R("RTL8169sb/8110sb", RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
135 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
136 _R("RTL8169sc/8110sc", RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
137 _R("RTL8102e", RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
138 _R("RTL8102e", RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
139 _R("RTL8102e", RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
140 _R("RTL8101e", RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
141 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
142 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
143 _R("RTL8101e", RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
144 _R("RTL8100e", RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
145 _R("RTL8100e", RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
146 _R("RTL8168b/8111b", RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
147 _R("RTL8101e", RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
148 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
149 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
150 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
151 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
152 _R("RTL8168c/8111c", RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
153 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
154 _R("RTL8168cp/8111cp", RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
155 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_25, 0xff7e1880), // PCI-E
156 _R("RTL8168d/8111d", RTL_GIGA_MAC_VER_26, 0xff7e1880), // PCI-E
157 _R("RTL8168dp/8111dp", RTL_GIGA_MAC_VER_27, 0xff7e1880) // PCI-E
158 };
159 #undef _R
160
161 enum cfg_version {
162 RTL_CFG_0 = 0x00,
163 RTL_CFG_1,
164 RTL_CFG_2
165 };
166
167 static void rtl_hw_start_8169(struct net_device *);
168 static void rtl_hw_start_8168(struct net_device *);
169 static void rtl_hw_start_8101(struct net_device *);
170
171 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
172 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
173 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
174 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
175 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
176 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
177 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
178 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
179 { PCI_DEVICE(0x16ec, 0x0116), 0, 0, RTL_CFG_0 },
180 { PCI_VENDOR_ID_LINKSYS, 0x1032,
181 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
182 { 0x0001, 0x8168,
183 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
184 {0,},
185 };
186
187 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
188
189 /*
190 * we set our copybreak very high so that we don't have
191 * to allocate 16k frames all the time (see note in
192 * rtl8169_open()
193 */
194 static int rx_copybreak = 16383;
195 static int use_dac;
196 static struct {
197 u32 msg_enable;
198 } debug = { -1 };
199
200 enum rtl_registers {
201 MAC0 = 0, /* Ethernet hardware address. */
202 MAC4 = 4,
203 MAR0 = 8, /* Multicast filter. */
204 CounterAddrLow = 0x10,
205 CounterAddrHigh = 0x14,
206 TxDescStartAddrLow = 0x20,
207 TxDescStartAddrHigh = 0x24,
208 TxHDescStartAddrLow = 0x28,
209 TxHDescStartAddrHigh = 0x2c,
210 FLASH = 0x30,
211 ERSR = 0x36,
212 ChipCmd = 0x37,
213 TxPoll = 0x38,
214 IntrMask = 0x3c,
215 IntrStatus = 0x3e,
216 TxConfig = 0x40,
217 RxConfig = 0x44,
218 RxMissed = 0x4c,
219 Cfg9346 = 0x50,
220 Config0 = 0x51,
221 Config1 = 0x52,
222 Config2 = 0x53,
223 Config3 = 0x54,
224 Config4 = 0x55,
225 Config5 = 0x56,
226 MultiIntr = 0x5c,
227 PHYAR = 0x60,
228 PHYstatus = 0x6c,
229 RxMaxSize = 0xda,
230 CPlusCmd = 0xe0,
231 IntrMitigate = 0xe2,
232 RxDescAddrLow = 0xe4,
233 RxDescAddrHigh = 0xe8,
234 EarlyTxThres = 0xec,
235 FuncEvent = 0xf0,
236 FuncEventMask = 0xf4,
237 FuncPresetState = 0xf8,
238 FuncForceEvent = 0xfc,
239 };
240
241 enum rtl8110_registers {
242 TBICSR = 0x64,
243 TBI_ANAR = 0x68,
244 TBI_LPAR = 0x6a,
245 };
246
247 enum rtl8168_8101_registers {
248 CSIDR = 0x64,
249 CSIAR = 0x68,
250 #define CSIAR_FLAG 0x80000000
251 #define CSIAR_WRITE_CMD 0x80000000
252 #define CSIAR_BYTE_ENABLE 0x0f
253 #define CSIAR_BYTE_ENABLE_SHIFT 12
254 #define CSIAR_ADDR_MASK 0x0fff
255
256 EPHYAR = 0x80,
257 #define EPHYAR_FLAG 0x80000000
258 #define EPHYAR_WRITE_CMD 0x80000000
259 #define EPHYAR_REG_MASK 0x1f
260 #define EPHYAR_REG_SHIFT 16
261 #define EPHYAR_DATA_MASK 0xffff
262 DBG_REG = 0xd1,
263 #define FIX_NAK_1 (1 << 4)
264 #define FIX_NAK_2 (1 << 3)
265 EFUSEAR = 0xdc,
266 #define EFUSEAR_FLAG 0x80000000
267 #define EFUSEAR_WRITE_CMD 0x80000000
268 #define EFUSEAR_READ_CMD 0x00000000
269 #define EFUSEAR_REG_MASK 0x03ff
270 #define EFUSEAR_REG_SHIFT 8
271 #define EFUSEAR_DATA_MASK 0xff
272 };
273
274 enum rtl_register_content {
275 /* InterruptStatusBits */
276 SYSErr = 0x8000,
277 PCSTimeout = 0x4000,
278 SWInt = 0x0100,
279 TxDescUnavail = 0x0080,
280 RxFIFOOver = 0x0040,
281 LinkChg = 0x0020,
282 RxOverflow = 0x0010,
283 TxErr = 0x0008,
284 TxOK = 0x0004,
285 RxErr = 0x0002,
286 RxOK = 0x0001,
287
288 /* RxStatusDesc */
289 RxFOVF = (1 << 23),
290 RxRWT = (1 << 22),
291 RxRES = (1 << 21),
292 RxRUNT = (1 << 20),
293 RxCRC = (1 << 19),
294
295 /* ChipCmdBits */
296 CmdReset = 0x10,
297 CmdRxEnb = 0x08,
298 CmdTxEnb = 0x04,
299 RxBufEmpty = 0x01,
300
301 /* TXPoll register p.5 */
302 HPQ = 0x80, /* Poll cmd on the high prio queue */
303 NPQ = 0x40, /* Poll cmd on the low prio queue */
304 FSWInt = 0x01, /* Forced software interrupt */
305
306 /* Cfg9346Bits */
307 Cfg9346_Lock = 0x00,
308 Cfg9346_Unlock = 0xc0,
309
310 /* rx_mode_bits */
311 AcceptErr = 0x20,
312 AcceptRunt = 0x10,
313 AcceptBroadcast = 0x08,
314 AcceptMulticast = 0x04,
315 AcceptMyPhys = 0x02,
316 AcceptAllPhys = 0x01,
317
318 /* RxConfigBits */
319 RxCfgFIFOShift = 13,
320 RxCfgDMAShift = 8,
321
322 /* TxConfigBits */
323 TxInterFrameGapShift = 24,
324 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
325
326 /* Config1 register p.24 */
327 LEDS1 = (1 << 7),
328 LEDS0 = (1 << 6),
329 MSIEnable = (1 << 5), /* Enable Message Signaled Interrupt */
330 Speed_down = (1 << 4),
331 MEMMAP = (1 << 3),
332 IOMAP = (1 << 2),
333 VPD = (1 << 1),
334 PMEnable = (1 << 0), /* Power Management Enable */
335
336 /* Config2 register p. 25 */
337 PCI_Clock_66MHz = 0x01,
338 PCI_Clock_33MHz = 0x00,
339
340 /* Config3 register p.25 */
341 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
342 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
343 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
344
345 /* Config5 register p.27 */
346 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
347 MWF = (1 << 5), /* Accept Multicast wakeup frame */
348 UWF = (1 << 4), /* Accept Unicast wakeup frame */
349 LanWake = (1 << 1), /* LanWake enable/disable */
350 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
351
352 /* TBICSR p.28 */
353 TBIReset = 0x80000000,
354 TBILoopback = 0x40000000,
355 TBINwEnable = 0x20000000,
356 TBINwRestart = 0x10000000,
357 TBILinkOk = 0x02000000,
358 TBINwComplete = 0x01000000,
359
360 /* CPlusCmd p.31 */
361 EnableBist = (1 << 15), // 8168 8101
362 Mac_dbgo_oe = (1 << 14), // 8168 8101
363 Normal_mode = (1 << 13), // unused
364 Force_half_dup = (1 << 12), // 8168 8101
365 Force_rxflow_en = (1 << 11), // 8168 8101
366 Force_txflow_en = (1 << 10), // 8168 8101
367 Cxpl_dbg_sel = (1 << 9), // 8168 8101
368 ASF = (1 << 8), // 8168 8101
369 PktCntrDisable = (1 << 7), // 8168 8101
370 Mac_dbgo_sel = 0x001c, // 8168
371 RxVlan = (1 << 6),
372 RxChkSum = (1 << 5),
373 PCIDAC = (1 << 4),
374 PCIMulRW = (1 << 3),
375 INTT_0 = 0x0000, // 8168
376 INTT_1 = 0x0001, // 8168
377 INTT_2 = 0x0002, // 8168
378 INTT_3 = 0x0003, // 8168
379
380 /* rtl8169_PHYstatus */
381 TBI_Enable = 0x80,
382 TxFlowCtrl = 0x40,
383 RxFlowCtrl = 0x20,
384 _1000bpsF = 0x10,
385 _100bps = 0x08,
386 _10bps = 0x04,
387 LinkStatus = 0x02,
388 FullDup = 0x01,
389
390 /* _TBICSRBit */
391 TBILinkOK = 0x02000000,
392
393 /* DumpCounterCommand */
394 CounterDump = 0x8,
395 };
396
397 enum desc_status_bit {
398 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
399 RingEnd = (1 << 30), /* End of descriptor ring */
400 FirstFrag = (1 << 29), /* First segment of a packet */
401 LastFrag = (1 << 28), /* Final segment of a packet */
402
403 /* Tx private */
404 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
405 MSSShift = 16, /* MSS value position */
406 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
407 IPCS = (1 << 18), /* Calculate IP checksum */
408 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
409 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
410 TxVlanTag = (1 << 17), /* Add VLAN tag */
411
412 /* Rx private */
413 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
414 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
415
416 #define RxProtoUDP (PID1)
417 #define RxProtoTCP (PID0)
418 #define RxProtoIP (PID1 | PID0)
419 #define RxProtoMask RxProtoIP
420
421 IPFail = (1 << 16), /* IP checksum failed */
422 UDPFail = (1 << 15), /* UDP/IP checksum failed */
423 TCPFail = (1 << 14), /* TCP/IP checksum failed */
424 RxVlanTag = (1 << 16), /* VLAN tag available */
425 };
426
427 #define RsvdMask 0x3fffc000
428
429 struct TxDesc {
430 __le32 opts1;
431 __le32 opts2;
432 __le64 addr;
433 };
434
435 struct RxDesc {
436 __le32 opts1;
437 __le32 opts2;
438 __le64 addr;
439 };
440
441 struct ring_info {
442 struct sk_buff *skb;
443 u32 len;
444 u8 __pad[sizeof(void *) - sizeof(u32)];
445 };
446
447 enum features {
448 RTL_FEATURE_WOL = (1 << 0),
449 RTL_FEATURE_MSI = (1 << 1),
450 RTL_FEATURE_GMII = (1 << 2),
451 };
452
453 struct rtl8169_counters {
454 __le64 tx_packets;
455 __le64 rx_packets;
456 __le64 tx_errors;
457 __le32 rx_errors;
458 __le16 rx_missed;
459 __le16 align_errors;
460 __le32 tx_one_collision;
461 __le32 tx_multi_collision;
462 __le64 rx_unicast;
463 __le64 rx_broadcast;
464 __le32 rx_multicast;
465 __le16 tx_aborted;
466 __le16 tx_underun;
467 };
468
469 struct rtl8169_private {
470 void __iomem *mmio_addr; /* memory map physical address */
471 struct pci_dev *pci_dev; /* Index of PCI device */
472 struct net_device *dev;
473 struct napi_struct napi;
474 spinlock_t lock; /* spin lock flag */
475 u32 msg_enable;
476 int chipset;
477 int mac_version;
478 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
479 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
480 u32 dirty_rx;
481 u32 dirty_tx;
482 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
483 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
484 dma_addr_t TxPhyAddr;
485 dma_addr_t RxPhyAddr;
486 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
487 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
488 unsigned align;
489 unsigned rx_buf_sz;
490 struct timer_list timer;
491 u16 cp_cmd;
492 u16 intr_event;
493 u16 napi_event;
494 u16 intr_mask;
495 int phy_1000_ctrl_reg;
496 #ifdef CONFIG_R8169_VLAN
497 struct vlan_group *vlgrp;
498 #endif
499 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
500 int (*get_settings)(struct net_device *, struct ethtool_cmd *);
501 void (*phy_reset_enable)(void __iomem *);
502 void (*hw_start)(struct net_device *);
503 unsigned int (*phy_reset_pending)(void __iomem *);
504 unsigned int (*link_ok)(void __iomem *);
505 int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
506 int pcie_cap;
507 struct delayed_work task;
508 unsigned features;
509
510 struct mii_if_info mii;
511 struct rtl8169_counters counters;
512 };
513
514 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
515 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
516 module_param(rx_copybreak, int, 0);
517 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
518 module_param(use_dac, int, 0);
519 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
520 module_param_named(debug, debug.msg_enable, int, 0);
521 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
522 MODULE_LICENSE("GPL");
523 MODULE_VERSION(RTL8169_VERSION);
524
525 static int rtl8169_open(struct net_device *dev);
526 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
527 struct net_device *dev);
528 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
529 static int rtl8169_init_ring(struct net_device *dev);
530 static void rtl_hw_start(struct net_device *dev);
531 static int rtl8169_close(struct net_device *dev);
532 static void rtl_set_rx_mode(struct net_device *dev);
533 static void rtl8169_tx_timeout(struct net_device *dev);
534 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
535 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
536 void __iomem *, u32 budget);
537 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
538 static void rtl8169_down(struct net_device *dev);
539 static void rtl8169_rx_clear(struct rtl8169_private *tp);
540 static int rtl8169_poll(struct napi_struct *napi, int budget);
541
542 static const unsigned int rtl8169_rx_config =
543 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
544
545 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
546 {
547 int i;
548
549 RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
550
551 for (i = 20; i > 0; i--) {
552 /*
553 * Check if the RTL8169 has completed writing to the specified
554 * MII register.
555 */
556 if (!(RTL_R32(PHYAR) & 0x80000000))
557 break;
558 udelay(25);
559 }
560 /*
561 * According to hardware specs a 20us delay is required after write
562 * complete indication, but before sending next command.
563 */
564 udelay(20);
565 }
566
567 static int mdio_read(void __iomem *ioaddr, int reg_addr)
568 {
569 int i, value = -1;
570
571 RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
572
573 for (i = 20; i > 0; i--) {
574 /*
575 * Check if the RTL8169 has completed retrieving data from
576 * the specified MII register.
577 */
578 if (RTL_R32(PHYAR) & 0x80000000) {
579 value = RTL_R32(PHYAR) & 0xffff;
580 break;
581 }
582 udelay(25);
583 }
584 /*
585 * According to hardware specs a 20us delay is required after read
586 * complete indication, but before sending next command.
587 */
588 udelay(20);
589
590 return value;
591 }
592
593 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
594 {
595 mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
596 }
597
598 static void mdio_plus_minus(void __iomem *ioaddr, int reg_addr, int p, int m)
599 {
600 int val;
601
602 val = mdio_read(ioaddr, reg_addr);
603 mdio_write(ioaddr, reg_addr, (val | p) & ~m);
604 }
605
606 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
607 int val)
608 {
609 struct rtl8169_private *tp = netdev_priv(dev);
610 void __iomem *ioaddr = tp->mmio_addr;
611
612 mdio_write(ioaddr, location, val);
613 }
614
615 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
616 {
617 struct rtl8169_private *tp = netdev_priv(dev);
618 void __iomem *ioaddr = tp->mmio_addr;
619
620 return mdio_read(ioaddr, location);
621 }
622
623 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
624 {
625 unsigned int i;
626
627 RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
628 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
629
630 for (i = 0; i < 100; i++) {
631 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
632 break;
633 udelay(10);
634 }
635 }
636
637 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
638 {
639 u16 value = 0xffff;
640 unsigned int i;
641
642 RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
643
644 for (i = 0; i < 100; i++) {
645 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
646 value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
647 break;
648 }
649 udelay(10);
650 }
651
652 return value;
653 }
654
655 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
656 {
657 unsigned int i;
658
659 RTL_W32(CSIDR, value);
660 RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
661 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
662
663 for (i = 0; i < 100; i++) {
664 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
665 break;
666 udelay(10);
667 }
668 }
669
670 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
671 {
672 u32 value = ~0x00;
673 unsigned int i;
674
675 RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
676 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
677
678 for (i = 0; i < 100; i++) {
679 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
680 value = RTL_R32(CSIDR);
681 break;
682 }
683 udelay(10);
684 }
685
686 return value;
687 }
688
689 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
690 {
691 u8 value = 0xff;
692 unsigned int i;
693
694 RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
695
696 for (i = 0; i < 300; i++) {
697 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
698 value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
699 break;
700 }
701 udelay(100);
702 }
703
704 return value;
705 }
706
707 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
708 {
709 RTL_W16(IntrMask, 0x0000);
710
711 RTL_W16(IntrStatus, 0xffff);
712 }
713
714 static void rtl8169_asic_down(void __iomem *ioaddr)
715 {
716 RTL_W8(ChipCmd, 0x00);
717 rtl8169_irq_mask_and_ack(ioaddr);
718 RTL_R16(CPlusCmd);
719 }
720
721 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
722 {
723 return RTL_R32(TBICSR) & TBIReset;
724 }
725
726 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
727 {
728 return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
729 }
730
731 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
732 {
733 return RTL_R32(TBICSR) & TBILinkOk;
734 }
735
736 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
737 {
738 return RTL_R8(PHYstatus) & LinkStatus;
739 }
740
741 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
742 {
743 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
744 }
745
746 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
747 {
748 unsigned int val;
749
750 val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
751 mdio_write(ioaddr, MII_BMCR, val & 0xffff);
752 }
753
754 static void rtl8169_check_link_status(struct net_device *dev,
755 struct rtl8169_private *tp,
756 void __iomem *ioaddr)
757 {
758 unsigned long flags;
759
760 spin_lock_irqsave(&tp->lock, flags);
761 if (tp->link_ok(ioaddr)) {
762 netif_carrier_on(dev);
763 netif_info(tp, ifup, dev, "link up\n");
764 } else {
765 netif_carrier_off(dev);
766 netif_info(tp, ifdown, dev, "link down\n");
767 }
768 spin_unlock_irqrestore(&tp->lock, flags);
769 }
770
771 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
772 {
773 struct rtl8169_private *tp = netdev_priv(dev);
774 void __iomem *ioaddr = tp->mmio_addr;
775 u8 options;
776
777 wol->wolopts = 0;
778
779 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
780 wol->supported = WAKE_ANY;
781
782 spin_lock_irq(&tp->lock);
783
784 options = RTL_R8(Config1);
785 if (!(options & PMEnable))
786 goto out_unlock;
787
788 options = RTL_R8(Config3);
789 if (options & LinkUp)
790 wol->wolopts |= WAKE_PHY;
791 if (options & MagicPacket)
792 wol->wolopts |= WAKE_MAGIC;
793
794 options = RTL_R8(Config5);
795 if (options & UWF)
796 wol->wolopts |= WAKE_UCAST;
797 if (options & BWF)
798 wol->wolopts |= WAKE_BCAST;
799 if (options & MWF)
800 wol->wolopts |= WAKE_MCAST;
801
802 out_unlock:
803 spin_unlock_irq(&tp->lock);
804 }
805
806 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
807 {
808 struct rtl8169_private *tp = netdev_priv(dev);
809 void __iomem *ioaddr = tp->mmio_addr;
810 unsigned int i;
811 static const struct {
812 u32 opt;
813 u16 reg;
814 u8 mask;
815 } cfg[] = {
816 { WAKE_ANY, Config1, PMEnable },
817 { WAKE_PHY, Config3, LinkUp },
818 { WAKE_MAGIC, Config3, MagicPacket },
819 { WAKE_UCAST, Config5, UWF },
820 { WAKE_BCAST, Config5, BWF },
821 { WAKE_MCAST, Config5, MWF },
822 { WAKE_ANY, Config5, LanWake }
823 };
824
825 spin_lock_irq(&tp->lock);
826
827 RTL_W8(Cfg9346, Cfg9346_Unlock);
828
829 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
830 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
831 if (wol->wolopts & cfg[i].opt)
832 options |= cfg[i].mask;
833 RTL_W8(cfg[i].reg, options);
834 }
835
836 RTL_W8(Cfg9346, Cfg9346_Lock);
837
838 if (wol->wolopts)
839 tp->features |= RTL_FEATURE_WOL;
840 else
841 tp->features &= ~RTL_FEATURE_WOL;
842 device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
843
844 spin_unlock_irq(&tp->lock);
845
846 return 0;
847 }
848
849 static void rtl8169_get_drvinfo(struct net_device *dev,
850 struct ethtool_drvinfo *info)
851 {
852 struct rtl8169_private *tp = netdev_priv(dev);
853
854 strcpy(info->driver, MODULENAME);
855 strcpy(info->version, RTL8169_VERSION);
856 strcpy(info->bus_info, pci_name(tp->pci_dev));
857 }
858
859 static int rtl8169_get_regs_len(struct net_device *dev)
860 {
861 return R8169_REGS_SIZE;
862 }
863
864 static int rtl8169_set_speed_tbi(struct net_device *dev,
865 u8 autoneg, u16 speed, u8 duplex)
866 {
867 struct rtl8169_private *tp = netdev_priv(dev);
868 void __iomem *ioaddr = tp->mmio_addr;
869 int ret = 0;
870 u32 reg;
871
872 reg = RTL_R32(TBICSR);
873 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
874 (duplex == DUPLEX_FULL)) {
875 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
876 } else if (autoneg == AUTONEG_ENABLE)
877 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
878 else {
879 netif_warn(tp, link, dev,
880 "incorrect speed setting refused in TBI mode\n");
881 ret = -EOPNOTSUPP;
882 }
883
884 return ret;
885 }
886
887 static int rtl8169_set_speed_xmii(struct net_device *dev,
888 u8 autoneg, u16 speed, u8 duplex)
889 {
890 struct rtl8169_private *tp = netdev_priv(dev);
891 void __iomem *ioaddr = tp->mmio_addr;
892 int giga_ctrl, bmcr;
893
894 if (autoneg == AUTONEG_ENABLE) {
895 int auto_nego;
896
897 auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
898 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
899 ADVERTISE_100HALF | ADVERTISE_100FULL);
900 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
901
902 giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
903 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
904
905 /* The 8100e/8101e/8102e do Fast Ethernet only. */
906 if ((tp->mac_version != RTL_GIGA_MAC_VER_07) &&
907 (tp->mac_version != RTL_GIGA_MAC_VER_08) &&
908 (tp->mac_version != RTL_GIGA_MAC_VER_09) &&
909 (tp->mac_version != RTL_GIGA_MAC_VER_10) &&
910 (tp->mac_version != RTL_GIGA_MAC_VER_13) &&
911 (tp->mac_version != RTL_GIGA_MAC_VER_14) &&
912 (tp->mac_version != RTL_GIGA_MAC_VER_15) &&
913 (tp->mac_version != RTL_GIGA_MAC_VER_16)) {
914 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
915 } else {
916 netif_info(tp, link, dev,
917 "PHY does not support 1000Mbps\n");
918 }
919
920 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
921
922 if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
923 (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
924 (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
925 /*
926 * Wake up the PHY.
927 * Vendor specific (0x1f) and reserved (0x0e) MII
928 * registers.
929 */
930 mdio_write(ioaddr, 0x1f, 0x0000);
931 mdio_write(ioaddr, 0x0e, 0x0000);
932 }
933
934 mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
935 mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
936 } else {
937 giga_ctrl = 0;
938
939 if (speed == SPEED_10)
940 bmcr = 0;
941 else if (speed == SPEED_100)
942 bmcr = BMCR_SPEED100;
943 else
944 return -EINVAL;
945
946 if (duplex == DUPLEX_FULL)
947 bmcr |= BMCR_FULLDPLX;
948
949 mdio_write(ioaddr, 0x1f, 0x0000);
950 }
951
952 tp->phy_1000_ctrl_reg = giga_ctrl;
953
954 mdio_write(ioaddr, MII_BMCR, bmcr);
955
956 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
957 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
958 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
959 mdio_write(ioaddr, 0x17, 0x2138);
960 mdio_write(ioaddr, 0x0e, 0x0260);
961 } else {
962 mdio_write(ioaddr, 0x17, 0x2108);
963 mdio_write(ioaddr, 0x0e, 0x0000);
964 }
965 }
966
967 return 0;
968 }
969
970 static int rtl8169_set_speed(struct net_device *dev,
971 u8 autoneg, u16 speed, u8 duplex)
972 {
973 struct rtl8169_private *tp = netdev_priv(dev);
974 int ret;
975
976 ret = tp->set_speed(dev, autoneg, speed, duplex);
977
978 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
979 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
980
981 return ret;
982 }
983
984 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
985 {
986 struct rtl8169_private *tp = netdev_priv(dev);
987 unsigned long flags;
988 int ret;
989
990 spin_lock_irqsave(&tp->lock, flags);
991 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
992 spin_unlock_irqrestore(&tp->lock, flags);
993
994 return ret;
995 }
996
997 static u32 rtl8169_get_rx_csum(struct net_device *dev)
998 {
999 struct rtl8169_private *tp = netdev_priv(dev);
1000
1001 return tp->cp_cmd & RxChkSum;
1002 }
1003
1004 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
1005 {
1006 struct rtl8169_private *tp = netdev_priv(dev);
1007 void __iomem *ioaddr = tp->mmio_addr;
1008 unsigned long flags;
1009
1010 spin_lock_irqsave(&tp->lock, flags);
1011
1012 if (data)
1013 tp->cp_cmd |= RxChkSum;
1014 else
1015 tp->cp_cmd &= ~RxChkSum;
1016
1017 RTL_W16(CPlusCmd, tp->cp_cmd);
1018 RTL_R16(CPlusCmd);
1019
1020 spin_unlock_irqrestore(&tp->lock, flags);
1021
1022 return 0;
1023 }
1024
1025 #ifdef CONFIG_R8169_VLAN
1026
1027 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1028 struct sk_buff *skb)
1029 {
1030 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
1031 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1032 }
1033
1034 static void rtl8169_vlan_rx_register(struct net_device *dev,
1035 struct vlan_group *grp)
1036 {
1037 struct rtl8169_private *tp = netdev_priv(dev);
1038 void __iomem *ioaddr = tp->mmio_addr;
1039 unsigned long flags;
1040
1041 spin_lock_irqsave(&tp->lock, flags);
1042 tp->vlgrp = grp;
1043 /*
1044 * Do not disable RxVlan on 8110SCd.
1045 */
1046 if (tp->vlgrp || (tp->mac_version == RTL_GIGA_MAC_VER_05))
1047 tp->cp_cmd |= RxVlan;
1048 else
1049 tp->cp_cmd &= ~RxVlan;
1050 RTL_W16(CPlusCmd, tp->cp_cmd);
1051 RTL_R16(CPlusCmd);
1052 spin_unlock_irqrestore(&tp->lock, flags);
1053 }
1054
1055 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1056 struct sk_buff *skb, int polling)
1057 {
1058 u32 opts2 = le32_to_cpu(desc->opts2);
1059 struct vlan_group *vlgrp = tp->vlgrp;
1060 int ret;
1061
1062 if (vlgrp && (opts2 & RxVlanTag)) {
1063 __vlan_hwaccel_rx(skb, vlgrp, swab16(opts2 & 0xffff), polling);
1064 ret = 0;
1065 } else
1066 ret = -1;
1067 desc->opts2 = 0;
1068 return ret;
1069 }
1070
1071 #else /* !CONFIG_R8169_VLAN */
1072
1073 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1074 struct sk_buff *skb)
1075 {
1076 return 0;
1077 }
1078
1079 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1080 struct sk_buff *skb, int polling)
1081 {
1082 return -1;
1083 }
1084
1085 #endif
1086
1087 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1088 {
1089 struct rtl8169_private *tp = netdev_priv(dev);
1090 void __iomem *ioaddr = tp->mmio_addr;
1091 u32 status;
1092
1093 cmd->supported =
1094 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1095 cmd->port = PORT_FIBRE;
1096 cmd->transceiver = XCVR_INTERNAL;
1097
1098 status = RTL_R32(TBICSR);
1099 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
1100 cmd->autoneg = !!(status & TBINwEnable);
1101
1102 cmd->speed = SPEED_1000;
1103 cmd->duplex = DUPLEX_FULL; /* Always set */
1104
1105 return 0;
1106 }
1107
1108 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1109 {
1110 struct rtl8169_private *tp = netdev_priv(dev);
1111
1112 return mii_ethtool_gset(&tp->mii, cmd);
1113 }
1114
1115 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1116 {
1117 struct rtl8169_private *tp = netdev_priv(dev);
1118 unsigned long flags;
1119 int rc;
1120
1121 spin_lock_irqsave(&tp->lock, flags);
1122
1123 rc = tp->get_settings(dev, cmd);
1124
1125 spin_unlock_irqrestore(&tp->lock, flags);
1126 return rc;
1127 }
1128
1129 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1130 void *p)
1131 {
1132 struct rtl8169_private *tp = netdev_priv(dev);
1133 unsigned long flags;
1134
1135 if (regs->len > R8169_REGS_SIZE)
1136 regs->len = R8169_REGS_SIZE;
1137
1138 spin_lock_irqsave(&tp->lock, flags);
1139 memcpy_fromio(p, tp->mmio_addr, regs->len);
1140 spin_unlock_irqrestore(&tp->lock, flags);
1141 }
1142
1143 static u32 rtl8169_get_msglevel(struct net_device *dev)
1144 {
1145 struct rtl8169_private *tp = netdev_priv(dev);
1146
1147 return tp->msg_enable;
1148 }
1149
1150 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1151 {
1152 struct rtl8169_private *tp = netdev_priv(dev);
1153
1154 tp->msg_enable = value;
1155 }
1156
1157 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1158 "tx_packets",
1159 "rx_packets",
1160 "tx_errors",
1161 "rx_errors",
1162 "rx_missed",
1163 "align_errors",
1164 "tx_single_collisions",
1165 "tx_multi_collisions",
1166 "unicast",
1167 "broadcast",
1168 "multicast",
1169 "tx_aborted",
1170 "tx_underrun",
1171 };
1172
1173 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1174 {
1175 switch (sset) {
1176 case ETH_SS_STATS:
1177 return ARRAY_SIZE(rtl8169_gstrings);
1178 default:
1179 return -EOPNOTSUPP;
1180 }
1181 }
1182
1183 static void rtl8169_update_counters(struct net_device *dev)
1184 {
1185 struct rtl8169_private *tp = netdev_priv(dev);
1186 void __iomem *ioaddr = tp->mmio_addr;
1187 struct rtl8169_counters *counters;
1188 dma_addr_t paddr;
1189 u32 cmd;
1190 int wait = 1000;
1191
1192 /*
1193 * Some chips are unable to dump tally counters when the receiver
1194 * is disabled.
1195 */
1196 if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1197 return;
1198
1199 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1200 if (!counters)
1201 return;
1202
1203 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1204 cmd = (u64)paddr & DMA_BIT_MASK(32);
1205 RTL_W32(CounterAddrLow, cmd);
1206 RTL_W32(CounterAddrLow, cmd | CounterDump);
1207
1208 while (wait--) {
1209 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1210 /* copy updated counters */
1211 memcpy(&tp->counters, counters, sizeof(*counters));
1212 break;
1213 }
1214 udelay(10);
1215 }
1216
1217 RTL_W32(CounterAddrLow, 0);
1218 RTL_W32(CounterAddrHigh, 0);
1219
1220 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1221 }
1222
1223 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1224 struct ethtool_stats *stats, u64 *data)
1225 {
1226 struct rtl8169_private *tp = netdev_priv(dev);
1227
1228 ASSERT_RTNL();
1229
1230 rtl8169_update_counters(dev);
1231
1232 data[0] = le64_to_cpu(tp->counters.tx_packets);
1233 data[1] = le64_to_cpu(tp->counters.rx_packets);
1234 data[2] = le64_to_cpu(tp->counters.tx_errors);
1235 data[3] = le32_to_cpu(tp->counters.rx_errors);
1236 data[4] = le16_to_cpu(tp->counters.rx_missed);
1237 data[5] = le16_to_cpu(tp->counters.align_errors);
1238 data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1239 data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1240 data[8] = le64_to_cpu(tp->counters.rx_unicast);
1241 data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1242 data[10] = le32_to_cpu(tp->counters.rx_multicast);
1243 data[11] = le16_to_cpu(tp->counters.tx_aborted);
1244 data[12] = le16_to_cpu(tp->counters.tx_underun);
1245 }
1246
1247 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1248 {
1249 switch(stringset) {
1250 case ETH_SS_STATS:
1251 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1252 break;
1253 }
1254 }
1255
1256 static const struct ethtool_ops rtl8169_ethtool_ops = {
1257 .get_drvinfo = rtl8169_get_drvinfo,
1258 .get_regs_len = rtl8169_get_regs_len,
1259 .get_link = ethtool_op_get_link,
1260 .get_settings = rtl8169_get_settings,
1261 .set_settings = rtl8169_set_settings,
1262 .get_msglevel = rtl8169_get_msglevel,
1263 .set_msglevel = rtl8169_set_msglevel,
1264 .get_rx_csum = rtl8169_get_rx_csum,
1265 .set_rx_csum = rtl8169_set_rx_csum,
1266 .set_tx_csum = ethtool_op_set_tx_csum,
1267 .set_sg = ethtool_op_set_sg,
1268 .set_tso = ethtool_op_set_tso,
1269 .get_regs = rtl8169_get_regs,
1270 .get_wol = rtl8169_get_wol,
1271 .set_wol = rtl8169_set_wol,
1272 .get_strings = rtl8169_get_strings,
1273 .get_sset_count = rtl8169_get_sset_count,
1274 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1275 };
1276
1277 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1278 void __iomem *ioaddr)
1279 {
1280 /*
1281 * The driver currently handles the 8168Bf and the 8168Be identically
1282 * but they can be identified more specifically through the test below
1283 * if needed:
1284 *
1285 * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1286 *
1287 * Same thing for the 8101Eb and the 8101Ec:
1288 *
1289 * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1290 */
1291 static const struct {
1292 u32 mask;
1293 u32 val;
1294 int mac_version;
1295 } mac_info[] = {
1296 /* 8168D family. */
1297 { 0x7cf00000, 0x28300000, RTL_GIGA_MAC_VER_26 },
1298 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
1299 { 0x7c800000, 0x28800000, RTL_GIGA_MAC_VER_27 },
1300 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
1301
1302 /* 8168C family. */
1303 { 0x7cf00000, 0x3ca00000, RTL_GIGA_MAC_VER_24 },
1304 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
1305 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
1306 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
1307 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
1308 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
1309 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
1310 { 0x7cf00000, 0x3c400000, RTL_GIGA_MAC_VER_22 },
1311 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
1312
1313 /* 8168B family. */
1314 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
1315 { 0x7cf00000, 0x38500000, RTL_GIGA_MAC_VER_17 },
1316 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
1317 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
1318
1319 /* 8101 family. */
1320 { 0x7cf00000, 0x34a00000, RTL_GIGA_MAC_VER_09 },
1321 { 0x7cf00000, 0x24a00000, RTL_GIGA_MAC_VER_09 },
1322 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
1323 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
1324 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
1325 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
1326 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
1327 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
1328 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
1329 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
1330 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
1331 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
1332 /* FIXME: where did these entries come from ? -- FR */
1333 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
1334 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
1335
1336 /* 8110 family. */
1337 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
1338 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
1339 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
1340 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
1341 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
1342 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
1343
1344 /* Catch-all */
1345 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
1346 }, *p = mac_info;
1347 u32 reg;
1348
1349 reg = RTL_R32(TxConfig);
1350 while ((reg & p->mask) != p->val)
1351 p++;
1352 tp->mac_version = p->mac_version;
1353 }
1354
1355 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1356 {
1357 dprintk("mac_version = 0x%02x\n", tp->mac_version);
1358 }
1359
1360 struct phy_reg {
1361 u16 reg;
1362 u16 val;
1363 };
1364
1365 static void rtl_phy_write(void __iomem *ioaddr, const struct phy_reg *regs, int len)
1366 {
1367 while (len-- > 0) {
1368 mdio_write(ioaddr, regs->reg, regs->val);
1369 regs++;
1370 }
1371 }
1372
1373 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1374 {
1375 static const struct phy_reg phy_reg_init[] = {
1376 { 0x1f, 0x0001 },
1377 { 0x06, 0x006e },
1378 { 0x08, 0x0708 },
1379 { 0x15, 0x4000 },
1380 { 0x18, 0x65c7 },
1381
1382 { 0x1f, 0x0001 },
1383 { 0x03, 0x00a1 },
1384 { 0x02, 0x0008 },
1385 { 0x01, 0x0120 },
1386 { 0x00, 0x1000 },
1387 { 0x04, 0x0800 },
1388 { 0x04, 0x0000 },
1389
1390 { 0x03, 0xff41 },
1391 { 0x02, 0xdf60 },
1392 { 0x01, 0x0140 },
1393 { 0x00, 0x0077 },
1394 { 0x04, 0x7800 },
1395 { 0x04, 0x7000 },
1396
1397 { 0x03, 0x802f },
1398 { 0x02, 0x4f02 },
1399 { 0x01, 0x0409 },
1400 { 0x00, 0xf0f9 },
1401 { 0x04, 0x9800 },
1402 { 0x04, 0x9000 },
1403
1404 { 0x03, 0xdf01 },
1405 { 0x02, 0xdf20 },
1406 { 0x01, 0xff95 },
1407 { 0x00, 0xba00 },
1408 { 0x04, 0xa800 },
1409 { 0x04, 0xa000 },
1410
1411 { 0x03, 0xff41 },
1412 { 0x02, 0xdf20 },
1413 { 0x01, 0x0140 },
1414 { 0x00, 0x00bb },
1415 { 0x04, 0xb800 },
1416 { 0x04, 0xb000 },
1417
1418 { 0x03, 0xdf41 },
1419 { 0x02, 0xdc60 },
1420 { 0x01, 0x6340 },
1421 { 0x00, 0x007d },
1422 { 0x04, 0xd800 },
1423 { 0x04, 0xd000 },
1424
1425 { 0x03, 0xdf01 },
1426 { 0x02, 0xdf20 },
1427 { 0x01, 0x100a },
1428 { 0x00, 0xa0ff },
1429 { 0x04, 0xf800 },
1430 { 0x04, 0xf000 },
1431
1432 { 0x1f, 0x0000 },
1433 { 0x0b, 0x0000 },
1434 { 0x00, 0x9200 }
1435 };
1436
1437 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1438 }
1439
1440 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1441 {
1442 static const struct phy_reg phy_reg_init[] = {
1443 { 0x1f, 0x0002 },
1444 { 0x01, 0x90d0 },
1445 { 0x1f, 0x0000 }
1446 };
1447
1448 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1449 }
1450
1451 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp,
1452 void __iomem *ioaddr)
1453 {
1454 struct pci_dev *pdev = tp->pci_dev;
1455 u16 vendor_id, device_id;
1456
1457 pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
1458 pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
1459
1460 if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
1461 return;
1462
1463 mdio_write(ioaddr, 0x1f, 0x0001);
1464 mdio_write(ioaddr, 0x10, 0xf01b);
1465 mdio_write(ioaddr, 0x1f, 0x0000);
1466 }
1467
1468 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
1469 void __iomem *ioaddr)
1470 {
1471 static const struct phy_reg phy_reg_init[] = {
1472 { 0x1f, 0x0001 },
1473 { 0x04, 0x0000 },
1474 { 0x03, 0x00a1 },
1475 { 0x02, 0x0008 },
1476 { 0x01, 0x0120 },
1477 { 0x00, 0x1000 },
1478 { 0x04, 0x0800 },
1479 { 0x04, 0x9000 },
1480 { 0x03, 0x802f },
1481 { 0x02, 0x4f02 },
1482 { 0x01, 0x0409 },
1483 { 0x00, 0xf099 },
1484 { 0x04, 0x9800 },
1485 { 0x04, 0xa000 },
1486 { 0x03, 0xdf01 },
1487 { 0x02, 0xdf20 },
1488 { 0x01, 0xff95 },
1489 { 0x00, 0xba00 },
1490 { 0x04, 0xa800 },
1491 { 0x04, 0xf000 },
1492 { 0x03, 0xdf01 },
1493 { 0x02, 0xdf20 },
1494 { 0x01, 0x101a },
1495 { 0x00, 0xa0ff },
1496 { 0x04, 0xf800 },
1497 { 0x04, 0x0000 },
1498 { 0x1f, 0x0000 },
1499
1500 { 0x1f, 0x0001 },
1501 { 0x10, 0xf41b },
1502 { 0x14, 0xfb54 },
1503 { 0x18, 0xf5c7 },
1504 { 0x1f, 0x0000 },
1505
1506 { 0x1f, 0x0001 },
1507 { 0x17, 0x0cc0 },
1508 { 0x1f, 0x0000 }
1509 };
1510
1511 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1512
1513 rtl8169scd_hw_phy_config_quirk(tp, ioaddr);
1514 }
1515
1516 static void rtl8169sce_hw_phy_config(void __iomem *ioaddr)
1517 {
1518 static const struct phy_reg phy_reg_init[] = {
1519 { 0x1f, 0x0001 },
1520 { 0x04, 0x0000 },
1521 { 0x03, 0x00a1 },
1522 { 0x02, 0x0008 },
1523 { 0x01, 0x0120 },
1524 { 0x00, 0x1000 },
1525 { 0x04, 0x0800 },
1526 { 0x04, 0x9000 },
1527 { 0x03, 0x802f },
1528 { 0x02, 0x4f02 },
1529 { 0x01, 0x0409 },
1530 { 0x00, 0xf099 },
1531 { 0x04, 0x9800 },
1532 { 0x04, 0xa000 },
1533 { 0x03, 0xdf01 },
1534 { 0x02, 0xdf20 },
1535 { 0x01, 0xff95 },
1536 { 0x00, 0xba00 },
1537 { 0x04, 0xa800 },
1538 { 0x04, 0xf000 },
1539 { 0x03, 0xdf01 },
1540 { 0x02, 0xdf20 },
1541 { 0x01, 0x101a },
1542 { 0x00, 0xa0ff },
1543 { 0x04, 0xf800 },
1544 { 0x04, 0x0000 },
1545 { 0x1f, 0x0000 },
1546
1547 { 0x1f, 0x0001 },
1548 { 0x0b, 0x8480 },
1549 { 0x1f, 0x0000 },
1550
1551 { 0x1f, 0x0001 },
1552 { 0x18, 0x67c7 },
1553 { 0x04, 0x2000 },
1554 { 0x03, 0x002f },
1555 { 0x02, 0x4360 },
1556 { 0x01, 0x0109 },
1557 { 0x00, 0x3022 },
1558 { 0x04, 0x2800 },
1559 { 0x1f, 0x0000 },
1560
1561 { 0x1f, 0x0001 },
1562 { 0x17, 0x0cc0 },
1563 { 0x1f, 0x0000 }
1564 };
1565
1566 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1567 }
1568
1569 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1570 {
1571 static const struct phy_reg phy_reg_init[] = {
1572 { 0x10, 0xf41b },
1573 { 0x1f, 0x0000 }
1574 };
1575
1576 mdio_write(ioaddr, 0x1f, 0x0001);
1577 mdio_patch(ioaddr, 0x16, 1 << 0);
1578
1579 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1580 }
1581
1582 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1583 {
1584 static const struct phy_reg phy_reg_init[] = {
1585 { 0x1f, 0x0001 },
1586 { 0x10, 0xf41b },
1587 { 0x1f, 0x0000 }
1588 };
1589
1590 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1591 }
1592
1593 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1594 {
1595 static const struct phy_reg phy_reg_init[] = {
1596 { 0x1f, 0x0000 },
1597 { 0x1d, 0x0f00 },
1598 { 0x1f, 0x0002 },
1599 { 0x0c, 0x1ec8 },
1600 { 0x1f, 0x0000 }
1601 };
1602
1603 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1604 }
1605
1606 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1607 {
1608 static const struct phy_reg phy_reg_init[] = {
1609 { 0x1f, 0x0001 },
1610 { 0x1d, 0x3d98 },
1611 { 0x1f, 0x0000 }
1612 };
1613
1614 mdio_write(ioaddr, 0x1f, 0x0000);
1615 mdio_patch(ioaddr, 0x14, 1 << 5);
1616 mdio_patch(ioaddr, 0x0d, 1 << 5);
1617
1618 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1619 }
1620
1621 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1622 {
1623 static const struct phy_reg phy_reg_init[] = {
1624 { 0x1f, 0x0001 },
1625 { 0x12, 0x2300 },
1626 { 0x1f, 0x0002 },
1627 { 0x00, 0x88d4 },
1628 { 0x01, 0x82b1 },
1629 { 0x03, 0x7002 },
1630 { 0x08, 0x9e30 },
1631 { 0x09, 0x01f0 },
1632 { 0x0a, 0x5500 },
1633 { 0x0c, 0x00c8 },
1634 { 0x1f, 0x0003 },
1635 { 0x12, 0xc096 },
1636 { 0x16, 0x000a },
1637 { 0x1f, 0x0000 },
1638 { 0x1f, 0x0000 },
1639 { 0x09, 0x2000 },
1640 { 0x09, 0x0000 }
1641 };
1642
1643 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1644
1645 mdio_patch(ioaddr, 0x14, 1 << 5);
1646 mdio_patch(ioaddr, 0x0d, 1 << 5);
1647 mdio_write(ioaddr, 0x1f, 0x0000);
1648 }
1649
1650 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1651 {
1652 static const struct phy_reg phy_reg_init[] = {
1653 { 0x1f, 0x0001 },
1654 { 0x12, 0x2300 },
1655 { 0x03, 0x802f },
1656 { 0x02, 0x4f02 },
1657 { 0x01, 0x0409 },
1658 { 0x00, 0xf099 },
1659 { 0x04, 0x9800 },
1660 { 0x04, 0x9000 },
1661 { 0x1d, 0x3d98 },
1662 { 0x1f, 0x0002 },
1663 { 0x0c, 0x7eb8 },
1664 { 0x06, 0x0761 },
1665 { 0x1f, 0x0003 },
1666 { 0x16, 0x0f0a },
1667 { 0x1f, 0x0000 }
1668 };
1669
1670 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1671
1672 mdio_patch(ioaddr, 0x16, 1 << 0);
1673 mdio_patch(ioaddr, 0x14, 1 << 5);
1674 mdio_patch(ioaddr, 0x0d, 1 << 5);
1675 mdio_write(ioaddr, 0x1f, 0x0000);
1676 }
1677
1678 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1679 {
1680 static const struct phy_reg phy_reg_init[] = {
1681 { 0x1f, 0x0001 },
1682 { 0x12, 0x2300 },
1683 { 0x1d, 0x3d98 },
1684 { 0x1f, 0x0002 },
1685 { 0x0c, 0x7eb8 },
1686 { 0x06, 0x5461 },
1687 { 0x1f, 0x0003 },
1688 { 0x16, 0x0f0a },
1689 { 0x1f, 0x0000 }
1690 };
1691
1692 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1693
1694 mdio_patch(ioaddr, 0x16, 1 << 0);
1695 mdio_patch(ioaddr, 0x14, 1 << 5);
1696 mdio_patch(ioaddr, 0x0d, 1 << 5);
1697 mdio_write(ioaddr, 0x1f, 0x0000);
1698 }
1699
1700 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1701 {
1702 rtl8168c_3_hw_phy_config(ioaddr);
1703 }
1704
1705 static void rtl8168d_1_hw_phy_config(void __iomem *ioaddr)
1706 {
1707 static const struct phy_reg phy_reg_init_0[] = {
1708 { 0x1f, 0x0001 },
1709 { 0x06, 0x4064 },
1710 { 0x07, 0x2863 },
1711 { 0x08, 0x059c },
1712 { 0x09, 0x26b4 },
1713 { 0x0a, 0x6a19 },
1714 { 0x0b, 0xdcc8 },
1715 { 0x10, 0xf06d },
1716 { 0x14, 0x7f68 },
1717 { 0x18, 0x7fd9 },
1718 { 0x1c, 0xf0ff },
1719 { 0x1d, 0x3d9c },
1720 { 0x1f, 0x0003 },
1721 { 0x12, 0xf49f },
1722 { 0x13, 0x070b },
1723 { 0x1a, 0x05ad },
1724 { 0x14, 0x94c0 }
1725 };
1726 static const struct phy_reg phy_reg_init_1[] = {
1727 { 0x1f, 0x0002 },
1728 { 0x06, 0x5561 },
1729 { 0x1f, 0x0005 },
1730 { 0x05, 0x8332 },
1731 { 0x06, 0x5561 }
1732 };
1733 static const struct phy_reg phy_reg_init_2[] = {
1734 { 0x1f, 0x0005 },
1735 { 0x05, 0xffc2 },
1736 { 0x1f, 0x0005 },
1737 { 0x05, 0x8000 },
1738 { 0x06, 0xf8f9 },
1739 { 0x06, 0xfaef },
1740 { 0x06, 0x59ee },
1741 { 0x06, 0xf8ea },
1742 { 0x06, 0x00ee },
1743 { 0x06, 0xf8eb },
1744 { 0x06, 0x00e0 },
1745 { 0x06, 0xf87c },
1746 { 0x06, 0xe1f8 },
1747 { 0x06, 0x7d59 },
1748 { 0x06, 0x0fef },
1749 { 0x06, 0x0139 },
1750 { 0x06, 0x029e },
1751 { 0x06, 0x06ef },
1752 { 0x06, 0x1039 },
1753 { 0x06, 0x089f },
1754 { 0x06, 0x2aee },
1755 { 0x06, 0xf8ea },
1756 { 0x06, 0x00ee },
1757 { 0x06, 0xf8eb },
1758 { 0x06, 0x01e0 },
1759 { 0x06, 0xf87c },
1760 { 0x06, 0xe1f8 },
1761 { 0x06, 0x7d58 },
1762 { 0x06, 0x409e },
1763 { 0x06, 0x0f39 },
1764 { 0x06, 0x46aa },
1765 { 0x06, 0x0bbf },
1766 { 0x06, 0x8290 },
1767 { 0x06, 0xd682 },
1768 { 0x06, 0x9802 },
1769 { 0x06, 0x014f },
1770 { 0x06, 0xae09 },
1771 { 0x06, 0xbf82 },
1772 { 0x06, 0x98d6 },
1773 { 0x06, 0x82a0 },
1774 { 0x06, 0x0201 },
1775 { 0x06, 0x4fef },
1776 { 0x06, 0x95fe },
1777 { 0x06, 0xfdfc },
1778 { 0x06, 0x05f8 },
1779 { 0x06, 0xf9fa },
1780 { 0x06, 0xeef8 },
1781 { 0x06, 0xea00 },
1782 { 0x06, 0xeef8 },
1783 { 0x06, 0xeb00 },
1784 { 0x06, 0xe2f8 },
1785 { 0x06, 0x7ce3 },
1786 { 0x06, 0xf87d },
1787 { 0x06, 0xa511 },
1788 { 0x06, 0x1112 },
1789 { 0x06, 0xd240 },
1790 { 0x06, 0xd644 },
1791 { 0x06, 0x4402 },
1792 { 0x06, 0x8217 },
1793 { 0x06, 0xd2a0 },
1794 { 0x06, 0xd6aa },
1795 { 0x06, 0xaa02 },
1796 { 0x06, 0x8217 },
1797 { 0x06, 0xae0f },
1798 { 0x06, 0xa544 },
1799 { 0x06, 0x4402 },
1800 { 0x06, 0xae4d },
1801 { 0x06, 0xa5aa },
1802 { 0x06, 0xaa02 },
1803 { 0x06, 0xae47 },
1804 { 0x06, 0xaf82 },
1805 { 0x06, 0x13ee },
1806 { 0x06, 0x834e },
1807 { 0x06, 0x00ee },
1808 { 0x06, 0x834d },
1809 { 0x06, 0x0fee },
1810 { 0x06, 0x834c },
1811 { 0x06, 0x0fee },
1812 { 0x06, 0x834f },
1813 { 0x06, 0x00ee },
1814 { 0x06, 0x8351 },
1815 { 0x06, 0x00ee },
1816 { 0x06, 0x834a },
1817 { 0x06, 0xffee },
1818 { 0x06, 0x834b },
1819 { 0x06, 0xffe0 },
1820 { 0x06, 0x8330 },
1821 { 0x06, 0xe183 },
1822 { 0x06, 0x3158 },
1823 { 0x06, 0xfee4 },
1824 { 0x06, 0xf88a },
1825 { 0x06, 0xe5f8 },
1826 { 0x06, 0x8be0 },
1827 { 0x06, 0x8332 },
1828 { 0x06, 0xe183 },
1829 { 0x06, 0x3359 },
1830 { 0x06, 0x0fe2 },
1831 { 0x06, 0x834d },
1832 { 0x06, 0x0c24 },
1833 { 0x06, 0x5af0 },
1834 { 0x06, 0x1e12 },
1835 { 0x06, 0xe4f8 },
1836 { 0x06, 0x8ce5 },
1837 { 0x06, 0xf88d },
1838 { 0x06, 0xaf82 },
1839 { 0x06, 0x13e0 },
1840 { 0x06, 0x834f },
1841 { 0x06, 0x10e4 },
1842 { 0x06, 0x834f },
1843 { 0x06, 0xe083 },
1844 { 0x06, 0x4e78 },
1845 { 0x06, 0x009f },
1846 { 0x06, 0x0ae0 },
1847 { 0x06, 0x834f },
1848 { 0x06, 0xa010 },
1849 { 0x06, 0xa5ee },
1850 { 0x06, 0x834e },
1851 { 0x06, 0x01e0 },
1852 { 0x06, 0x834e },
1853 { 0x06, 0x7805 },
1854 { 0x06, 0x9e9a },
1855 { 0x06, 0xe083 },
1856 { 0x06, 0x4e78 },
1857 { 0x06, 0x049e },
1858 { 0x06, 0x10e0 },
1859 { 0x06, 0x834e },
1860 { 0x06, 0x7803 },
1861 { 0x06, 0x9e0f },
1862 { 0x06, 0xe083 },
1863 { 0x06, 0x4e78 },
1864 { 0x06, 0x019e },
1865 { 0x06, 0x05ae },
1866 { 0x06, 0x0caf },
1867 { 0x06, 0x81f8 },
1868 { 0x06, 0xaf81 },
1869 { 0x06, 0xa3af },
1870 { 0x06, 0x81dc },
1871 { 0x06, 0xaf82 },
1872 { 0x06, 0x13ee },
1873 { 0x06, 0x8348 },
1874 { 0x06, 0x00ee },
1875 { 0x06, 0x8349 },
1876 { 0x06, 0x00e0 },
1877 { 0x06, 0x8351 },
1878 { 0x06, 0x10e4 },
1879 { 0x06, 0x8351 },
1880 { 0x06, 0x5801 },
1881 { 0x06, 0x9fea },
1882 { 0x06, 0xd000 },
1883 { 0x06, 0xd180 },
1884 { 0x06, 0x1f66 },
1885 { 0x06, 0xe2f8 },
1886 { 0x06, 0xeae3 },
1887 { 0x06, 0xf8eb },
1888 { 0x06, 0x5af8 },
1889 { 0x06, 0x1e20 },
1890 { 0x06, 0xe6f8 },
1891 { 0x06, 0xeae5 },
1892 { 0x06, 0xf8eb },
1893 { 0x06, 0xd302 },
1894 { 0x06, 0xb3fe },
1895 { 0x06, 0xe2f8 },
1896 { 0x06, 0x7cef },
1897 { 0x06, 0x325b },
1898 { 0x06, 0x80e3 },
1899 { 0x06, 0xf87d },
1900 { 0x06, 0x9e03 },
1901 { 0x06, 0x7dff },
1902 { 0x06, 0xff0d },
1903 { 0x06, 0x581c },
1904 { 0x06, 0x551a },
1905 { 0x06, 0x6511 },
1906 { 0x06, 0xa190 },
1907 { 0x06, 0xd3e2 },
1908 { 0x06, 0x8348 },
1909 { 0x06, 0xe383 },
1910 { 0x06, 0x491b },
1911 { 0x06, 0x56ab },
1912 { 0x06, 0x08ef },
1913 { 0x06, 0x56e6 },
1914 { 0x06, 0x8348 },
1915 { 0x06, 0xe783 },
1916 { 0x06, 0x4910 },
1917 { 0x06, 0xd180 },
1918 { 0x06, 0x1f66 },
1919 { 0x06, 0xa004 },
1920 { 0x06, 0xb9e2 },
1921 { 0x06, 0x8348 },
1922 { 0x06, 0xe383 },
1923 { 0x06, 0x49ef },
1924 { 0x06, 0x65e2 },
1925 { 0x06, 0x834a },
1926 { 0x06, 0xe383 },
1927 { 0x06, 0x4b1b },
1928 { 0x06, 0x56aa },
1929 { 0x06, 0x0eef },
1930 { 0x06, 0x56e6 },
1931 { 0x06, 0x834a },
1932 { 0x06, 0xe783 },
1933 { 0x06, 0x4be2 },
1934 { 0x06, 0x834d },
1935 { 0x06, 0xe683 },
1936 { 0x06, 0x4ce0 },
1937 { 0x06, 0x834d },
1938 { 0x06, 0xa000 },
1939 { 0x06, 0x0caf },
1940 { 0x06, 0x81dc },
1941 { 0x06, 0xe083 },
1942 { 0x06, 0x4d10 },
1943 { 0x06, 0xe483 },
1944 { 0x06, 0x4dae },
1945 { 0x06, 0x0480 },
1946 { 0x06, 0xe483 },
1947 { 0x06, 0x4de0 },
1948 { 0x06, 0x834e },
1949 { 0x06, 0x7803 },
1950 { 0x06, 0x9e0b },
1951 { 0x06, 0xe083 },
1952 { 0x06, 0x4e78 },
1953 { 0x06, 0x049e },
1954 { 0x06, 0x04ee },
1955 { 0x06, 0x834e },
1956 { 0x06, 0x02e0 },
1957 { 0x06, 0x8332 },
1958 { 0x06, 0xe183 },
1959 { 0x06, 0x3359 },
1960 { 0x06, 0x0fe2 },
1961 { 0x06, 0x834d },
1962 { 0x06, 0x0c24 },
1963 { 0x06, 0x5af0 },
1964 { 0x06, 0x1e12 },
1965 { 0x06, 0xe4f8 },
1966 { 0x06, 0x8ce5 },
1967 { 0x06, 0xf88d },
1968 { 0x06, 0xe083 },
1969 { 0x06, 0x30e1 },
1970 { 0x06, 0x8331 },
1971 { 0x06, 0x6801 },
1972 { 0x06, 0xe4f8 },
1973 { 0x06, 0x8ae5 },
1974 { 0x06, 0xf88b },
1975 { 0x06, 0xae37 },
1976 { 0x06, 0xee83 },
1977 { 0x06, 0x4e03 },
1978 { 0x06, 0xe083 },
1979 { 0x06, 0x4ce1 },
1980 { 0x06, 0x834d },
1981 { 0x06, 0x1b01 },
1982 { 0x06, 0x9e04 },
1983 { 0x06, 0xaaa1 },
1984 { 0x06, 0xaea8 },
1985 { 0x06, 0xee83 },
1986 { 0x06, 0x4e04 },
1987 { 0x06, 0xee83 },
1988 { 0x06, 0x4f00 },
1989 { 0x06, 0xaeab },
1990 { 0x06, 0xe083 },
1991 { 0x06, 0x4f78 },
1992 { 0x06, 0x039f },
1993 { 0x06, 0x14ee },
1994 { 0x06, 0x834e },
1995 { 0x06, 0x05d2 },
1996 { 0x06, 0x40d6 },
1997 { 0x06, 0x5554 },
1998 { 0x06, 0x0282 },
1999 { 0x06, 0x17d2 },
2000 { 0x06, 0xa0d6 },
2001 { 0x06, 0xba00 },
2002 { 0x06, 0x0282 },
2003 { 0x06, 0x17fe },
2004 { 0x06, 0xfdfc },
2005 { 0x06, 0x05f8 },
2006 { 0x06, 0xe0f8 },
2007 { 0x06, 0x60e1 },
2008 { 0x06, 0xf861 },
2009 { 0x06, 0x6802 },
2010 { 0x06, 0xe4f8 },
2011 { 0x06, 0x60e5 },
2012 { 0x06, 0xf861 },
2013 { 0x06, 0xe0f8 },
2014 { 0x06, 0x48e1 },
2015 { 0x06, 0xf849 },
2016 { 0x06, 0x580f },
2017 { 0x06, 0x1e02 },
2018 { 0x06, 0xe4f8 },
2019 { 0x06, 0x48e5 },
2020 { 0x06, 0xf849 },
2021 { 0x06, 0xd000 },
2022 { 0x06, 0x0282 },
2023 { 0x06, 0x5bbf },
2024 { 0x06, 0x8350 },
2025 { 0x06, 0xef46 },
2026 { 0x06, 0xdc19 },
2027 { 0x06, 0xddd0 },
2028 { 0x06, 0x0102 },
2029 { 0x06, 0x825b },
2030 { 0x06, 0x0282 },
2031 { 0x06, 0x77e0 },
2032 { 0x06, 0xf860 },
2033 { 0x06, 0xe1f8 },
2034 { 0x06, 0x6158 },
2035 { 0x06, 0xfde4 },
2036 { 0x06, 0xf860 },
2037 { 0x06, 0xe5f8 },
2038 { 0x06, 0x61fc },
2039 { 0x06, 0x04f9 },
2040 { 0x06, 0xfafb },
2041 { 0x06, 0xc6bf },
2042 { 0x06, 0xf840 },
2043 { 0x06, 0xbe83 },
2044 { 0x06, 0x50a0 },
2045 { 0x06, 0x0101 },
2046 { 0x06, 0x071b },
2047 { 0x06, 0x89cf },
2048 { 0x06, 0xd208 },
2049 { 0x06, 0xebdb },
2050 { 0x06, 0x19b2 },
2051 { 0x06, 0xfbff },
2052 { 0x06, 0xfefd },
2053 { 0x06, 0x04f8 },
2054 { 0x06, 0xe0f8 },
2055 { 0x06, 0x48e1 },
2056 { 0x06, 0xf849 },
2057 { 0x06, 0x6808 },
2058 { 0x06, 0xe4f8 },
2059 { 0x06, 0x48e5 },
2060 { 0x06, 0xf849 },
2061 { 0x06, 0x58f7 },
2062 { 0x06, 0xe4f8 },
2063 { 0x06, 0x48e5 },
2064 { 0x06, 0xf849 },
2065 { 0x06, 0xfc04 },
2066 { 0x06, 0x4d20 },
2067 { 0x06, 0x0002 },
2068 { 0x06, 0x4e22 },
2069 { 0x06, 0x0002 },
2070 { 0x06, 0x4ddf },
2071 { 0x06, 0xff01 },
2072 { 0x06, 0x4edd },
2073 { 0x06, 0xff01 },
2074 { 0x05, 0x83d4 },
2075 { 0x06, 0x8000 },
2076 { 0x05, 0x83d8 },
2077 { 0x06, 0x8051 },
2078 { 0x02, 0x6010 },
2079 { 0x03, 0xdc00 },
2080 { 0x05, 0xfff6 },
2081 { 0x06, 0x00fc },
2082 { 0x1f, 0x0000 },
2083
2084 { 0x1f, 0x0000 },
2085 { 0x0d, 0xf880 },
2086 { 0x1f, 0x0000 }
2087 };
2088
2089 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2090
2091 mdio_write(ioaddr, 0x1f, 0x0002);
2092 mdio_plus_minus(ioaddr, 0x0b, 0x0010, 0x00ef);
2093 mdio_plus_minus(ioaddr, 0x0c, 0xa200, 0x5d00);
2094
2095 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2096
2097 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2098 static const struct phy_reg phy_reg_init[] = {
2099 { 0x1f, 0x0002 },
2100 { 0x05, 0x669a },
2101 { 0x1f, 0x0005 },
2102 { 0x05, 0x8330 },
2103 { 0x06, 0x669a },
2104 { 0x1f, 0x0002 }
2105 };
2106 int val;
2107
2108 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2109
2110 val = mdio_read(ioaddr, 0x0d);
2111
2112 if ((val & 0x00ff) != 0x006c) {
2113 static const u32 set[] = {
2114 0x0065, 0x0066, 0x0067, 0x0068,
2115 0x0069, 0x006a, 0x006b, 0x006c
2116 };
2117 int i;
2118
2119 mdio_write(ioaddr, 0x1f, 0x0002);
2120
2121 val &= 0xff00;
2122 for (i = 0; i < ARRAY_SIZE(set); i++)
2123 mdio_write(ioaddr, 0x0d, val | set[i]);
2124 }
2125 } else {
2126 static const struct phy_reg phy_reg_init[] = {
2127 { 0x1f, 0x0002 },
2128 { 0x05, 0x6662 },
2129 { 0x1f, 0x0005 },
2130 { 0x05, 0x8330 },
2131 { 0x06, 0x6662 }
2132 };
2133
2134 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2135 }
2136
2137 mdio_write(ioaddr, 0x1f, 0x0002);
2138 mdio_patch(ioaddr, 0x0d, 0x0300);
2139 mdio_patch(ioaddr, 0x0f, 0x0010);
2140
2141 mdio_write(ioaddr, 0x1f, 0x0002);
2142 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2143 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2144
2145 rtl_phy_write(ioaddr, phy_reg_init_2, ARRAY_SIZE(phy_reg_init_2));
2146 }
2147
2148 static void rtl8168d_2_hw_phy_config(void __iomem *ioaddr)
2149 {
2150 static const struct phy_reg phy_reg_init_0[] = {
2151 { 0x1f, 0x0001 },
2152 { 0x06, 0x4064 },
2153 { 0x07, 0x2863 },
2154 { 0x08, 0x059c },
2155 { 0x09, 0x26b4 },
2156 { 0x0a, 0x6a19 },
2157 { 0x0b, 0xdcc8 },
2158 { 0x10, 0xf06d },
2159 { 0x14, 0x7f68 },
2160 { 0x18, 0x7fd9 },
2161 { 0x1c, 0xf0ff },
2162 { 0x1d, 0x3d9c },
2163 { 0x1f, 0x0003 },
2164 { 0x12, 0xf49f },
2165 { 0x13, 0x070b },
2166 { 0x1a, 0x05ad },
2167 { 0x14, 0x94c0 },
2168
2169 { 0x1f, 0x0002 },
2170 { 0x06, 0x5561 },
2171 { 0x1f, 0x0005 },
2172 { 0x05, 0x8332 },
2173 { 0x06, 0x5561 }
2174 };
2175 static const struct phy_reg phy_reg_init_1[] = {
2176 { 0x1f, 0x0005 },
2177 { 0x05, 0xffc2 },
2178 { 0x1f, 0x0005 },
2179 { 0x05, 0x8000 },
2180 { 0x06, 0xf8f9 },
2181 { 0x06, 0xfaee },
2182 { 0x06, 0xf8ea },
2183 { 0x06, 0x00ee },
2184 { 0x06, 0xf8eb },
2185 { 0x06, 0x00e2 },
2186 { 0x06, 0xf87c },
2187 { 0x06, 0xe3f8 },
2188 { 0x06, 0x7da5 },
2189 { 0x06, 0x1111 },
2190 { 0x06, 0x12d2 },
2191 { 0x06, 0x40d6 },
2192 { 0x06, 0x4444 },
2193 { 0x06, 0x0281 },
2194 { 0x06, 0xc6d2 },
2195 { 0x06, 0xa0d6 },
2196 { 0x06, 0xaaaa },
2197 { 0x06, 0x0281 },
2198 { 0x06, 0xc6ae },
2199 { 0x06, 0x0fa5 },
2200 { 0x06, 0x4444 },
2201 { 0x06, 0x02ae },
2202 { 0x06, 0x4da5 },
2203 { 0x06, 0xaaaa },
2204 { 0x06, 0x02ae },
2205 { 0x06, 0x47af },
2206 { 0x06, 0x81c2 },
2207 { 0x06, 0xee83 },
2208 { 0x06, 0x4e00 },
2209 { 0x06, 0xee83 },
2210 { 0x06, 0x4d0f },
2211 { 0x06, 0xee83 },
2212 { 0x06, 0x4c0f },
2213 { 0x06, 0xee83 },
2214 { 0x06, 0x4f00 },
2215 { 0x06, 0xee83 },
2216 { 0x06, 0x5100 },
2217 { 0x06, 0xee83 },
2218 { 0x06, 0x4aff },
2219 { 0x06, 0xee83 },
2220 { 0x06, 0x4bff },
2221 { 0x06, 0xe083 },
2222 { 0x06, 0x30e1 },
2223 { 0x06, 0x8331 },
2224 { 0x06, 0x58fe },
2225 { 0x06, 0xe4f8 },
2226 { 0x06, 0x8ae5 },
2227 { 0x06, 0xf88b },
2228 { 0x06, 0xe083 },
2229 { 0x06, 0x32e1 },
2230 { 0x06, 0x8333 },
2231 { 0x06, 0x590f },
2232 { 0x06, 0xe283 },
2233 { 0x06, 0x4d0c },
2234 { 0x06, 0x245a },
2235 { 0x06, 0xf01e },
2236 { 0x06, 0x12e4 },
2237 { 0x06, 0xf88c },
2238 { 0x06, 0xe5f8 },
2239 { 0x06, 0x8daf },
2240 { 0x06, 0x81c2 },
2241 { 0x06, 0xe083 },
2242 { 0x06, 0x4f10 },
2243 { 0x06, 0xe483 },
2244 { 0x06, 0x4fe0 },
2245 { 0x06, 0x834e },
2246 { 0x06, 0x7800 },
2247 { 0x06, 0x9f0a },
2248 { 0x06, 0xe083 },
2249 { 0x06, 0x4fa0 },
2250 { 0x06, 0x10a5 },
2251 { 0x06, 0xee83 },
2252 { 0x06, 0x4e01 },
2253 { 0x06, 0xe083 },
2254 { 0x06, 0x4e78 },
2255 { 0x06, 0x059e },
2256 { 0x06, 0x9ae0 },
2257 { 0x06, 0x834e },
2258 { 0x06, 0x7804 },
2259 { 0x06, 0x9e10 },
2260 { 0x06, 0xe083 },
2261 { 0x06, 0x4e78 },
2262 { 0x06, 0x039e },
2263 { 0x06, 0x0fe0 },
2264 { 0x06, 0x834e },
2265 { 0x06, 0x7801 },
2266 { 0x06, 0x9e05 },
2267 { 0x06, 0xae0c },
2268 { 0x06, 0xaf81 },
2269 { 0x06, 0xa7af },
2270 { 0x06, 0x8152 },
2271 { 0x06, 0xaf81 },
2272 { 0x06, 0x8baf },
2273 { 0x06, 0x81c2 },
2274 { 0x06, 0xee83 },
2275 { 0x06, 0x4800 },
2276 { 0x06, 0xee83 },
2277 { 0x06, 0x4900 },
2278 { 0x06, 0xe083 },
2279 { 0x06, 0x5110 },
2280 { 0x06, 0xe483 },
2281 { 0x06, 0x5158 },
2282 { 0x06, 0x019f },
2283 { 0x06, 0xead0 },
2284 { 0x06, 0x00d1 },
2285 { 0x06, 0x801f },
2286 { 0x06, 0x66e2 },
2287 { 0x06, 0xf8ea },
2288 { 0x06, 0xe3f8 },
2289 { 0x06, 0xeb5a },
2290 { 0x06, 0xf81e },
2291 { 0x06, 0x20e6 },
2292 { 0x06, 0xf8ea },
2293 { 0x06, 0xe5f8 },
2294 { 0x06, 0xebd3 },
2295 { 0x06, 0x02b3 },
2296 { 0x06, 0xfee2 },
2297 { 0x06, 0xf87c },
2298 { 0x06, 0xef32 },
2299 { 0x06, 0x5b80 },
2300 { 0x06, 0xe3f8 },
2301 { 0x06, 0x7d9e },
2302 { 0x06, 0x037d },
2303 { 0x06, 0xffff },
2304 { 0x06, 0x0d58 },
2305 { 0x06, 0x1c55 },
2306 { 0x06, 0x1a65 },
2307 { 0x06, 0x11a1 },
2308 { 0x06, 0x90d3 },
2309 { 0x06, 0xe283 },
2310 { 0x06, 0x48e3 },
2311 { 0x06, 0x8349 },
2312 { 0x06, 0x1b56 },
2313 { 0x06, 0xab08 },
2314 { 0x06, 0xef56 },
2315 { 0x06, 0xe683 },
2316 { 0x06, 0x48e7 },
2317 { 0x06, 0x8349 },
2318 { 0x06, 0x10d1 },
2319 { 0x06, 0x801f },
2320 { 0x06, 0x66a0 },
2321 { 0x06, 0x04b9 },
2322 { 0x06, 0xe283 },
2323 { 0x06, 0x48e3 },
2324 { 0x06, 0x8349 },
2325 { 0x06, 0xef65 },
2326 { 0x06, 0xe283 },
2327 { 0x06, 0x4ae3 },
2328 { 0x06, 0x834b },
2329 { 0x06, 0x1b56 },
2330 { 0x06, 0xaa0e },
2331 { 0x06, 0xef56 },
2332 { 0x06, 0xe683 },
2333 { 0x06, 0x4ae7 },
2334 { 0x06, 0x834b },
2335 { 0x06, 0xe283 },
2336 { 0x06, 0x4de6 },
2337 { 0x06, 0x834c },
2338 { 0x06, 0xe083 },
2339 { 0x06, 0x4da0 },
2340 { 0x06, 0x000c },
2341 { 0x06, 0xaf81 },
2342 { 0x06, 0x8be0 },
2343 { 0x06, 0x834d },
2344 { 0x06, 0x10e4 },
2345 { 0x06, 0x834d },
2346 { 0x06, 0xae04 },
2347 { 0x06, 0x80e4 },
2348 { 0x06, 0x834d },
2349 { 0x06, 0xe083 },
2350 { 0x06, 0x4e78 },
2351 { 0x06, 0x039e },
2352 { 0x06, 0x0be0 },
2353 { 0x06, 0x834e },
2354 { 0x06, 0x7804 },
2355 { 0x06, 0x9e04 },
2356 { 0x06, 0xee83 },
2357 { 0x06, 0x4e02 },
2358 { 0x06, 0xe083 },
2359 { 0x06, 0x32e1 },
2360 { 0x06, 0x8333 },
2361 { 0x06, 0x590f },
2362 { 0x06, 0xe283 },
2363 { 0x06, 0x4d0c },
2364 { 0x06, 0x245a },
2365 { 0x06, 0xf01e },
2366 { 0x06, 0x12e4 },
2367 { 0x06, 0xf88c },
2368 { 0x06, 0xe5f8 },
2369 { 0x06, 0x8de0 },
2370 { 0x06, 0x8330 },
2371 { 0x06, 0xe183 },
2372 { 0x06, 0x3168 },
2373 { 0x06, 0x01e4 },
2374 { 0x06, 0xf88a },
2375 { 0x06, 0xe5f8 },
2376 { 0x06, 0x8bae },
2377 { 0x06, 0x37ee },
2378 { 0x06, 0x834e },
2379 { 0x06, 0x03e0 },
2380 { 0x06, 0x834c },
2381 { 0x06, 0xe183 },
2382 { 0x06, 0x4d1b },
2383 { 0x06, 0x019e },
2384 { 0x06, 0x04aa },
2385 { 0x06, 0xa1ae },
2386 { 0x06, 0xa8ee },
2387 { 0x06, 0x834e },
2388 { 0x06, 0x04ee },
2389 { 0x06, 0x834f },
2390 { 0x06, 0x00ae },
2391 { 0x06, 0xabe0 },
2392 { 0x06, 0x834f },
2393 { 0x06, 0x7803 },
2394 { 0x06, 0x9f14 },
2395 { 0x06, 0xee83 },
2396 { 0x06, 0x4e05 },
2397 { 0x06, 0xd240 },
2398 { 0x06, 0xd655 },
2399 { 0x06, 0x5402 },
2400 { 0x06, 0x81c6 },
2401 { 0x06, 0xd2a0 },
2402 { 0x06, 0xd6ba },
2403 { 0x06, 0x0002 },
2404 { 0x06, 0x81c6 },
2405 { 0x06, 0xfefd },
2406 { 0x06, 0xfc05 },
2407 { 0x06, 0xf8e0 },
2408 { 0x06, 0xf860 },
2409 { 0x06, 0xe1f8 },
2410 { 0x06, 0x6168 },
2411 { 0x06, 0x02e4 },
2412 { 0x06, 0xf860 },
2413 { 0x06, 0xe5f8 },
2414 { 0x06, 0x61e0 },
2415 { 0x06, 0xf848 },
2416 { 0x06, 0xe1f8 },
2417 { 0x06, 0x4958 },
2418 { 0x06, 0x0f1e },
2419 { 0x06, 0x02e4 },
2420 { 0x06, 0xf848 },
2421 { 0x06, 0xe5f8 },
2422 { 0x06, 0x49d0 },
2423 { 0x06, 0x0002 },
2424 { 0x06, 0x820a },
2425 { 0x06, 0xbf83 },
2426 { 0x06, 0x50ef },
2427 { 0x06, 0x46dc },
2428 { 0x06, 0x19dd },
2429 { 0x06, 0xd001 },
2430 { 0x06, 0x0282 },
2431 { 0x06, 0x0a02 },
2432 { 0x06, 0x8226 },
2433 { 0x06, 0xe0f8 },
2434 { 0x06, 0x60e1 },
2435 { 0x06, 0xf861 },
2436 { 0x06, 0x58fd },
2437 { 0x06, 0xe4f8 },
2438 { 0x06, 0x60e5 },
2439 { 0x06, 0xf861 },
2440 { 0x06, 0xfc04 },
2441 { 0x06, 0xf9fa },
2442 { 0x06, 0xfbc6 },
2443 { 0x06, 0xbff8 },
2444 { 0x06, 0x40be },
2445 { 0x06, 0x8350 },
2446 { 0x06, 0xa001 },
2447 { 0x06, 0x0107 },
2448 { 0x06, 0x1b89 },
2449 { 0x06, 0xcfd2 },
2450 { 0x06, 0x08eb },
2451 { 0x06, 0xdb19 },
2452 { 0x06, 0xb2fb },
2453 { 0x06, 0xfffe },
2454 { 0x06, 0xfd04 },
2455 { 0x06, 0xf8e0 },
2456 { 0x06, 0xf848 },
2457 { 0x06, 0xe1f8 },
2458 { 0x06, 0x4968 },
2459 { 0x06, 0x08e4 },
2460 { 0x06, 0xf848 },
2461 { 0x06, 0xe5f8 },
2462 { 0x06, 0x4958 },
2463 { 0x06, 0xf7e4 },
2464 { 0x06, 0xf848 },
2465 { 0x06, 0xe5f8 },
2466 { 0x06, 0x49fc },
2467 { 0x06, 0x044d },
2468 { 0x06, 0x2000 },
2469 { 0x06, 0x024e },
2470 { 0x06, 0x2200 },
2471 { 0x06, 0x024d },
2472 { 0x06, 0xdfff },
2473 { 0x06, 0x014e },
2474 { 0x06, 0xddff },
2475 { 0x06, 0x0100 },
2476 { 0x05, 0x83d8 },
2477 { 0x06, 0x8000 },
2478 { 0x03, 0xdc00 },
2479 { 0x05, 0xfff6 },
2480 { 0x06, 0x00fc },
2481 { 0x1f, 0x0000 },
2482
2483 { 0x1f, 0x0000 },
2484 { 0x0d, 0xf880 },
2485 { 0x1f, 0x0000 }
2486 };
2487
2488 rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2489
2490 if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2491 static const struct phy_reg phy_reg_init[] = {
2492 { 0x1f, 0x0002 },
2493 { 0x05, 0x669a },
2494 { 0x1f, 0x0005 },
2495 { 0x05, 0x8330 },
2496 { 0x06, 0x669a },
2497
2498 { 0x1f, 0x0002 }
2499 };
2500 int val;
2501
2502 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2503
2504 val = mdio_read(ioaddr, 0x0d);
2505 if ((val & 0x00ff) != 0x006c) {
2506 u32 set[] = {
2507 0x0065, 0x0066, 0x0067, 0x0068,
2508 0x0069, 0x006a, 0x006b, 0x006c
2509 };
2510 int i;
2511
2512 mdio_write(ioaddr, 0x1f, 0x0002);
2513
2514 val &= 0xff00;
2515 for (i = 0; i < ARRAY_SIZE(set); i++)
2516 mdio_write(ioaddr, 0x0d, val | set[i]);
2517 }
2518 } else {
2519 static const struct phy_reg phy_reg_init[] = {
2520 { 0x1f, 0x0002 },
2521 { 0x05, 0x2642 },
2522 { 0x1f, 0x0005 },
2523 { 0x05, 0x8330 },
2524 { 0x06, 0x2642 }
2525 };
2526
2527 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2528 }
2529
2530 mdio_write(ioaddr, 0x1f, 0x0002);
2531 mdio_plus_minus(ioaddr, 0x02, 0x0100, 0x0600);
2532 mdio_plus_minus(ioaddr, 0x03, 0x0000, 0xe000);
2533
2534 mdio_write(ioaddr, 0x1f, 0x0001);
2535 mdio_write(ioaddr, 0x17, 0x0cc0);
2536
2537 mdio_write(ioaddr, 0x1f, 0x0002);
2538 mdio_patch(ioaddr, 0x0f, 0x0017);
2539
2540 rtl_phy_write(ioaddr, phy_reg_init_1, ARRAY_SIZE(phy_reg_init_1));
2541 }
2542
2543 static void rtl8168d_3_hw_phy_config(void __iomem *ioaddr)
2544 {
2545 static const struct phy_reg phy_reg_init[] = {
2546 { 0x1f, 0x0002 },
2547 { 0x10, 0x0008 },
2548 { 0x0d, 0x006c },
2549
2550 { 0x1f, 0x0000 },
2551 { 0x0d, 0xf880 },
2552
2553 { 0x1f, 0x0001 },
2554 { 0x17, 0x0cc0 },
2555
2556 { 0x1f, 0x0001 },
2557 { 0x0b, 0xa4d8 },
2558 { 0x09, 0x281c },
2559 { 0x07, 0x2883 },
2560 { 0x0a, 0x6b35 },
2561 { 0x1d, 0x3da4 },
2562 { 0x1c, 0xeffd },
2563 { 0x14, 0x7f52 },
2564 { 0x18, 0x7fc6 },
2565 { 0x08, 0x0601 },
2566 { 0x06, 0x4063 },
2567 { 0x10, 0xf074 },
2568 { 0x1f, 0x0003 },
2569 { 0x13, 0x0789 },
2570 { 0x12, 0xf4bd },
2571 { 0x1a, 0x04fd },
2572 { 0x14, 0x84b0 },
2573 { 0x1f, 0x0000 },
2574 { 0x00, 0x9200 },
2575
2576 { 0x1f, 0x0005 },
2577 { 0x01, 0x0340 },
2578 { 0x1f, 0x0001 },
2579 { 0x04, 0x4000 },
2580 { 0x03, 0x1d21 },
2581 { 0x02, 0x0c32 },
2582 { 0x01, 0x0200 },
2583 { 0x00, 0x5554 },
2584 { 0x04, 0x4800 },
2585 { 0x04, 0x4000 },
2586 { 0x04, 0xf000 },
2587 { 0x03, 0xdf01 },
2588 { 0x02, 0xdf20 },
2589 { 0x01, 0x101a },
2590 { 0x00, 0xa0ff },
2591 { 0x04, 0xf800 },
2592 { 0x04, 0xf000 },
2593 { 0x1f, 0x0000 },
2594
2595 { 0x1f, 0x0007 },
2596 { 0x1e, 0x0023 },
2597 { 0x16, 0x0000 },
2598 { 0x1f, 0x0000 }
2599 };
2600
2601 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2602 }
2603
2604 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
2605 {
2606 static const struct phy_reg phy_reg_init[] = {
2607 { 0x1f, 0x0003 },
2608 { 0x08, 0x441d },
2609 { 0x01, 0x9100 },
2610 { 0x1f, 0x0000 }
2611 };
2612
2613 mdio_write(ioaddr, 0x1f, 0x0000);
2614 mdio_patch(ioaddr, 0x11, 1 << 12);
2615 mdio_patch(ioaddr, 0x19, 1 << 13);
2616 mdio_patch(ioaddr, 0x10, 1 << 15);
2617
2618 rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2619 }
2620
2621 static void rtl_hw_phy_config(struct net_device *dev)
2622 {
2623 struct rtl8169_private *tp = netdev_priv(dev);
2624 void __iomem *ioaddr = tp->mmio_addr;
2625
2626 rtl8169_print_mac_version(tp);
2627
2628 switch (tp->mac_version) {
2629 case RTL_GIGA_MAC_VER_01:
2630 break;
2631 case RTL_GIGA_MAC_VER_02:
2632 case RTL_GIGA_MAC_VER_03:
2633 rtl8169s_hw_phy_config(ioaddr);
2634 break;
2635 case RTL_GIGA_MAC_VER_04:
2636 rtl8169sb_hw_phy_config(ioaddr);
2637 break;
2638 case RTL_GIGA_MAC_VER_05:
2639 rtl8169scd_hw_phy_config(tp, ioaddr);
2640 break;
2641 case RTL_GIGA_MAC_VER_06:
2642 rtl8169sce_hw_phy_config(ioaddr);
2643 break;
2644 case RTL_GIGA_MAC_VER_07:
2645 case RTL_GIGA_MAC_VER_08:
2646 case RTL_GIGA_MAC_VER_09:
2647 rtl8102e_hw_phy_config(ioaddr);
2648 break;
2649 case RTL_GIGA_MAC_VER_11:
2650 rtl8168bb_hw_phy_config(ioaddr);
2651 break;
2652 case RTL_GIGA_MAC_VER_12:
2653 rtl8168bef_hw_phy_config(ioaddr);
2654 break;
2655 case RTL_GIGA_MAC_VER_17:
2656 rtl8168bef_hw_phy_config(ioaddr);
2657 break;
2658 case RTL_GIGA_MAC_VER_18:
2659 rtl8168cp_1_hw_phy_config(ioaddr);
2660 break;
2661 case RTL_GIGA_MAC_VER_19:
2662 rtl8168c_1_hw_phy_config(ioaddr);
2663 break;
2664 case RTL_GIGA_MAC_VER_20:
2665 rtl8168c_2_hw_phy_config(ioaddr);
2666 break;
2667 case RTL_GIGA_MAC_VER_21:
2668 rtl8168c_3_hw_phy_config(ioaddr);
2669 break;
2670 case RTL_GIGA_MAC_VER_22:
2671 rtl8168c_4_hw_phy_config(ioaddr);
2672 break;
2673 case RTL_GIGA_MAC_VER_23:
2674 case RTL_GIGA_MAC_VER_24:
2675 rtl8168cp_2_hw_phy_config(ioaddr);
2676 break;
2677 case RTL_GIGA_MAC_VER_25:
2678 rtl8168d_1_hw_phy_config(ioaddr);
2679 break;
2680 case RTL_GIGA_MAC_VER_26:
2681 rtl8168d_2_hw_phy_config(ioaddr);
2682 break;
2683 case RTL_GIGA_MAC_VER_27:
2684 rtl8168d_3_hw_phy_config(ioaddr);
2685 break;
2686
2687 default:
2688 break;
2689 }
2690 }
2691
2692 static void rtl8169_phy_timer(unsigned long __opaque)
2693 {
2694 struct net_device *dev = (struct net_device *)__opaque;
2695 struct rtl8169_private *tp = netdev_priv(dev);
2696 struct timer_list *timer = &tp->timer;
2697 void __iomem *ioaddr = tp->mmio_addr;
2698 unsigned long timeout = RTL8169_PHY_TIMEOUT;
2699
2700 assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2701
2702 if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
2703 return;
2704
2705 spin_lock_irq(&tp->lock);
2706
2707 if (tp->phy_reset_pending(ioaddr)) {
2708 /*
2709 * A busy loop could burn quite a few cycles on nowadays CPU.
2710 * Let's delay the execution of the timer for a few ticks.
2711 */
2712 timeout = HZ/10;
2713 goto out_mod_timer;
2714 }
2715
2716 if (tp->link_ok(ioaddr))
2717 goto out_unlock;
2718
2719 netif_warn(tp, link, dev, "PHY reset until link up\n");
2720
2721 tp->phy_reset_enable(ioaddr);
2722
2723 out_mod_timer:
2724 mod_timer(timer, jiffies + timeout);
2725 out_unlock:
2726 spin_unlock_irq(&tp->lock);
2727 }
2728
2729 static inline void rtl8169_delete_timer(struct net_device *dev)
2730 {
2731 struct rtl8169_private *tp = netdev_priv(dev);
2732 struct timer_list *timer = &tp->timer;
2733
2734 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2735 return;
2736
2737 del_timer_sync(timer);
2738 }
2739
2740 static inline void rtl8169_request_timer(struct net_device *dev)
2741 {
2742 struct rtl8169_private *tp = netdev_priv(dev);
2743 struct timer_list *timer = &tp->timer;
2744
2745 if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
2746 return;
2747
2748 mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
2749 }
2750
2751 #ifdef CONFIG_NET_POLL_CONTROLLER
2752 /*
2753 * Polling 'interrupt' - used by things like netconsole to send skbs
2754 * without having to re-enable interrupts. It's not called while
2755 * the interrupt routine is executing.
2756 */
2757 static void rtl8169_netpoll(struct net_device *dev)
2758 {
2759 struct rtl8169_private *tp = netdev_priv(dev);
2760 struct pci_dev *pdev = tp->pci_dev;
2761
2762 disable_irq(pdev->irq);
2763 rtl8169_interrupt(pdev->irq, dev);
2764 enable_irq(pdev->irq);
2765 }
2766 #endif
2767
2768 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2769 void __iomem *ioaddr)
2770 {
2771 iounmap(ioaddr);
2772 pci_release_regions(pdev);
2773 pci_clear_mwi(pdev);
2774 pci_disable_device(pdev);
2775 free_netdev(dev);
2776 }
2777
2778 static void rtl8169_phy_reset(struct net_device *dev,
2779 struct rtl8169_private *tp)
2780 {
2781 void __iomem *ioaddr = tp->mmio_addr;
2782 unsigned int i;
2783
2784 tp->phy_reset_enable(ioaddr);
2785 for (i = 0; i < 100; i++) {
2786 if (!tp->phy_reset_pending(ioaddr))
2787 return;
2788 msleep(1);
2789 }
2790 netif_err(tp, link, dev, "PHY reset failed\n");
2791 }
2792
2793 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2794 {
2795 void __iomem *ioaddr = tp->mmio_addr;
2796
2797 rtl_hw_phy_config(dev);
2798
2799 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2800 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2801 RTL_W8(0x82, 0x01);
2802 }
2803
2804 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2805
2806 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2807 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2808
2809 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2810 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2811 RTL_W8(0x82, 0x01);
2812 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2813 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
2814 }
2815
2816 rtl8169_phy_reset(dev, tp);
2817
2818 /*
2819 * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
2820 * only 8101. Don't panic.
2821 */
2822 rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
2823
2824 if (RTL_R8(PHYstatus) & TBI_Enable)
2825 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2826 }
2827
2828 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2829 {
2830 void __iomem *ioaddr = tp->mmio_addr;
2831 u32 high;
2832 u32 low;
2833
2834 low = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2835 high = addr[4] | (addr[5] << 8);
2836
2837 spin_lock_irq(&tp->lock);
2838
2839 RTL_W8(Cfg9346, Cfg9346_Unlock);
2840
2841 RTL_W32(MAC4, high);
2842 RTL_R32(MAC4);
2843
2844 RTL_W32(MAC0, low);
2845 RTL_R32(MAC0);
2846
2847 RTL_W8(Cfg9346, Cfg9346_Lock);
2848
2849 spin_unlock_irq(&tp->lock);
2850 }
2851
2852 static int rtl_set_mac_address(struct net_device *dev, void *p)
2853 {
2854 struct rtl8169_private *tp = netdev_priv(dev);
2855 struct sockaddr *addr = p;
2856
2857 if (!is_valid_ether_addr(addr->sa_data))
2858 return -EADDRNOTAVAIL;
2859
2860 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2861
2862 rtl_rar_set(tp, dev->dev_addr);
2863
2864 return 0;
2865 }
2866
2867 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2868 {
2869 struct rtl8169_private *tp = netdev_priv(dev);
2870 struct mii_ioctl_data *data = if_mii(ifr);
2871
2872 return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2873 }
2874
2875 static int rtl_xmii_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2876 {
2877 switch (cmd) {
2878 case SIOCGMIIPHY:
2879 data->phy_id = 32; /* Internal PHY */
2880 return 0;
2881
2882 case SIOCGMIIREG:
2883 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
2884 return 0;
2885
2886 case SIOCSMIIREG:
2887 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
2888 return 0;
2889 }
2890 return -EOPNOTSUPP;
2891 }
2892
2893 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2894 {
2895 return -EOPNOTSUPP;
2896 }
2897
2898 static const struct rtl_cfg_info {
2899 void (*hw_start)(struct net_device *);
2900 unsigned int region;
2901 unsigned int align;
2902 u16 intr_event;
2903 u16 napi_event;
2904 unsigned features;
2905 u8 default_ver;
2906 } rtl_cfg_infos [] = {
2907 [RTL_CFG_0] = {
2908 .hw_start = rtl_hw_start_8169,
2909 .region = 1,
2910 .align = 0,
2911 .intr_event = SYSErr | LinkChg | RxOverflow |
2912 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2913 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2914 .features = RTL_FEATURE_GMII,
2915 .default_ver = RTL_GIGA_MAC_VER_01,
2916 },
2917 [RTL_CFG_1] = {
2918 .hw_start = rtl_hw_start_8168,
2919 .region = 2,
2920 .align = 8,
2921 .intr_event = SYSErr | LinkChg | RxOverflow |
2922 TxErr | TxOK | RxOK | RxErr,
2923 .napi_event = TxErr | TxOK | RxOK | RxOverflow,
2924 .features = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
2925 .default_ver = RTL_GIGA_MAC_VER_11,
2926 },
2927 [RTL_CFG_2] = {
2928 .hw_start = rtl_hw_start_8101,
2929 .region = 2,
2930 .align = 8,
2931 .intr_event = SYSErr | LinkChg | RxOverflow | PCSTimeout |
2932 RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
2933 .napi_event = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
2934 .features = RTL_FEATURE_MSI,
2935 .default_ver = RTL_GIGA_MAC_VER_13,
2936 }
2937 };
2938
2939 /* Cfg9346_Unlock assumed. */
2940 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
2941 const struct rtl_cfg_info *cfg)
2942 {
2943 unsigned msi = 0;
2944 u8 cfg2;
2945
2946 cfg2 = RTL_R8(Config2) & ~MSIEnable;
2947 if (cfg->features & RTL_FEATURE_MSI) {
2948 if (pci_enable_msi(pdev)) {
2949 dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
2950 } else {
2951 cfg2 |= MSIEnable;
2952 msi = RTL_FEATURE_MSI;
2953 }
2954 }
2955 RTL_W8(Config2, cfg2);
2956 return msi;
2957 }
2958
2959 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
2960 {
2961 if (tp->features & RTL_FEATURE_MSI) {
2962 pci_disable_msi(pdev);
2963 tp->features &= ~RTL_FEATURE_MSI;
2964 }
2965 }
2966
2967 static const struct net_device_ops rtl8169_netdev_ops = {
2968 .ndo_open = rtl8169_open,
2969 .ndo_stop = rtl8169_close,
2970 .ndo_get_stats = rtl8169_get_stats,
2971 .ndo_start_xmit = rtl8169_start_xmit,
2972 .ndo_tx_timeout = rtl8169_tx_timeout,
2973 .ndo_validate_addr = eth_validate_addr,
2974 .ndo_change_mtu = rtl8169_change_mtu,
2975 .ndo_set_mac_address = rtl_set_mac_address,
2976 .ndo_do_ioctl = rtl8169_ioctl,
2977 .ndo_set_multicast_list = rtl_set_rx_mode,
2978 #ifdef CONFIG_R8169_VLAN
2979 .ndo_vlan_rx_register = rtl8169_vlan_rx_register,
2980 #endif
2981 #ifdef CONFIG_NET_POLL_CONTROLLER
2982 .ndo_poll_controller = rtl8169_netpoll,
2983 #endif
2984
2985 };
2986
2987 static int __devinit
2988 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2989 {
2990 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
2991 const unsigned int region = cfg->region;
2992 struct rtl8169_private *tp;
2993 struct mii_if_info *mii;
2994 struct net_device *dev;
2995 void __iomem *ioaddr;
2996 unsigned int i;
2997 int rc;
2998
2999 if (netif_msg_drv(&debug)) {
3000 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3001 MODULENAME, RTL8169_VERSION);
3002 }
3003
3004 dev = alloc_etherdev(sizeof (*tp));
3005 if (!dev) {
3006 if (netif_msg_drv(&debug))
3007 dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3008 rc = -ENOMEM;
3009 goto out;
3010 }
3011
3012 SET_NETDEV_DEV(dev, &pdev->dev);
3013 dev->netdev_ops = &rtl8169_netdev_ops;
3014 tp = netdev_priv(dev);
3015 tp->dev = dev;
3016 tp->pci_dev = pdev;
3017 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3018
3019 mii = &tp->mii;
3020 mii->dev = dev;
3021 mii->mdio_read = rtl_mdio_read;
3022 mii->mdio_write = rtl_mdio_write;
3023 mii->phy_id_mask = 0x1f;
3024 mii->reg_num_mask = 0x1f;
3025 mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3026
3027 /* enable device (incl. PCI PM wakeup and hotplug setup) */
3028 rc = pci_enable_device(pdev);
3029 if (rc < 0) {
3030 netif_err(tp, probe, dev, "enable failure\n");
3031 goto err_out_free_dev_1;
3032 }
3033
3034 if (pci_set_mwi(pdev) < 0)
3035 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3036
3037 /* make sure PCI base addr 1 is MMIO */
3038 if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3039 netif_err(tp, probe, dev,
3040 "region #%d not an MMIO resource, aborting\n",
3041 region);
3042 rc = -ENODEV;
3043 goto err_out_mwi_2;
3044 }
3045
3046 /* check for weird/broken PCI region reporting */
3047 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3048 netif_err(tp, probe, dev,
3049 "Invalid PCI region size(s), aborting\n");
3050 rc = -ENODEV;
3051 goto err_out_mwi_2;
3052 }
3053
3054 rc = pci_request_regions(pdev, MODULENAME);
3055 if (rc < 0) {
3056 netif_err(tp, probe, dev, "could not request regions\n");
3057 goto err_out_mwi_2;
3058 }
3059
3060 tp->cp_cmd = PCIMulRW | RxChkSum;
3061
3062 if ((sizeof(dma_addr_t) > 4) &&
3063 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3064 tp->cp_cmd |= PCIDAC;
3065 dev->features |= NETIF_F_HIGHDMA;
3066 } else {
3067 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3068 if (rc < 0) {
3069 netif_err(tp, probe, dev, "DMA configuration failed\n");
3070 goto err_out_free_res_3;
3071 }
3072 }
3073
3074 /* ioremap MMIO region */
3075 ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3076 if (!ioaddr) {
3077 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3078 rc = -EIO;
3079 goto err_out_free_res_3;
3080 }
3081
3082 tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3083 if (!tp->pcie_cap)
3084 netif_info(tp, probe, dev, "no PCI Express capability\n");
3085
3086 RTL_W16(IntrMask, 0x0000);
3087
3088 /* Soft reset the chip. */
3089 RTL_W8(ChipCmd, CmdReset);
3090
3091 /* Check that the chip has finished the reset. */
3092 for (i = 0; i < 100; i++) {
3093 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3094 break;
3095 msleep_interruptible(1);
3096 }
3097
3098 RTL_W16(IntrStatus, 0xffff);
3099
3100 pci_set_master(pdev);
3101
3102 /* Identify chip attached to board */
3103 rtl8169_get_mac_version(tp, ioaddr);
3104
3105 /* Use appropriate default if unknown */
3106 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
3107 netif_notice(tp, probe, dev,
3108 "unknown MAC, using family default\n");
3109 tp->mac_version = cfg->default_ver;
3110 }
3111
3112 rtl8169_print_mac_version(tp);
3113
3114 for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
3115 if (tp->mac_version == rtl_chip_info[i].mac_version)
3116 break;
3117 }
3118 if (i == ARRAY_SIZE(rtl_chip_info)) {
3119 dev_err(&pdev->dev,
3120 "driver bug, MAC version not found in rtl_chip_info\n");
3121 goto err_out_msi_4;
3122 }
3123 tp->chipset = i;
3124
3125 RTL_W8(Cfg9346, Cfg9346_Unlock);
3126 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3127 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3128 if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3129 tp->features |= RTL_FEATURE_WOL;
3130 if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3131 tp->features |= RTL_FEATURE_WOL;
3132 tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3133 RTL_W8(Cfg9346, Cfg9346_Lock);
3134
3135 if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3136 (RTL_R8(PHYstatus) & TBI_Enable)) {
3137 tp->set_speed = rtl8169_set_speed_tbi;
3138 tp->get_settings = rtl8169_gset_tbi;
3139 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3140 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3141 tp->link_ok = rtl8169_tbi_link_ok;
3142 tp->do_ioctl = rtl_tbi_ioctl;
3143
3144 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
3145 } else {
3146 tp->set_speed = rtl8169_set_speed_xmii;
3147 tp->get_settings = rtl8169_gset_xmii;
3148 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3149 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3150 tp->link_ok = rtl8169_xmii_link_ok;
3151 tp->do_ioctl = rtl_xmii_ioctl;
3152 }
3153
3154 spin_lock_init(&tp->lock);
3155
3156 tp->mmio_addr = ioaddr;
3157
3158 /* Get MAC address */
3159 for (i = 0; i < MAC_ADDR_LEN; i++)
3160 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3161 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3162
3163 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3164 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3165 dev->irq = pdev->irq;
3166 dev->base_addr = (unsigned long) ioaddr;
3167
3168 netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3169
3170 #ifdef CONFIG_R8169_VLAN
3171 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3172 #endif
3173
3174 tp->intr_mask = 0xffff;
3175 tp->align = cfg->align;
3176 tp->hw_start = cfg->hw_start;
3177 tp->intr_event = cfg->intr_event;
3178 tp->napi_event = cfg->napi_event;
3179
3180 init_timer(&tp->timer);
3181 tp->timer.data = (unsigned long) dev;
3182 tp->timer.function = rtl8169_phy_timer;
3183
3184 rc = register_netdev(dev);
3185 if (rc < 0)
3186 goto err_out_msi_4;
3187
3188 pci_set_drvdata(pdev, dev);
3189
3190 netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3191 rtl_chip_info[tp->chipset].name,
3192 dev->base_addr, dev->dev_addr,
3193 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3194
3195 rtl8169_init_phy(dev, tp);
3196
3197 /*
3198 * Pretend we are using VLANs; This bypasses a nasty bug where
3199 * Interrupts stop flowing on high load on 8110SCd controllers.
3200 */
3201 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3202 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | RxVlan);
3203
3204 device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3205
3206 out:
3207 return rc;
3208
3209 err_out_msi_4:
3210 rtl_disable_msi(pdev, tp);
3211 iounmap(ioaddr);
3212 err_out_free_res_3:
3213 pci_release_regions(pdev);
3214 err_out_mwi_2:
3215 pci_clear_mwi(pdev);
3216 pci_disable_device(pdev);
3217 err_out_free_dev_1:
3218 free_netdev(dev);
3219 goto out;
3220 }
3221
3222 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3223 {
3224 struct net_device *dev = pci_get_drvdata(pdev);
3225 struct rtl8169_private *tp = netdev_priv(dev);
3226
3227 flush_scheduled_work();
3228
3229 unregister_netdev(dev);
3230
3231 /* restore original MAC address */
3232 rtl_rar_set(tp, dev->perm_addr);
3233
3234 rtl_disable_msi(pdev, tp);
3235 rtl8169_release_board(pdev, dev, tp->mmio_addr);
3236 pci_set_drvdata(pdev, NULL);
3237 }
3238
3239 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
3240 unsigned int mtu)
3241 {
3242 unsigned int max_frame = mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3243
3244 if (max_frame != 16383)
3245 printk(KERN_WARNING PFX "WARNING! Changing of MTU on this "
3246 "NIC may lead to frame reception errors!\n");
3247
3248 tp->rx_buf_sz = (max_frame > RX_BUF_SIZE) ? max_frame : RX_BUF_SIZE;
3249 }
3250
3251 static int rtl8169_open(struct net_device *dev)
3252 {
3253 struct rtl8169_private *tp = netdev_priv(dev);
3254 struct pci_dev *pdev = tp->pci_dev;
3255 int retval = -ENOMEM;
3256
3257
3258 /*
3259 * Note that we use a magic value here, its wierd I know
3260 * its done because, some subset of rtl8169 hardware suffers from
3261 * a problem in which frames received that are longer than
3262 * the size set in RxMaxSize register return garbage sizes
3263 * when received. To avoid this we need to turn off filtering,
3264 * which is done by setting a value of 16383 in the RxMaxSize register
3265 * and allocating 16k frames to handle the largest possible rx value
3266 * thats what the magic math below does.
3267 */
3268 rtl8169_set_rxbufsize(tp, 16383 - VLAN_ETH_HLEN - ETH_FCS_LEN);
3269
3270 /*
3271 * Rx and Tx desscriptors needs 256 bytes alignment.
3272 * pci_alloc_consistent provides more.
3273 */
3274 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
3275 &tp->TxPhyAddr);
3276 if (!tp->TxDescArray)
3277 goto out;
3278
3279 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
3280 &tp->RxPhyAddr);
3281 if (!tp->RxDescArray)
3282 goto err_free_tx_0;
3283
3284 retval = rtl8169_init_ring(dev);
3285 if (retval < 0)
3286 goto err_free_rx_1;
3287
3288 INIT_DELAYED_WORK(&tp->task, NULL);
3289
3290 smp_mb();
3291
3292 retval = request_irq(dev->irq, rtl8169_interrupt,
3293 (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3294 dev->name, dev);
3295 if (retval < 0)
3296 goto err_release_ring_2;
3297
3298 napi_enable(&tp->napi);
3299
3300 rtl_hw_start(dev);
3301
3302 rtl8169_request_timer(dev);
3303
3304 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3305 out:
3306 return retval;
3307
3308 err_release_ring_2:
3309 rtl8169_rx_clear(tp);
3310 err_free_rx_1:
3311 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3312 tp->RxPhyAddr);
3313 err_free_tx_0:
3314 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3315 tp->TxPhyAddr);
3316 goto out;
3317 }
3318
3319 static void rtl8169_hw_reset(void __iomem *ioaddr)
3320 {
3321 /* Disable interrupts */
3322 rtl8169_irq_mask_and_ack(ioaddr);
3323
3324 /* Reset the chipset */
3325 RTL_W8(ChipCmd, CmdReset);
3326
3327 /* PCI commit */
3328 RTL_R8(ChipCmd);
3329 }
3330
3331 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3332 {
3333 void __iomem *ioaddr = tp->mmio_addr;
3334 u32 cfg = rtl8169_rx_config;
3335
3336 cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3337 RTL_W32(RxConfig, cfg);
3338
3339 /* Set DMA burst size and Interframe Gap Time */
3340 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3341 (InterFrameGap << TxInterFrameGapShift));
3342 }
3343
3344 static void rtl_hw_start(struct net_device *dev)
3345 {
3346 struct rtl8169_private *tp = netdev_priv(dev);
3347 void __iomem *ioaddr = tp->mmio_addr;
3348 unsigned int i;
3349
3350 /* Soft reset the chip. */
3351 RTL_W8(ChipCmd, CmdReset);
3352
3353 /* Check that the chip has finished the reset. */
3354 for (i = 0; i < 100; i++) {
3355 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3356 break;
3357 msleep_interruptible(1);
3358 }
3359
3360 tp->hw_start(dev);
3361
3362 netif_start_queue(dev);
3363 }
3364
3365
3366 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3367 void __iomem *ioaddr)
3368 {
3369 /*
3370 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3371 * register to be written before TxDescAddrLow to work.
3372 * Switching from MMIO to I/O access fixes the issue as well.
3373 */
3374 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3375 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3376 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3377 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3378 }
3379
3380 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3381 {
3382 u16 cmd;
3383
3384 cmd = RTL_R16(CPlusCmd);
3385 RTL_W16(CPlusCmd, cmd);
3386 return cmd;
3387 }
3388
3389 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3390 {
3391 /* Low hurts. Let's disable the filtering. */
3392 RTL_W16(RxMaxSize, rx_buf_sz + 1);
3393 }
3394
3395 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3396 {
3397 static const struct {
3398 u32 mac_version;
3399 u32 clk;
3400 u32 val;
3401 } cfg2_info [] = {
3402 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3403 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3404 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3405 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3406 }, *p = cfg2_info;
3407 unsigned int i;
3408 u32 clk;
3409
3410 clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3411 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3412 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3413 RTL_W32(0x7c, p->val);
3414 break;
3415 }
3416 }
3417 }
3418
3419 static void rtl_hw_start_8169(struct net_device *dev)
3420 {
3421 struct rtl8169_private *tp = netdev_priv(dev);
3422 void __iomem *ioaddr = tp->mmio_addr;
3423 struct pci_dev *pdev = tp->pci_dev;
3424
3425 if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3426 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3427 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3428 }
3429
3430 RTL_W8(Cfg9346, Cfg9346_Unlock);
3431 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3432 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3433 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3434 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3435 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3436
3437 RTL_W8(EarlyTxThres, EarlyTxThld);
3438
3439 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3440
3441 if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
3442 (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3443 (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
3444 (tp->mac_version == RTL_GIGA_MAC_VER_04))
3445 rtl_set_rx_tx_config_registers(tp);
3446
3447 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3448
3449 if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
3450 (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
3451 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3452 "Bit-3 and bit-14 MUST be 1\n");
3453 tp->cp_cmd |= (1 << 14);
3454 }
3455
3456 RTL_W16(CPlusCmd, tp->cp_cmd);
3457
3458 rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3459
3460 /*
3461 * Undocumented corner. Supposedly:
3462 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3463 */
3464 RTL_W16(IntrMitigate, 0x0000);
3465
3466 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3467
3468 if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
3469 (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
3470 (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
3471 (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
3472 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3473 rtl_set_rx_tx_config_registers(tp);
3474 }
3475
3476 RTL_W8(Cfg9346, Cfg9346_Lock);
3477
3478 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3479 RTL_R8(IntrMask);
3480
3481 RTL_W32(RxMissed, 0);
3482
3483 rtl_set_rx_mode(dev);
3484
3485 /* no early-rx interrupts */
3486 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3487
3488 /* Enable all known interrupts by setting the interrupt mask. */
3489 RTL_W16(IntrMask, tp->intr_event);
3490 }
3491
3492 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3493 {
3494 struct net_device *dev = pci_get_drvdata(pdev);
3495 struct rtl8169_private *tp = netdev_priv(dev);
3496 int cap = tp->pcie_cap;
3497
3498 if (cap) {
3499 u16 ctl;
3500
3501 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3502 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3503 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3504 }
3505 }
3506
3507 static void rtl_csi_access_enable(void __iomem *ioaddr)
3508 {
3509 u32 csi;
3510
3511 csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3512 rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
3513 }
3514
3515 struct ephy_info {
3516 unsigned int offset;
3517 u16 mask;
3518 u16 bits;
3519 };
3520
3521 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3522 {
3523 u16 w;
3524
3525 while (len-- > 0) {
3526 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3527 rtl_ephy_write(ioaddr, e->offset, w);
3528 e++;
3529 }
3530 }
3531
3532 static void rtl_disable_clock_request(struct pci_dev *pdev)
3533 {
3534 struct net_device *dev = pci_get_drvdata(pdev);
3535 struct rtl8169_private *tp = netdev_priv(dev);
3536 int cap = tp->pcie_cap;
3537
3538 if (cap) {
3539 u16 ctl;
3540
3541 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3542 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3543 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3544 }
3545 }
3546
3547 #define R8168_CPCMD_QUIRK_MASK (\
3548 EnableBist | \
3549 Mac_dbgo_oe | \
3550 Force_half_dup | \
3551 Force_rxflow_en | \
3552 Force_txflow_en | \
3553 Cxpl_dbg_sel | \
3554 ASF | \
3555 PktCntrDisable | \
3556 Mac_dbgo_sel)
3557
3558 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3559 {
3560 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3561
3562 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3563
3564 rtl_tx_performance_tweak(pdev,
3565 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3566 }
3567
3568 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
3569 {
3570 rtl_hw_start_8168bb(ioaddr, pdev);
3571
3572 RTL_W8(EarlyTxThres, EarlyTxThld);
3573
3574 RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
3575 }
3576
3577 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
3578 {
3579 RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
3580
3581 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3582
3583 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3584
3585 rtl_disable_clock_request(pdev);
3586
3587 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3588 }
3589
3590 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
3591 {
3592 static const struct ephy_info e_info_8168cp[] = {
3593 { 0x01, 0, 0x0001 },
3594 { 0x02, 0x0800, 0x1000 },
3595 { 0x03, 0, 0x0042 },
3596 { 0x06, 0x0080, 0x0000 },
3597 { 0x07, 0, 0x2000 }
3598 };
3599
3600 rtl_csi_access_enable(ioaddr);
3601
3602 rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
3603
3604 __rtl_hw_start_8168cp(ioaddr, pdev);
3605 }
3606
3607 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
3608 {
3609 rtl_csi_access_enable(ioaddr);
3610
3611 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3612
3613 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3614
3615 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3616 }
3617
3618 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
3619 {
3620 rtl_csi_access_enable(ioaddr);
3621
3622 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3623
3624 /* Magic. */
3625 RTL_W8(DBG_REG, 0x20);
3626
3627 RTL_W8(EarlyTxThres, EarlyTxThld);
3628
3629 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3630
3631 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3632 }
3633
3634 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
3635 {
3636 static const struct ephy_info e_info_8168c_1[] = {
3637 { 0x02, 0x0800, 0x1000 },
3638 { 0x03, 0, 0x0002 },
3639 { 0x06, 0x0080, 0x0000 }
3640 };
3641
3642 rtl_csi_access_enable(ioaddr);
3643
3644 RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
3645
3646 rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
3647
3648 __rtl_hw_start_8168cp(ioaddr, pdev);
3649 }
3650
3651 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
3652 {
3653 static const struct ephy_info e_info_8168c_2[] = {
3654 { 0x01, 0, 0x0001 },
3655 { 0x03, 0x0400, 0x0220 }
3656 };
3657
3658 rtl_csi_access_enable(ioaddr);
3659
3660 rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
3661
3662 __rtl_hw_start_8168cp(ioaddr, pdev);
3663 }
3664
3665 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
3666 {
3667 rtl_hw_start_8168c_2(ioaddr, pdev);
3668 }
3669
3670 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
3671 {
3672 rtl_csi_access_enable(ioaddr);
3673
3674 __rtl_hw_start_8168cp(ioaddr, pdev);
3675 }
3676
3677 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
3678 {
3679 rtl_csi_access_enable(ioaddr);
3680
3681 rtl_disable_clock_request(pdev);
3682
3683 RTL_W8(EarlyTxThres, EarlyTxThld);
3684
3685 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3686
3687 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3688 }
3689
3690 static void rtl_hw_start_8168(struct net_device *dev)
3691 {
3692 struct rtl8169_private *tp = netdev_priv(dev);
3693 void __iomem *ioaddr = tp->mmio_addr;
3694 struct pci_dev *pdev = tp->pci_dev;
3695
3696 RTL_W8(Cfg9346, Cfg9346_Unlock);
3697
3698 RTL_W8(EarlyTxThres, EarlyTxThld);
3699
3700 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3701
3702 tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
3703
3704 RTL_W16(CPlusCmd, tp->cp_cmd);
3705
3706 RTL_W16(IntrMitigate, 0x5151);
3707
3708 /* Work around for RxFIFO overflow. */
3709 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
3710 tp->intr_event |= RxFIFOOver | PCSTimeout;
3711 tp->intr_event &= ~RxOverflow;
3712 }
3713
3714 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3715
3716 rtl_set_rx_mode(dev);
3717
3718 RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3719 (InterFrameGap << TxInterFrameGapShift));
3720
3721 RTL_R8(IntrMask);
3722
3723 switch (tp->mac_version) {
3724 case RTL_GIGA_MAC_VER_11:
3725 rtl_hw_start_8168bb(ioaddr, pdev);
3726 break;
3727
3728 case RTL_GIGA_MAC_VER_12:
3729 case RTL_GIGA_MAC_VER_17:
3730 rtl_hw_start_8168bef(ioaddr, pdev);
3731 break;
3732
3733 case RTL_GIGA_MAC_VER_18:
3734 rtl_hw_start_8168cp_1(ioaddr, pdev);
3735 break;
3736
3737 case RTL_GIGA_MAC_VER_19:
3738 rtl_hw_start_8168c_1(ioaddr, pdev);
3739 break;
3740
3741 case RTL_GIGA_MAC_VER_20:
3742 rtl_hw_start_8168c_2(ioaddr, pdev);
3743 break;
3744
3745 case RTL_GIGA_MAC_VER_21:
3746 rtl_hw_start_8168c_3(ioaddr, pdev);
3747 break;
3748
3749 case RTL_GIGA_MAC_VER_22:
3750 rtl_hw_start_8168c_4(ioaddr, pdev);
3751 break;
3752
3753 case RTL_GIGA_MAC_VER_23:
3754 rtl_hw_start_8168cp_2(ioaddr, pdev);
3755 break;
3756
3757 case RTL_GIGA_MAC_VER_24:
3758 rtl_hw_start_8168cp_3(ioaddr, pdev);
3759 break;
3760
3761 case RTL_GIGA_MAC_VER_25:
3762 case RTL_GIGA_MAC_VER_26:
3763 case RTL_GIGA_MAC_VER_27:
3764 rtl_hw_start_8168d(ioaddr, pdev);
3765 break;
3766
3767 default:
3768 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
3769 dev->name, tp->mac_version);
3770 break;
3771 }
3772
3773 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3774
3775 RTL_W8(Cfg9346, Cfg9346_Lock);
3776
3777 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3778
3779 RTL_W16(IntrMask, tp->intr_event);
3780 }
3781
3782 #define R810X_CPCMD_QUIRK_MASK (\
3783 EnableBist | \
3784 Mac_dbgo_oe | \
3785 Force_half_dup | \
3786 Force_rxflow_en | \
3787 Force_txflow_en | \
3788 Cxpl_dbg_sel | \
3789 ASF | \
3790 PktCntrDisable | \
3791 PCIDAC | \
3792 PCIMulRW)
3793
3794 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
3795 {
3796 static const struct ephy_info e_info_8102e_1[] = {
3797 { 0x01, 0, 0x6e65 },
3798 { 0x02, 0, 0x091f },
3799 { 0x03, 0, 0xc2f9 },
3800 { 0x06, 0, 0xafb5 },
3801 { 0x07, 0, 0x0e00 },
3802 { 0x19, 0, 0xec80 },
3803 { 0x01, 0, 0x2e65 },
3804 { 0x01, 0, 0x6e65 }
3805 };
3806 u8 cfg1;
3807
3808 rtl_csi_access_enable(ioaddr);
3809
3810 RTL_W8(DBG_REG, FIX_NAK_1);
3811
3812 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3813
3814 RTL_W8(Config1,
3815 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
3816 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3817
3818 cfg1 = RTL_R8(Config1);
3819 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
3820 RTL_W8(Config1, cfg1 & ~LEDS0);
3821
3822 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3823
3824 rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
3825 }
3826
3827 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
3828 {
3829 rtl_csi_access_enable(ioaddr);
3830
3831 rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
3832
3833 RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
3834 RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3835
3836 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
3837 }
3838
3839 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
3840 {
3841 rtl_hw_start_8102e_2(ioaddr, pdev);
3842
3843 rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
3844 }
3845
3846 static void rtl_hw_start_8101(struct net_device *dev)
3847 {
3848 struct rtl8169_private *tp = netdev_priv(dev);
3849 void __iomem *ioaddr = tp->mmio_addr;
3850 struct pci_dev *pdev = tp->pci_dev;
3851
3852 if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
3853 (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
3854 int cap = tp->pcie_cap;
3855
3856 if (cap) {
3857 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
3858 PCI_EXP_DEVCTL_NOSNOOP_EN);
3859 }
3860 }
3861
3862 switch (tp->mac_version) {
3863 case RTL_GIGA_MAC_VER_07:
3864 rtl_hw_start_8102e_1(ioaddr, pdev);
3865 break;
3866
3867 case RTL_GIGA_MAC_VER_08:
3868 rtl_hw_start_8102e_3(ioaddr, pdev);
3869 break;
3870
3871 case RTL_GIGA_MAC_VER_09:
3872 rtl_hw_start_8102e_2(ioaddr, pdev);
3873 break;
3874 }
3875
3876 RTL_W8(Cfg9346, Cfg9346_Unlock);
3877
3878 RTL_W8(EarlyTxThres, EarlyTxThld);
3879
3880 rtl_set_rx_max_size(ioaddr, tp->rx_buf_sz);
3881
3882 tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3883
3884 RTL_W16(CPlusCmd, tp->cp_cmd);
3885
3886 RTL_W16(IntrMitigate, 0x0000);
3887
3888 rtl_set_rx_tx_desc_registers(tp, ioaddr);
3889
3890 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3891 rtl_set_rx_tx_config_registers(tp);
3892
3893 RTL_W8(Cfg9346, Cfg9346_Lock);
3894
3895 RTL_R8(IntrMask);
3896
3897 rtl_set_rx_mode(dev);
3898
3899 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3900
3901 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
3902
3903 RTL_W16(IntrMask, tp->intr_event);
3904 }
3905
3906 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
3907 {
3908 struct rtl8169_private *tp = netdev_priv(dev);
3909 int ret = 0;
3910
3911 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
3912 return -EINVAL;
3913
3914 dev->mtu = new_mtu;
3915
3916 if (!netif_running(dev))
3917 goto out;
3918
3919 rtl8169_down(dev);
3920
3921 rtl8169_set_rxbufsize(tp, dev->mtu);
3922
3923 ret = rtl8169_init_ring(dev);
3924 if (ret < 0)
3925 goto out;
3926
3927 napi_enable(&tp->napi);
3928
3929 rtl_hw_start(dev);
3930
3931 rtl8169_request_timer(dev);
3932
3933 out:
3934 return ret;
3935 }
3936
3937 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
3938 {
3939 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
3940 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
3941 }
3942
3943 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
3944 struct sk_buff **sk_buff, struct RxDesc *desc)
3945 {
3946 struct pci_dev *pdev = tp->pci_dev;
3947
3948 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
3949 PCI_DMA_FROMDEVICE);
3950 dev_kfree_skb(*sk_buff);
3951 *sk_buff = NULL;
3952 rtl8169_make_unusable_by_asic(desc);
3953 }
3954
3955 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
3956 {
3957 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
3958
3959 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
3960 }
3961
3962 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
3963 u32 rx_buf_sz)
3964 {
3965 desc->addr = cpu_to_le64(mapping);
3966 wmb();
3967 rtl8169_mark_to_asic(desc, rx_buf_sz);
3968 }
3969
3970 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
3971 struct net_device *dev,
3972 struct RxDesc *desc, int rx_buf_sz,
3973 unsigned int align)
3974 {
3975 struct sk_buff *skb;
3976 dma_addr_t mapping;
3977 unsigned int pad;
3978
3979 pad = align ? align : NET_IP_ALIGN;
3980
3981 skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
3982 if (!skb)
3983 goto err_out;
3984
3985 skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
3986
3987 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
3988 PCI_DMA_FROMDEVICE);
3989
3990 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
3991 out:
3992 return skb;
3993
3994 err_out:
3995 rtl8169_make_unusable_by_asic(desc);
3996 goto out;
3997 }
3998
3999 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4000 {
4001 unsigned int i;
4002
4003 for (i = 0; i < NUM_RX_DESC; i++) {
4004 if (tp->Rx_skbuff[i]) {
4005 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
4006 tp->RxDescArray + i);
4007 }
4008 }
4009 }
4010
4011 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
4012 u32 start, u32 end)
4013 {
4014 u32 cur;
4015
4016 for (cur = start; end - cur != 0; cur++) {
4017 struct sk_buff *skb;
4018 unsigned int i = cur % NUM_RX_DESC;
4019
4020 WARN_ON((s32)(end - cur) < 0);
4021
4022 if (tp->Rx_skbuff[i])
4023 continue;
4024
4025 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
4026 tp->RxDescArray + i,
4027 tp->rx_buf_sz, tp->align);
4028 if (!skb)
4029 break;
4030
4031 tp->Rx_skbuff[i] = skb;
4032 }
4033 return cur - start;
4034 }
4035
4036 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4037 {
4038 desc->opts1 |= cpu_to_le32(RingEnd);
4039 }
4040
4041 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4042 {
4043 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4044 }
4045
4046 static int rtl8169_init_ring(struct net_device *dev)
4047 {
4048 struct rtl8169_private *tp = netdev_priv(dev);
4049
4050 rtl8169_init_ring_indexes(tp);
4051
4052 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4053 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
4054
4055 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
4056 goto err_out;
4057
4058 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4059
4060 return 0;
4061
4062 err_out:
4063 rtl8169_rx_clear(tp);
4064 return -ENOMEM;
4065 }
4066
4067 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
4068 struct TxDesc *desc)
4069 {
4070 unsigned int len = tx_skb->len;
4071
4072 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
4073 desc->opts1 = 0x00;
4074 desc->opts2 = 0x00;
4075 desc->addr = 0x00;
4076 tx_skb->len = 0;
4077 }
4078
4079 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4080 {
4081 unsigned int i;
4082
4083 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
4084 unsigned int entry = i % NUM_TX_DESC;
4085 struct ring_info *tx_skb = tp->tx_skb + entry;
4086 unsigned int len = tx_skb->len;
4087
4088 if (len) {
4089 struct sk_buff *skb = tx_skb->skb;
4090
4091 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
4092 tp->TxDescArray + entry);
4093 if (skb) {
4094 dev_kfree_skb(skb);
4095 tx_skb->skb = NULL;
4096 }
4097 tp->dev->stats.tx_dropped++;
4098 }
4099 }
4100 tp->cur_tx = tp->dirty_tx = 0;
4101 }
4102
4103 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4104 {
4105 struct rtl8169_private *tp = netdev_priv(dev);
4106
4107 PREPARE_DELAYED_WORK(&tp->task, task);
4108 schedule_delayed_work(&tp->task, 4);
4109 }
4110
4111 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4112 {
4113 struct rtl8169_private *tp = netdev_priv(dev);
4114 void __iomem *ioaddr = tp->mmio_addr;
4115
4116 synchronize_irq(dev->irq);
4117
4118 /* Wait for any pending NAPI task to complete */
4119 napi_disable(&tp->napi);
4120
4121 rtl8169_irq_mask_and_ack(ioaddr);
4122
4123 tp->intr_mask = 0xffff;
4124 RTL_W16(IntrMask, tp->intr_event);
4125 napi_enable(&tp->napi);
4126 }
4127
4128 static void rtl8169_reinit_task(struct work_struct *work)
4129 {
4130 struct rtl8169_private *tp =
4131 container_of(work, struct rtl8169_private, task.work);
4132 struct net_device *dev = tp->dev;
4133 int ret;
4134
4135 rtnl_lock();
4136
4137 if (!netif_running(dev))
4138 goto out_unlock;
4139
4140 rtl8169_wait_for_quiescence(dev);
4141 rtl8169_close(dev);
4142
4143 ret = rtl8169_open(dev);
4144 if (unlikely(ret < 0)) {
4145 if (net_ratelimit())
4146 netif_err(tp, drv, dev,
4147 "reinit failure (status = %d). Rescheduling\n",
4148 ret);
4149 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4150 }
4151
4152 out_unlock:
4153 rtnl_unlock();
4154 }
4155
4156 static void rtl8169_reset_task(struct work_struct *work)
4157 {
4158 struct rtl8169_private *tp =
4159 container_of(work, struct rtl8169_private, task.work);
4160 struct net_device *dev = tp->dev;
4161
4162 rtnl_lock();
4163
4164 if (!netif_running(dev))
4165 goto out_unlock;
4166
4167 rtl8169_wait_for_quiescence(dev);
4168
4169 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
4170 rtl8169_tx_clear(tp);
4171
4172 if (tp->dirty_rx == tp->cur_rx) {
4173 rtl8169_init_ring_indexes(tp);
4174 rtl_hw_start(dev);
4175 netif_wake_queue(dev);
4176 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4177 } else {
4178 if (net_ratelimit())
4179 netif_emerg(tp, intr, dev, "Rx buffers shortage\n");
4180 rtl8169_schedule_work(dev, rtl8169_reset_task);
4181 }
4182
4183 out_unlock:
4184 rtnl_unlock();
4185 }
4186
4187 static void rtl8169_tx_timeout(struct net_device *dev)
4188 {
4189 struct rtl8169_private *tp = netdev_priv(dev);
4190
4191 rtl8169_hw_reset(tp->mmio_addr);
4192
4193 /* Let's wait a bit while any (async) irq lands on */
4194 rtl8169_schedule_work(dev, rtl8169_reset_task);
4195 }
4196
4197 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4198 u32 opts1)
4199 {
4200 struct skb_shared_info *info = skb_shinfo(skb);
4201 unsigned int cur_frag, entry;
4202 struct TxDesc * uninitialized_var(txd);
4203
4204 entry = tp->cur_tx;
4205 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4206 skb_frag_t *frag = info->frags + cur_frag;
4207 dma_addr_t mapping;
4208 u32 status, len;
4209 void *addr;
4210
4211 entry = (entry + 1) % NUM_TX_DESC;
4212
4213 txd = tp->TxDescArray + entry;
4214 len = frag->size;
4215 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4216 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
4217
4218 /* anti gcc 2.95.3 bugware (sic) */
4219 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4220
4221 txd->opts1 = cpu_to_le32(status);
4222 txd->addr = cpu_to_le64(mapping);
4223
4224 tp->tx_skb[entry].len = len;
4225 }
4226
4227 if (cur_frag) {
4228 tp->tx_skb[entry].skb = skb;
4229 txd->opts1 |= cpu_to_le32(LastFrag);
4230 }
4231
4232 return cur_frag;
4233 }
4234
4235 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
4236 {
4237 if (dev->features & NETIF_F_TSO) {
4238 u32 mss = skb_shinfo(skb)->gso_size;
4239
4240 if (mss)
4241 return LargeSend | ((mss & MSSMask) << MSSShift);
4242 }
4243 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4244 const struct iphdr *ip = ip_hdr(skb);
4245
4246 if (ip->protocol == IPPROTO_TCP)
4247 return IPCS | TCPCS;
4248 else if (ip->protocol == IPPROTO_UDP)
4249 return IPCS | UDPCS;
4250 WARN_ON(1); /* we need a WARN() */
4251 }
4252 return 0;
4253 }
4254
4255 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4256 struct net_device *dev)
4257 {
4258 struct rtl8169_private *tp = netdev_priv(dev);
4259 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
4260 struct TxDesc *txd = tp->TxDescArray + entry;
4261 void __iomem *ioaddr = tp->mmio_addr;
4262 dma_addr_t mapping;
4263 u32 status, len;
4264 u32 opts1;
4265
4266 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4267 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4268 goto err_stop;
4269 }
4270
4271 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4272 goto err_stop;
4273
4274 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
4275
4276 frags = rtl8169_xmit_frags(tp, skb, opts1);
4277 if (frags) {
4278 len = skb_headlen(skb);
4279 opts1 |= FirstFrag;
4280 } else {
4281 len = skb->len;
4282 opts1 |= FirstFrag | LastFrag;
4283 tp->tx_skb[entry].skb = skb;
4284 }
4285
4286 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
4287
4288 tp->tx_skb[entry].len = len;
4289 txd->addr = cpu_to_le64(mapping);
4290 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4291
4292 wmb();
4293
4294 /* anti gcc 2.95.3 bugware (sic) */
4295 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4296 txd->opts1 = cpu_to_le32(status);
4297
4298 tp->cur_tx += frags + 1;
4299
4300 wmb();
4301
4302 RTL_W8(TxPoll, NPQ); /* set polling bit */
4303
4304 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4305 netif_stop_queue(dev);
4306 smp_rmb();
4307 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4308 netif_wake_queue(dev);
4309 }
4310
4311 return NETDEV_TX_OK;
4312
4313 err_stop:
4314 netif_stop_queue(dev);
4315 dev->stats.tx_dropped++;
4316 return NETDEV_TX_BUSY;
4317 }
4318
4319 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4320 {
4321 struct rtl8169_private *tp = netdev_priv(dev);
4322 struct pci_dev *pdev = tp->pci_dev;
4323 void __iomem *ioaddr = tp->mmio_addr;
4324 u16 pci_status, pci_cmd;
4325
4326 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4327 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4328
4329 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4330 pci_cmd, pci_status);
4331
4332 /*
4333 * The recovery sequence below admits a very elaborated explanation:
4334 * - it seems to work;
4335 * - I did not see what else could be done;
4336 * - it makes iop3xx happy.
4337 *
4338 * Feel free to adjust to your needs.
4339 */
4340 if (pdev->broken_parity_status)
4341 pci_cmd &= ~PCI_COMMAND_PARITY;
4342 else
4343 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4344
4345 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4346
4347 pci_write_config_word(pdev, PCI_STATUS,
4348 pci_status & (PCI_STATUS_DETECTED_PARITY |
4349 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4350 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4351
4352 /* The infamous DAC f*ckup only happens at boot time */
4353 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4354 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4355 tp->cp_cmd &= ~PCIDAC;
4356 RTL_W16(CPlusCmd, tp->cp_cmd);
4357 dev->features &= ~NETIF_F_HIGHDMA;
4358 }
4359
4360 rtl8169_hw_reset(ioaddr);
4361
4362 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4363 }
4364
4365 static void rtl8169_tx_interrupt(struct net_device *dev,
4366 struct rtl8169_private *tp,
4367 void __iomem *ioaddr)
4368 {
4369 unsigned int dirty_tx, tx_left;
4370
4371 dirty_tx = tp->dirty_tx;
4372 smp_rmb();
4373 tx_left = tp->cur_tx - dirty_tx;
4374
4375 while (tx_left > 0) {
4376 unsigned int entry = dirty_tx % NUM_TX_DESC;
4377 struct ring_info *tx_skb = tp->tx_skb + entry;
4378 u32 len = tx_skb->len;
4379 u32 status;
4380
4381 rmb();
4382 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4383 if (status & DescOwn)
4384 break;
4385
4386 dev->stats.tx_bytes += len;
4387 dev->stats.tx_packets++;
4388
4389 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
4390
4391 if (status & LastFrag) {
4392 dev_kfree_skb(tx_skb->skb);
4393 tx_skb->skb = NULL;
4394 }
4395 dirty_tx++;
4396 tx_left--;
4397 }
4398
4399 if (tp->dirty_tx != dirty_tx) {
4400 tp->dirty_tx = dirty_tx;
4401 smp_wmb();
4402 if (netif_queue_stopped(dev) &&
4403 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4404 netif_wake_queue(dev);
4405 }
4406 /*
4407 * 8168 hack: TxPoll requests are lost when the Tx packets are
4408 * too close. Let's kick an extra TxPoll request when a burst
4409 * of start_xmit activity is detected (if it is not detected,
4410 * it is slow enough). -- FR
4411 */
4412 smp_rmb();
4413 if (tp->cur_tx != dirty_tx)
4414 RTL_W8(TxPoll, NPQ);
4415 }
4416 }
4417
4418 static inline int rtl8169_fragmented_frame(u32 status)
4419 {
4420 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4421 }
4422
4423 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
4424 {
4425 u32 opts1 = le32_to_cpu(desc->opts1);
4426 u32 status = opts1 & RxProtoMask;
4427
4428 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4429 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
4430 ((status == RxProtoIP) && !(opts1 & IPFail)))
4431 skb->ip_summed = CHECKSUM_UNNECESSARY;
4432 else
4433 skb->ip_summed = CHECKSUM_NONE;
4434 }
4435
4436 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
4437 struct rtl8169_private *tp, int pkt_size,
4438 dma_addr_t addr)
4439 {
4440 struct sk_buff *skb;
4441 bool done = false;
4442
4443 if (pkt_size >= rx_copybreak)
4444 goto out;
4445
4446 skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
4447 if (!skb)
4448 goto out;
4449
4450 pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
4451 PCI_DMA_FROMDEVICE);
4452 skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
4453 *sk_buff = skb;
4454 done = true;
4455 out:
4456 return done;
4457 }
4458
4459 /*
4460 * Warning : rtl8169_rx_interrupt() might be called :
4461 * 1) from NAPI (softirq) context
4462 * (polling = 1 : we should call netif_receive_skb())
4463 * 2) from process context (rtl8169_reset_task())
4464 * (polling = 0 : we must call netif_rx() instead)
4465 */
4466 static int rtl8169_rx_interrupt(struct net_device *dev,
4467 struct rtl8169_private *tp,
4468 void __iomem *ioaddr, u32 budget)
4469 {
4470 unsigned int cur_rx, rx_left;
4471 unsigned int delta, count;
4472 int polling = (budget != ~(u32)0) ? 1 : 0;
4473
4474 cur_rx = tp->cur_rx;
4475 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
4476 rx_left = min(rx_left, budget);
4477
4478 for (; rx_left > 0; rx_left--, cur_rx++) {
4479 unsigned int entry = cur_rx % NUM_RX_DESC;
4480 struct RxDesc *desc = tp->RxDescArray + entry;
4481 u32 status;
4482
4483 rmb();
4484 status = le32_to_cpu(desc->opts1);
4485
4486 if (status & DescOwn)
4487 break;
4488 if (unlikely(status & RxRES)) {
4489 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
4490 status);
4491 dev->stats.rx_errors++;
4492 if (status & (RxRWT | RxRUNT))
4493 dev->stats.rx_length_errors++;
4494 if (status & RxCRC)
4495 dev->stats.rx_crc_errors++;
4496 if (status & RxFOVF) {
4497 rtl8169_schedule_work(dev, rtl8169_reset_task);
4498 dev->stats.rx_fifo_errors++;
4499 }
4500 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4501 } else {
4502 struct sk_buff *skb = tp->Rx_skbuff[entry];
4503 dma_addr_t addr = le64_to_cpu(desc->addr);
4504 int pkt_size = (status & 0x00001FFF) - 4;
4505 struct pci_dev *pdev = tp->pci_dev;
4506
4507 /*
4508 * The driver does not support incoming fragmented
4509 * frames. They are seen as a symptom of over-mtu
4510 * sized frames.
4511 */
4512 if (unlikely(rtl8169_fragmented_frame(status))) {
4513 dev->stats.rx_dropped++;
4514 dev->stats.rx_length_errors++;
4515 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4516 continue;
4517 }
4518
4519 rtl8169_rx_csum(skb, desc);
4520
4521 if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
4522 pci_dma_sync_single_for_device(pdev, addr,
4523 pkt_size, PCI_DMA_FROMDEVICE);
4524 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
4525 } else {
4526 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
4527 PCI_DMA_FROMDEVICE);
4528 tp->Rx_skbuff[entry] = NULL;
4529 }
4530
4531 skb_put(skb, pkt_size);
4532 skb->protocol = eth_type_trans(skb, dev);
4533
4534 if (rtl8169_rx_vlan_skb(tp, desc, skb, polling) < 0) {
4535 if (likely(polling))
4536 netif_receive_skb(skb);
4537 else
4538 netif_rx(skb);
4539 }
4540
4541 dev->stats.rx_bytes += pkt_size;
4542 dev->stats.rx_packets++;
4543 }
4544
4545 /* Work around for AMD plateform. */
4546 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
4547 (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
4548 desc->opts2 = 0;
4549 cur_rx++;
4550 }
4551 }
4552
4553 count = cur_rx - tp->cur_rx;
4554 tp->cur_rx = cur_rx;
4555
4556 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
4557 if (!delta && count)
4558 netif_info(tp, intr, dev, "no Rx buffer allocated\n");
4559 tp->dirty_rx += delta;
4560
4561 /*
4562 * FIXME: until there is periodic timer to try and refill the ring,
4563 * a temporary shortage may definitely kill the Rx process.
4564 * - disable the asic to try and avoid an overflow and kick it again
4565 * after refill ?
4566 * - how do others driver handle this condition (Uh oh...).
4567 */
4568 if (tp->dirty_rx + NUM_RX_DESC == tp->cur_rx)
4569 netif_emerg(tp, intr, dev, "Rx buffers exhausted\n");
4570
4571 return count;
4572 }
4573
4574 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
4575 {
4576 struct net_device *dev = dev_instance;
4577 struct rtl8169_private *tp = netdev_priv(dev);
4578 void __iomem *ioaddr = tp->mmio_addr;
4579 int handled = 0;
4580 int status;
4581
4582 /* loop handling interrupts until we have no new ones or
4583 * we hit a invalid/hotplug case.
4584 */
4585 status = RTL_R16(IntrStatus);
4586 while (status && status != 0xffff) {
4587 handled = 1;
4588
4589 /* Handle all of the error cases first. These will reset
4590 * the chip, so just exit the loop.
4591 */
4592 if (unlikely(!netif_running(dev))) {
4593 rtl8169_asic_down(ioaddr);
4594 break;
4595 }
4596
4597 /* Work around for rx fifo overflow */
4598 if (unlikely(status & RxFIFOOver) &&
4599 (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4600 netif_stop_queue(dev);
4601 rtl8169_tx_timeout(dev);
4602 break;
4603 }
4604
4605 if (unlikely(status & SYSErr)) {
4606 rtl8169_pcierr_interrupt(dev);
4607 break;
4608 }
4609
4610 if (status & LinkChg)
4611 rtl8169_check_link_status(dev, tp, ioaddr);
4612
4613 /* We need to see the lastest version of tp->intr_mask to
4614 * avoid ignoring an MSI interrupt and having to wait for
4615 * another event which may never come.
4616 */
4617 smp_rmb();
4618 if (status & tp->intr_mask & tp->napi_event) {
4619 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
4620 tp->intr_mask = ~tp->napi_event;
4621
4622 if (likely(napi_schedule_prep(&tp->napi)))
4623 __napi_schedule(&tp->napi);
4624 else
4625 netif_info(tp, intr, dev,
4626 "interrupt %04x in poll\n", status);
4627 }
4628
4629 /* We only get a new MSI interrupt when all active irq
4630 * sources on the chip have been acknowledged. So, ack
4631 * everything we've seen and check if new sources have become
4632 * active to avoid blocking all interrupts from the chip.
4633 */
4634 RTL_W16(IntrStatus,
4635 (status & RxFIFOOver) ? (status | RxOverflow) : status);
4636 status = RTL_R16(IntrStatus);
4637 }
4638
4639 return IRQ_RETVAL(handled);
4640 }
4641
4642 static int rtl8169_poll(struct napi_struct *napi, int budget)
4643 {
4644 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4645 struct net_device *dev = tp->dev;
4646 void __iomem *ioaddr = tp->mmio_addr;
4647 int work_done;
4648
4649 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
4650 rtl8169_tx_interrupt(dev, tp, ioaddr);
4651
4652 if (work_done < budget) {
4653 napi_complete(napi);
4654
4655 /* We need for force the visibility of tp->intr_mask
4656 * for other CPUs, as we can loose an MSI interrupt
4657 * and potentially wait for a retransmit timeout if we don't.
4658 * The posted write to IntrMask is safe, as it will
4659 * eventually make it to the chip and we won't loose anything
4660 * until it does.
4661 */
4662 tp->intr_mask = 0xffff;
4663 wmb();
4664 RTL_W16(IntrMask, tp->intr_event);
4665 }
4666
4667 return work_done;
4668 }
4669
4670 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
4671 {
4672 struct rtl8169_private *tp = netdev_priv(dev);
4673
4674 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
4675 return;
4676
4677 dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
4678 RTL_W32(RxMissed, 0);
4679 }
4680
4681 static void rtl8169_down(struct net_device *dev)
4682 {
4683 struct rtl8169_private *tp = netdev_priv(dev);
4684 void __iomem *ioaddr = tp->mmio_addr;
4685 unsigned int intrmask;
4686
4687 rtl8169_delete_timer(dev);
4688
4689 netif_stop_queue(dev);
4690
4691 napi_disable(&tp->napi);
4692
4693 core_down:
4694 spin_lock_irq(&tp->lock);
4695
4696 rtl8169_asic_down(ioaddr);
4697
4698 rtl8169_rx_missed(dev, ioaddr);
4699
4700 spin_unlock_irq(&tp->lock);
4701
4702 synchronize_irq(dev->irq);
4703
4704 /* Give a racing hard_start_xmit a few cycles to complete. */
4705 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
4706
4707 /*
4708 * And now for the 50k$ question: are IRQ disabled or not ?
4709 *
4710 * Two paths lead here:
4711 * 1) dev->close
4712 * -> netif_running() is available to sync the current code and the
4713 * IRQ handler. See rtl8169_interrupt for details.
4714 * 2) dev->change_mtu
4715 * -> rtl8169_poll can not be issued again and re-enable the
4716 * interruptions. Let's simply issue the IRQ down sequence again.
4717 *
4718 * No loop if hotpluged or major error (0xffff).
4719 */
4720 intrmask = RTL_R16(IntrMask);
4721 if (intrmask && (intrmask != 0xffff))
4722 goto core_down;
4723
4724 rtl8169_tx_clear(tp);
4725
4726 rtl8169_rx_clear(tp);
4727 }
4728
4729 static int rtl8169_close(struct net_device *dev)
4730 {
4731 struct rtl8169_private *tp = netdev_priv(dev);
4732 struct pci_dev *pdev = tp->pci_dev;
4733
4734 /* update counters before going down */
4735 rtl8169_update_counters(dev);
4736
4737 rtl8169_down(dev);
4738
4739 free_irq(dev->irq, dev);
4740
4741 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
4742 tp->RxPhyAddr);
4743 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
4744 tp->TxPhyAddr);
4745 tp->TxDescArray = NULL;
4746 tp->RxDescArray = NULL;
4747
4748 return 0;
4749 }
4750
4751 static void rtl_set_rx_mode(struct net_device *dev)
4752 {
4753 struct rtl8169_private *tp = netdev_priv(dev);
4754 void __iomem *ioaddr = tp->mmio_addr;
4755 unsigned long flags;
4756 u32 mc_filter[2]; /* Multicast hash filter */
4757 int rx_mode;
4758 u32 tmp = 0;
4759
4760 if (dev->flags & IFF_PROMISC) {
4761 /* Unconditionally log net taps. */
4762 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4763 rx_mode =
4764 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4765 AcceptAllPhys;
4766 mc_filter[1] = mc_filter[0] = 0xffffffff;
4767 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4768 (dev->flags & IFF_ALLMULTI)) {
4769 /* Too many to filter perfectly -- accept all multicasts. */
4770 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4771 mc_filter[1] = mc_filter[0] = 0xffffffff;
4772 } else {
4773 struct dev_mc_list *mclist;
4774
4775 rx_mode = AcceptBroadcast | AcceptMyPhys;
4776 mc_filter[1] = mc_filter[0] = 0;
4777 netdev_for_each_mc_addr(mclist, dev) {
4778 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
4779 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4780 rx_mode |= AcceptMulticast;
4781 }
4782 }
4783
4784 spin_lock_irqsave(&tp->lock, flags);
4785
4786 tmp = rtl8169_rx_config | rx_mode |
4787 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
4788
4789 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4790 u32 data = mc_filter[0];
4791
4792 mc_filter[0] = swab32(mc_filter[1]);
4793 mc_filter[1] = swab32(data);
4794 }
4795
4796 RTL_W32(MAR0 + 4, mc_filter[1]);
4797 RTL_W32(MAR0 + 0, mc_filter[0]);
4798
4799 RTL_W32(RxConfig, tmp);
4800
4801 spin_unlock_irqrestore(&tp->lock, flags);
4802 }
4803
4804 /**
4805 * rtl8169_get_stats - Get rtl8169 read/write statistics
4806 * @dev: The Ethernet Device to get statistics for
4807 *
4808 * Get TX/RX statistics for rtl8169
4809 */
4810 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
4811 {
4812 struct rtl8169_private *tp = netdev_priv(dev);
4813 void __iomem *ioaddr = tp->mmio_addr;
4814 unsigned long flags;
4815
4816 if (netif_running(dev)) {
4817 spin_lock_irqsave(&tp->lock, flags);
4818 rtl8169_rx_missed(dev, ioaddr);
4819 spin_unlock_irqrestore(&tp->lock, flags);
4820 }
4821
4822 return &dev->stats;
4823 }
4824
4825 static void rtl8169_net_suspend(struct net_device *dev)
4826 {
4827 if (!netif_running(dev))
4828 return;
4829
4830 netif_device_detach(dev);
4831 netif_stop_queue(dev);
4832 }
4833
4834 #ifdef CONFIG_PM
4835
4836 static int rtl8169_suspend(struct device *device)
4837 {
4838 struct pci_dev *pdev = to_pci_dev(device);
4839 struct net_device *dev = pci_get_drvdata(pdev);
4840
4841 rtl8169_net_suspend(dev);
4842
4843 return 0;
4844 }
4845
4846 static int rtl8169_resume(struct device *device)
4847 {
4848 struct pci_dev *pdev = to_pci_dev(device);
4849 struct net_device *dev = pci_get_drvdata(pdev);
4850
4851 if (!netif_running(dev))
4852 goto out;
4853
4854 netif_device_attach(dev);
4855
4856 rtl8169_schedule_work(dev, rtl8169_reset_task);
4857 out:
4858 return 0;
4859 }
4860
4861 static const struct dev_pm_ops rtl8169_pm_ops = {
4862 .suspend = rtl8169_suspend,
4863 .resume = rtl8169_resume,
4864 .freeze = rtl8169_suspend,
4865 .thaw = rtl8169_resume,
4866 .poweroff = rtl8169_suspend,
4867 .restore = rtl8169_resume,
4868 };
4869
4870 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
4871
4872 #else /* !CONFIG_PM */
4873
4874 #define RTL8169_PM_OPS NULL
4875
4876 #endif /* !CONFIG_PM */
4877
4878 static void rtl_shutdown(struct pci_dev *pdev)
4879 {
4880 struct net_device *dev = pci_get_drvdata(pdev);
4881 struct rtl8169_private *tp = netdev_priv(dev);
4882 void __iomem *ioaddr = tp->mmio_addr;
4883
4884 rtl8169_net_suspend(dev);
4885
4886 /* restore original MAC address */
4887 rtl_rar_set(tp, dev->perm_addr);
4888
4889 spin_lock_irq(&tp->lock);
4890
4891 rtl8169_asic_down(ioaddr);
4892
4893 spin_unlock_irq(&tp->lock);
4894
4895 if (system_state == SYSTEM_POWER_OFF) {
4896 /* WoL fails with some 8168 when the receiver is disabled. */
4897 if (tp->features & RTL_FEATURE_WOL) {
4898 pci_clear_master(pdev);
4899
4900 RTL_W8(ChipCmd, CmdRxEnb);
4901 /* PCI commit */
4902 RTL_R8(ChipCmd);
4903 }
4904
4905 pci_wake_from_d3(pdev, true);
4906 pci_set_power_state(pdev, PCI_D3hot);
4907 }
4908 }
4909
4910 static struct pci_driver rtl8169_pci_driver = {
4911 .name = MODULENAME,
4912 .id_table = rtl8169_pci_tbl,
4913 .probe = rtl8169_init_one,
4914 .remove = __devexit_p(rtl8169_remove_one),
4915 .shutdown = rtl_shutdown,
4916 .driver.pm = RTL8169_PM_OPS,
4917 };
4918
4919 static int __init rtl8169_init_module(void)
4920 {
4921 return pci_register_driver(&rtl8169_pci_driver);
4922 }
4923
4924 static void __exit rtl8169_cleanup_module(void)
4925 {
4926 pci_unregister_driver(&rtl8169_pci_driver);
4927 }
4928
4929 module_init(rtl8169_init_module);
4930 module_exit(rtl8169_cleanup_module);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree