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drm/i915: Remove the random SyncFlush during initialisation
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_dma.c
blob315326d5dc2224f863fa70e4a0ee300581f40b49
1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
2 */
3 /*
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "drm_crtc_helper.h"
32 #include "drm_fb_helper.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "i915_trace.h"
37 #include <linux/pci.h>
38 #include <linux/vgaarb.h>
39 #include <linux/acpi.h>
40 #include <linux/pnp.h>
41 #include <linux/vga_switcheroo.h>
42 #include <linux/slab.h>
43 #include <acpi/video.h>
44
45 extern int intel_max_stolen; /* from AGP driver */
46
47 /**
48 * Sets up the hardware status page for devices that need a physical address
49 * in the register.
50 */
51 static int i915_init_phys_hws(struct drm_device *dev)
52 {
53 drm_i915_private_t *dev_priv = dev->dev_private;
54 /* Program Hardware Status Page */
55 dev_priv->status_page_dmah =
56 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
57
58 if (!dev_priv->status_page_dmah) {
59 DRM_ERROR("Can not allocate hardware status page\n");
60 return -ENOMEM;
61 }
62 dev_priv->render_ring.status_page.page_addr
63 = dev_priv->status_page_dmah->vaddr;
64 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
65
66 memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
67
68 if (IS_I965G(dev))
69 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
70 0xf0;
71
72 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
73 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
74 return 0;
75 }
76
77 /**
78 * Frees the hardware status page, whether it's a physical address or a virtual
79 * address set up by the X Server.
80 */
81 static void i915_free_hws(struct drm_device *dev)
82 {
83 drm_i915_private_t *dev_priv = dev->dev_private;
84 if (dev_priv->status_page_dmah) {
85 drm_pci_free(dev, dev_priv->status_page_dmah);
86 dev_priv->status_page_dmah = NULL;
87 }
88
89 if (dev_priv->render_ring.status_page.gfx_addr) {
90 dev_priv->render_ring.status_page.gfx_addr = 0;
91 drm_core_ioremapfree(&dev_priv->hws_map, dev);
92 }
93
94 /* Need to rewrite hardware status page */
95 I915_WRITE(HWS_PGA, 0x1ffff000);
96 }
97
98 void i915_kernel_lost_context(struct drm_device * dev)
99 {
100 drm_i915_private_t *dev_priv = dev->dev_private;
101 struct drm_i915_master_private *master_priv;
102 struct intel_ring_buffer *ring = &dev_priv->render_ring;
103
104 /*
105 * We should never lose context on the ring with modesetting
106 * as we don't expose it to userspace
107 */
108 if (drm_core_check_feature(dev, DRIVER_MODESET))
109 return;
110
111 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
112 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
113 ring->space = ring->head - (ring->tail + 8);
114 if (ring->space < 0)
115 ring->space += ring->size;
116
117 if (!dev->primary->master)
118 return;
119
120 master_priv = dev->primary->master->driver_priv;
121 if (ring->head == ring->tail && master_priv->sarea_priv)
122 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
123 }
124
125 static int i915_dma_cleanup(struct drm_device * dev)
126 {
127 drm_i915_private_t *dev_priv = dev->dev_private;
128 /* Make sure interrupts are disabled here because the uninstall ioctl
129 * may not have been called from userspace and after dev_private
130 * is freed, it's too late.
131 */
132 if (dev->irq_enabled)
133 drm_irq_uninstall(dev);
134
135 mutex_lock(&dev->struct_mutex);
136 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
137 if (HAS_BSD(dev))
138 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
139 mutex_unlock(&dev->struct_mutex);
140
141 /* Clear the HWS virtual address at teardown */
142 if (I915_NEED_GFX_HWS(dev))
143 i915_free_hws(dev);
144
145 return 0;
146 }
147
148 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
149 {
150 drm_i915_private_t *dev_priv = dev->dev_private;
151 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
152
153 master_priv->sarea = drm_getsarea(dev);
154 if (master_priv->sarea) {
155 master_priv->sarea_priv = (drm_i915_sarea_t *)
156 ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
157 } else {
158 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
159 }
160
161 if (init->ring_size != 0) {
162 if (dev_priv->render_ring.gem_object != NULL) {
163 i915_dma_cleanup(dev);
164 DRM_ERROR("Client tried to initialize ringbuffer in "
165 "GEM mode\n");
166 return -EINVAL;
167 }
168
169 dev_priv->render_ring.size = init->ring_size;
170
171 dev_priv->render_ring.map.offset = init->ring_start;
172 dev_priv->render_ring.map.size = init->ring_size;
173 dev_priv->render_ring.map.type = 0;
174 dev_priv->render_ring.map.flags = 0;
175 dev_priv->render_ring.map.mtrr = 0;
176
177 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
178
179 if (dev_priv->render_ring.map.handle == NULL) {
180 i915_dma_cleanup(dev);
181 DRM_ERROR("can not ioremap virtual address for"
182 " ring buffer\n");
183 return -ENOMEM;
184 }
185 }
186
187 dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
188
189 dev_priv->cpp = init->cpp;
190 dev_priv->back_offset = init->back_offset;
191 dev_priv->front_offset = init->front_offset;
192 dev_priv->current_page = 0;
193 if (master_priv->sarea_priv)
194 master_priv->sarea_priv->pf_current_page = 0;
195
196 /* Allow hardware batchbuffers unless told otherwise.
197 */
198 dev_priv->allow_batchbuffer = 1;
199
200 return 0;
201 }
202
203 static int i915_dma_resume(struct drm_device * dev)
204 {
205 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
206
207 struct intel_ring_buffer *ring;
208 DRM_DEBUG_DRIVER("%s\n", __func__);
209
210 ring = &dev_priv->render_ring;
211
212 if (ring->map.handle == NULL) {
213 DRM_ERROR("can not ioremap virtual address for"
214 " ring buffer\n");
215 return -ENOMEM;
216 }
217
218 /* Program Hardware Status Page */
219 if (!ring->status_page.page_addr) {
220 DRM_ERROR("Can not find hardware status page\n");
221 return -EINVAL;
222 }
223 DRM_DEBUG_DRIVER("hw status page @ %p\n",
224 ring->status_page.page_addr);
225 if (ring->status_page.gfx_addr != 0)
226 ring->setup_status_page(dev, ring);
227 else
228 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
229
230 DRM_DEBUG_DRIVER("Enabled hardware status page\n");
231
232 return 0;
233 }
234
235 static int i915_dma_init(struct drm_device *dev, void *data,
236 struct drm_file *file_priv)
237 {
238 drm_i915_init_t *init = data;
239 int retcode = 0;
240
241 switch (init->func) {
242 case I915_INIT_DMA:
243 retcode = i915_initialize(dev, init);
244 break;
245 case I915_CLEANUP_DMA:
246 retcode = i915_dma_cleanup(dev);
247 break;
248 case I915_RESUME_DMA:
249 retcode = i915_dma_resume(dev);
250 break;
251 default:
252 retcode = -EINVAL;
253 break;
254 }
255
256 return retcode;
257 }
258
259 /* Implement basically the same security restrictions as hardware does
260 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
261 *
262 * Most of the calculations below involve calculating the size of a
263 * particular instruction. It's important to get the size right as
264 * that tells us where the next instruction to check is. Any illegal
265 * instruction detected will be given a size of zero, which is a
266 * signal to abort the rest of the buffer.
267 */
268 static int do_validate_cmd(int cmd)
269 {
270 switch (((cmd >> 29) & 0x7)) {
271 case 0x0:
272 switch ((cmd >> 23) & 0x3f) {
273 case 0x0:
274 return 1; /* MI_NOOP */
275 case 0x4:
276 return 1; /* MI_FLUSH */
277 default:
278 return 0; /* disallow everything else */
279 }
280 break;
281 case 0x1:
282 return 0; /* reserved */
283 case 0x2:
284 return (cmd & 0xff) + 2; /* 2d commands */
285 case 0x3:
286 if (((cmd >> 24) & 0x1f) <= 0x18)
287 return 1;
288
289 switch ((cmd >> 24) & 0x1f) {
290 case 0x1c:
291 return 1;
292 case 0x1d:
293 switch ((cmd >> 16) & 0xff) {
294 case 0x3:
295 return (cmd & 0x1f) + 2;
296 case 0x4:
297 return (cmd & 0xf) + 2;
298 default:
299 return (cmd & 0xffff) + 2;
300 }
301 case 0x1e:
302 if (cmd & (1 << 23))
303 return (cmd & 0xffff) + 1;
304 else
305 return 1;
306 case 0x1f:
307 if ((cmd & (1 << 23)) == 0) /* inline vertices */
308 return (cmd & 0x1ffff) + 2;
309 else if (cmd & (1 << 17)) /* indirect random */
310 if ((cmd & 0xffff) == 0)
311 return 0; /* unknown length, too hard */
312 else
313 return (((cmd & 0xffff) + 1) / 2) + 1;
314 else
315 return 2; /* indirect sequential */
316 default:
317 return 0;
318 }
319 default:
320 return 0;
321 }
322
323 return 0;
324 }
325
326 static int validate_cmd(int cmd)
327 {
328 int ret = do_validate_cmd(cmd);
329
330 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
331
332 return ret;
333 }
334
335 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
336 {
337 drm_i915_private_t *dev_priv = dev->dev_private;
338 int i;
339
340 if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
341 return -EINVAL;
342
343 BEGIN_LP_RING((dwords+1)&~1);
344
345 for (i = 0; i < dwords;) {
346 int cmd, sz;
347
348 cmd = buffer[i];
349
350 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
351 return -EINVAL;
352
353 OUT_RING(cmd);
354
355 while (++i, --sz) {
356 OUT_RING(buffer[i]);
357 }
358 }
359
360 if (dwords & 1)
361 OUT_RING(0);
362
363 ADVANCE_LP_RING();
364
365 return 0;
366 }
367
368 int
369 i915_emit_box(struct drm_device *dev,
370 struct drm_clip_rect *boxes,
371 int i, int DR1, int DR4)
372 {
373 struct drm_clip_rect box = boxes[i];
374
375 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
376 DRM_ERROR("Bad box %d,%d..%d,%d\n",
377 box.x1, box.y1, box.x2, box.y2);
378 return -EINVAL;
379 }
380
381 if (IS_I965G(dev)) {
382 BEGIN_LP_RING(4);
383 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
384 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
385 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
386 OUT_RING(DR4);
387 ADVANCE_LP_RING();
388 } else {
389 BEGIN_LP_RING(6);
390 OUT_RING(GFX_OP_DRAWRECT_INFO);
391 OUT_RING(DR1);
392 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
393 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
394 OUT_RING(DR4);
395 OUT_RING(0);
396 ADVANCE_LP_RING();
397 }
398
399 return 0;
400 }
401
402 /* XXX: Emitting the counter should really be moved to part of the IRQ
403 * emit. For now, do it in both places:
404 */
405
406 static void i915_emit_breadcrumb(struct drm_device *dev)
407 {
408 drm_i915_private_t *dev_priv = dev->dev_private;
409 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
410
411 dev_priv->counter++;
412 if (dev_priv->counter > 0x7FFFFFFFUL)
413 dev_priv->counter = 0;
414 if (master_priv->sarea_priv)
415 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
416
417 BEGIN_LP_RING(4);
418 OUT_RING(MI_STORE_DWORD_INDEX);
419 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
420 OUT_RING(dev_priv->counter);
421 OUT_RING(0);
422 ADVANCE_LP_RING();
423 }
424
425 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
426 drm_i915_cmdbuffer_t *cmd,
427 struct drm_clip_rect *cliprects,
428 void *cmdbuf)
429 {
430 int nbox = cmd->num_cliprects;
431 int i = 0, count, ret;
432
433 if (cmd->sz & 0x3) {
434 DRM_ERROR("alignment");
435 return -EINVAL;
436 }
437
438 i915_kernel_lost_context(dev);
439
440 count = nbox ? nbox : 1;
441
442 for (i = 0; i < count; i++) {
443 if (i < nbox) {
444 ret = i915_emit_box(dev, cliprects, i,
445 cmd->DR1, cmd->DR4);
446 if (ret)
447 return ret;
448 }
449
450 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
451 if (ret)
452 return ret;
453 }
454
455 i915_emit_breadcrumb(dev);
456 return 0;
457 }
458
459 static int i915_dispatch_batchbuffer(struct drm_device * dev,
460 drm_i915_batchbuffer_t * batch,
461 struct drm_clip_rect *cliprects)
462 {
463 int nbox = batch->num_cliprects;
464 int i = 0, count;
465
466 if ((batch->start | batch->used) & 0x7) {
467 DRM_ERROR("alignment");
468 return -EINVAL;
469 }
470
471 i915_kernel_lost_context(dev);
472
473 count = nbox ? nbox : 1;
474
475 for (i = 0; i < count; i++) {
476 if (i < nbox) {
477 int ret = i915_emit_box(dev, cliprects, i,
478 batch->DR1, batch->DR4);
479 if (ret)
480 return ret;
481 }
482
483 if (!IS_I830(dev) && !IS_845G(dev)) {
484 BEGIN_LP_RING(2);
485 if (IS_I965G(dev)) {
486 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
487 OUT_RING(batch->start);
488 } else {
489 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
490 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
491 }
492 ADVANCE_LP_RING();
493 } else {
494 BEGIN_LP_RING(4);
495 OUT_RING(MI_BATCH_BUFFER);
496 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
497 OUT_RING(batch->start + batch->used - 4);
498 OUT_RING(0);
499 ADVANCE_LP_RING();
500 }
501 }
502
503
504 if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
505 BEGIN_LP_RING(2);
506 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
507 OUT_RING(MI_NOOP);
508 ADVANCE_LP_RING();
509 }
510 i915_emit_breadcrumb(dev);
511
512 return 0;
513 }
514
515 static int i915_dispatch_flip(struct drm_device * dev)
516 {
517 drm_i915_private_t *dev_priv = dev->dev_private;
518 struct drm_i915_master_private *master_priv =
519 dev->primary->master->driver_priv;
520
521 if (!master_priv->sarea_priv)
522 return -EINVAL;
523
524 DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
525 __func__,
526 dev_priv->current_page,
527 master_priv->sarea_priv->pf_current_page);
528
529 i915_kernel_lost_context(dev);
530
531 BEGIN_LP_RING(2);
532 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
533 OUT_RING(0);
534 ADVANCE_LP_RING();
535
536 BEGIN_LP_RING(6);
537 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
538 OUT_RING(0);
539 if (dev_priv->current_page == 0) {
540 OUT_RING(dev_priv->back_offset);
541 dev_priv->current_page = 1;
542 } else {
543 OUT_RING(dev_priv->front_offset);
544 dev_priv->current_page = 0;
545 }
546 OUT_RING(0);
547 ADVANCE_LP_RING();
548
549 BEGIN_LP_RING(2);
550 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
551 OUT_RING(0);
552 ADVANCE_LP_RING();
553
554 master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
555
556 BEGIN_LP_RING(4);
557 OUT_RING(MI_STORE_DWORD_INDEX);
558 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
559 OUT_RING(dev_priv->counter);
560 OUT_RING(0);
561 ADVANCE_LP_RING();
562
563 master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
564 return 0;
565 }
566
567 static int i915_quiescent(struct drm_device * dev)
568 {
569 drm_i915_private_t *dev_priv = dev->dev_private;
570
571 i915_kernel_lost_context(dev);
572 return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
573 dev_priv->render_ring.size - 8);
574 }
575
576 static int i915_flush_ioctl(struct drm_device *dev, void *data,
577 struct drm_file *file_priv)
578 {
579 int ret;
580
581 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
582
583 mutex_lock(&dev->struct_mutex);
584 ret = i915_quiescent(dev);
585 mutex_unlock(&dev->struct_mutex);
586
587 return ret;
588 }
589
590 static int i915_batchbuffer(struct drm_device *dev, void *data,
591 struct drm_file *file_priv)
592 {
593 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
594 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
595 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
596 master_priv->sarea_priv;
597 drm_i915_batchbuffer_t *batch = data;
598 int ret;
599 struct drm_clip_rect *cliprects = NULL;
600
601 if (!dev_priv->allow_batchbuffer) {
602 DRM_ERROR("Batchbuffer ioctl disabled\n");
603 return -EINVAL;
604 }
605
606 DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
607 batch->start, batch->used, batch->num_cliprects);
608
609 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
610
611 if (batch->num_cliprects < 0)
612 return -EINVAL;
613
614 if (batch->num_cliprects) {
615 cliprects = kcalloc(batch->num_cliprects,
616 sizeof(struct drm_clip_rect),
617 GFP_KERNEL);
618 if (cliprects == NULL)
619 return -ENOMEM;
620
621 ret = copy_from_user(cliprects, batch->cliprects,
622 batch->num_cliprects *
623 sizeof(struct drm_clip_rect));
624 if (ret != 0) {
625 ret = -EFAULT;
626 goto fail_free;
627 }
628 }
629
630 mutex_lock(&dev->struct_mutex);
631 ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
632 mutex_unlock(&dev->struct_mutex);
633
634 if (sarea_priv)
635 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
636
637 fail_free:
638 kfree(cliprects);
639
640 return ret;
641 }
642
643 static int i915_cmdbuffer(struct drm_device *dev, void *data,
644 struct drm_file *file_priv)
645 {
646 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
647 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
648 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
649 master_priv->sarea_priv;
650 drm_i915_cmdbuffer_t *cmdbuf = data;
651 struct drm_clip_rect *cliprects = NULL;
652 void *batch_data;
653 int ret;
654
655 DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
656 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
657
658 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
659
660 if (cmdbuf->num_cliprects < 0)
661 return -EINVAL;
662
663 batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
664 if (batch_data == NULL)
665 return -ENOMEM;
666
667 ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
668 if (ret != 0) {
669 ret = -EFAULT;
670 goto fail_batch_free;
671 }
672
673 if (cmdbuf->num_cliprects) {
674 cliprects = kcalloc(cmdbuf->num_cliprects,
675 sizeof(struct drm_clip_rect), GFP_KERNEL);
676 if (cliprects == NULL) {
677 ret = -ENOMEM;
678 goto fail_batch_free;
679 }
680
681 ret = copy_from_user(cliprects, cmdbuf->cliprects,
682 cmdbuf->num_cliprects *
683 sizeof(struct drm_clip_rect));
684 if (ret != 0) {
685 ret = -EFAULT;
686 goto fail_clip_free;
687 }
688 }
689
690 mutex_lock(&dev->struct_mutex);
691 ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
692 mutex_unlock(&dev->struct_mutex);
693 if (ret) {
694 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
695 goto fail_clip_free;
696 }
697
698 if (sarea_priv)
699 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
700
701 fail_clip_free:
702 kfree(cliprects);
703 fail_batch_free:
704 kfree(batch_data);
705
706 return ret;
707 }
708
709 static int i915_flip_bufs(struct drm_device *dev, void *data,
710 struct drm_file *file_priv)
711 {
712 int ret;
713
714 DRM_DEBUG_DRIVER("%s\n", __func__);
715
716 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
717
718 mutex_lock(&dev->struct_mutex);
719 ret = i915_dispatch_flip(dev);
720 mutex_unlock(&dev->struct_mutex);
721
722 return ret;
723 }
724
725 static int i915_getparam(struct drm_device *dev, void *data,
726 struct drm_file *file_priv)
727 {
728 drm_i915_private_t *dev_priv = dev->dev_private;
729 drm_i915_getparam_t *param = data;
730 int value;
731
732 if (!dev_priv) {
733 DRM_ERROR("called with no initialization\n");
734 return -EINVAL;
735 }
736
737 switch (param->param) {
738 case I915_PARAM_IRQ_ACTIVE:
739 value = dev->pdev->irq ? 1 : 0;
740 break;
741 case I915_PARAM_ALLOW_BATCHBUFFER:
742 value = dev_priv->allow_batchbuffer ? 1 : 0;
743 break;
744 case I915_PARAM_LAST_DISPATCH:
745 value = READ_BREADCRUMB(dev_priv);
746 break;
747 case I915_PARAM_CHIPSET_ID:
748 value = dev->pci_device;
749 break;
750 case I915_PARAM_HAS_GEM:
751 value = dev_priv->has_gem;
752 break;
753 case I915_PARAM_NUM_FENCES_AVAIL:
754 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
755 break;
756 case I915_PARAM_HAS_OVERLAY:
757 value = dev_priv->overlay ? 1 : 0;
758 break;
759 case I915_PARAM_HAS_PAGEFLIPPING:
760 value = 1;
761 break;
762 case I915_PARAM_HAS_EXECBUF2:
763 /* depends on GEM */
764 value = dev_priv->has_gem;
765 break;
766 case I915_PARAM_HAS_BSD:
767 value = HAS_BSD(dev);
768 break;
769 default:
770 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
771 param->param);
772 return -EINVAL;
773 }
774
775 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
776 DRM_ERROR("DRM_COPY_TO_USER failed\n");
777 return -EFAULT;
778 }
779
780 return 0;
781 }
782
783 static int i915_setparam(struct drm_device *dev, void *data,
784 struct drm_file *file_priv)
785 {
786 drm_i915_private_t *dev_priv = dev->dev_private;
787 drm_i915_setparam_t *param = data;
788
789 if (!dev_priv) {
790 DRM_ERROR("called with no initialization\n");
791 return -EINVAL;
792 }
793
794 switch (param->param) {
795 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
796 break;
797 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
798 dev_priv->tex_lru_log_granularity = param->value;
799 break;
800 case I915_SETPARAM_ALLOW_BATCHBUFFER:
801 dev_priv->allow_batchbuffer = param->value;
802 break;
803 case I915_SETPARAM_NUM_USED_FENCES:
804 if (param->value > dev_priv->num_fence_regs ||
805 param->value < 0)
806 return -EINVAL;
807 /* Userspace can use first N regs */
808 dev_priv->fence_reg_start = param->value;
809 break;
810 default:
811 DRM_DEBUG_DRIVER("unknown parameter %d\n",
812 param->param);
813 return -EINVAL;
814 }
815
816 return 0;
817 }
818
819 static int i915_set_status_page(struct drm_device *dev, void *data,
820 struct drm_file *file_priv)
821 {
822 drm_i915_private_t *dev_priv = dev->dev_private;
823 drm_i915_hws_addr_t *hws = data;
824 struct intel_ring_buffer *ring = &dev_priv->render_ring;
825
826 if (!I915_NEED_GFX_HWS(dev))
827 return -EINVAL;
828
829 if (!dev_priv) {
830 DRM_ERROR("called with no initialization\n");
831 return -EINVAL;
832 }
833
834 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
835 WARN(1, "tried to set status page when mode setting active\n");
836 return 0;
837 }
838
839 DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
840
841 ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
842
843 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
844 dev_priv->hws_map.size = 4*1024;
845 dev_priv->hws_map.type = 0;
846 dev_priv->hws_map.flags = 0;
847 dev_priv->hws_map.mtrr = 0;
848
849 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
850 if (dev_priv->hws_map.handle == NULL) {
851 i915_dma_cleanup(dev);
852 ring->status_page.gfx_addr = 0;
853 DRM_ERROR("can not ioremap virtual address for"
854 " G33 hw status page\n");
855 return -ENOMEM;
856 }
857 ring->status_page.page_addr = dev_priv->hws_map.handle;
858 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
859 I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
860
861 DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
862 ring->status_page.gfx_addr);
863 DRM_DEBUG_DRIVER("load hws at %p\n",
864 ring->status_page.page_addr);
865 return 0;
866 }
867
868 static int i915_get_bridge_dev(struct drm_device *dev)
869 {
870 struct drm_i915_private *dev_priv = dev->dev_private;
871
872 dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
873 if (!dev_priv->bridge_dev) {
874 DRM_ERROR("bridge device not found\n");
875 return -1;
876 }
877 return 0;
878 }
879
880 #define MCHBAR_I915 0x44
881 #define MCHBAR_I965 0x48
882 #define MCHBAR_SIZE (4*4096)
883
884 #define DEVEN_REG 0x54
885 #define DEVEN_MCHBAR_EN (1 << 28)
886
887 /* Allocate space for the MCH regs if needed, return nonzero on error */
888 static int
889 intel_alloc_mchbar_resource(struct drm_device *dev)
890 {
891 drm_i915_private_t *dev_priv = dev->dev_private;
892 int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
893 u32 temp_lo, temp_hi = 0;
894 u64 mchbar_addr;
895 int ret;
896
897 if (IS_I965G(dev))
898 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
899 pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
900 mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
901
902 /* If ACPI doesn't have it, assume we need to allocate it ourselves */
903 #ifdef CONFIG_PNP
904 if (mchbar_addr &&
905 pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
906 return 0;
907 #endif
908
909 /* Get some space for it */
910 dev_priv->mch_res.name = "i915 MCHBAR";
911 dev_priv->mch_res.flags = IORESOURCE_MEM;
912 ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
913 &dev_priv->mch_res,
914 MCHBAR_SIZE, MCHBAR_SIZE,
915 PCIBIOS_MIN_MEM,
916 0, pcibios_align_resource,
917 dev_priv->bridge_dev);
918 if (ret) {
919 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
920 dev_priv->mch_res.start = 0;
921 return ret;
922 }
923
924 if (IS_I965G(dev))
925 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
926 upper_32_bits(dev_priv->mch_res.start));
927
928 pci_write_config_dword(dev_priv->bridge_dev, reg,
929 lower_32_bits(dev_priv->mch_res.start));
930 return 0;
931 }
932
933 /* Setup MCHBAR if possible, return true if we should disable it again */
934 static void
935 intel_setup_mchbar(struct drm_device *dev)
936 {
937 drm_i915_private_t *dev_priv = dev->dev_private;
938 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
939 u32 temp;
940 bool enabled;
941
942 dev_priv->mchbar_need_disable = false;
943
944 if (IS_I915G(dev) || IS_I915GM(dev)) {
945 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
946 enabled = !!(temp & DEVEN_MCHBAR_EN);
947 } else {
948 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
949 enabled = temp & 1;
950 }
951
952 /* If it's already enabled, don't have to do anything */
953 if (enabled)
954 return;
955
956 if (intel_alloc_mchbar_resource(dev))
957 return;
958
959 dev_priv->mchbar_need_disable = true;
960
961 /* Space is allocated or reserved, so enable it. */
962 if (IS_I915G(dev) || IS_I915GM(dev)) {
963 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
964 temp | DEVEN_MCHBAR_EN);
965 } else {
966 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
967 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
968 }
969 }
970
971 static void
972 intel_teardown_mchbar(struct drm_device *dev)
973 {
974 drm_i915_private_t *dev_priv = dev->dev_private;
975 int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
976 u32 temp;
977
978 if (dev_priv->mchbar_need_disable) {
979 if (IS_I915G(dev) || IS_I915GM(dev)) {
980 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
981 temp &= ~DEVEN_MCHBAR_EN;
982 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
983 } else {
984 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
985 temp &= ~1;
986 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
987 }
988 }
989
990 if (dev_priv->mch_res.start)
991 release_resource(&dev_priv->mch_res);
992 }
993
994 /**
995 * i915_probe_agp - get AGP bootup configuration
996 * @pdev: PCI device
997 * @aperture_size: returns AGP aperture configured size
998 * @preallocated_size: returns size of BIOS preallocated AGP space
999 *
1000 * Since Intel integrated graphics are UMA, the BIOS has to set aside
1001 * some RAM for the framebuffer at early boot. This code figures out
1002 * how much was set aside so we can use it for our own purposes.
1003 */
1004 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
1005 uint32_t *preallocated_size,
1006 uint32_t *start)
1007 {
1008 struct drm_i915_private *dev_priv = dev->dev_private;
1009 u16 tmp = 0;
1010 unsigned long overhead;
1011 unsigned long stolen;
1012
1013 /* Get the fb aperture size and "stolen" memory amount. */
1014 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1015
1016 *aperture_size = 1024 * 1024;
1017 *preallocated_size = 1024 * 1024;
1018
1019 switch (dev->pdev->device) {
1020 case PCI_DEVICE_ID_INTEL_82830_CGC:
1021 case PCI_DEVICE_ID_INTEL_82845G_IG:
1022 case PCI_DEVICE_ID_INTEL_82855GM_IG:
1023 case PCI_DEVICE_ID_INTEL_82865_IG:
1024 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1025 *aperture_size *= 64;
1026 else
1027 *aperture_size *= 128;
1028 break;
1029 default:
1030 /* 9xx supports large sizes, just look at the length */
1031 *aperture_size = pci_resource_len(dev->pdev, 2);
1032 break;
1033 }
1034
1035 /*
1036 * Some of the preallocated space is taken by the GTT
1037 * and popup. GTT is 1K per MB of aperture size, and popup is 4K.
1038 */
1039 if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1040 overhead = 4096;
1041 else
1042 overhead = (*aperture_size / 1024) + 4096;
1043
1044 if (IS_GEN6(dev)) {
1045 /* SNB has memory control reg at 0x50.w */
1046 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1047
1048 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1049 case INTEL_855_GMCH_GMS_DISABLED:
1050 DRM_ERROR("video memory is disabled\n");
1051 return -1;
1052 case SNB_GMCH_GMS_STOLEN_32M:
1053 stolen = 32 * 1024 * 1024;
1054 break;
1055 case SNB_GMCH_GMS_STOLEN_64M:
1056 stolen = 64 * 1024 * 1024;
1057 break;
1058 case SNB_GMCH_GMS_STOLEN_96M:
1059 stolen = 96 * 1024 * 1024;
1060 break;
1061 case SNB_GMCH_GMS_STOLEN_128M:
1062 stolen = 128 * 1024 * 1024;
1063 break;
1064 case SNB_GMCH_GMS_STOLEN_160M:
1065 stolen = 160 * 1024 * 1024;
1066 break;
1067 case SNB_GMCH_GMS_STOLEN_192M:
1068 stolen = 192 * 1024 * 1024;
1069 break;
1070 case SNB_GMCH_GMS_STOLEN_224M:
1071 stolen = 224 * 1024 * 1024;
1072 break;
1073 case SNB_GMCH_GMS_STOLEN_256M:
1074 stolen = 256 * 1024 * 1024;
1075 break;
1076 case SNB_GMCH_GMS_STOLEN_288M:
1077 stolen = 288 * 1024 * 1024;
1078 break;
1079 case SNB_GMCH_GMS_STOLEN_320M:
1080 stolen = 320 * 1024 * 1024;
1081 break;
1082 case SNB_GMCH_GMS_STOLEN_352M:
1083 stolen = 352 * 1024 * 1024;
1084 break;
1085 case SNB_GMCH_GMS_STOLEN_384M:
1086 stolen = 384 * 1024 * 1024;
1087 break;
1088 case SNB_GMCH_GMS_STOLEN_416M:
1089 stolen = 416 * 1024 * 1024;
1090 break;
1091 case SNB_GMCH_GMS_STOLEN_448M:
1092 stolen = 448 * 1024 * 1024;
1093 break;
1094 case SNB_GMCH_GMS_STOLEN_480M:
1095 stolen = 480 * 1024 * 1024;
1096 break;
1097 case SNB_GMCH_GMS_STOLEN_512M:
1098 stolen = 512 * 1024 * 1024;
1099 break;
1100 default:
1101 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1102 tmp & SNB_GMCH_GMS_STOLEN_MASK);
1103 return -1;
1104 }
1105 } else {
1106 switch (tmp & INTEL_GMCH_GMS_MASK) {
1107 case INTEL_855_GMCH_GMS_DISABLED:
1108 DRM_ERROR("video memory is disabled\n");
1109 return -1;
1110 case INTEL_855_GMCH_GMS_STOLEN_1M:
1111 stolen = 1 * 1024 * 1024;
1112 break;
1113 case INTEL_855_GMCH_GMS_STOLEN_4M:
1114 stolen = 4 * 1024 * 1024;
1115 break;
1116 case INTEL_855_GMCH_GMS_STOLEN_8M:
1117 stolen = 8 * 1024 * 1024;
1118 break;
1119 case INTEL_855_GMCH_GMS_STOLEN_16M:
1120 stolen = 16 * 1024 * 1024;
1121 break;
1122 case INTEL_855_GMCH_GMS_STOLEN_32M:
1123 stolen = 32 * 1024 * 1024;
1124 break;
1125 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1126 stolen = 48 * 1024 * 1024;
1127 break;
1128 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1129 stolen = 64 * 1024 * 1024;
1130 break;
1131 case INTEL_GMCH_GMS_STOLEN_128M:
1132 stolen = 128 * 1024 * 1024;
1133 break;
1134 case INTEL_GMCH_GMS_STOLEN_256M:
1135 stolen = 256 * 1024 * 1024;
1136 break;
1137 case INTEL_GMCH_GMS_STOLEN_96M:
1138 stolen = 96 * 1024 * 1024;
1139 break;
1140 case INTEL_GMCH_GMS_STOLEN_160M:
1141 stolen = 160 * 1024 * 1024;
1142 break;
1143 case INTEL_GMCH_GMS_STOLEN_224M:
1144 stolen = 224 * 1024 * 1024;
1145 break;
1146 case INTEL_GMCH_GMS_STOLEN_352M:
1147 stolen = 352 * 1024 * 1024;
1148 break;
1149 default:
1150 DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1151 tmp & INTEL_GMCH_GMS_MASK);
1152 return -1;
1153 }
1154 }
1155
1156 *preallocated_size = stolen - overhead;
1157 *start = overhead;
1158
1159 return 0;
1160 }
1161
1162 #define PTE_ADDRESS_MASK 0xfffff000
1163 #define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
1164 #define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
1165 #define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
1166 #define PTE_MAPPING_TYPE_CACHED (3 << 1)
1167 #define PTE_MAPPING_TYPE_MASK (3 << 1)
1168 #define PTE_VALID (1 << 0)
1169
1170 /**
1171 * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1172 * @dev: drm device
1173 * @gtt_addr: address to translate
1174 *
1175 * Some chip functions require allocations from stolen space but need the
1176 * physical address of the memory in question. We use this routine
1177 * to get a physical address suitable for register programming from a given
1178 * GTT address.
1179 */
1180 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1181 unsigned long gtt_addr)
1182 {
1183 unsigned long *gtt;
1184 unsigned long entry, phys;
1185 int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1186 int gtt_offset, gtt_size;
1187
1188 if (IS_I965G(dev)) {
1189 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1190 gtt_offset = 2*1024*1024;
1191 gtt_size = 2*1024*1024;
1192 } else {
1193 gtt_offset = 512*1024;
1194 gtt_size = 512*1024;
1195 }
1196 } else {
1197 gtt_bar = 3;
1198 gtt_offset = 0;
1199 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1200 }
1201
1202 gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1203 gtt_size);
1204 if (!gtt) {
1205 DRM_ERROR("ioremap of GTT failed\n");
1206 return 0;
1207 }
1208
1209 entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1210
1211 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1212
1213 /* Mask out these reserved bits on this hardware. */
1214 if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1215 IS_I945G(dev) || IS_I945GM(dev)) {
1216 entry &= ~PTE_ADDRESS_MASK_HIGH;
1217 }
1218
1219 /* If it's not a mapping type we know, then bail. */
1220 if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1221 (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1222 iounmap(gtt);
1223 return 0;
1224 }
1225
1226 if (!(entry & PTE_VALID)) {
1227 DRM_ERROR("bad GTT entry in stolen space\n");
1228 iounmap(gtt);
1229 return 0;
1230 }
1231
1232 iounmap(gtt);
1233
1234 phys =(entry & PTE_ADDRESS_MASK) |
1235 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1236
1237 DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1238
1239 return phys;
1240 }
1241
1242 static void i915_warn_stolen(struct drm_device *dev)
1243 {
1244 DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1245 DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1246 }
1247
1248 static void i915_setup_compression(struct drm_device *dev, int size)
1249 {
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1252 unsigned long cfb_base;
1253 unsigned long ll_base = 0;
1254
1255 /* Leave 1M for line length buffer & misc. */
1256 compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1257 if (!compressed_fb) {
1258 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1259 i915_warn_stolen(dev);
1260 return;
1261 }
1262
1263 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1264 if (!compressed_fb) {
1265 i915_warn_stolen(dev);
1266 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1267 return;
1268 }
1269
1270 cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1271 if (!cfb_base) {
1272 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1273 drm_mm_put_block(compressed_fb);
1274 }
1275
1276 if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1277 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1278 4096, 0);
1279 if (!compressed_llb) {
1280 i915_warn_stolen(dev);
1281 return;
1282 }
1283
1284 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1285 if (!compressed_llb) {
1286 i915_warn_stolen(dev);
1287 return;
1288 }
1289
1290 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1291 if (!ll_base) {
1292 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1293 drm_mm_put_block(compressed_fb);
1294 drm_mm_put_block(compressed_llb);
1295 }
1296 }
1297
1298 dev_priv->cfb_size = size;
1299
1300 intel_disable_fbc(dev);
1301 dev_priv->compressed_fb = compressed_fb;
1302 if (IS_IRONLAKE_M(dev))
1303 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1304 else if (IS_GM45(dev)) {
1305 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1306 } else {
1307 I915_WRITE(FBC_CFB_BASE, cfb_base);
1308 I915_WRITE(FBC_LL_BASE, ll_base);
1309 dev_priv->compressed_llb = compressed_llb;
1310 }
1311
1312 DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1313 ll_base, size >> 20);
1314 }
1315
1316 static void i915_cleanup_compression(struct drm_device *dev)
1317 {
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319
1320 drm_mm_put_block(dev_priv->compressed_fb);
1321 if (dev_priv->compressed_llb)
1322 drm_mm_put_block(dev_priv->compressed_llb);
1323 }
1324
1325 /* true = enable decode, false = disable decoder */
1326 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1327 {
1328 struct drm_device *dev = cookie;
1329
1330 intel_modeset_vga_set_state(dev, state);
1331 if (state)
1332 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1333 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1334 else
1335 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1336 }
1337
1338 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1339 {
1340 struct drm_device *dev = pci_get_drvdata(pdev);
1341 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1342 if (state == VGA_SWITCHEROO_ON) {
1343 printk(KERN_INFO "i915: switched on\n");
1344 /* i915 resume handler doesn't set to D0 */
1345 pci_set_power_state(dev->pdev, PCI_D0);
1346 i915_resume(dev);
1347 drm_kms_helper_poll_enable(dev);
1348 } else {
1349 printk(KERN_ERR "i915: switched off\n");
1350 drm_kms_helper_poll_disable(dev);
1351 i915_suspend(dev, pmm);
1352 }
1353 }
1354
1355 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1356 {
1357 struct drm_device *dev = pci_get_drvdata(pdev);
1358 bool can_switch;
1359
1360 spin_lock(&dev->count_lock);
1361 can_switch = (dev->open_count == 0);
1362 spin_unlock(&dev->count_lock);
1363 return can_switch;
1364 }
1365
1366 static int i915_load_modeset_init(struct drm_device *dev,
1367 unsigned long prealloc_start,
1368 unsigned long prealloc_size,
1369 unsigned long agp_size)
1370 {
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int fb_bar = IS_I9XX(dev) ? 2 : 0;
1373 int ret = 0;
1374
1375 dev->mode_config.fb_base = pci_resource_start(dev->pdev, fb_bar) &
1376 0xff000000;
1377
1378 /* Basic memrange allocator for stolen space (aka vram) */
1379 drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1380 DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1381
1382 /* We're off and running w/KMS */
1383 dev_priv->mm.suspended = 0;
1384
1385 /* Let GEM Manage from end of prealloc space to end of aperture.
1386 *
1387 * However, leave one page at the end still bound to the scratch page.
1388 * There are a number of places where the hardware apparently
1389 * prefetches past the end of the object, and we've seen multiple
1390 * hangs with the GPU head pointer stuck in a batchbuffer bound
1391 * at the last page of the aperture. One page should be enough to
1392 * keep any prefetching inside of the aperture.
1393 */
1394 i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1395
1396 mutex_lock(&dev->struct_mutex);
1397 ret = i915_gem_init_ringbuffer(dev);
1398 mutex_unlock(&dev->struct_mutex);
1399 if (ret)
1400 goto out;
1401
1402 /* Try to set up FBC with a reasonable compressed buffer size */
1403 if (I915_HAS_FBC(dev) && i915_powersave) {
1404 int cfb_size;
1405
1406 /* Try to get an 8M buffer... */
1407 if (prealloc_size > (9*1024*1024))
1408 cfb_size = 8*1024*1024;
1409 else /* fall back to 7/8 of the stolen space */
1410 cfb_size = prealloc_size * 7 / 8;
1411 i915_setup_compression(dev, cfb_size);
1412 }
1413
1414 /* Allow hardware batchbuffers unless told otherwise.
1415 */
1416 dev_priv->allow_batchbuffer = 1;
1417
1418 ret = intel_init_bios(dev);
1419 if (ret)
1420 DRM_INFO("failed to find VBIOS tables\n");
1421
1422 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1423 ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1424 if (ret)
1425 goto cleanup_ringbuffer;
1426
1427 ret = vga_switcheroo_register_client(dev->pdev,
1428 i915_switcheroo_set_state,
1429 i915_switcheroo_can_switch);
1430 if (ret)
1431 goto cleanup_vga_client;
1432
1433 /* IIR "flip pending" bit means done if this bit is set */
1434 if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1435 dev_priv->flip_pending_is_done = true;
1436
1437 intel_modeset_init(dev);
1438
1439 ret = drm_irq_install(dev);
1440 if (ret)
1441 goto cleanup_vga_switcheroo;
1442
1443 /* Always safe in the mode setting case. */
1444 /* FIXME: do pre/post-mode set stuff in core KMS code */
1445 dev->vblank_disable_allowed = 1;
1446
1447 ret = intel_fbdev_init(dev);
1448 if (ret)
1449 goto cleanup_irq;
1450
1451 drm_kms_helper_poll_init(dev);
1452 return 0;
1453
1454 cleanup_irq:
1455 drm_irq_uninstall(dev);
1456 cleanup_vga_switcheroo:
1457 vga_switcheroo_unregister_client(dev->pdev);
1458 cleanup_vga_client:
1459 vga_client_register(dev->pdev, NULL, NULL, NULL);
1460 cleanup_ringbuffer:
1461 mutex_lock(&dev->struct_mutex);
1462 i915_gem_cleanup_ringbuffer(dev);
1463 mutex_unlock(&dev->struct_mutex);
1464 out:
1465 return ret;
1466 }
1467
1468 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1469 {
1470 struct drm_i915_master_private *master_priv;
1471
1472 master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1473 if (!master_priv)
1474 return -ENOMEM;
1475
1476 master->driver_priv = master_priv;
1477 return 0;
1478 }
1479
1480 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1481 {
1482 struct drm_i915_master_private *master_priv = master->driver_priv;
1483
1484 if (!master_priv)
1485 return;
1486
1487 kfree(master_priv);
1488
1489 master->driver_priv = NULL;
1490 }
1491
1492 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1493 {
1494 drm_i915_private_t *dev_priv = dev->dev_private;
1495 u32 tmp;
1496
1497 tmp = I915_READ(CLKCFG);
1498
1499 switch (tmp & CLKCFG_FSB_MASK) {
1500 case CLKCFG_FSB_533:
1501 dev_priv->fsb_freq = 533; /* 133*4 */
1502 break;
1503 case CLKCFG_FSB_800:
1504 dev_priv->fsb_freq = 800; /* 200*4 */
1505 break;
1506 case CLKCFG_FSB_667:
1507 dev_priv->fsb_freq = 667; /* 167*4 */
1508 break;
1509 case CLKCFG_FSB_400:
1510 dev_priv->fsb_freq = 400; /* 100*4 */
1511 break;
1512 }
1513
1514 switch (tmp & CLKCFG_MEM_MASK) {
1515 case CLKCFG_MEM_533:
1516 dev_priv->mem_freq = 533;
1517 break;
1518 case CLKCFG_MEM_667:
1519 dev_priv->mem_freq = 667;
1520 break;
1521 case CLKCFG_MEM_800:
1522 dev_priv->mem_freq = 800;
1523 break;
1524 }
1525
1526 /* detect pineview DDR3 setting */
1527 tmp = I915_READ(CSHRDDR3CTL);
1528 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1529 }
1530
1531 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1532 {
1533 drm_i915_private_t *dev_priv = dev->dev_private;
1534 u16 ddrpll, csipll;
1535
1536 ddrpll = I915_READ16(DDRMPLL1);
1537 csipll = I915_READ16(CSIPLL0);
1538
1539 switch (ddrpll & 0xff) {
1540 case 0xc:
1541 dev_priv->mem_freq = 800;
1542 break;
1543 case 0x10:
1544 dev_priv->mem_freq = 1066;
1545 break;
1546 case 0x14:
1547 dev_priv->mem_freq = 1333;
1548 break;
1549 case 0x18:
1550 dev_priv->mem_freq = 1600;
1551 break;
1552 default:
1553 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1554 ddrpll & 0xff);
1555 dev_priv->mem_freq = 0;
1556 break;
1557 }
1558
1559 dev_priv->r_t = dev_priv->mem_freq;
1560
1561 switch (csipll & 0x3ff) {
1562 case 0x00c:
1563 dev_priv->fsb_freq = 3200;
1564 break;
1565 case 0x00e:
1566 dev_priv->fsb_freq = 3733;
1567 break;
1568 case 0x010:
1569 dev_priv->fsb_freq = 4266;
1570 break;
1571 case 0x012:
1572 dev_priv->fsb_freq = 4800;
1573 break;
1574 case 0x014:
1575 dev_priv->fsb_freq = 5333;
1576 break;
1577 case 0x016:
1578 dev_priv->fsb_freq = 5866;
1579 break;
1580 case 0x018:
1581 dev_priv->fsb_freq = 6400;
1582 break;
1583 default:
1584 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1585 csipll & 0x3ff);
1586 dev_priv->fsb_freq = 0;
1587 break;
1588 }
1589
1590 if (dev_priv->fsb_freq == 3200) {
1591 dev_priv->c_m = 0;
1592 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1593 dev_priv->c_m = 1;
1594 } else {
1595 dev_priv->c_m = 2;
1596 }
1597 }
1598
1599 struct v_table {
1600 u8 vid;
1601 unsigned long vd; /* in .1 mil */
1602 unsigned long vm; /* in .1 mil */
1603 u8 pvid;
1604 };
1605
1606 static struct v_table v_table[] = {
1607 { 0, 16125, 15000, 0x7f, },
1608 { 1, 16000, 14875, 0x7e, },
1609 { 2, 15875, 14750, 0x7d, },
1610 { 3, 15750, 14625, 0x7c, },
1611 { 4, 15625, 14500, 0x7b, },
1612 { 5, 15500, 14375, 0x7a, },
1613 { 6, 15375, 14250, 0x79, },
1614 { 7, 15250, 14125, 0x78, },
1615 { 8, 15125, 14000, 0x77, },
1616 { 9, 15000, 13875, 0x76, },
1617 { 10, 14875, 13750, 0x75, },
1618 { 11, 14750, 13625, 0x74, },
1619 { 12, 14625, 13500, 0x73, },
1620 { 13, 14500, 13375, 0x72, },
1621 { 14, 14375, 13250, 0x71, },
1622 { 15, 14250, 13125, 0x70, },
1623 { 16, 14125, 13000, 0x6f, },
1624 { 17, 14000, 12875, 0x6e, },
1625 { 18, 13875, 12750, 0x6d, },
1626 { 19, 13750, 12625, 0x6c, },
1627 { 20, 13625, 12500, 0x6b, },
1628 { 21, 13500, 12375, 0x6a, },
1629 { 22, 13375, 12250, 0x69, },
1630 { 23, 13250, 12125, 0x68, },
1631 { 24, 13125, 12000, 0x67, },
1632 { 25, 13000, 11875, 0x66, },
1633 { 26, 12875, 11750, 0x65, },
1634 { 27, 12750, 11625, 0x64, },
1635 { 28, 12625, 11500, 0x63, },
1636 { 29, 12500, 11375, 0x62, },
1637 { 30, 12375, 11250, 0x61, },
1638 { 31, 12250, 11125, 0x60, },
1639 { 32, 12125, 11000, 0x5f, },
1640 { 33, 12000, 10875, 0x5e, },
1641 { 34, 11875, 10750, 0x5d, },
1642 { 35, 11750, 10625, 0x5c, },
1643 { 36, 11625, 10500, 0x5b, },
1644 { 37, 11500, 10375, 0x5a, },
1645 { 38, 11375, 10250, 0x59, },
1646 { 39, 11250, 10125, 0x58, },
1647 { 40, 11125, 10000, 0x57, },
1648 { 41, 11000, 9875, 0x56, },
1649 { 42, 10875, 9750, 0x55, },
1650 { 43, 10750, 9625, 0x54, },
1651 { 44, 10625, 9500, 0x53, },
1652 { 45, 10500, 9375, 0x52, },
1653 { 46, 10375, 9250, 0x51, },
1654 { 47, 10250, 9125, 0x50, },
1655 { 48, 10125, 9000, 0x4f, },
1656 { 49, 10000, 8875, 0x4e, },
1657 { 50, 9875, 8750, 0x4d, },
1658 { 51, 9750, 8625, 0x4c, },
1659 { 52, 9625, 8500, 0x4b, },
1660 { 53, 9500, 8375, 0x4a, },
1661 { 54, 9375, 8250, 0x49, },
1662 { 55, 9250, 8125, 0x48, },
1663 { 56, 9125, 8000, 0x47, },
1664 { 57, 9000, 7875, 0x46, },
1665 { 58, 8875, 7750, 0x45, },
1666 { 59, 8750, 7625, 0x44, },
1667 { 60, 8625, 7500, 0x43, },
1668 { 61, 8500, 7375, 0x42, },
1669 { 62, 8375, 7250, 0x41, },
1670 { 63, 8250, 7125, 0x40, },
1671 { 64, 8125, 7000, 0x3f, },
1672 { 65, 8000, 6875, 0x3e, },
1673 { 66, 7875, 6750, 0x3d, },
1674 { 67, 7750, 6625, 0x3c, },
1675 { 68, 7625, 6500, 0x3b, },
1676 { 69, 7500, 6375, 0x3a, },
1677 { 70, 7375, 6250, 0x39, },
1678 { 71, 7250, 6125, 0x38, },
1679 { 72, 7125, 6000, 0x37, },
1680 { 73, 7000, 5875, 0x36, },
1681 { 74, 6875, 5750, 0x35, },
1682 { 75, 6750, 5625, 0x34, },
1683 { 76, 6625, 5500, 0x33, },
1684 { 77, 6500, 5375, 0x32, },
1685 { 78, 6375, 5250, 0x31, },
1686 { 79, 6250, 5125, 0x30, },
1687 { 80, 6125, 5000, 0x2f, },
1688 { 81, 6000, 4875, 0x2e, },
1689 { 82, 5875, 4750, 0x2d, },
1690 { 83, 5750, 4625, 0x2c, },
1691 { 84, 5625, 4500, 0x2b, },
1692 { 85, 5500, 4375, 0x2a, },
1693 { 86, 5375, 4250, 0x29, },
1694 { 87, 5250, 4125, 0x28, },
1695 { 88, 5125, 4000, 0x27, },
1696 { 89, 5000, 3875, 0x26, },
1697 { 90, 4875, 3750, 0x25, },
1698 { 91, 4750, 3625, 0x24, },
1699 { 92, 4625, 3500, 0x23, },
1700 { 93, 4500, 3375, 0x22, },
1701 { 94, 4375, 3250, 0x21, },
1702 { 95, 4250, 3125, 0x20, },
1703 { 96, 4125, 3000, 0x1f, },
1704 { 97, 4125, 3000, 0x1e, },
1705 { 98, 4125, 3000, 0x1d, },
1706 { 99, 4125, 3000, 0x1c, },
1707 { 100, 4125, 3000, 0x1b, },
1708 { 101, 4125, 3000, 0x1a, },
1709 { 102, 4125, 3000, 0x19, },
1710 { 103, 4125, 3000, 0x18, },
1711 { 104, 4125, 3000, 0x17, },
1712 { 105, 4125, 3000, 0x16, },
1713 { 106, 4125, 3000, 0x15, },
1714 { 107, 4125, 3000, 0x14, },
1715 { 108, 4125, 3000, 0x13, },
1716 { 109, 4125, 3000, 0x12, },
1717 { 110, 4125, 3000, 0x11, },
1718 { 111, 4125, 3000, 0x10, },
1719 { 112, 4125, 3000, 0x0f, },
1720 { 113, 4125, 3000, 0x0e, },
1721 { 114, 4125, 3000, 0x0d, },
1722 { 115, 4125, 3000, 0x0c, },
1723 { 116, 4125, 3000, 0x0b, },
1724 { 117, 4125, 3000, 0x0a, },
1725 { 118, 4125, 3000, 0x09, },
1726 { 119, 4125, 3000, 0x08, },
1727 { 120, 1125, 0, 0x07, },
1728 { 121, 1000, 0, 0x06, },
1729 { 122, 875, 0, 0x05, },
1730 { 123, 750, 0, 0x04, },
1731 { 124, 625, 0, 0x03, },
1732 { 125, 500, 0, 0x02, },
1733 { 126, 375, 0, 0x01, },
1734 { 127, 0, 0, 0x00, },
1735 };
1736
1737 struct cparams {
1738 int i;
1739 int t;
1740 int m;
1741 int c;
1742 };
1743
1744 static struct cparams cparams[] = {
1745 { 1, 1333, 301, 28664 },
1746 { 1, 1066, 294, 24460 },
1747 { 1, 800, 294, 25192 },
1748 { 0, 1333, 276, 27605 },
1749 { 0, 1066, 276, 27605 },
1750 { 0, 800, 231, 23784 },
1751 };
1752
1753 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1754 {
1755 u64 total_count, diff, ret;
1756 u32 count1, count2, count3, m = 0, c = 0;
1757 unsigned long now = jiffies_to_msecs(jiffies), diff1;
1758 int i;
1759
1760 diff1 = now - dev_priv->last_time1;
1761
1762 count1 = I915_READ(DMIEC);
1763 count2 = I915_READ(DDREC);
1764 count3 = I915_READ(CSIEC);
1765
1766 total_count = count1 + count2 + count3;
1767
1768 /* FIXME: handle per-counter overflow */
1769 if (total_count < dev_priv->last_count1) {
1770 diff = ~0UL - dev_priv->last_count1;
1771 diff += total_count;
1772 } else {
1773 diff = total_count - dev_priv->last_count1;
1774 }
1775
1776 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1777 if (cparams[i].i == dev_priv->c_m &&
1778 cparams[i].t == dev_priv->r_t) {
1779 m = cparams[i].m;
1780 c = cparams[i].c;
1781 break;
1782 }
1783 }
1784
1785 div_u64(diff, diff1);
1786 ret = ((m * diff) + c);
1787 div_u64(ret, 10);
1788
1789 dev_priv->last_count1 = total_count;
1790 dev_priv->last_time1 = now;
1791
1792 return ret;
1793 }
1794
1795 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1796 {
1797 unsigned long m, x, b;
1798 u32 tsfs;
1799
1800 tsfs = I915_READ(TSFS);
1801
1802 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1803 x = I915_READ8(TR1);
1804
1805 b = tsfs & TSFS_INTR_MASK;
1806
1807 return ((m * x) / 127) - b;
1808 }
1809
1810 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1811 {
1812 unsigned long val = 0;
1813 int i;
1814
1815 for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1816 if (v_table[i].pvid == pxvid) {
1817 if (IS_MOBILE(dev_priv->dev))
1818 val = v_table[i].vm;
1819 else
1820 val = v_table[i].vd;
1821 }
1822 }
1823
1824 return val;
1825 }
1826
1827 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1828 {
1829 struct timespec now, diff1;
1830 u64 diff;
1831 unsigned long diffms;
1832 u32 count;
1833
1834 getrawmonotonic(&now);
1835 diff1 = timespec_sub(now, dev_priv->last_time2);
1836
1837 /* Don't divide by 0 */
1838 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1839 if (!diffms)
1840 return;
1841
1842 count = I915_READ(GFXEC);
1843
1844 if (count < dev_priv->last_count2) {
1845 diff = ~0UL - dev_priv->last_count2;
1846 diff += count;
1847 } else {
1848 diff = count - dev_priv->last_count2;
1849 }
1850
1851 dev_priv->last_count2 = count;
1852 dev_priv->last_time2 = now;
1853
1854 /* More magic constants... */
1855 diff = diff * 1181;
1856 div_u64(diff, diffms * 10);
1857 dev_priv->gfx_power = diff;
1858 }
1859
1860 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1861 {
1862 unsigned long t, corr, state1, corr2, state2;
1863 u32 pxvid, ext_v;
1864
1865 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1866 pxvid = (pxvid >> 24) & 0x7f;
1867 ext_v = pvid_to_extvid(dev_priv, pxvid);
1868
1869 state1 = ext_v;
1870
1871 t = i915_mch_val(dev_priv);
1872
1873 /* Revel in the empirically derived constants */
1874
1875 /* Correction factor in 1/100000 units */
1876 if (t > 80)
1877 corr = ((t * 2349) + 135940);
1878 else if (t >= 50)
1879 corr = ((t * 964) + 29317);
1880 else /* < 50 */
1881 corr = ((t * 301) + 1004);
1882
1883 corr = corr * ((150142 * state1) / 10000 - 78642);
1884 corr /= 100000;
1885 corr2 = (corr * dev_priv->corr);
1886
1887 state2 = (corr2 * state1) / 10000;
1888 state2 /= 100; /* convert to mW */
1889
1890 i915_update_gfx_val(dev_priv);
1891
1892 return dev_priv->gfx_power + state2;
1893 }
1894
1895 /* Global for IPS driver to get at the current i915 device */
1896 static struct drm_i915_private *i915_mch_dev;
1897 /*
1898 * Lock protecting IPS related data structures
1899 * - i915_mch_dev
1900 * - dev_priv->max_delay
1901 * - dev_priv->min_delay
1902 * - dev_priv->fmax
1903 * - dev_priv->gpu_busy
1904 */
1905 DEFINE_SPINLOCK(mchdev_lock);
1906
1907 /**
1908 * i915_read_mch_val - return value for IPS use
1909 *
1910 * Calculate and return a value for the IPS driver to use when deciding whether
1911 * we have thermal and power headroom to increase CPU or GPU power budget.
1912 */
1913 unsigned long i915_read_mch_val(void)
1914 {
1915 struct drm_i915_private *dev_priv;
1916 unsigned long chipset_val, graphics_val, ret = 0;
1917
1918 spin_lock(&mchdev_lock);
1919 if (!i915_mch_dev)
1920 goto out_unlock;
1921 dev_priv = i915_mch_dev;
1922
1923 chipset_val = i915_chipset_val(dev_priv);
1924 graphics_val = i915_gfx_val(dev_priv);
1925
1926 ret = chipset_val + graphics_val;
1927
1928 out_unlock:
1929 spin_unlock(&mchdev_lock);
1930
1931 return ret;
1932 }
1933 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1934
1935 /**
1936 * i915_gpu_raise - raise GPU frequency limit
1937 *
1938 * Raise the limit; IPS indicates we have thermal headroom.
1939 */
1940 bool i915_gpu_raise(void)
1941 {
1942 struct drm_i915_private *dev_priv;
1943 bool ret = true;
1944
1945 spin_lock(&mchdev_lock);
1946 if (!i915_mch_dev) {
1947 ret = false;
1948 goto out_unlock;
1949 }
1950 dev_priv = i915_mch_dev;
1951
1952 if (dev_priv->max_delay > dev_priv->fmax)
1953 dev_priv->max_delay--;
1954
1955 out_unlock:
1956 spin_unlock(&mchdev_lock);
1957
1958 return ret;
1959 }
1960 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1961
1962 /**
1963 * i915_gpu_lower - lower GPU frequency limit
1964 *
1965 * IPS indicates we're close to a thermal limit, so throttle back the GPU
1966 * frequency maximum.
1967 */
1968 bool i915_gpu_lower(void)
1969 {
1970 struct drm_i915_private *dev_priv;
1971 bool ret = true;
1972
1973 spin_lock(&mchdev_lock);
1974 if (!i915_mch_dev) {
1975 ret = false;
1976 goto out_unlock;
1977 }
1978 dev_priv = i915_mch_dev;
1979
1980 if (dev_priv->max_delay < dev_priv->min_delay)
1981 dev_priv->max_delay++;
1982
1983 out_unlock:
1984 spin_unlock(&mchdev_lock);
1985
1986 return ret;
1987 }
1988 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1989
1990 /**
1991 * i915_gpu_busy - indicate GPU business to IPS
1992 *
1993 * Tell the IPS driver whether or not the GPU is busy.
1994 */
1995 bool i915_gpu_busy(void)
1996 {
1997 struct drm_i915_private *dev_priv;
1998 bool ret = false;
1999
2000 spin_lock(&mchdev_lock);
2001 if (!i915_mch_dev)
2002 goto out_unlock;
2003 dev_priv = i915_mch_dev;
2004
2005 ret = dev_priv->busy;
2006
2007 out_unlock:
2008 spin_unlock(&mchdev_lock);
2009
2010 return ret;
2011 }
2012 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2013
2014 /**
2015 * i915_gpu_turbo_disable - disable graphics turbo
2016 *
2017 * Disable graphics turbo by resetting the max frequency and setting the
2018 * current frequency to the default.
2019 */
2020 bool i915_gpu_turbo_disable(void)
2021 {
2022 struct drm_i915_private *dev_priv;
2023 bool ret = true;
2024
2025 spin_lock(&mchdev_lock);
2026 if (!i915_mch_dev) {
2027 ret = false;
2028 goto out_unlock;
2029 }
2030 dev_priv = i915_mch_dev;
2031
2032 dev_priv->max_delay = dev_priv->fstart;
2033
2034 if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2035 ret = false;
2036
2037 out_unlock:
2038 spin_unlock(&mchdev_lock);
2039
2040 return ret;
2041 }
2042 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2043
2044 /**
2045 * i915_driver_load - setup chip and create an initial config
2046 * @dev: DRM device
2047 * @flags: startup flags
2048 *
2049 * The driver load routine has to do several things:
2050 * - drive output discovery via intel_modeset_init()
2051 * - initialize the memory manager
2052 * - allocate initial config memory
2053 * - setup the DRM framebuffer with the allocated memory
2054 */
2055 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2056 {
2057 struct drm_i915_private *dev_priv;
2058 resource_size_t base, size;
2059 int ret = 0, mmio_bar;
2060 uint32_t agp_size, prealloc_size, prealloc_start;
2061 /* i915 has 4 more counters */
2062 dev->counters += 4;
2063 dev->types[6] = _DRM_STAT_IRQ;
2064 dev->types[7] = _DRM_STAT_PRIMARY;
2065 dev->types[8] = _DRM_STAT_SECONDARY;
2066 dev->types[9] = _DRM_STAT_DMA;
2067
2068 dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2069 if (dev_priv == NULL)
2070 return -ENOMEM;
2071
2072 dev->dev_private = (void *)dev_priv;
2073 dev_priv->dev = dev;
2074 dev_priv->info = (struct intel_device_info *) flags;
2075
2076 /* Add register map (needed for suspend/resume) */
2077 mmio_bar = IS_I9XX(dev) ? 0 : 1;
2078 base = pci_resource_start(dev->pdev, mmio_bar);
2079 size = pci_resource_len(dev->pdev, mmio_bar);
2080
2081 if (i915_get_bridge_dev(dev)) {
2082 ret = -EIO;
2083 goto free_priv;
2084 }
2085
2086 /* overlay on gen2 is broken and can't address above 1G */
2087 if (IS_GEN2(dev))
2088 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
2089
2090 dev_priv->regs = ioremap(base, size);
2091 if (!dev_priv->regs) {
2092 DRM_ERROR("failed to map registers\n");
2093 ret = -EIO;
2094 goto put_bridge;
2095 }
2096
2097 dev_priv->mm.gtt_mapping =
2098 io_mapping_create_wc(dev->agp->base,
2099 dev->agp->agp_info.aper_size * 1024*1024);
2100 if (dev_priv->mm.gtt_mapping == NULL) {
2101 ret = -EIO;
2102 goto out_rmmap;
2103 }
2104
2105 /* Set up a WC MTRR for non-PAT systems. This is more common than
2106 * one would think, because the kernel disables PAT on first
2107 * generation Core chips because WC PAT gets overridden by a UC
2108 * MTRR if present. Even if a UC MTRR isn't present.
2109 */
2110 dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2111 dev->agp->agp_info.aper_size *
2112 1024 * 1024,
2113 MTRR_TYPE_WRCOMB, 1);
2114 if (dev_priv->mm.gtt_mtrr < 0) {
2115 DRM_INFO("MTRR allocation failed. Graphics "
2116 "performance may suffer.\n");
2117 }
2118
2119 ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2120 if (ret)
2121 goto out_iomapfree;
2122
2123 if (prealloc_size > intel_max_stolen) {
2124 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2125 prealloc_size >> 20, intel_max_stolen >> 20);
2126 prealloc_size = intel_max_stolen;
2127 }
2128
2129 dev_priv->wq = create_singlethread_workqueue("i915");
2130 if (dev_priv->wq == NULL) {
2131 DRM_ERROR("Failed to create our workqueue.\n");
2132 ret = -ENOMEM;
2133 goto out_iomapfree;
2134 }
2135
2136 /* enable GEM by default */
2137 dev_priv->has_gem = 1;
2138
2139 if (prealloc_size > agp_size * 3 / 4) {
2140 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2141 "memory stolen.\n",
2142 prealloc_size / 1024, agp_size / 1024);
2143 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2144 "updating the BIOS to fix).\n");
2145 dev_priv->has_gem = 0;
2146 }
2147
2148 if (dev_priv->has_gem == 0 &&
2149 drm_core_check_feature(dev, DRIVER_MODESET)) {
2150 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2151 ret = -ENODEV;
2152 goto out_iomapfree;
2153 }
2154
2155 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2156 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2157 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2158 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2159 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2160 }
2161
2162 /* Try to make sure MCHBAR is enabled before poking at it */
2163 intel_setup_mchbar(dev);
2164 intel_opregion_setup(dev);
2165
2166 i915_gem_load(dev);
2167
2168 /* Init HWS */
2169 if (!I915_NEED_GFX_HWS(dev)) {
2170 ret = i915_init_phys_hws(dev);
2171 if (ret != 0)
2172 goto out_workqueue_free;
2173 }
2174
2175 if (IS_PINEVIEW(dev))
2176 i915_pineview_get_mem_freq(dev);
2177 else if (IS_IRONLAKE(dev))
2178 i915_ironlake_get_mem_freq(dev);
2179
2180 /* On the 945G/GM, the chipset reports the MSI capability on the
2181 * integrated graphics even though the support isn't actually there
2182 * according to the published specs. It doesn't appear to function
2183 * correctly in testing on 945G.
2184 * This may be a side effect of MSI having been made available for PEG
2185 * and the registers being closely associated.
2186 *
2187 * According to chipset errata, on the 965GM, MSI interrupts may
2188 * be lost or delayed, but we use them anyways to avoid
2189 * stuck interrupts on some machines.
2190 */
2191 if (!IS_I945G(dev) && !IS_I945GM(dev))
2192 pci_enable_msi(dev->pdev);
2193
2194 spin_lock_init(&dev_priv->user_irq_lock);
2195 spin_lock_init(&dev_priv->error_lock);
2196 dev_priv->trace_irq_seqno = 0;
2197
2198 ret = drm_vblank_init(dev, I915_NUM_PIPE);
2199
2200 if (ret) {
2201 (void) i915_driver_unload(dev);
2202 return ret;
2203 }
2204
2205 /* Start out suspended */
2206 dev_priv->mm.suspended = 1;
2207
2208 intel_detect_pch(dev);
2209
2210 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2211 ret = i915_load_modeset_init(dev, prealloc_start,
2212 prealloc_size, agp_size);
2213 if (ret < 0) {
2214 DRM_ERROR("failed to init modeset\n");
2215 goto out_workqueue_free;
2216 }
2217 }
2218
2219 /* Must be done after probing outputs */
2220 intel_opregion_init(dev);
2221 acpi_video_register();
2222
2223 setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2224 (unsigned long) dev);
2225
2226 spin_lock(&mchdev_lock);
2227 i915_mch_dev = dev_priv;
2228 dev_priv->mchdev_lock = &mchdev_lock;
2229 spin_unlock(&mchdev_lock);
2230
2231 return 0;
2232
2233 out_workqueue_free:
2234 destroy_workqueue(dev_priv->wq);
2235 out_iomapfree:
2236 io_mapping_free(dev_priv->mm.gtt_mapping);
2237 out_rmmap:
2238 iounmap(dev_priv->regs);
2239 put_bridge:
2240 pci_dev_put(dev_priv->bridge_dev);
2241 free_priv:
2242 kfree(dev_priv);
2243 return ret;
2244 }
2245
2246 int i915_driver_unload(struct drm_device *dev)
2247 {
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 int ret;
2250
2251 spin_lock(&mchdev_lock);
2252 i915_mch_dev = NULL;
2253 spin_unlock(&mchdev_lock);
2254
2255 mutex_lock(&dev->struct_mutex);
2256 ret = i915_gpu_idle(dev);
2257 if (ret)
2258 DRM_ERROR("failed to idle hardware: %d\n", ret);
2259 mutex_unlock(&dev->struct_mutex);
2260
2261 /* Cancel the retire work handler, which should be idle now. */
2262 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2263
2264 io_mapping_free(dev_priv->mm.gtt_mapping);
2265 if (dev_priv->mm.gtt_mtrr >= 0) {
2266 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2267 dev->agp->agp_info.aper_size * 1024 * 1024);
2268 dev_priv->mm.gtt_mtrr = -1;
2269 }
2270
2271 acpi_video_unregister();
2272
2273 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2274 intel_modeset_cleanup(dev);
2275
2276 /*
2277 * free the memory space allocated for the child device
2278 * config parsed from VBT
2279 */
2280 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2281 kfree(dev_priv->child_dev);
2282 dev_priv->child_dev = NULL;
2283 dev_priv->child_dev_num = 0;
2284 }
2285
2286 vga_switcheroo_unregister_client(dev->pdev);
2287 vga_client_register(dev->pdev, NULL, NULL, NULL);
2288 }
2289
2290 /* Free error state after interrupts are fully disabled. */
2291 del_timer_sync(&dev_priv->hangcheck_timer);
2292 cancel_work_sync(&dev_priv->error_work);
2293 i915_destroy_error_state(dev);
2294
2295 if (dev->pdev->msi_enabled)
2296 pci_disable_msi(dev->pdev);
2297
2298 if (dev_priv->regs != NULL)
2299 iounmap(dev_priv->regs);
2300
2301 intel_opregion_fini(dev);
2302
2303 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2304 /* Flush any outstanding unpin_work. */
2305 flush_workqueue(dev_priv->wq);
2306
2307 i915_gem_free_all_phys_object(dev);
2308
2309 mutex_lock(&dev->struct_mutex);
2310 i915_gem_cleanup_ringbuffer(dev);
2311 mutex_unlock(&dev->struct_mutex);
2312 if (I915_HAS_FBC(dev) && i915_powersave)
2313 i915_cleanup_compression(dev);
2314 drm_mm_takedown(&dev_priv->vram);
2315
2316 intel_cleanup_overlay(dev);
2317 }
2318
2319 intel_teardown_mchbar(dev);
2320
2321 destroy_workqueue(dev_priv->wq);
2322
2323 pci_dev_put(dev_priv->bridge_dev);
2324 kfree(dev->dev_private);
2325
2326 return 0;
2327 }
2328
2329 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2330 {
2331 struct drm_i915_file_private *i915_file_priv;
2332
2333 DRM_DEBUG_DRIVER("\n");
2334 i915_file_priv = (struct drm_i915_file_private *)
2335 kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2336
2337 if (!i915_file_priv)
2338 return -ENOMEM;
2339
2340 file_priv->driver_priv = i915_file_priv;
2341
2342 INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2343
2344 return 0;
2345 }
2346
2347 /**
2348 * i915_driver_lastclose - clean up after all DRM clients have exited
2349 * @dev: DRM device
2350 *
2351 * Take care of cleaning up after all DRM clients have exited. In the
2352 * mode setting case, we want to restore the kernel's initial mode (just
2353 * in case the last client left us in a bad state).
2354 *
2355 * Additionally, in the non-mode setting case, we'll tear down the AGP
2356 * and DMA structures, since the kernel won't be using them, and clea
2357 * up any GEM state.
2358 */
2359 void i915_driver_lastclose(struct drm_device * dev)
2360 {
2361 drm_i915_private_t *dev_priv = dev->dev_private;
2362
2363 if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2364 drm_fb_helper_restore();
2365 vga_switcheroo_process_delayed_switch();
2366 return;
2367 }
2368
2369 i915_gem_lastclose(dev);
2370
2371 if (dev_priv->agp_heap)
2372 i915_mem_takedown(&(dev_priv->agp_heap));
2373
2374 i915_dma_cleanup(dev);
2375 }
2376
2377 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2378 {
2379 drm_i915_private_t *dev_priv = dev->dev_private;
2380 i915_gem_release(dev, file_priv);
2381 if (!drm_core_check_feature(dev, DRIVER_MODESET))
2382 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2383 }
2384
2385 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2386 {
2387 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2388
2389 kfree(i915_file_priv);
2390 }
2391
2392 struct drm_ioctl_desc i915_ioctls[] = {
2393 DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2394 DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2395 DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2396 DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2397 DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2398 DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2399 DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2400 DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2401 DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2402 DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2403 DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2404 DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2405 DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2406 DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2407 DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
2408 DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2409 DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2410 DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2411 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2412 DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2413 DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2414 DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2415 DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2416 DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2417 DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2418 DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2419 DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2420 DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2421 DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2422 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2423 DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2424 DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2425 DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2426 DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2427 DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2428 DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2429 DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2430 DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2431 DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2432 DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2433 };
2434
2435 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2436
2437 /**
2438 * Determine if the device really is AGP or not.
2439 *
2440 * All Intel graphics chipsets are treated as AGP, even if they are really
2441 * PCI-e.
2442 *
2443 * \param dev The device to be tested.
2444 *
2445 * \returns
2446 * A value of 1 is always retured to indictate every i9x5 is AGP.
2447 */
2448 int i915_driver_device_is_agp(struct drm_device * dev)
2449 {
2450 return 1;
2451 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree