?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
usb: dwc3: gaget: clear DWC3_EP_WILL_SHUTDOWN bit
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / usb / dwc3 / gadget.c
blob2ee6714bda4be89c8bb78ece8248ad89807fbd31
1 /**
2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
3 *
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
5 * All rights reserved.
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions, and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. The names of the above-listed copyright holders may not be used
20 * to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * ALTERNATIVELY, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2, as published by the Free
25 * Software Foundation.
26 *
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
28 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
29 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
31 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
32 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
33 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
34 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
35 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
36 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
37 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 */
39
40 #include <linux/kernel.h>
41 #include <linux/delay.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/platform_device.h>
45 #include <linux/pm_runtime.h>
46 #include <linux/interrupt.h>
47 #include <linux/io.h>
48 #include <linux/list.h>
49 #include <linux/dma-mapping.h>
50
51 #include <linux/usb/ch9.h>
52 #include <linux/usb/gadget.h>
53
54 #include "core.h"
55 #include "gadget.h"
56 #include "io.h"
57
58 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
59
60 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
61 {
62 struct dwc3 *dwc = req->dep->dwc;
63
64 if (req->request.dma == DMA_ADDR_INVALID) {
65 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
66 req->request.length, req->direction
67 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
68 req->mapped = true;
69 } else {
70 dma_sync_single_for_device(dwc->dev, req->request.dma,
71 req->request.length, req->direction
72 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
73 req->mapped = false;
74 }
75 }
76
77 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
78 {
79 struct dwc3 *dwc = req->dep->dwc;
80
81 if (req->mapped) {
82 dma_unmap_single(dwc->dev, req->request.dma,
83 req->request.length, req->direction
84 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
85 req->mapped = 0;
86 } else {
87 dma_sync_single_for_cpu(dwc->dev, req->request.dma,
88 req->request.length, req->direction
89 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
90 }
91 }
92
93 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
94 int status)
95 {
96 struct dwc3 *dwc = dep->dwc;
97
98 if (req->queued) {
99 dep->busy_slot++;
100 /*
101 * Skip LINK TRB. We can't use req->trb and check for
102 * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
103 * completed (not the LINK TRB).
104 */
105 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
106 usb_endpoint_xfer_isoc(dep->desc))
107 dep->busy_slot++;
108 }
109 list_del(&req->list);
110
111 if (req->request.status == -EINPROGRESS)
112 req->request.status = status;
113
114 dwc3_unmap_buffer_from_dma(req);
115
116 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
117 req, dep->name, req->request.actual,
118 req->request.length, status);
119
120 spin_unlock(&dwc->lock);
121 req->request.complete(&req->dep->endpoint, &req->request);
122 spin_lock(&dwc->lock);
123 }
124
125 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
126 {
127 switch (cmd) {
128 case DWC3_DEPCMD_DEPSTARTCFG:
129 return "Start New Configuration";
130 case DWC3_DEPCMD_ENDTRANSFER:
131 return "End Transfer";
132 case DWC3_DEPCMD_UPDATETRANSFER:
133 return "Update Transfer";
134 case DWC3_DEPCMD_STARTTRANSFER:
135 return "Start Transfer";
136 case DWC3_DEPCMD_CLEARSTALL:
137 return "Clear Stall";
138 case DWC3_DEPCMD_SETSTALL:
139 return "Set Stall";
140 case DWC3_DEPCMD_GETSEQNUMBER:
141 return "Get Data Sequence Number";
142 case DWC3_DEPCMD_SETTRANSFRESOURCE:
143 return "Set Endpoint Transfer Resource";
144 case DWC3_DEPCMD_SETEPCONFIG:
145 return "Set Endpoint Configuration";
146 default:
147 return "UNKNOWN command";
148 }
149 }
150
151 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
152 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
153 {
154 struct dwc3_ep *dep = dwc->eps[ep];
155 unsigned long timeout = 500;
156 u32 reg;
157
158 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
159 dep->name,
160 dwc3_gadget_ep_cmd_string(cmd), params->param0.raw,
161 params->param1.raw, params->param2.raw);
162
163 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0.raw);
164 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1.raw);
165 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2.raw);
166
167 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
168 do {
169 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
170 if (!(reg & DWC3_DEPCMD_CMDACT)) {
171 dev_vdbg(dwc->dev, "CMD Compl Status %d DEPCMD %04x\n",
172 ((reg & 0xf000) >> 12), reg);
173 return 0;
174 }
175
176 /*
177 * XXX Figure out a sane timeout here. 500ms is way too much.
178 * We can't sleep here, because it is also called from
179 * interrupt context.
180 */
181 timeout--;
182 if (!timeout)
183 return -ETIMEDOUT;
184
185 mdelay(1);
186 } while (1);
187 }
188
189 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
190 struct dwc3_trb_hw *trb)
191 {
192 u32 offset = trb - dep->trb_pool;
193
194 return dep->trb_pool_dma + offset;
195 }
196
197 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
198 {
199 struct dwc3 *dwc = dep->dwc;
200
201 if (dep->trb_pool)
202 return 0;
203
204 if (dep->number == 0 || dep->number == 1)
205 return 0;
206
207 dep->trb_pool = dma_alloc_coherent(dwc->dev,
208 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
209 &dep->trb_pool_dma, GFP_KERNEL);
210 if (!dep->trb_pool) {
211 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
212 dep->name);
213 return -ENOMEM;
214 }
215
216 return 0;
217 }
218
219 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
220 {
221 struct dwc3 *dwc = dep->dwc;
222
223 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
224 dep->trb_pool, dep->trb_pool_dma);
225
226 dep->trb_pool = NULL;
227 dep->trb_pool_dma = 0;
228 }
229
230 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
231 {
232 struct dwc3_gadget_ep_cmd_params params;
233 u32 cmd;
234
235 memset(&params, 0x00, sizeof(params));
236
237 if (dep->number != 1) {
238 cmd = DWC3_DEPCMD_DEPSTARTCFG;
239 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
240 if (dep->number > 1)
241 cmd |= DWC3_DEPCMD_PARAM(2);
242
243 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
244 }
245
246 return 0;
247 }
248
249 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
250 const struct usb_endpoint_descriptor *desc)
251 {
252 struct dwc3_gadget_ep_cmd_params params;
253
254 memset(&params, 0x00, sizeof(params));
255
256 params.param0.depcfg.ep_type = usb_endpoint_type(desc);
257 params.param0.depcfg.max_packet_size = usb_endpoint_maxp(desc);
258
259 params.param1.depcfg.xfer_complete_enable = true;
260 params.param1.depcfg.xfer_not_ready_enable = true;
261
262 if (usb_endpoint_xfer_isoc(desc))
263 params.param1.depcfg.xfer_in_progress_enable = true;
264
265 /*
266 * We are doing 1:1 mapping for endpoints, meaning
267 * Physical Endpoints 2 maps to Logical Endpoint 2 and
268 * so on. We consider the direction bit as part of the physical
269 * endpoint number. So USB endpoint 0x81 is 0x03.
270 */
271 params.param1.depcfg.ep_number = dep->number;
272
273 /*
274 * We must use the lower 16 TX FIFOs even though
275 * HW might have more
276 */
277 if (dep->direction)
278 params.param0.depcfg.fifo_number = dep->number >> 1;
279
280 if (desc->bInterval) {
281 params.param1.depcfg.binterval_m1 = desc->bInterval - 1;
282 dep->interval = 1 << (desc->bInterval - 1);
283 }
284
285 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
286 DWC3_DEPCMD_SETEPCONFIG, &params);
287 }
288
289 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
290 {
291 struct dwc3_gadget_ep_cmd_params params;
292
293 memset(&params, 0x00, sizeof(params));
294
295 params.param0.depxfercfg.number_xfer_resources = 1;
296
297 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
298 DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
299 }
300
301 /**
302 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
303 * @dep: endpoint to be initialized
304 * @desc: USB Endpoint Descriptor
305 *
306 * Caller should take care of locking
307 */
308 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
309 const struct usb_endpoint_descriptor *desc)
310 {
311 struct dwc3 *dwc = dep->dwc;
312 u32 reg;
313 int ret = -ENOMEM;
314
315 if (!(dep->flags & DWC3_EP_ENABLED)) {
316 ret = dwc3_gadget_start_config(dwc, dep);
317 if (ret)
318 return ret;
319 }
320
321 ret = dwc3_gadget_set_ep_config(dwc, dep, desc);
322 if (ret)
323 return ret;
324
325 if (!(dep->flags & DWC3_EP_ENABLED)) {
326 struct dwc3_trb_hw *trb_st_hw;
327 struct dwc3_trb_hw *trb_link_hw;
328 struct dwc3_trb trb_link;
329
330 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
331 if (ret)
332 return ret;
333
334 dep->desc = desc;
335 dep->type = usb_endpoint_type(desc);
336 dep->flags |= DWC3_EP_ENABLED;
337
338 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
339 reg |= DWC3_DALEPENA_EP(dep->number);
340 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
341
342 if (!usb_endpoint_xfer_isoc(desc))
343 return 0;
344
345 memset(&trb_link, 0, sizeof(trb_link));
346
347 /* Link TRB for ISOC. The HWO but is never reset */
348 trb_st_hw = &dep->trb_pool[0];
349
350 trb_link.bplh = dwc3_trb_dma_offset(dep, trb_st_hw);
351 trb_link.trbctl = DWC3_TRBCTL_LINK_TRB;
352 trb_link.hwo = true;
353
354 trb_link_hw = &dep->trb_pool[DWC3_TRB_NUM - 1];
355 dwc3_trb_to_hw(&trb_link, trb_link_hw);
356 }
357
358 return 0;
359 }
360
361 static void dwc3_gadget_nuke_reqs(struct dwc3_ep *dep, const int status)
362 {
363 struct dwc3_request *req;
364
365 while (!list_empty(&dep->request_list)) {
366 req = next_request(&dep->request_list);
367
368 dwc3_gadget_giveback(dep, req, status);
369 }
370 /* nuke queued TRBs as well on command complete */
371 dep->flags |= DWC3_EP_WILL_SHUTDOWN;
372 }
373
374 /**
375 * __dwc3_gadget_ep_disable - Disables a HW endpoint
376 * @dep: the endpoint to disable
377 *
378 * Caller should take care of locking
379 */
380 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
381 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
382 {
383 struct dwc3 *dwc = dep->dwc;
384 u32 reg;
385
386 dep->flags &= ~DWC3_EP_ENABLED;
387 dwc3_stop_active_transfer(dwc, dep->number);
388 dwc3_gadget_nuke_reqs(dep, -ESHUTDOWN);
389
390 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
391 reg &= ~DWC3_DALEPENA_EP(dep->number);
392 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
393
394 dep->desc = NULL;
395 dep->type = 0;
396
397 return 0;
398 }
399
400 /* -------------------------------------------------------------------------- */
401
402 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
403 const struct usb_endpoint_descriptor *desc)
404 {
405 return -EINVAL;
406 }
407
408 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
409 {
410 return -EINVAL;
411 }
412
413 /* -------------------------------------------------------------------------- */
414
415 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
416 const struct usb_endpoint_descriptor *desc)
417 {
418 struct dwc3_ep *dep;
419 struct dwc3 *dwc;
420 unsigned long flags;
421 int ret;
422
423 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
424 pr_debug("dwc3: invalid parameters\n");
425 return -EINVAL;
426 }
427
428 if (!desc->wMaxPacketSize) {
429 pr_debug("dwc3: missing wMaxPacketSize\n");
430 return -EINVAL;
431 }
432
433 dep = to_dwc3_ep(ep);
434 dwc = dep->dwc;
435
436 switch (usb_endpoint_type(desc)) {
437 case USB_ENDPOINT_XFER_CONTROL:
438 strncat(dep->name, "-control", sizeof(dep->name));
439 break;
440 case USB_ENDPOINT_XFER_ISOC:
441 strncat(dep->name, "-isoc", sizeof(dep->name));
442 break;
443 case USB_ENDPOINT_XFER_BULK:
444 strncat(dep->name, "-bulk", sizeof(dep->name));
445 break;
446 case USB_ENDPOINT_XFER_INT:
447 strncat(dep->name, "-int", sizeof(dep->name));
448 break;
449 default:
450 dev_err(dwc->dev, "invalid endpoint transfer type\n");
451 }
452
453 if (dep->flags & DWC3_EP_ENABLED) {
454 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
455 dep->name);
456 return 0;
457 }
458
459 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
460
461 spin_lock_irqsave(&dwc->lock, flags);
462 ret = __dwc3_gadget_ep_enable(dep, desc);
463 spin_unlock_irqrestore(&dwc->lock, flags);
464
465 return ret;
466 }
467
468 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
469 {
470 struct dwc3_ep *dep;
471 struct dwc3 *dwc;
472 unsigned long flags;
473 int ret;
474
475 if (!ep) {
476 pr_debug("dwc3: invalid parameters\n");
477 return -EINVAL;
478 }
479
480 dep = to_dwc3_ep(ep);
481 dwc = dep->dwc;
482
483 if (!(dep->flags & DWC3_EP_ENABLED)) {
484 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
485 dep->name);
486 return 0;
487 }
488
489 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
490 dep->number >> 1,
491 (dep->number & 1) ? "in" : "out");
492
493 spin_lock_irqsave(&dwc->lock, flags);
494 ret = __dwc3_gadget_ep_disable(dep);
495 spin_unlock_irqrestore(&dwc->lock, flags);
496
497 return ret;
498 }
499
500 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
501 gfp_t gfp_flags)
502 {
503 struct dwc3_request *req;
504 struct dwc3_ep *dep = to_dwc3_ep(ep);
505 struct dwc3 *dwc = dep->dwc;
506
507 req = kzalloc(sizeof(*req), gfp_flags);
508 if (!req) {
509 dev_err(dwc->dev, "not enough memory\n");
510 return NULL;
511 }
512
513 req->epnum = dep->number;
514 req->dep = dep;
515 req->request.dma = DMA_ADDR_INVALID;
516
517 return &req->request;
518 }
519
520 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
521 struct usb_request *request)
522 {
523 struct dwc3_request *req = to_dwc3_request(request);
524
525 kfree(req);
526 }
527
528 /*
529 * dwc3_prepare_trbs - setup TRBs from requests
530 * @dep: endpoint for which requests are being prepared
531 * @starting: true if the endpoint is idle and no requests are queued.
532 *
533 * The functions goes through the requests list and setups TRBs for the
534 * transfers. The functions returns once there are not more TRBs available or
535 * it run out of requests.
536 */
537 static struct dwc3_request *dwc3_prepare_trbs(struct dwc3_ep *dep,
538 bool starting)
539 {
540 struct dwc3_request *req, *n, *ret = NULL;
541 struct dwc3_trb_hw *trb_hw;
542 struct dwc3_trb trb;
543 u32 trbs_left;
544
545 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
546
547 /* the first request must not be queued */
548 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
549 /*
550 * if busy & slot are equal than it is either full or empty. If we are
551 * starting to proceed requests then we are empty. Otherwise we ar
552 * full and don't do anything
553 */
554 if (!trbs_left) {
555 if (!starting)
556 return NULL;
557 trbs_left = DWC3_TRB_NUM;
558 /*
559 * In case we start from scratch, we queue the ISOC requests
560 * starting from slot 1. This is done because we use ring
561 * buffer and have no LST bit to stop us. Instead, we place
562 * IOC bit TRB_NUM/4. We try to avoid to having an interrupt
563 * after the first request so we start at slot 1 and have
564 * 7 requests proceed before we hit the first IOC.
565 * Other transfer types don't use the ring buffer and are
566 * processed from the first TRB until the last one. Since we
567 * don't wrap around we have to start at the beginning.
568 */
569 if (usb_endpoint_xfer_isoc(dep->desc)) {
570 dep->busy_slot = 1;
571 dep->free_slot = 1;
572 } else {
573 dep->busy_slot = 0;
574 dep->free_slot = 0;
575 }
576 }
577
578 /* The last TRB is a link TRB, not used for xfer */
579 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
580 return NULL;
581
582 list_for_each_entry_safe(req, n, &dep->request_list, list) {
583 unsigned int last_one = 0;
584 unsigned int cur_slot;
585
586 trb_hw = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
587 cur_slot = dep->free_slot;
588 dep->free_slot++;
589
590 /* Skip the LINK-TRB on ISOC */
591 if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
592 usb_endpoint_xfer_isoc(dep->desc))
593 continue;
594
595 dwc3_gadget_move_request_queued(req);
596 memset(&trb, 0, sizeof(trb));
597 trbs_left--;
598
599 /* Is our TRB pool empty? */
600 if (!trbs_left)
601 last_one = 1;
602 /* Is this the last request? */
603 if (list_empty(&dep->request_list))
604 last_one = 1;
605
606 /*
607 * FIXME we shouldn't need to set LST bit always but we are
608 * facing some weird problem with the Hardware where it doesn't
609 * complete even though it has been previously started.
610 *
611 * While we're debugging the problem, as a workaround to
612 * multiple TRBs handling, use only one TRB at a time.
613 */
614 last_one = 1;
615
616 req->trb = trb_hw;
617 if (!ret)
618 ret = req;
619
620 trb.bplh = req->request.dma;
621
622 if (usb_endpoint_xfer_isoc(dep->desc)) {
623 trb.isp_imi = true;
624 trb.csp = true;
625 } else {
626 trb.lst = last_one;
627 }
628
629 switch (usb_endpoint_type(dep->desc)) {
630 case USB_ENDPOINT_XFER_CONTROL:
631 trb.trbctl = DWC3_TRBCTL_CONTROL_SETUP;
632 break;
633
634 case USB_ENDPOINT_XFER_ISOC:
635 trb.trbctl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
636
637 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
638 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
639 trb.ioc = last_one;
640 break;
641
642 case USB_ENDPOINT_XFER_BULK:
643 case USB_ENDPOINT_XFER_INT:
644 trb.trbctl = DWC3_TRBCTL_NORMAL;
645 break;
646 default:
647 /*
648 * This is only possible with faulty memory because we
649 * checked it already :)
650 */
651 BUG();
652 }
653
654 trb.length = req->request.length;
655 trb.hwo = true;
656
657 dwc3_trb_to_hw(&trb, trb_hw);
658 req->trb_dma = dwc3_trb_dma_offset(dep, trb_hw);
659
660 if (last_one)
661 break;
662 }
663
664 return ret;
665 }
666
667 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
668 int start_new)
669 {
670 struct dwc3_gadget_ep_cmd_params params;
671 struct dwc3_request *req;
672 struct dwc3 *dwc = dep->dwc;
673 int ret;
674 u32 cmd;
675
676 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
677 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
678 return -EBUSY;
679 }
680 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
681
682 /*
683 * If we are getting here after a short-out-packet we don't enqueue any
684 * new requests as we try to set the IOC bit only on the last request.
685 */
686 if (start_new) {
687 if (list_empty(&dep->req_queued))
688 dwc3_prepare_trbs(dep, start_new);
689
690 /* req points to the first request which will be sent */
691 req = next_request(&dep->req_queued);
692 } else {
693 /*
694 * req points to the first request where HWO changed
695 * from 0 to 1
696 */
697 req = dwc3_prepare_trbs(dep, start_new);
698 }
699 if (!req) {
700 dep->flags |= DWC3_EP_PENDING_REQUEST;
701 return 0;
702 }
703
704 memset(&params, 0, sizeof(params));
705 params.param0.depstrtxfer.transfer_desc_addr_high =
706 upper_32_bits(req->trb_dma);
707 params.param1.depstrtxfer.transfer_desc_addr_low =
708 lower_32_bits(req->trb_dma);
709
710 if (start_new)
711 cmd = DWC3_DEPCMD_STARTTRANSFER;
712 else
713 cmd = DWC3_DEPCMD_UPDATETRANSFER;
714
715 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
716 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
717 if (ret < 0) {
718 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
719
720 /*
721 * FIXME we need to iterate over the list of requests
722 * here and stop, unmap, free and del each of the linked
723 * requests instead of we do now.
724 */
725 dwc3_unmap_buffer_from_dma(req);
726 list_del(&req->list);
727 return ret;
728 }
729
730 dep->flags |= DWC3_EP_BUSY;
731 dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
732 dep->number);
733 if (!dep->res_trans_idx)
734 printk_once(KERN_ERR "%s() res_trans_idx is invalid\n", __func__);
735 return 0;
736 }
737
738 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
739 {
740 req->request.actual = 0;
741 req->request.status = -EINPROGRESS;
742 req->direction = dep->direction;
743 req->epnum = dep->number;
744
745 /*
746 * We only add to our list of requests now and
747 * start consuming the list once we get XferNotReady
748 * IRQ.
749 *
750 * That way, we avoid doing anything that we don't need
751 * to do now and defer it until the point we receive a
752 * particular token from the Host side.
753 *
754 * This will also avoid Host cancelling URBs due to too
755 * many NACKs.
756 */
757 dwc3_map_buffer_to_dma(req);
758 list_add_tail(&req->list, &dep->request_list);
759
760 /*
761 * There is one special case: XferNotReady with
762 * empty list of requests. We need to kick the
763 * transfer here in that situation, otherwise
764 * we will be NAKing forever.
765 *
766 * If we get XferNotReady before gadget driver
767 * has a chance to queue a request, we will ACK
768 * the IRQ but won't be able to receive the data
769 * until the next request is queued. The following
770 * code is handling exactly that.
771 */
772 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
773 int ret;
774 int start_trans;
775
776 start_trans = 1;
777 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
778 dep->flags & DWC3_EP_BUSY)
779 start_trans = 0;
780
781 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
782 if (ret && ret != -EBUSY) {
783 struct dwc3 *dwc = dep->dwc;
784
785 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
786 dep->name);
787 }
788 };
789
790 return 0;
791 }
792
793 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
794 gfp_t gfp_flags)
795 {
796 struct dwc3_request *req = to_dwc3_request(request);
797 struct dwc3_ep *dep = to_dwc3_ep(ep);
798 struct dwc3 *dwc = dep->dwc;
799
800 unsigned long flags;
801
802 int ret;
803
804 if (!dep->desc) {
805 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
806 request, ep->name);
807 return -ESHUTDOWN;
808 }
809
810 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
811 request, ep->name, request->length);
812
813 spin_lock_irqsave(&dwc->lock, flags);
814 ret = __dwc3_gadget_ep_queue(dep, req);
815 spin_unlock_irqrestore(&dwc->lock, flags);
816
817 return ret;
818 }
819
820 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
821 struct usb_request *request)
822 {
823 struct dwc3_request *req = to_dwc3_request(request);
824 struct dwc3_request *r = NULL;
825
826 struct dwc3_ep *dep = to_dwc3_ep(ep);
827 struct dwc3 *dwc = dep->dwc;
828
829 unsigned long flags;
830 int ret = 0;
831
832 spin_lock_irqsave(&dwc->lock, flags);
833
834 list_for_each_entry(r, &dep->request_list, list) {
835 if (r == req)
836 break;
837 }
838
839 if (r != req) {
840 list_for_each_entry(r, &dep->req_queued, list) {
841 if (r == req)
842 break;
843 }
844 if (r == req) {
845 /* wait until it is processed */
846 dwc3_stop_active_transfer(dwc, dep->number);
847 goto out0;
848 }
849 dev_err(dwc->dev, "request %p was not queued to %s\n",
850 request, ep->name);
851 ret = -EINVAL;
852 goto out0;
853 }
854
855 /* giveback the request */
856 dwc3_gadget_giveback(dep, req, -ECONNRESET);
857
858 out0:
859 spin_unlock_irqrestore(&dwc->lock, flags);
860
861 return ret;
862 }
863
864 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
865 {
866 struct dwc3_gadget_ep_cmd_params params;
867 struct dwc3 *dwc = dep->dwc;
868 int ret;
869
870 memset(&params, 0x00, sizeof(params));
871
872 if (value) {
873 if (dep->number == 0 || dep->number == 1)
874 dwc->ep0state = EP0_STALL;
875
876 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
877 DWC3_DEPCMD_SETSTALL, &params);
878 if (ret)
879 dev_err(dwc->dev, "failed to %s STALL on %s\n",
880 value ? "set" : "clear",
881 dep->name);
882 else
883 dep->flags |= DWC3_EP_STALL;
884 } else {
885 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
886 DWC3_DEPCMD_CLEARSTALL, &params);
887 if (ret)
888 dev_err(dwc->dev, "failed to %s STALL on %s\n",
889 value ? "set" : "clear",
890 dep->name);
891 else
892 dep->flags &= ~DWC3_EP_STALL;
893 }
894 return ret;
895 }
896
897 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
898 {
899 struct dwc3_ep *dep = to_dwc3_ep(ep);
900 struct dwc3 *dwc = dep->dwc;
901
902 unsigned long flags;
903
904 int ret;
905
906 spin_lock_irqsave(&dwc->lock, flags);
907
908 if (usb_endpoint_xfer_isoc(dep->desc)) {
909 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
910 ret = -EINVAL;
911 goto out;
912 }
913
914 ret = __dwc3_gadget_ep_set_halt(dep, value);
915 out:
916 spin_unlock_irqrestore(&dwc->lock, flags);
917
918 return ret;
919 }
920
921 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
922 {
923 struct dwc3_ep *dep = to_dwc3_ep(ep);
924
925 dep->flags |= DWC3_EP_WEDGE;
926
927 return usb_ep_set_halt(ep);
928 }
929
930 /* -------------------------------------------------------------------------- */
931
932 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
933 .bLength = USB_DT_ENDPOINT_SIZE,
934 .bDescriptorType = USB_DT_ENDPOINT,
935 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
936 };
937
938 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
939 .enable = dwc3_gadget_ep0_enable,
940 .disable = dwc3_gadget_ep0_disable,
941 .alloc_request = dwc3_gadget_ep_alloc_request,
942 .free_request = dwc3_gadget_ep_free_request,
943 .queue = dwc3_gadget_ep0_queue,
944 .dequeue = dwc3_gadget_ep_dequeue,
945 .set_halt = dwc3_gadget_ep_set_halt,
946 .set_wedge = dwc3_gadget_ep_set_wedge,
947 };
948
949 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
950 .enable = dwc3_gadget_ep_enable,
951 .disable = dwc3_gadget_ep_disable,
952 .alloc_request = dwc3_gadget_ep_alloc_request,
953 .free_request = dwc3_gadget_ep_free_request,
954 .queue = dwc3_gadget_ep_queue,
955 .dequeue = dwc3_gadget_ep_dequeue,
956 .set_halt = dwc3_gadget_ep_set_halt,
957 .set_wedge = dwc3_gadget_ep_set_wedge,
958 };
959
960 /* -------------------------------------------------------------------------- */
961
962 static int dwc3_gadget_get_frame(struct usb_gadget *g)
963 {
964 struct dwc3 *dwc = gadget_to_dwc(g);
965 u32 reg;
966
967 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
968 return DWC3_DSTS_SOFFN(reg);
969 }
970
971 static int dwc3_gadget_wakeup(struct usb_gadget *g)
972 {
973 struct dwc3 *dwc = gadget_to_dwc(g);
974
975 unsigned long timeout;
976 unsigned long flags;
977
978 u32 reg;
979
980 int ret = 0;
981
982 u8 link_state;
983 u8 speed;
984
985 spin_lock_irqsave(&dwc->lock, flags);
986
987 /*
988 * According to the Databook Remote wakeup request should
989 * be issued only when the device is in early suspend state.
990 *
991 * We can check that via USB Link State bits in DSTS register.
992 */
993 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
994
995 speed = reg & DWC3_DSTS_CONNECTSPD;
996 if (speed == DWC3_DSTS_SUPERSPEED) {
997 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
998 ret = -EINVAL;
999 goto out;
1000 }
1001
1002 link_state = DWC3_DSTS_USBLNKST(reg);
1003
1004 switch (link_state) {
1005 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1006 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1007 break;
1008 default:
1009 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1010 link_state);
1011 ret = -EINVAL;
1012 goto out;
1013 }
1014
1015 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1016
1017 /*
1018 * Switch link state to Recovery. In HS/FS/LS this means
1019 * RemoteWakeup Request
1020 */
1021 reg |= DWC3_DCTL_ULSTCHNG_RECOVERY;
1022 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1023
1024 /* wait for at least 2000us */
1025 usleep_range(2000, 2500);
1026
1027 /* write zeroes to Link Change Request */
1028 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1029 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1030
1031 /* pool until Link State change to ON */
1032 timeout = jiffies + msecs_to_jiffies(100);
1033
1034 while (!(time_after(jiffies, timeout))) {
1035 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1036
1037 /* in HS, means ON */
1038 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1039 break;
1040 }
1041
1042 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1043 dev_err(dwc->dev, "failed to send remote wakeup\n");
1044 ret = -EINVAL;
1045 }
1046
1047 out:
1048 spin_unlock_irqrestore(&dwc->lock, flags);
1049
1050 return ret;
1051 }
1052
1053 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1054 int is_selfpowered)
1055 {
1056 struct dwc3 *dwc = gadget_to_dwc(g);
1057
1058 dwc->is_selfpowered = !!is_selfpowered;
1059
1060 return 0;
1061 }
1062
1063 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1064 {
1065 u32 reg;
1066 unsigned long timeout = 500;
1067
1068 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1069 if (is_on)
1070 reg |= DWC3_DCTL_RUN_STOP;
1071 else
1072 reg &= ~DWC3_DCTL_RUN_STOP;
1073
1074 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1075
1076 do {
1077 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1078 if (is_on) {
1079 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1080 break;
1081 } else {
1082 if (reg & DWC3_DSTS_DEVCTRLHLT)
1083 break;
1084 }
1085 /*
1086 * XXX reduce the 500ms delay
1087 */
1088 timeout--;
1089 if (!timeout)
1090 break;
1091 mdelay(1);
1092 } while (1);
1093
1094 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1095 dwc->gadget_driver
1096 ? dwc->gadget_driver->function : "no-function",
1097 is_on ? "connect" : "disconnect");
1098 }
1099
1100 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1101 {
1102 struct dwc3 *dwc = gadget_to_dwc(g);
1103 unsigned long flags;
1104
1105 is_on = !!is_on;
1106
1107 spin_lock_irqsave(&dwc->lock, flags);
1108 dwc3_gadget_run_stop(dwc, is_on);
1109 spin_unlock_irqrestore(&dwc->lock, flags);
1110
1111 return 0;
1112 }
1113
1114 static int dwc3_gadget_start(struct usb_gadget *g,
1115 struct usb_gadget_driver *driver)
1116 {
1117 struct dwc3 *dwc = gadget_to_dwc(g);
1118 struct dwc3_ep *dep;
1119 unsigned long flags;
1120 int ret = 0;
1121 u32 reg;
1122
1123 spin_lock_irqsave(&dwc->lock, flags);
1124
1125 if (dwc->gadget_driver) {
1126 dev_err(dwc->dev, "%s is already bound to %s\n",
1127 dwc->gadget.name,
1128 dwc->gadget_driver->driver.name);
1129 ret = -EBUSY;
1130 goto err0;
1131 }
1132
1133 dwc->gadget_driver = driver;
1134 dwc->gadget.dev.driver = &driver->driver;
1135
1136 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1137
1138 /*
1139 * REVISIT: power down scale might be different
1140 * depending on PHY used, need to pass that via platform_data
1141 */
1142 reg |= DWC3_GCTL_PWRDNSCALE(0x61a)
1143 | DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_DEVICE);
1144 reg &= ~DWC3_GCTL_DISSCRAMBLE;
1145
1146 /*
1147 * WORKAROUND: DWC3 revisions <1.90a have a bug
1148 * when The device fails to connect at SuperSpeed
1149 * and falls back to high-speed mode which causes
1150 * the device to enter in a Connect/Disconnect loop
1151 */
1152 if (dwc->revision < DWC3_REVISION_190A)
1153 reg |= DWC3_GCTL_U2RSTECN;
1154
1155 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1156
1157 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1158 reg &= ~(DWC3_DCFG_SPEED_MASK);
1159 reg |= DWC3_DCFG_SUPERSPEED;
1160 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1161
1162 /* Start with SuperSpeed Default */
1163 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1164
1165 dep = dwc->eps[0];
1166 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1167 if (ret) {
1168 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1169 goto err0;
1170 }
1171
1172 dep = dwc->eps[1];
1173 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1174 if (ret) {
1175 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1176 goto err1;
1177 }
1178
1179 /* begin to receive SETUP packets */
1180 dwc->ep0state = EP0_IDLE;
1181 dwc3_ep0_out_start(dwc);
1182
1183 spin_unlock_irqrestore(&dwc->lock, flags);
1184
1185 return 0;
1186
1187 err1:
1188 __dwc3_gadget_ep_disable(dwc->eps[0]);
1189
1190 err0:
1191 spin_unlock_irqrestore(&dwc->lock, flags);
1192
1193 return ret;
1194 }
1195
1196 static int dwc3_gadget_stop(struct usb_gadget *g,
1197 struct usb_gadget_driver *driver)
1198 {
1199 struct dwc3 *dwc = gadget_to_dwc(g);
1200 unsigned long flags;
1201
1202 spin_lock_irqsave(&dwc->lock, flags);
1203
1204 __dwc3_gadget_ep_disable(dwc->eps[0]);
1205 __dwc3_gadget_ep_disable(dwc->eps[1]);
1206
1207 dwc->gadget_driver = NULL;
1208 dwc->gadget.dev.driver = NULL;
1209
1210 spin_unlock_irqrestore(&dwc->lock, flags);
1211
1212 return 0;
1213 }
1214 static const struct usb_gadget_ops dwc3_gadget_ops = {
1215 .get_frame = dwc3_gadget_get_frame,
1216 .wakeup = dwc3_gadget_wakeup,
1217 .set_selfpowered = dwc3_gadget_set_selfpowered,
1218 .pullup = dwc3_gadget_pullup,
1219 .udc_start = dwc3_gadget_start,
1220 .udc_stop = dwc3_gadget_stop,
1221 };
1222
1223 /* -------------------------------------------------------------------------- */
1224
1225 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1226 {
1227 struct dwc3_ep *dep;
1228 u8 epnum;
1229
1230 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1231
1232 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1233 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1234 if (!dep) {
1235 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1236 epnum);
1237 return -ENOMEM;
1238 }
1239
1240 dep->dwc = dwc;
1241 dep->number = epnum;
1242 dwc->eps[epnum] = dep;
1243
1244 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1245 (epnum & 1) ? "in" : "out");
1246 dep->endpoint.name = dep->name;
1247 dep->direction = (epnum & 1);
1248
1249 if (epnum == 0 || epnum == 1) {
1250 dep->endpoint.maxpacket = 512;
1251 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1252 if (!epnum)
1253 dwc->gadget.ep0 = &dep->endpoint;
1254 } else {
1255 int ret;
1256
1257 dep->endpoint.maxpacket = 1024;
1258 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1259 list_add_tail(&dep->endpoint.ep_list,
1260 &dwc->gadget.ep_list);
1261
1262 ret = dwc3_alloc_trb_pool(dep);
1263 if (ret) {
1264 dev_err(dwc->dev, "%s: failed to allocate TRB pool\n", dep->name);
1265 return ret;
1266 }
1267 }
1268 INIT_LIST_HEAD(&dep->request_list);
1269 INIT_LIST_HEAD(&dep->req_queued);
1270 }
1271
1272 return 0;
1273 }
1274
1275 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1276 {
1277 struct dwc3_ep *dep;
1278 u8 epnum;
1279
1280 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1281 dep = dwc->eps[epnum];
1282 dwc3_free_trb_pool(dep);
1283
1284 if (epnum != 0 && epnum != 1)
1285 list_del(&dep->endpoint.ep_list);
1286
1287 kfree(dep);
1288 }
1289 }
1290
1291 static void dwc3_gadget_release(struct device *dev)
1292 {
1293 dev_dbg(dev, "%s\n", __func__);
1294 }
1295
1296 /* -------------------------------------------------------------------------- */
1297 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1298 const struct dwc3_event_depevt *event, int status)
1299 {
1300 struct dwc3_request *req;
1301 struct dwc3_trb trb;
1302 unsigned int count;
1303 unsigned int s_pkt = 0;
1304
1305 do {
1306 req = next_request(&dep->req_queued);
1307 if (!req)
1308 break;
1309
1310 dwc3_trb_to_nat(req->trb, &trb);
1311
1312 if (trb.hwo && status != -ESHUTDOWN)
1313 /*
1314 * We continue despite the error. There is not much we
1315 * can do. If we don't clean in up we loop for ever. If
1316 * we skip the TRB than it gets overwritten reused after
1317 * a while since we use them in a ring buffer. a BUG()
1318 * would help. Lets hope that if this occures, someone
1319 * fixes the root cause instead of looking away :)
1320 */
1321 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1322 dep->name, req->trb);
1323 count = trb.length;
1324
1325 if (dep->direction) {
1326 if (count) {
1327 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1328 dep->name);
1329 status = -ECONNRESET;
1330 }
1331 } else {
1332 if (count && (event->status & DEPEVT_STATUS_SHORT))
1333 s_pkt = 1;
1334 }
1335
1336 /*
1337 * We assume here we will always receive the entire data block
1338 * which we should receive. Meaning, if we program RX to
1339 * receive 4K but we receive only 2K, we assume that's all we
1340 * should receive and we simply bounce the request back to the
1341 * gadget driver for further processing.
1342 */
1343 req->request.actual += req->request.length - count;
1344 dwc3_gadget_giveback(dep, req, status);
1345 if (s_pkt)
1346 break;
1347 if ((event->status & DEPEVT_STATUS_LST) && trb.lst)
1348 break;
1349 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1350 break;
1351 } while (1);
1352
1353 if ((event->status & DEPEVT_STATUS_IOC) && trb.ioc)
1354 return 0;
1355 return 1;
1356 }
1357
1358 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1359 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1360 int start_new)
1361 {
1362 unsigned status = 0;
1363 int clean_busy;
1364
1365 if (event->status & DEPEVT_STATUS_BUSERR)
1366 status = -ECONNRESET;
1367
1368 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1369 if (clean_busy) {
1370 dep->flags &= ~DWC3_EP_BUSY;
1371 dep->res_trans_idx = 0;
1372 }
1373 }
1374
1375 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1376 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1377 {
1378 u32 uf;
1379
1380 if (list_empty(&dep->request_list)) {
1381 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1382 dep->name);
1383 return;
1384 }
1385
1386 if (event->parameters) {
1387 u32 mask;
1388
1389 mask = ~(dep->interval - 1);
1390 uf = event->parameters & mask;
1391 /* 4 micro frames in the future */
1392 uf += dep->interval * 4;
1393 } else {
1394 uf = 0;
1395 }
1396
1397 __dwc3_gadget_kick_transfer(dep, uf, 1);
1398 }
1399
1400 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1401 const struct dwc3_event_depevt *event)
1402 {
1403 struct dwc3 *dwc = dep->dwc;
1404 struct dwc3_event_depevt mod_ev = *event;
1405
1406 /*
1407 * We were asked to remove one requests. It is possible that this
1408 * request and a few other were started together and have the same
1409 * transfer index. Since we stopped the complete endpoint we don't
1410 * know how many requests were already completed (and not yet)
1411 * reported and how could be done (later). We purge them all until
1412 * the end of the list.
1413 */
1414 mod_ev.status = DEPEVT_STATUS_LST;
1415 dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1416 dep->flags &= ~DWC3_EP_BUSY;
1417 /* pending requets are ignored and are queued on XferNotReady */
1418
1419 if (dep->flags & DWC3_EP_WILL_SHUTDOWN) {
1420 while (!list_empty(&dep->req_queued)) {
1421 struct dwc3_request *req;
1422
1423 req = next_request(&dep->req_queued);
1424 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
1425 }
1426 dep->flags &= ~DWC3_EP_WILL_SHUTDOWN;
1427 }
1428 }
1429
1430 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1431 const struct dwc3_event_depevt *event)
1432 {
1433 u32 param = event->parameters;
1434 u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1435
1436 switch (cmd_type) {
1437 case DWC3_DEPCMD_ENDTRANSFER:
1438 dwc3_process_ep_cmd_complete(dep, event);
1439 break;
1440 case DWC3_DEPCMD_STARTTRANSFER:
1441 dep->res_trans_idx = param & 0x7f;
1442 break;
1443 default:
1444 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1445 __func__, cmd_type);
1446 break;
1447 };
1448 }
1449
1450 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1451 const struct dwc3_event_depevt *event)
1452 {
1453 struct dwc3_ep *dep;
1454 u8 epnum = event->endpoint_number;
1455
1456 dep = dwc->eps[epnum];
1457
1458 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1459 dwc3_ep_event_string(event->endpoint_event));
1460
1461 if (epnum == 0 || epnum == 1) {
1462 dwc3_ep0_interrupt(dwc, event);
1463 return;
1464 }
1465
1466 switch (event->endpoint_event) {
1467 case DWC3_DEPEVT_XFERCOMPLETE:
1468 if (usb_endpoint_xfer_isoc(dep->desc)) {
1469 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1470 dep->name);
1471 return;
1472 }
1473
1474 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1475 break;
1476 case DWC3_DEPEVT_XFERINPROGRESS:
1477 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1478 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1479 dep->name);
1480 return;
1481 }
1482
1483 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1484 break;
1485 case DWC3_DEPEVT_XFERNOTREADY:
1486 if (usb_endpoint_xfer_isoc(dep->desc)) {
1487 dwc3_gadget_start_isoc(dwc, dep, event);
1488 } else {
1489 int ret;
1490
1491 dev_vdbg(dwc->dev, "%s: reason %s\n",
1492 dep->name, event->status
1493 ? "Transfer Active"
1494 : "Transfer Not Active");
1495
1496 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1497 if (!ret || ret == -EBUSY)
1498 return;
1499
1500 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1501 dep->name);
1502 }
1503
1504 break;
1505 case DWC3_DEPEVT_RXTXFIFOEVT:
1506 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1507 break;
1508 case DWC3_DEPEVT_STREAMEVT:
1509 dev_dbg(dwc->dev, "%s Stream Event\n", dep->name);
1510 break;
1511 case DWC3_DEPEVT_EPCMDCMPLT:
1512 dwc3_ep_cmd_compl(dep, event);
1513 break;
1514 }
1515 }
1516
1517 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1518 {
1519 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1520 spin_unlock(&dwc->lock);
1521 dwc->gadget_driver->disconnect(&dwc->gadget);
1522 spin_lock(&dwc->lock);
1523 }
1524 }
1525
1526 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1527 {
1528 struct dwc3_ep *dep;
1529 struct dwc3_gadget_ep_cmd_params params;
1530 u32 cmd;
1531 int ret;
1532
1533 dep = dwc->eps[epnum];
1534
1535 if (dep->res_trans_idx) {
1536 cmd = DWC3_DEPCMD_ENDTRANSFER;
1537 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1538 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1539 memset(&params, 0, sizeof(params));
1540 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1541 WARN_ON_ONCE(ret);
1542 dep->res_trans_idx = 0;
1543 }
1544 }
1545
1546 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1547 {
1548 u32 epnum;
1549
1550 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1551 struct dwc3_ep *dep;
1552
1553 dep = dwc->eps[epnum];
1554 if (!(dep->flags & DWC3_EP_ENABLED))
1555 continue;
1556
1557 __dwc3_gadget_ep_disable(dep);
1558 }
1559 }
1560
1561 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1562 {
1563 u32 epnum;
1564
1565 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1566 struct dwc3_ep *dep;
1567 struct dwc3_gadget_ep_cmd_params params;
1568 int ret;
1569
1570 dep = dwc->eps[epnum];
1571
1572 if (!(dep->flags & DWC3_EP_STALL))
1573 continue;
1574
1575 dep->flags &= ~DWC3_EP_STALL;
1576
1577 memset(&params, 0, sizeof(params));
1578 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1579 DWC3_DEPCMD_CLEARSTALL, &params);
1580 WARN_ON_ONCE(ret);
1581 }
1582 }
1583
1584 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1585 {
1586 dev_vdbg(dwc->dev, "%s\n", __func__);
1587 #if 0
1588 XXX
1589 U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1590 enable it before we can disable it.
1591
1592 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1593 reg &= ~DWC3_DCTL_INITU1ENA;
1594 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1595
1596 reg &= ~DWC3_DCTL_INITU2ENA;
1597 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1598 #endif
1599
1600 dwc3_stop_active_transfers(dwc);
1601 dwc3_disconnect_gadget(dwc);
1602
1603 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1604 }
1605
1606 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1607 {
1608 u32 reg;
1609
1610 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1611
1612 if (on)
1613 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1614 else
1615 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1616
1617 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1618 }
1619
1620 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1621 {
1622 u32 reg;
1623
1624 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1625
1626 if (on)
1627 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1628 else
1629 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1630
1631 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1632 }
1633
1634 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1635 {
1636 u32 reg;
1637
1638 dev_vdbg(dwc->dev, "%s\n", __func__);
1639
1640 /* Enable PHYs */
1641 dwc3_gadget_usb2_phy_power(dwc, true);
1642 dwc3_gadget_usb3_phy_power(dwc, true);
1643
1644 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1645 dwc3_disconnect_gadget(dwc);
1646
1647 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1648 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1649 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1650
1651 dwc3_stop_active_transfers(dwc);
1652 dwc3_clear_stall_all_ep(dwc);
1653
1654 /* Reset device address to zero */
1655 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1656 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1657 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1658
1659 /*
1660 * Wait for RxFifo to drain
1661 *
1662 * REVISIT probably shouldn't wait forever.
1663 * In case Hardware ends up in a screwed up
1664 * case, we error out, notify the user and,
1665 * maybe, WARN() or BUG() but leave the rest
1666 * of the kernel working fine.
1667 *
1668 * REVISIT the below is rather CPU intensive,
1669 * maybe we should read and if it doesn't work
1670 * sleep (not busy wait) for a few useconds.
1671 *
1672 * REVISIT why wait until the RXFIFO is empty anyway?
1673 */
1674 while (!(dwc3_readl(dwc->regs, DWC3_DSTS)
1675 & DWC3_DSTS_RXFIFOEMPTY))
1676 cpu_relax();
1677 }
1678
1679 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1680 {
1681 u32 reg;
1682 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1683
1684 /*
1685 * We change the clock only at SS but I dunno why I would want to do
1686 * this. Maybe it becomes part of the power saving plan.
1687 */
1688
1689 if (speed != DWC3_DSTS_SUPERSPEED)
1690 return;
1691
1692 /*
1693 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
1694 * each time on Connect Done.
1695 */
1696 if (!usb30_clock)
1697 return;
1698
1699 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1700 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
1701 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1702 }
1703
1704 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
1705 {
1706 switch (speed) {
1707 case USB_SPEED_SUPER:
1708 dwc3_gadget_usb2_phy_power(dwc, false);
1709 break;
1710 case USB_SPEED_HIGH:
1711 case USB_SPEED_FULL:
1712 case USB_SPEED_LOW:
1713 dwc3_gadget_usb3_phy_power(dwc, false);
1714 break;
1715 }
1716 }
1717
1718 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
1719 {
1720 struct dwc3_gadget_ep_cmd_params params;
1721 struct dwc3_ep *dep;
1722 int ret;
1723 u32 reg;
1724 u8 speed;
1725
1726 dev_vdbg(dwc->dev, "%s\n", __func__);
1727
1728 memset(&params, 0x00, sizeof(params));
1729
1730 dwc->ep0state = EP0_IDLE;
1731 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1732 speed = reg & DWC3_DSTS_CONNECTSPD;
1733 dwc->speed = speed;
1734
1735 dwc3_update_ram_clk_sel(dwc, speed);
1736
1737 switch (speed) {
1738 case DWC3_DCFG_SUPERSPEED:
1739 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1740 dwc->gadget.ep0->maxpacket = 512;
1741 dwc->gadget.speed = USB_SPEED_SUPER;
1742 break;
1743 case DWC3_DCFG_HIGHSPEED:
1744 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1745 dwc->gadget.ep0->maxpacket = 64;
1746 dwc->gadget.speed = USB_SPEED_HIGH;
1747 break;
1748 case DWC3_DCFG_FULLSPEED2:
1749 case DWC3_DCFG_FULLSPEED1:
1750 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
1751 dwc->gadget.ep0->maxpacket = 64;
1752 dwc->gadget.speed = USB_SPEED_FULL;
1753 break;
1754 case DWC3_DCFG_LOWSPEED:
1755 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
1756 dwc->gadget.ep0->maxpacket = 8;
1757 dwc->gadget.speed = USB_SPEED_LOW;
1758 break;
1759 }
1760
1761 /* Disable unneded PHY */
1762 dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
1763
1764 dep = dwc->eps[0];
1765 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1766 if (ret) {
1767 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1768 return;
1769 }
1770
1771 dep = dwc->eps[1];
1772 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc);
1773 if (ret) {
1774 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1775 return;
1776 }
1777
1778 /*
1779 * Configure PHY via GUSB3PIPECTLn if required.
1780 *
1781 * Update GTXFIFOSIZn
1782 *
1783 * In both cases reset values should be sufficient.
1784 */
1785 }
1786
1787 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
1788 {
1789 dev_vdbg(dwc->dev, "%s\n", __func__);
1790
1791 /*
1792 * TODO take core out of low power mode when that's
1793 * implemented.
1794 */
1795
1796 dwc->gadget_driver->resume(&dwc->gadget);
1797 }
1798
1799 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
1800 unsigned int evtinfo)
1801 {
1802 dev_vdbg(dwc->dev, "%s\n", __func__);
1803
1804 /* The fith bit says SuperSpeed yes or no. */
1805 dwc->link_state = evtinfo & DWC3_LINK_STATE_MASK;
1806 }
1807
1808 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
1809 const struct dwc3_event_devt *event)
1810 {
1811 switch (event->type) {
1812 case DWC3_DEVICE_EVENT_DISCONNECT:
1813 dwc3_gadget_disconnect_interrupt(dwc);
1814 break;
1815 case DWC3_DEVICE_EVENT_RESET:
1816 dwc3_gadget_reset_interrupt(dwc);
1817 break;
1818 case DWC3_DEVICE_EVENT_CONNECT_DONE:
1819 dwc3_gadget_conndone_interrupt(dwc);
1820 break;
1821 case DWC3_DEVICE_EVENT_WAKEUP:
1822 dwc3_gadget_wakeup_interrupt(dwc);
1823 break;
1824 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
1825 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
1826 break;
1827 case DWC3_DEVICE_EVENT_EOPF:
1828 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
1829 break;
1830 case DWC3_DEVICE_EVENT_SOF:
1831 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
1832 break;
1833 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
1834 dev_vdbg(dwc->dev, "Erratic Error\n");
1835 break;
1836 case DWC3_DEVICE_EVENT_CMD_CMPL:
1837 dev_vdbg(dwc->dev, "Command Complete\n");
1838 break;
1839 case DWC3_DEVICE_EVENT_OVERFLOW:
1840 dev_vdbg(dwc->dev, "Overflow\n");
1841 break;
1842 default:
1843 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
1844 }
1845 }
1846
1847 static void dwc3_process_event_entry(struct dwc3 *dwc,
1848 const union dwc3_event *event)
1849 {
1850 /* Endpoint IRQ, handle it and return early */
1851 if (event->type.is_devspec == 0) {
1852 /* depevt */
1853 return dwc3_endpoint_interrupt(dwc, &event->depevt);
1854 }
1855
1856 switch (event->type.type) {
1857 case DWC3_EVENT_TYPE_DEV:
1858 dwc3_gadget_interrupt(dwc, &event->devt);
1859 break;
1860 /* REVISIT what to do with Carkit and I2C events ? */
1861 default:
1862 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
1863 }
1864 }
1865
1866 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
1867 {
1868 struct dwc3_event_buffer *evt;
1869 int left;
1870 u32 count;
1871
1872 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
1873 count &= DWC3_GEVNTCOUNT_MASK;
1874 if (!count)
1875 return IRQ_NONE;
1876
1877 evt = dwc->ev_buffs[buf];
1878 left = count;
1879
1880 while (left > 0) {
1881 union dwc3_event event;
1882
1883 memcpy(&event.raw, (evt->buf + evt->lpos), sizeof(event.raw));
1884 dwc3_process_event_entry(dwc, &event);
1885 /*
1886 * XXX we wrap around correctly to the next entry as almost all
1887 * entries are 4 bytes in size. There is one entry which has 12
1888 * bytes which is a regular entry followed by 8 bytes data. ATM
1889 * I don't know how things are organized if were get next to the
1890 * a boundary so I worry about that once we try to handle that.
1891 */
1892 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
1893 left -= 4;
1894
1895 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
1896 }
1897
1898 return IRQ_HANDLED;
1899 }
1900
1901 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
1902 {
1903 struct dwc3 *dwc = _dwc;
1904 int i;
1905 irqreturn_t ret = IRQ_NONE;
1906
1907 spin_lock(&dwc->lock);
1908
1909 for (i = 0; i < DWC3_EVENT_BUFFERS_NUM; i++) {
1910 irqreturn_t status;
1911
1912 status = dwc3_process_event_buf(dwc, i);
1913 if (status == IRQ_HANDLED)
1914 ret = status;
1915 }
1916
1917 spin_unlock(&dwc->lock);
1918
1919 return ret;
1920 }
1921
1922 /**
1923 * dwc3_gadget_init - Initializes gadget related registers
1924 * @dwc: Pointer to out controller context structure
1925 *
1926 * Returns 0 on success otherwise negative errno.
1927 */
1928 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
1929 {
1930 u32 reg;
1931 int ret;
1932 int irq;
1933
1934 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
1935 &dwc->ctrl_req_addr, GFP_KERNEL);
1936 if (!dwc->ctrl_req) {
1937 dev_err(dwc->dev, "failed to allocate ctrl request\n");
1938 ret = -ENOMEM;
1939 goto err0;
1940 }
1941
1942 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
1943 &dwc->ep0_trb_addr, GFP_KERNEL);
1944 if (!dwc->ep0_trb) {
1945 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
1946 ret = -ENOMEM;
1947 goto err1;
1948 }
1949
1950 dwc->setup_buf = dma_alloc_coherent(dwc->dev,
1951 sizeof(*dwc->setup_buf) * 2,
1952 &dwc->setup_buf_addr, GFP_KERNEL);
1953 if (!dwc->setup_buf) {
1954 dev_err(dwc->dev, "failed to allocate setup buffer\n");
1955 ret = -ENOMEM;
1956 goto err2;
1957 }
1958
1959 dev_set_name(&dwc->gadget.dev, "gadget");
1960
1961 dwc->gadget.ops = &dwc3_gadget_ops;
1962 dwc->gadget.is_dualspeed = true;
1963 dwc->gadget.speed = USB_SPEED_UNKNOWN;
1964 dwc->gadget.dev.parent = dwc->dev;
1965
1966 dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
1967
1968 dwc->gadget.dev.dma_parms = dwc->dev->dma_parms;
1969 dwc->gadget.dev.dma_mask = dwc->dev->dma_mask;
1970 dwc->gadget.dev.release = dwc3_gadget_release;
1971 dwc->gadget.name = "dwc3-gadget";
1972
1973 /*
1974 * REVISIT: Here we should clear all pending IRQs to be
1975 * sure we're starting from a well known location.
1976 */
1977
1978 ret = dwc3_gadget_init_endpoints(dwc);
1979 if (ret)
1980 goto err3;
1981
1982 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1983
1984 ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
1985 "dwc3", dwc);
1986 if (ret) {
1987 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1988 irq, ret);
1989 goto err4;
1990 }
1991
1992 /* Enable all but Start and End of Frame IRQs */
1993 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1994 DWC3_DEVTEN_EVNTOVERFLOWEN |
1995 DWC3_DEVTEN_CMDCMPLTEN |
1996 DWC3_DEVTEN_ERRTICERREN |
1997 DWC3_DEVTEN_WKUPEVTEN |
1998 DWC3_DEVTEN_ULSTCNGEN |
1999 DWC3_DEVTEN_CONNECTDONEEN |
2000 DWC3_DEVTEN_USBRSTEN |
2001 DWC3_DEVTEN_DISCONNEVTEN);
2002 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2003
2004 ret = device_register(&dwc->gadget.dev);
2005 if (ret) {
2006 dev_err(dwc->dev, "failed to register gadget device\n");
2007 put_device(&dwc->gadget.dev);
2008 goto err5;
2009 }
2010
2011 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2012 if (ret) {
2013 dev_err(dwc->dev, "failed to register udc\n");
2014 goto err6;
2015 }
2016
2017 return 0;
2018
2019 err6:
2020 device_unregister(&dwc->gadget.dev);
2021
2022 err5:
2023 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2024 free_irq(irq, dwc);
2025
2026 err4:
2027 dwc3_gadget_free_endpoints(dwc);
2028
2029 err3:
2030 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2031 dwc->setup_buf, dwc->setup_buf_addr);
2032
2033 err2:
2034 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2035 dwc->ep0_trb, dwc->ep0_trb_addr);
2036
2037 err1:
2038 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2039 dwc->ctrl_req, dwc->ctrl_req_addr);
2040
2041 err0:
2042 return ret;
2043 }
2044
2045 void dwc3_gadget_exit(struct dwc3 *dwc)
2046 {
2047 int irq;
2048 int i;
2049
2050 usb_del_gadget_udc(&dwc->gadget);
2051 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2052
2053 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2054 free_irq(irq, dwc);
2055
2056 for (i = 0; i < ARRAY_SIZE(dwc->eps); i++)
2057 __dwc3_gadget_ep_disable(dwc->eps[i]);
2058
2059 dwc3_gadget_free_endpoints(dwc);
2060
2061 dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2062 dwc->setup_buf, dwc->setup_buf_addr);
2063
2064 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2065 dwc->ep0_trb, dwc->ep0_trb_addr);
2066
2067 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2068 dwc->ctrl_req, dwc->ctrl_req_addr);
2069
2070 device_unregister(&dwc->gadget.dev);
2071 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree