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lib/list_sort: test: unify test messages
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / spi / spi_bfin5xx.c
blobab483a0ec6d05b7738ab85aed075ee0a293598bf
1 /*
2 * Blackfin On-Chip SPI Driver
3 *
4 * Copyright 2004-2010 Analog Devices Inc.
5 *
6 * Enter bugs at http://blackfin.uclinux.org/
7 *
8 * Licensed under the GPL-2 or later.
9 */
10
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
16 #include <linux/io.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/dma.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
30
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
35
36 MODULE_AUTHOR(DRV_AUTHOR);
37 MODULE_DESCRIPTION(DRV_DESC);
38 MODULE_LICENSE("GPL");
39
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
44
45 struct bfin_spi_master_data;
46
47 struct bfin_spi_transfer_ops {
48 void (*write) (struct bfin_spi_master_data *);
49 void (*read) (struct bfin_spi_master_data *);
50 void (*duplex) (struct bfin_spi_master_data *);
51 };
52
53 struct bfin_spi_master_data {
54 /* Driver model hookup */
55 struct platform_device *pdev;
56
57 /* SPI framework hookup */
58 struct spi_master *master;
59
60 /* Regs base of SPI controller */
61 void __iomem *regs_base;
62
63 /* Pin request list */
64 u16 *pin_req;
65
66 /* BFIN hookup */
67 struct bfin5xx_spi_master *master_info;
68
69 /* Driver message queue */
70 struct workqueue_struct *workqueue;
71 struct work_struct pump_messages;
72 spinlock_t lock;
73 struct list_head queue;
74 int busy;
75 bool running;
76
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers;
79
80 /* Current message transfer state info */
81 struct spi_message *cur_msg;
82 struct spi_transfer *cur_transfer;
83 struct bfin_spi_slave_data *cur_chip;
84 size_t len_in_bytes;
85 size_t len;
86 void *tx;
87 void *tx_end;
88 void *rx;
89 void *rx_end;
90
91 /* DMA stuffs */
92 int dma_channel;
93 int dma_mapped;
94 int dma_requested;
95 dma_addr_t rx_dma;
96 dma_addr_t tx_dma;
97
98 int irq_requested;
99 int spi_irq;
100
101 size_t rx_map_len;
102 size_t tx_map_len;
103 u8 n_bytes;
104 u16 ctrl_reg;
105 u16 flag_reg;
106
107 int cs_change;
108 const struct bfin_spi_transfer_ops *ops;
109 };
110
111 struct bfin_spi_slave_data {
112 u16 ctl_reg;
113 u16 baud;
114 u16 flag;
115
116 u8 chip_select_num;
117 u8 enable_dma;
118 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
119 u32 cs_gpio;
120 u16 idle_tx_val;
121 u8 pio_interrupt; /* use spi data irq */
122 const struct bfin_spi_transfer_ops *ops;
123 };
124
125 #define DEFINE_SPI_REG(reg, off) \
126 static inline u16 read_##reg(struct bfin_spi_master_data *drv_data) \
127 { return bfin_read16(drv_data->regs_base + off); } \
128 static inline void write_##reg(struct bfin_spi_master_data *drv_data, u16 v) \
129 { bfin_write16(drv_data->regs_base + off, v); }
130
131 DEFINE_SPI_REG(CTRL, 0x00)
132 DEFINE_SPI_REG(FLAG, 0x04)
133 DEFINE_SPI_REG(STAT, 0x08)
134 DEFINE_SPI_REG(TDBR, 0x0C)
135 DEFINE_SPI_REG(RDBR, 0x10)
136 DEFINE_SPI_REG(BAUD, 0x14)
137 DEFINE_SPI_REG(SHAW, 0x18)
138
139 static void bfin_spi_enable(struct bfin_spi_master_data *drv_data)
140 {
141 u16 cr;
142
143 cr = read_CTRL(drv_data);
144 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
145 }
146
147 static void bfin_spi_disable(struct bfin_spi_master_data *drv_data)
148 {
149 u16 cr;
150
151 cr = read_CTRL(drv_data);
152 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
153 }
154
155 /* Caculate the SPI_BAUD register value based on input HZ */
156 static u16 hz_to_spi_baud(u32 speed_hz)
157 {
158 u_long sclk = get_sclk();
159 u16 spi_baud = (sclk / (2 * speed_hz));
160
161 if ((sclk % (2 * speed_hz)) > 0)
162 spi_baud++;
163
164 if (spi_baud < MIN_SPI_BAUD_VAL)
165 spi_baud = MIN_SPI_BAUD_VAL;
166
167 return spi_baud;
168 }
169
170 static int bfin_spi_flush(struct bfin_spi_master_data *drv_data)
171 {
172 unsigned long limit = loops_per_jiffy << 1;
173
174 /* wait for stop and clear stat */
175 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit)
176 cpu_relax();
177
178 write_STAT(drv_data, BIT_STAT_CLR);
179
180 return limit;
181 }
182
183 /* Chip select operation functions for cs_change flag */
184 static void bfin_spi_cs_active(struct bfin_spi_master_data *drv_data, struct bfin_spi_slave_data *chip)
185 {
186 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
187 u16 flag = read_FLAG(drv_data);
188
189 flag &= ~chip->flag;
190
191 write_FLAG(drv_data, flag);
192 } else {
193 gpio_set_value(chip->cs_gpio, 0);
194 }
195 }
196
197 static void bfin_spi_cs_deactive(struct bfin_spi_master_data *drv_data,
198 struct bfin_spi_slave_data *chip)
199 {
200 if (likely(chip->chip_select_num < MAX_CTRL_CS)) {
201 u16 flag = read_FLAG(drv_data);
202
203 flag |= chip->flag;
204
205 write_FLAG(drv_data, flag);
206 } else {
207 gpio_set_value(chip->cs_gpio, 1);
208 }
209
210 /* Move delay here for consistency */
211 if (chip->cs_chg_udelay)
212 udelay(chip->cs_chg_udelay);
213 }
214
215 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
216 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data *drv_data,
217 struct bfin_spi_slave_data *chip)
218 {
219 if (chip->chip_select_num < MAX_CTRL_CS) {
220 u16 flag = read_FLAG(drv_data);
221
222 flag |= (chip->flag >> 8);
223
224 write_FLAG(drv_data, flag);
225 }
226 }
227
228 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data *drv_data,
229 struct bfin_spi_slave_data *chip)
230 {
231 if (chip->chip_select_num < MAX_CTRL_CS) {
232 u16 flag = read_FLAG(drv_data);
233
234 flag &= ~(chip->flag >> 8);
235
236 write_FLAG(drv_data, flag);
237 }
238 }
239
240 /* stop controller and re-config current chip*/
241 static void bfin_spi_restore_state(struct bfin_spi_master_data *drv_data)
242 {
243 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
244
245 /* Clear status and disable clock */
246 write_STAT(drv_data, BIT_STAT_CLR);
247 bfin_spi_disable(drv_data);
248 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
249
250 SSYNC();
251
252 /* Load the registers */
253 write_CTRL(drv_data, chip->ctl_reg);
254 write_BAUD(drv_data, chip->baud);
255
256 bfin_spi_enable(drv_data);
257 bfin_spi_cs_active(drv_data, chip);
258 }
259
260 /* used to kick off transfer in rx mode and read unwanted RX data */
261 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data *drv_data)
262 {
263 (void) read_RDBR(drv_data);
264 }
265
266 static void bfin_spi_u8_writer(struct bfin_spi_master_data *drv_data)
267 {
268 /* clear RXS (we check for RXS inside the loop) */
269 bfin_spi_dummy_read(drv_data);
270
271 while (drv_data->tx < drv_data->tx_end) {
272 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
273 /* wait until transfer finished.
274 checking SPIF or TXS may not guarantee transfer completion */
275 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
276 cpu_relax();
277 /* discard RX data and clear RXS */
278 bfin_spi_dummy_read(drv_data);
279 }
280 }
281
282 static void bfin_spi_u8_reader(struct bfin_spi_master_data *drv_data)
283 {
284 u16 tx_val = drv_data->cur_chip->idle_tx_val;
285
286 /* discard old RX data and clear RXS */
287 bfin_spi_dummy_read(drv_data);
288
289 while (drv_data->rx < drv_data->rx_end) {
290 write_TDBR(drv_data, tx_val);
291 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
292 cpu_relax();
293 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
294 }
295 }
296
297 static void bfin_spi_u8_duplex(struct bfin_spi_master_data *drv_data)
298 {
299 /* discard old RX data and clear RXS */
300 bfin_spi_dummy_read(drv_data);
301
302 while (drv_data->rx < drv_data->rx_end) {
303 write_TDBR(drv_data, (*(u8 *) (drv_data->tx++)));
304 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
305 cpu_relax();
306 *(u8 *) (drv_data->rx++) = read_RDBR(drv_data);
307 }
308 }
309
310 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8 = {
311 .write = bfin_spi_u8_writer,
312 .read = bfin_spi_u8_reader,
313 .duplex = bfin_spi_u8_duplex,
314 };
315
316 static void bfin_spi_u16_writer(struct bfin_spi_master_data *drv_data)
317 {
318 /* clear RXS (we check for RXS inside the loop) */
319 bfin_spi_dummy_read(drv_data);
320
321 while (drv_data->tx < drv_data->tx_end) {
322 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
323 drv_data->tx += 2;
324 /* wait until transfer finished.
325 checking SPIF or TXS may not guarantee transfer completion */
326 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
327 cpu_relax();
328 /* discard RX data and clear RXS */
329 bfin_spi_dummy_read(drv_data);
330 }
331 }
332
333 static void bfin_spi_u16_reader(struct bfin_spi_master_data *drv_data)
334 {
335 u16 tx_val = drv_data->cur_chip->idle_tx_val;
336
337 /* discard old RX data and clear RXS */
338 bfin_spi_dummy_read(drv_data);
339
340 while (drv_data->rx < drv_data->rx_end) {
341 write_TDBR(drv_data, tx_val);
342 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
343 cpu_relax();
344 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
345 drv_data->rx += 2;
346 }
347 }
348
349 static void bfin_spi_u16_duplex(struct bfin_spi_master_data *drv_data)
350 {
351 /* discard old RX data and clear RXS */
352 bfin_spi_dummy_read(drv_data);
353
354 while (drv_data->rx < drv_data->rx_end) {
355 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
356 drv_data->tx += 2;
357 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
358 cpu_relax();
359 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
360 drv_data->rx += 2;
361 }
362 }
363
364 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16 = {
365 .write = bfin_spi_u16_writer,
366 .read = bfin_spi_u16_reader,
367 .duplex = bfin_spi_u16_duplex,
368 };
369
370 /* test if there is more transfer to be done */
371 static void *bfin_spi_next_transfer(struct bfin_spi_master_data *drv_data)
372 {
373 struct spi_message *msg = drv_data->cur_msg;
374 struct spi_transfer *trans = drv_data->cur_transfer;
375
376 /* Move to next transfer */
377 if (trans->transfer_list.next != &msg->transfers) {
378 drv_data->cur_transfer =
379 list_entry(trans->transfer_list.next,
380 struct spi_transfer, transfer_list);
381 return RUNNING_STATE;
382 } else
383 return DONE_STATE;
384 }
385
386 /*
387 * caller already set message->status;
388 * dma and pio irqs are blocked give finished message back
389 */
390 static void bfin_spi_giveback(struct bfin_spi_master_data *drv_data)
391 {
392 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
393 struct spi_transfer *last_transfer;
394 unsigned long flags;
395 struct spi_message *msg;
396
397 spin_lock_irqsave(&drv_data->lock, flags);
398 msg = drv_data->cur_msg;
399 drv_data->cur_msg = NULL;
400 drv_data->cur_transfer = NULL;
401 drv_data->cur_chip = NULL;
402 queue_work(drv_data->workqueue, &drv_data->pump_messages);
403 spin_unlock_irqrestore(&drv_data->lock, flags);
404
405 last_transfer = list_entry(msg->transfers.prev,
406 struct spi_transfer, transfer_list);
407
408 msg->state = NULL;
409
410 if (!drv_data->cs_change)
411 bfin_spi_cs_deactive(drv_data, chip);
412
413 /* Not stop spi in autobuffer mode */
414 if (drv_data->tx_dma != 0xFFFF)
415 bfin_spi_disable(drv_data);
416
417 if (msg->complete)
418 msg->complete(msg->context);
419 }
420
421 /* spi data irq handler */
422 static irqreturn_t bfin_spi_pio_irq_handler(int irq, void *dev_id)
423 {
424 struct bfin_spi_master_data *drv_data = dev_id;
425 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
426 struct spi_message *msg = drv_data->cur_msg;
427 int n_bytes = drv_data->n_bytes;
428
429 /* wait until transfer finished. */
430 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
431 cpu_relax();
432
433 if ((drv_data->tx && drv_data->tx >= drv_data->tx_end) ||
434 (drv_data->rx && drv_data->rx >= (drv_data->rx_end - n_bytes))) {
435 /* last read */
436 if (drv_data->rx) {
437 dev_dbg(&drv_data->pdev->dev, "last read\n");
438 if (n_bytes == 2)
439 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
440 else if (n_bytes == 1)
441 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
442 drv_data->rx += n_bytes;
443 }
444
445 msg->actual_length += drv_data->len_in_bytes;
446 if (drv_data->cs_change)
447 bfin_spi_cs_deactive(drv_data, chip);
448 /* Move to next transfer */
449 msg->state = bfin_spi_next_transfer(drv_data);
450
451 disable_irq_nosync(drv_data->spi_irq);
452
453 /* Schedule transfer tasklet */
454 tasklet_schedule(&drv_data->pump_transfers);
455 return IRQ_HANDLED;
456 }
457
458 if (drv_data->rx && drv_data->tx) {
459 /* duplex */
460 dev_dbg(&drv_data->pdev->dev, "duplex: write_TDBR\n");
461 if (drv_data->n_bytes == 2) {
462 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
463 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
464 } else if (drv_data->n_bytes == 1) {
465 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
466 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
467 }
468 } else if (drv_data->rx) {
469 /* read */
470 dev_dbg(&drv_data->pdev->dev, "read: write_TDBR\n");
471 if (drv_data->n_bytes == 2)
472 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
473 else if (drv_data->n_bytes == 1)
474 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
475 write_TDBR(drv_data, chip->idle_tx_val);
476 } else if (drv_data->tx) {
477 /* write */
478 dev_dbg(&drv_data->pdev->dev, "write: write_TDBR\n");
479 bfin_spi_dummy_read(drv_data);
480 if (drv_data->n_bytes == 2)
481 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
482 else if (drv_data->n_bytes == 1)
483 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
484 }
485
486 if (drv_data->tx)
487 drv_data->tx += n_bytes;
488 if (drv_data->rx)
489 drv_data->rx += n_bytes;
490
491 return IRQ_HANDLED;
492 }
493
494 static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id)
495 {
496 struct bfin_spi_master_data *drv_data = dev_id;
497 struct bfin_spi_slave_data *chip = drv_data->cur_chip;
498 struct spi_message *msg = drv_data->cur_msg;
499 unsigned long timeout;
500 unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel);
501 u16 spistat = read_STAT(drv_data);
502
503 dev_dbg(&drv_data->pdev->dev,
504 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
505 dmastat, spistat);
506
507 clear_dma_irqstat(drv_data->dma_channel);
508
509 /*
510 * wait for the last transaction shifted out. HRM states:
511 * at this point there may still be data in the SPI DMA FIFO waiting
512 * to be transmitted ... software needs to poll TXS in the SPI_STAT
513 * register until it goes low for 2 successive reads
514 */
515 if (drv_data->tx != NULL) {
516 while ((read_STAT(drv_data) & BIT_STAT_TXS) ||
517 (read_STAT(drv_data) & BIT_STAT_TXS))
518 cpu_relax();
519 }
520
521 dev_dbg(&drv_data->pdev->dev,
522 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
523 dmastat, read_STAT(drv_data));
524
525 timeout = jiffies + HZ;
526 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
527 if (!time_before(jiffies, timeout)) {
528 dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF");
529 break;
530 } else
531 cpu_relax();
532
533 if ((dmastat & DMA_ERR) && (spistat & BIT_STAT_RBSY)) {
534 msg->state = ERROR_STATE;
535 dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n");
536 } else {
537 msg->actual_length += drv_data->len_in_bytes;
538
539 if (drv_data->cs_change)
540 bfin_spi_cs_deactive(drv_data, chip);
541
542 /* Move to next transfer */
543 msg->state = bfin_spi_next_transfer(drv_data);
544 }
545
546 /* Schedule transfer tasklet */
547 tasklet_schedule(&drv_data->pump_transfers);
548
549 /* free the irq handler before next transfer */
550 dev_dbg(&drv_data->pdev->dev,
551 "disable dma channel irq%d\n",
552 drv_data->dma_channel);
553 dma_disable_irq_nosync(drv_data->dma_channel);
554
555 return IRQ_HANDLED;
556 }
557
558 static void bfin_spi_pump_transfers(unsigned long data)
559 {
560 struct bfin_spi_master_data *drv_data = (struct bfin_spi_master_data *)data;
561 struct spi_message *message = NULL;
562 struct spi_transfer *transfer = NULL;
563 struct spi_transfer *previous = NULL;
564 struct bfin_spi_slave_data *chip = NULL;
565 unsigned int bits_per_word;
566 u16 cr, cr_width, dma_width, dma_config;
567 u32 tranf_success = 1;
568 u8 full_duplex = 0;
569
570 /* Get current state information */
571 message = drv_data->cur_msg;
572 transfer = drv_data->cur_transfer;
573 chip = drv_data->cur_chip;
574
575 /*
576 * if msg is error or done, report it back using complete() callback
577 */
578
579 /* Handle for abort */
580 if (message->state == ERROR_STATE) {
581 dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n");
582 message->status = -EIO;
583 bfin_spi_giveback(drv_data);
584 return;
585 }
586
587 /* Handle end of message */
588 if (message->state == DONE_STATE) {
589 dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n");
590 message->status = 0;
591 bfin_spi_giveback(drv_data);
592 return;
593 }
594
595 /* Delay if requested at end of transfer */
596 if (message->state == RUNNING_STATE) {
597 dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n");
598 previous = list_entry(transfer->transfer_list.prev,
599 struct spi_transfer, transfer_list);
600 if (previous->delay_usecs)
601 udelay(previous->delay_usecs);
602 }
603
604 /* Flush any existing transfers that may be sitting in the hardware */
605 if (bfin_spi_flush(drv_data) == 0) {
606 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
607 message->status = -EIO;
608 bfin_spi_giveback(drv_data);
609 return;
610 }
611
612 if (transfer->len == 0) {
613 /* Move to next transfer of this msg */
614 message->state = bfin_spi_next_transfer(drv_data);
615 /* Schedule next transfer tasklet */
616 tasklet_schedule(&drv_data->pump_transfers);
617 }
618
619 if (transfer->tx_buf != NULL) {
620 drv_data->tx = (void *)transfer->tx_buf;
621 drv_data->tx_end = drv_data->tx + transfer->len;
622 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
623 transfer->tx_buf, drv_data->tx_end);
624 } else {
625 drv_data->tx = NULL;
626 }
627
628 if (transfer->rx_buf != NULL) {
629 full_duplex = transfer->tx_buf != NULL;
630 drv_data->rx = transfer->rx_buf;
631 drv_data->rx_end = drv_data->rx + transfer->len;
632 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
633 transfer->rx_buf, drv_data->rx_end);
634 } else {
635 drv_data->rx = NULL;
636 }
637
638 drv_data->rx_dma = transfer->rx_dma;
639 drv_data->tx_dma = transfer->tx_dma;
640 drv_data->len_in_bytes = transfer->len;
641 drv_data->cs_change = transfer->cs_change;
642
643 /* Bits per word setup */
644 bits_per_word = transfer->bits_per_word ? : message->spi->bits_per_word;
645 if (bits_per_word == 8) {
646 drv_data->n_bytes = 1;
647 drv_data->len = transfer->len;
648 cr_width = 0;
649 drv_data->ops = &bfin_bfin_spi_transfer_ops_u8;
650 } else if (bits_per_word == 16) {
651 drv_data->n_bytes = 2;
652 drv_data->len = (transfer->len) >> 1;
653 cr_width = BIT_CTL_WORDSIZE;
654 drv_data->ops = &bfin_bfin_spi_transfer_ops_u16;
655 } else {
656 dev_err(&drv_data->pdev->dev, "transfer: unsupported bits_per_word\n");
657 message->status = -EINVAL;
658 bfin_spi_giveback(drv_data);
659 return;
660 }
661 cr = read_CTRL(drv_data) & ~(BIT_CTL_TIMOD | BIT_CTL_WORDSIZE);
662 cr |= cr_width;
663 write_CTRL(drv_data, cr);
664
665 dev_dbg(&drv_data->pdev->dev,
666 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
667 drv_data->ops, chip->ops, &bfin_bfin_spi_transfer_ops_u8);
668
669 message->state = RUNNING_STATE;
670 dma_config = 0;
671
672 /* Speed setup (surely valid because already checked) */
673 if (transfer->speed_hz)
674 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
675 else
676 write_BAUD(drv_data, chip->baud);
677
678 write_STAT(drv_data, BIT_STAT_CLR);
679 bfin_spi_cs_active(drv_data, chip);
680
681 dev_dbg(&drv_data->pdev->dev,
682 "now pumping a transfer: width is %d, len is %d\n",
683 cr_width, transfer->len);
684
685 /*
686 * Try to map dma buffer and do a dma transfer. If successful use,
687 * different way to r/w according to the enable_dma settings and if
688 * we are not doing a full duplex transfer (since the hardware does
689 * not support full duplex DMA transfers).
690 */
691 if (!full_duplex && drv_data->cur_chip->enable_dma
692 && drv_data->len > 6) {
693
694 unsigned long dma_start_addr, flags;
695
696 disable_dma(drv_data->dma_channel);
697 clear_dma_irqstat(drv_data->dma_channel);
698
699 /* config dma channel */
700 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
701 set_dma_x_count(drv_data->dma_channel, drv_data->len);
702 if (cr_width == BIT_CTL_WORDSIZE) {
703 set_dma_x_modify(drv_data->dma_channel, 2);
704 dma_width = WDSIZE_16;
705 } else {
706 set_dma_x_modify(drv_data->dma_channel, 1);
707 dma_width = WDSIZE_8;
708 }
709
710 /* poll for SPI completion before start */
711 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
712 cpu_relax();
713
714 /* dirty hack for autobuffer DMA mode */
715 if (drv_data->tx_dma == 0xFFFF) {
716 dev_dbg(&drv_data->pdev->dev,
717 "doing autobuffer DMA out.\n");
718
719 /* no irq in autobuffer mode */
720 dma_config =
721 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
722 set_dma_config(drv_data->dma_channel, dma_config);
723 set_dma_start_addr(drv_data->dma_channel,
724 (unsigned long)drv_data->tx);
725 enable_dma(drv_data->dma_channel);
726
727 /* start SPI transfer */
728 write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX);
729
730 /* just return here, there can only be one transfer
731 * in this mode
732 */
733 message->status = 0;
734 bfin_spi_giveback(drv_data);
735 return;
736 }
737
738 /* In dma mode, rx or tx must be NULL in one transfer */
739 dma_config = (RESTART | dma_width | DI_EN);
740 if (drv_data->rx != NULL) {
741 /* set transfer mode, and enable SPI */
742 dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n",
743 drv_data->rx, drv_data->len_in_bytes);
744
745 /* invalidate caches, if needed */
746 if (bfin_addr_dcacheable((unsigned long) drv_data->rx))
747 invalidate_dcache_range((unsigned long) drv_data->rx,
748 (unsigned long) (drv_data->rx +
749 drv_data->len_in_bytes));
750
751 dma_config |= WNR;
752 dma_start_addr = (unsigned long)drv_data->rx;
753 cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT;
754
755 } else if (drv_data->tx != NULL) {
756 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
757
758 /* flush caches, if needed */
759 if (bfin_addr_dcacheable((unsigned long) drv_data->tx))
760 flush_dcache_range((unsigned long) drv_data->tx,
761 (unsigned long) (drv_data->tx +
762 drv_data->len_in_bytes));
763
764 dma_start_addr = (unsigned long)drv_data->tx;
765 cr |= BIT_CTL_TIMOD_DMA_TX;
766
767 } else
768 BUG();
769
770 /* oh man, here there be monsters ... and i dont mean the
771 * fluffy cute ones from pixar, i mean the kind that'll eat
772 * your data, kick your dog, and love it all. do *not* try
773 * and change these lines unless you (1) heavily test DMA
774 * with SPI flashes on a loaded system (e.g. ping floods),
775 * (2) know just how broken the DMA engine interaction with
776 * the SPI peripheral is, and (3) have someone else to blame
777 * when you screw it all up anyways.
778 */
779 set_dma_start_addr(drv_data->dma_channel, dma_start_addr);
780 set_dma_config(drv_data->dma_channel, dma_config);
781 local_irq_save(flags);
782 SSYNC();
783 write_CTRL(drv_data, cr);
784 enable_dma(drv_data->dma_channel);
785 dma_enable_irq(drv_data->dma_channel);
786 local_irq_restore(flags);
787
788 return;
789 }
790
791 /*
792 * We always use SPI_WRITE mode (transfer starts with TDBR write).
793 * SPI_READ mode (transfer starts with RDBR read) seems to have
794 * problems with setting up the output value in TDBR prior to the
795 * start of the transfer.
796 */
797 write_CTRL(drv_data, cr | BIT_CTL_TXMOD);
798
799 if (chip->pio_interrupt) {
800 /* SPI irq should have been disabled by now */
801
802 /* discard old RX data and clear RXS */
803 bfin_spi_dummy_read(drv_data);
804
805 /* start transfer */
806 if (drv_data->tx == NULL)
807 write_TDBR(drv_data, chip->idle_tx_val);
808 else {
809 if (bits_per_word == 8)
810 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
811 else
812 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
813 drv_data->tx += drv_data->n_bytes;
814 }
815
816 /* once TDBR is empty, interrupt is triggered */
817 enable_irq(drv_data->spi_irq);
818 return;
819 }
820
821 /* IO mode */
822 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
823
824 if (full_duplex) {
825 /* full duplex mode */
826 BUG_ON((drv_data->tx_end - drv_data->tx) !=
827 (drv_data->rx_end - drv_data->rx));
828 dev_dbg(&drv_data->pdev->dev,
829 "IO duplex: cr is 0x%x\n", cr);
830
831 drv_data->ops->duplex(drv_data);
832
833 if (drv_data->tx != drv_data->tx_end)
834 tranf_success = 0;
835 } else if (drv_data->tx != NULL) {
836 /* write only half duplex */
837 dev_dbg(&drv_data->pdev->dev,
838 "IO write: cr is 0x%x\n", cr);
839
840 drv_data->ops->write(drv_data);
841
842 if (drv_data->tx != drv_data->tx_end)
843 tranf_success = 0;
844 } else if (drv_data->rx != NULL) {
845 /* read only half duplex */
846 dev_dbg(&drv_data->pdev->dev,
847 "IO read: cr is 0x%x\n", cr);
848
849 drv_data->ops->read(drv_data);
850 if (drv_data->rx != drv_data->rx_end)
851 tranf_success = 0;
852 }
853
854 if (!tranf_success) {
855 dev_dbg(&drv_data->pdev->dev,
856 "IO write error!\n");
857 message->state = ERROR_STATE;
858 } else {
859 /* Update total byte transfered */
860 message->actual_length += drv_data->len_in_bytes;
861 /* Move to next transfer of this msg */
862 message->state = bfin_spi_next_transfer(drv_data);
863 if (drv_data->cs_change)
864 bfin_spi_cs_deactive(drv_data, chip);
865 }
866
867 /* Schedule next transfer tasklet */
868 tasklet_schedule(&drv_data->pump_transfers);
869 }
870
871 /* pop a msg from queue and kick off real transfer */
872 static void bfin_spi_pump_messages(struct work_struct *work)
873 {
874 struct bfin_spi_master_data *drv_data;
875 unsigned long flags;
876
877 drv_data = container_of(work, struct bfin_spi_master_data, pump_messages);
878
879 /* Lock queue and check for queue work */
880 spin_lock_irqsave(&drv_data->lock, flags);
881 if (list_empty(&drv_data->queue) || !drv_data->running) {
882 /* pumper kicked off but no work to do */
883 drv_data->busy = 0;
884 spin_unlock_irqrestore(&drv_data->lock, flags);
885 return;
886 }
887
888 /* Make sure we are not already running a message */
889 if (drv_data->cur_msg) {
890 spin_unlock_irqrestore(&drv_data->lock, flags);
891 return;
892 }
893
894 /* Extract head of queue */
895 drv_data->cur_msg = list_entry(drv_data->queue.next,
896 struct spi_message, queue);
897
898 /* Setup the SSP using the per chip configuration */
899 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
900 bfin_spi_restore_state(drv_data);
901
902 list_del_init(&drv_data->cur_msg->queue);
903
904 /* Initial message state */
905 drv_data->cur_msg->state = START_STATE;
906 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
907 struct spi_transfer, transfer_list);
908
909 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
910 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
911 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
912 drv_data->cur_chip->ctl_reg);
913
914 dev_dbg(&drv_data->pdev->dev,
915 "the first transfer len is %d\n",
916 drv_data->cur_transfer->len);
917
918 /* Mark as busy and launch transfers */
919 tasklet_schedule(&drv_data->pump_transfers);
920
921 drv_data->busy = 1;
922 spin_unlock_irqrestore(&drv_data->lock, flags);
923 }
924
925 /*
926 * got a msg to transfer, queue it in drv_data->queue.
927 * And kick off message pumper
928 */
929 static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg)
930 {
931 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
932 unsigned long flags;
933
934 spin_lock_irqsave(&drv_data->lock, flags);
935
936 if (!drv_data->running) {
937 spin_unlock_irqrestore(&drv_data->lock, flags);
938 return -ESHUTDOWN;
939 }
940
941 msg->actual_length = 0;
942 msg->status = -EINPROGRESS;
943 msg->state = START_STATE;
944
945 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
946 list_add_tail(&msg->queue, &drv_data->queue);
947
948 if (drv_data->running && !drv_data->busy)
949 queue_work(drv_data->workqueue, &drv_data->pump_messages);
950
951 spin_unlock_irqrestore(&drv_data->lock, flags);
952
953 return 0;
954 }
955
956 #define MAX_SPI_SSEL 7
957
958 static u16 ssel[][MAX_SPI_SSEL] = {
959 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
960 P_SPI0_SSEL4, P_SPI0_SSEL5,
961 P_SPI0_SSEL6, P_SPI0_SSEL7},
962
963 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
964 P_SPI1_SSEL4, P_SPI1_SSEL5,
965 P_SPI1_SSEL6, P_SPI1_SSEL7},
966
967 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
968 P_SPI2_SSEL4, P_SPI2_SSEL5,
969 P_SPI2_SSEL6, P_SPI2_SSEL7},
970 };
971
972 /* setup for devices (may be called multiple times -- not just first setup) */
973 static int bfin_spi_setup(struct spi_device *spi)
974 {
975 struct bfin5xx_spi_chip *chip_info;
976 struct bfin_spi_slave_data *chip = NULL;
977 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
978 u16 bfin_ctl_reg;
979 int ret = -EINVAL;
980
981 /* Only alloc (or use chip_info) on first setup */
982 chip_info = NULL;
983 chip = spi_get_ctldata(spi);
984 if (chip == NULL) {
985 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
986 if (!chip) {
987 dev_err(&spi->dev, "cannot allocate chip data\n");
988 ret = -ENOMEM;
989 goto error;
990 }
991
992 chip->enable_dma = 0;
993 chip_info = spi->controller_data;
994 }
995
996 /* Let people set non-standard bits directly */
997 bfin_ctl_reg = BIT_CTL_OPENDRAIN | BIT_CTL_EMISO |
998 BIT_CTL_PSSE | BIT_CTL_GM | BIT_CTL_SZ;
999
1000 /* chip_info isn't always needed */
1001 if (chip_info) {
1002 /* Make sure people stop trying to set fields via ctl_reg
1003 * when they should actually be using common SPI framework.
1004 * Currently we let through: WOM EMISO PSSE GM SZ.
1005 * Not sure if a user actually needs/uses any of these,
1006 * but let's assume (for now) they do.
1007 */
1008 if (chip_info->ctl_reg & ~bfin_ctl_reg) {
1009 dev_err(&spi->dev, "do not set bits in ctl_reg "
1010 "that the SPI framework manages\n");
1011 goto error;
1012 }
1013 chip->enable_dma = chip_info->enable_dma != 0
1014 && drv_data->master_info->enable_dma;
1015 chip->ctl_reg = chip_info->ctl_reg;
1016 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1017 chip->idle_tx_val = chip_info->idle_tx_val;
1018 chip->pio_interrupt = chip_info->pio_interrupt;
1019 spi->bits_per_word = chip_info->bits_per_word;
1020 } else {
1021 /* force a default base state */
1022 chip->ctl_reg &= bfin_ctl_reg;
1023 }
1024
1025 if (spi->bits_per_word != 8 && spi->bits_per_word != 16) {
1026 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1027 spi->bits_per_word);
1028 goto error;
1029 }
1030
1031 /* translate common spi framework into our register */
1032 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1033 dev_err(&spi->dev, "unsupported spi modes detected\n");
1034 goto error;
1035 }
1036 if (spi->mode & SPI_CPOL)
1037 chip->ctl_reg |= BIT_CTL_CPOL;
1038 if (spi->mode & SPI_CPHA)
1039 chip->ctl_reg |= BIT_CTL_CPHA;
1040 if (spi->mode & SPI_LSB_FIRST)
1041 chip->ctl_reg |= BIT_CTL_LSBF;
1042 /* we dont support running in slave mode (yet?) */
1043 chip->ctl_reg |= BIT_CTL_MASTER;
1044
1045 /*
1046 * Notice: for blackfin, the speed_hz is the value of register
1047 * SPI_BAUD, not the real baudrate
1048 */
1049 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1050 chip->chip_select_num = spi->chip_select;
1051 if (chip->chip_select_num < MAX_CTRL_CS) {
1052 if (!(spi->mode & SPI_CPHA))
1053 dev_warn(&spi->dev, "Warning: SPI CPHA not set:"
1054 " Slave Select not under software control!\n"
1055 " See Documentation/blackfin/bfin-spi-notes.txt");
1056
1057 chip->flag = (1 << spi->chip_select) << 8;
1058 } else
1059 chip->cs_gpio = chip->chip_select_num - MAX_CTRL_CS;
1060
1061 if (chip->enable_dma && chip->pio_interrupt) {
1062 dev_err(&spi->dev, "enable_dma is set, "
1063 "do not set pio_interrupt\n");
1064 goto error;
1065 }
1066 /*
1067 * if any one SPI chip is registered and wants DMA, request the
1068 * DMA channel for it
1069 */
1070 if (chip->enable_dma && !drv_data->dma_requested) {
1071 /* register dma irq handler */
1072 ret = request_dma(drv_data->dma_channel, "BFIN_SPI_DMA");
1073 if (ret) {
1074 dev_err(&spi->dev,
1075 "Unable to request BlackFin SPI DMA channel\n");
1076 goto error;
1077 }
1078 drv_data->dma_requested = 1;
1079
1080 ret = set_dma_callback(drv_data->dma_channel,
1081 bfin_spi_dma_irq_handler, drv_data);
1082 if (ret) {
1083 dev_err(&spi->dev, "Unable to set dma callback\n");
1084 goto error;
1085 }
1086 dma_disable_irq(drv_data->dma_channel);
1087 }
1088
1089 if (chip->pio_interrupt && !drv_data->irq_requested) {
1090 ret = request_irq(drv_data->spi_irq, bfin_spi_pio_irq_handler,
1091 IRQF_DISABLED, "BFIN_SPI", drv_data);
1092 if (ret) {
1093 dev_err(&spi->dev, "Unable to register spi IRQ\n");
1094 goto error;
1095 }
1096 drv_data->irq_requested = 1;
1097 /* we use write mode, spi irq has to be disabled here */
1098 disable_irq(drv_data->spi_irq);
1099 }
1100
1101 if (chip->chip_select_num >= MAX_CTRL_CS) {
1102 ret = gpio_request(chip->cs_gpio, spi->modalias);
1103 if (ret) {
1104 dev_err(&spi->dev, "gpio_request() error\n");
1105 goto pin_error;
1106 }
1107 gpio_direction_output(chip->cs_gpio, 1);
1108 }
1109
1110 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1111 spi->modalias, spi->bits_per_word, chip->enable_dma);
1112 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1113 chip->ctl_reg, chip->flag);
1114
1115 spi_set_ctldata(spi, chip);
1116
1117 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1118 if (chip->chip_select_num < MAX_CTRL_CS) {
1119 ret = peripheral_request(ssel[spi->master->bus_num]
1120 [chip->chip_select_num-1], spi->modalias);
1121 if (ret) {
1122 dev_err(&spi->dev, "peripheral_request() error\n");
1123 goto pin_error;
1124 }
1125 }
1126
1127 bfin_spi_cs_enable(drv_data, chip);
1128 bfin_spi_cs_deactive(drv_data, chip);
1129
1130 return 0;
1131
1132 pin_error:
1133 if (chip->chip_select_num >= MAX_CTRL_CS)
1134 gpio_free(chip->cs_gpio);
1135 else
1136 peripheral_free(ssel[spi->master->bus_num]
1137 [chip->chip_select_num - 1]);
1138 error:
1139 if (chip) {
1140 if (drv_data->dma_requested)
1141 free_dma(drv_data->dma_channel);
1142 drv_data->dma_requested = 0;
1143
1144 kfree(chip);
1145 /* prevent free 'chip' twice */
1146 spi_set_ctldata(spi, NULL);
1147 }
1148
1149 return ret;
1150 }
1151
1152 /*
1153 * callback for spi framework.
1154 * clean driver specific data
1155 */
1156 static void bfin_spi_cleanup(struct spi_device *spi)
1157 {
1158 struct bfin_spi_slave_data *chip = spi_get_ctldata(spi);
1159 struct bfin_spi_master_data *drv_data = spi_master_get_devdata(spi->master);
1160
1161 if (!chip)
1162 return;
1163
1164 if (chip->chip_select_num < MAX_CTRL_CS) {
1165 peripheral_free(ssel[spi->master->bus_num]
1166 [chip->chip_select_num-1]);
1167 bfin_spi_cs_disable(drv_data, chip);
1168 } else
1169 gpio_free(chip->cs_gpio);
1170
1171 kfree(chip);
1172 /* prevent free 'chip' twice */
1173 spi_set_ctldata(spi, NULL);
1174 }
1175
1176 static inline int bfin_spi_init_queue(struct bfin_spi_master_data *drv_data)
1177 {
1178 INIT_LIST_HEAD(&drv_data->queue);
1179 spin_lock_init(&drv_data->lock);
1180
1181 drv_data->running = false;
1182 drv_data->busy = 0;
1183
1184 /* init transfer tasklet */
1185 tasklet_init(&drv_data->pump_transfers,
1186 bfin_spi_pump_transfers, (unsigned long)drv_data);
1187
1188 /* init messages workqueue */
1189 INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages);
1190 drv_data->workqueue = create_singlethread_workqueue(
1191 dev_name(drv_data->master->dev.parent));
1192 if (drv_data->workqueue == NULL)
1193 return -EBUSY;
1194
1195 return 0;
1196 }
1197
1198 static inline int bfin_spi_start_queue(struct bfin_spi_master_data *drv_data)
1199 {
1200 unsigned long flags;
1201
1202 spin_lock_irqsave(&drv_data->lock, flags);
1203
1204 if (drv_data->running || drv_data->busy) {
1205 spin_unlock_irqrestore(&drv_data->lock, flags);
1206 return -EBUSY;
1207 }
1208
1209 drv_data->running = true;
1210 drv_data->cur_msg = NULL;
1211 drv_data->cur_transfer = NULL;
1212 drv_data->cur_chip = NULL;
1213 spin_unlock_irqrestore(&drv_data->lock, flags);
1214
1215 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1216
1217 return 0;
1218 }
1219
1220 static inline int bfin_spi_stop_queue(struct bfin_spi_master_data *drv_data)
1221 {
1222 unsigned long flags;
1223 unsigned limit = 500;
1224 int status = 0;
1225
1226 spin_lock_irqsave(&drv_data->lock, flags);
1227
1228 /*
1229 * This is a bit lame, but is optimized for the common execution path.
1230 * A wait_queue on the drv_data->busy could be used, but then the common
1231 * execution path (pump_messages) would be required to call wake_up or
1232 * friends on every SPI message. Do this instead
1233 */
1234 drv_data->running = false;
1235 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1236 spin_unlock_irqrestore(&drv_data->lock, flags);
1237 msleep(10);
1238 spin_lock_irqsave(&drv_data->lock, flags);
1239 }
1240
1241 if (!list_empty(&drv_data->queue) || drv_data->busy)
1242 status = -EBUSY;
1243
1244 spin_unlock_irqrestore(&drv_data->lock, flags);
1245
1246 return status;
1247 }
1248
1249 static inline int bfin_spi_destroy_queue(struct bfin_spi_master_data *drv_data)
1250 {
1251 int status;
1252
1253 status = bfin_spi_stop_queue(drv_data);
1254 if (status != 0)
1255 return status;
1256
1257 destroy_workqueue(drv_data->workqueue);
1258
1259 return 0;
1260 }
1261
1262 static int __init bfin_spi_probe(struct platform_device *pdev)
1263 {
1264 struct device *dev = &pdev->dev;
1265 struct bfin5xx_spi_master *platform_info;
1266 struct spi_master *master;
1267 struct bfin_spi_master_data *drv_data;
1268 struct resource *res;
1269 int status = 0;
1270
1271 platform_info = dev->platform_data;
1272
1273 /* Allocate master with space for drv_data */
1274 master = spi_alloc_master(dev, sizeof(*drv_data));
1275 if (!master) {
1276 dev_err(&pdev->dev, "can not alloc spi_master\n");
1277 return -ENOMEM;
1278 }
1279
1280 drv_data = spi_master_get_devdata(master);
1281 drv_data->master = master;
1282 drv_data->master_info = platform_info;
1283 drv_data->pdev = pdev;
1284 drv_data->pin_req = platform_info->pin_req;
1285
1286 /* the spi->mode bits supported by this driver: */
1287 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1288
1289 master->bus_num = pdev->id;
1290 master->num_chipselect = platform_info->num_chipselect;
1291 master->cleanup = bfin_spi_cleanup;
1292 master->setup = bfin_spi_setup;
1293 master->transfer = bfin_spi_transfer;
1294
1295 /* Find and map our resources */
1296 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1297 if (res == NULL) {
1298 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1299 status = -ENOENT;
1300 goto out_error_get_res;
1301 }
1302
1303 drv_data->regs_base = ioremap(res->start, resource_size(res));
1304 if (drv_data->regs_base == NULL) {
1305 dev_err(dev, "Cannot map IO\n");
1306 status = -ENXIO;
1307 goto out_error_ioremap;
1308 }
1309
1310 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1311 if (res == NULL) {
1312 dev_err(dev, "No DMA channel specified\n");
1313 status = -ENOENT;
1314 goto out_error_free_io;
1315 }
1316 drv_data->dma_channel = res->start;
1317
1318 drv_data->spi_irq = platform_get_irq(pdev, 0);
1319 if (drv_data->spi_irq < 0) {
1320 dev_err(dev, "No spi pio irq specified\n");
1321 status = -ENOENT;
1322 goto out_error_free_io;
1323 }
1324
1325 /* Initial and start queue */
1326 status = bfin_spi_init_queue(drv_data);
1327 if (status != 0) {
1328 dev_err(dev, "problem initializing queue\n");
1329 goto out_error_queue_alloc;
1330 }
1331
1332 status = bfin_spi_start_queue(drv_data);
1333 if (status != 0) {
1334 dev_err(dev, "problem starting queue\n");
1335 goto out_error_queue_alloc;
1336 }
1337
1338 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1339 if (status != 0) {
1340 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1341 goto out_error_queue_alloc;
1342 }
1343
1344 /* Reset SPI registers. If these registers were used by the boot loader,
1345 * the sky may fall on your head if you enable the dma controller.
1346 */
1347 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1348 write_FLAG(drv_data, 0xFF00);
1349
1350 /* Register with the SPI framework */
1351 platform_set_drvdata(pdev, drv_data);
1352 status = spi_register_master(master);
1353 if (status != 0) {
1354 dev_err(dev, "problem registering spi master\n");
1355 goto out_error_queue_alloc;
1356 }
1357
1358 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1359 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1360 drv_data->dma_channel);
1361 return status;
1362
1363 out_error_queue_alloc:
1364 bfin_spi_destroy_queue(drv_data);
1365 out_error_free_io:
1366 iounmap((void *) drv_data->regs_base);
1367 out_error_ioremap:
1368 out_error_get_res:
1369 spi_master_put(master);
1370
1371 return status;
1372 }
1373
1374 /* stop hardware and remove the driver */
1375 static int __devexit bfin_spi_remove(struct platform_device *pdev)
1376 {
1377 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1378 int status = 0;
1379
1380 if (!drv_data)
1381 return 0;
1382
1383 /* Remove the queue */
1384 status = bfin_spi_destroy_queue(drv_data);
1385 if (status != 0)
1386 return status;
1387
1388 /* Disable the SSP at the peripheral and SOC level */
1389 bfin_spi_disable(drv_data);
1390
1391 /* Release DMA */
1392 if (drv_data->master_info->enable_dma) {
1393 if (dma_channel_active(drv_data->dma_channel))
1394 free_dma(drv_data->dma_channel);
1395 }
1396
1397 if (drv_data->irq_requested) {
1398 free_irq(drv_data->spi_irq, drv_data);
1399 drv_data->irq_requested = 0;
1400 }
1401
1402 /* Disconnect from the SPI framework */
1403 spi_unregister_master(drv_data->master);
1404
1405 peripheral_free_list(drv_data->pin_req);
1406
1407 /* Prevent double remove */
1408 platform_set_drvdata(pdev, NULL);
1409
1410 return 0;
1411 }
1412
1413 #ifdef CONFIG_PM
1414 static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state)
1415 {
1416 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1417 int status = 0;
1418
1419 status = bfin_spi_stop_queue(drv_data);
1420 if (status != 0)
1421 return status;
1422
1423 drv_data->ctrl_reg = read_CTRL(drv_data);
1424 drv_data->flag_reg = read_FLAG(drv_data);
1425
1426 /*
1427 * reset SPI_CTL and SPI_FLG registers
1428 */
1429 write_CTRL(drv_data, BIT_CTL_CPHA | BIT_CTL_MASTER);
1430 write_FLAG(drv_data, 0xFF00);
1431
1432 return 0;
1433 }
1434
1435 static int bfin_spi_resume(struct platform_device *pdev)
1436 {
1437 struct bfin_spi_master_data *drv_data = platform_get_drvdata(pdev);
1438 int status = 0;
1439
1440 write_CTRL(drv_data, drv_data->ctrl_reg);
1441 write_FLAG(drv_data, drv_data->flag_reg);
1442
1443 /* Start the queue running */
1444 status = bfin_spi_start_queue(drv_data);
1445 if (status != 0) {
1446 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1447 return status;
1448 }
1449
1450 return 0;
1451 }
1452 #else
1453 #define bfin_spi_suspend NULL
1454 #define bfin_spi_resume NULL
1455 #endif /* CONFIG_PM */
1456
1457 MODULE_ALIAS("platform:bfin-spi");
1458 static struct platform_driver bfin_spi_driver = {
1459 .driver = {
1460 .name = DRV_NAME,
1461 .owner = THIS_MODULE,
1462 },
1463 .suspend = bfin_spi_suspend,
1464 .resume = bfin_spi_resume,
1465 .remove = __devexit_p(bfin_spi_remove),
1466 };
1467
1468 static int __init bfin_spi_init(void)
1469 {
1470 return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe);
1471 }
1472 subsys_initcall(bfin_spi_init);
1473
1474 static void __exit bfin_spi_exit(void)
1475 {
1476 platform_driver_unregister(&bfin_spi_driver);
1477 }
1478 module_exit(bfin_spi_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree