sound/soc/codecs/wm8580.c

   1 /*
   2  * wm8580.c  --  WM8580 ALSA Soc Audio driver
   3  *
   4  * Copyright 2008, 2009 Wolfson Microelectronics PLC.
   5  *
   6  *  This program is free software; you can redistribute  it and/or modify it
   7  *  under  the terms of  the GNU General  Public License as published by the
   8  *  Free Software Foundation;  either version 2 of the  License, or (at your
   9  *  option) any later version.
  10  *
  11  * Notes:
  12  *  The WM8580 is a multichannel codec with S/PDIF support, featuring six
  13  *  DAC channels and two ADC channels.
  14  *
  15  *  Currently only the primary audio interface is supported - S/PDIF and
  16  *  the secondary audio interfaces are not.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/init.h>
  23 #include <linux/delay.h>
  24 #include <linux/pm.h>
  25 #include <linux/i2c.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/regulator/consumer.h>
  28 #include <linux/slab.h>
  29
  30 #include <sound/core.h>
  31 #include <sound/pcm.h>
  32 #include <sound/pcm_params.h>
  33 #include <sound/soc.h>
  34 #include <sound/soc-dapm.h>
  35 #include <sound/tlv.h>
  36 #include <sound/initval.h>
  37 #include <asm/div64.h>
  38
  39 #include "wm8580.h"
  40
  41 /* WM8580 register space */
  42 #define WM8580_PLLA1                         0x00
  43 #define WM8580_PLLA2                         0x01
  44 #define WM8580_PLLA3                         0x02
  45 #define WM8580_PLLA4                         0x03
  46 #define WM8580_PLLB1                         0x04
  47 #define WM8580_PLLB2                         0x05
  48 #define WM8580_PLLB3                         0x06
  49 #define WM8580_PLLB4                         0x07
  50 #define WM8580_CLKSEL                        0x08
  51 #define WM8580_PAIF1                         0x09
  52 #define WM8580_PAIF2                         0x0A
  53 #define WM8580_SAIF1                         0x0B
  54 #define WM8580_PAIF3                         0x0C
  55 #define WM8580_PAIF4                         0x0D
  56 #define WM8580_SAIF2                         0x0E
  57 #define WM8580_DAC_CONTROL1                  0x0F
  58 #define WM8580_DAC_CONTROL2                  0x10
  59 #define WM8580_DAC_CONTROL3                  0x11
  60 #define WM8580_DAC_CONTROL4                  0x12
  61 #define WM8580_DAC_CONTROL5                  0x13
  62 #define WM8580_DIGITAL_ATTENUATION_DACL1     0x14
  63 #define WM8580_DIGITAL_ATTENUATION_DACR1     0x15
  64 #define WM8580_DIGITAL_ATTENUATION_DACL2     0x16
  65 #define WM8580_DIGITAL_ATTENUATION_DACR2     0x17
  66 #define WM8580_DIGITAL_ATTENUATION_DACL3     0x18
  67 #define WM8580_DIGITAL_ATTENUATION_DACR3     0x19
  68 #define WM8580_MASTER_DIGITAL_ATTENUATION    0x1C
  69 #define WM8580_ADC_CONTROL1                  0x1D
  70 #define WM8580_SPDTXCHAN0                    0x1E
  71 #define WM8580_SPDTXCHAN1                    0x1F
  72 #define WM8580_SPDTXCHAN2                    0x20
  73 #define WM8580_SPDTXCHAN3                    0x21
  74 #define WM8580_SPDTXCHAN4                    0x22
  75 #define WM8580_SPDTXCHAN5                    0x23
  76 #define WM8580_SPDMODE                       0x24
  77 #define WM8580_INTMASK                       0x25
  78 #define WM8580_GPO1                          0x26
  79 #define WM8580_GPO2                          0x27
  80 #define WM8580_GPO3                          0x28
  81 #define WM8580_GPO4                          0x29
  82 #define WM8580_GPO5                          0x2A
  83 #define WM8580_INTSTAT                       0x2B
  84 #define WM8580_SPDRXCHAN1                    0x2C
  85 #define WM8580_SPDRXCHAN2                    0x2D
  86 #define WM8580_SPDRXCHAN3                    0x2E
  87 #define WM8580_SPDRXCHAN4                    0x2F
  88 #define WM8580_SPDRXCHAN5                    0x30
  89 #define WM8580_SPDSTAT                       0x31
  90 #define WM8580_PWRDN1                        0x32
  91 #define WM8580_PWRDN2                        0x33
  92 #define WM8580_READBACK                      0x34
  93 #define WM8580_RESET                         0x35
  94
  95 #define WM8580_MAX_REGISTER                  0x35
  96
  97 #define WM8580_DACOSR 0x40
  98
  99 /* PLLB4 (register 7h) */
 100 #define WM8580_PLLB4_MCLKOUTSRC_MASK   0x60
 101 #define WM8580_PLLB4_MCLKOUTSRC_PLLA   0x20
 102 #define WM8580_PLLB4_MCLKOUTSRC_PLLB   0x40
 103 #define WM8580_PLLB4_MCLKOUTSRC_OSC    0x60
 104
 105 #define WM8580_PLLB4_CLKOUTSRC_MASK    0x180
 106 #define WM8580_PLLB4_CLKOUTSRC_PLLACLK 0x080
 107 #define WM8580_PLLB4_CLKOUTSRC_PLLBCLK 0x100
 108 #define WM8580_PLLB4_CLKOUTSRC_OSCCLK  0x180
 109
 110 /* CLKSEL (register 8h) */
 111 #define WM8580_CLKSEL_DAC_CLKSEL_MASK 0x03
 112 #define WM8580_CLKSEL_DAC_CLKSEL_PLLA 0x01
 113 #define WM8580_CLKSEL_DAC_CLKSEL_PLLB 0x02
 114
 115 /* AIF control 1 (registers 9h-bh) */
 116 #define WM8580_AIF_RATE_MASK       0x7
 117 #define WM8580_AIF_BCLKSEL_MASK   0x18
 118
 119 #define WM8580_AIF_MS             0x20
 120
 121 #define WM8580_AIF_CLKSRC_MASK    0xc0
 122 #define WM8580_AIF_CLKSRC_PLLA    0x40
 123 #define WM8580_AIF_CLKSRC_PLLB    0x40
 124 #define WM8580_AIF_CLKSRC_MCLK    0xc0
 125
 126 /* AIF control 2 (registers ch-eh) */
 127 #define WM8580_AIF_FMT_MASK    0x03
 128 #define WM8580_AIF_FMT_RIGHTJ  0x00
 129 #define WM8580_AIF_FMT_LEFTJ   0x01
 130 #define WM8580_AIF_FMT_I2S     0x02
 131 #define WM8580_AIF_FMT_DSP     0x03
 132
 133 #define WM8580_AIF_LENGTH_MASK   0x0c
 134 #define WM8580_AIF_LENGTH_16     0x00
 135 #define WM8580_AIF_LENGTH_20     0x04
 136 #define WM8580_AIF_LENGTH_24     0x08
 137 #define WM8580_AIF_LENGTH_32     0x0c
 138
 139 #define WM8580_AIF_LRP         0x10
 140 #define WM8580_AIF_BCP         0x20
 141
 142 /* Powerdown Register 1 (register 32h) */
 143 #define WM8580_PWRDN1_PWDN     0x001
 144 #define WM8580_PWRDN1_ALLDACPD 0x040
 145
 146 /* Powerdown Register 2 (register 33h) */
 147 #define WM8580_PWRDN2_OSSCPD   0x001
 148 #define WM8580_PWRDN2_PLLAPD   0x002
 149 #define WM8580_PWRDN2_PLLBPD   0x004
 150 #define WM8580_PWRDN2_SPDIFPD  0x008
 151 #define WM8580_PWRDN2_SPDIFTXD 0x010
 152 #define WM8580_PWRDN2_SPDIFRXD 0x020
 153
 154 #define WM8580_DAC_CONTROL5_MUTEALL 0x10
 155
 156 /*
 157  * wm8580 register cache
 158  * We can't read the WM8580 register space when we
 159  * are using 2 wire for device control, so we cache them instead.
 160  */
 161 static const u16 wm8580_reg[] = {
 162         0x0121, 0x017e, 0x007d, 0x0014, /*R3*/
 163         0x0121, 0x017e, 0x007d, 0x0194, /*R7*/
 164         0x001c, 0x0002, 0x0002, 0x00c2, /*R11*/
 165         0x0182, 0x0082, 0x000a, 0x0024, /*R15*/
 166         0x0009, 0x0000, 0x00ff, 0x0000, /*R19*/
 167         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R23*/
 168         0x00ff, 0x00ff, 0x00ff, 0x00ff, /*R27*/
 169         0x01f0, 0x0040, 0x0000, 0x0000, /*R31(0x1F)*/
 170         0x0000, 0x0000, 0x0031, 0x000b, /*R35*/
 171         0x0039, 0x0000, 0x0010, 0x0032, /*R39*/
 172         0x0054, 0x0076, 0x0098, 0x0000, /*R43(0x2B)*/
 173         0x0000, 0x0000, 0x0000, 0x0000, /*R47*/
 174         0x0000, 0x0000, 0x005e, 0x003e, /*R51(0x33)*/
 175         0x0000, 0x0000 /*R53*/
 176 };
 177
 178 struct pll_state {
 179         unsigned int in;
 180         unsigned int out;
 181 };
 182
 183 #define WM8580_NUM_SUPPLIES 3
 184 static const char *wm8580_supply_names[WM8580_NUM_SUPPLIES] = {
 185         "AVDD",
 186         "DVDD",
 187         "PVDD",
 188 };
 189
 190 /* codec private data */
 191 struct wm8580_priv {
 192         enum snd_soc_control_type control_type;
 193         struct regulator_bulk_data supplies[WM8580_NUM_SUPPLIES];
 194         u16 reg_cache[WM8580_MAX_REGISTER + 1];
 195         struct pll_state a;
 196         struct pll_state b;
 197         int sysclk[2];
 198 };
 199
 200 static const DECLARE_TLV_DB_SCALE(dac_tlv, -12750, 50, 1);
 201
 202 static int wm8580_out_vu(struct snd_kcontrol *kcontrol,
 203                          struct snd_ctl_elem_value *ucontrol)
 204 {
 205         struct soc_mixer_control *mc =
 206                 (struct soc_mixer_control *)kcontrol->private_value;
 207         struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
 208         u16 *reg_cache = codec->reg_cache;
 209         unsigned int reg = mc->reg;
 210         unsigned int reg2 = mc->rreg;
 211         int ret;
 212
 213         /* Clear the register cache so we write without VU set */
 214         reg_cache[reg] = 0;
 215         reg_cache[reg2] = 0;
 216
 217         ret = snd_soc_put_volsw_2r(kcontrol, ucontrol);
 218         if (ret < 0)
 219                 return ret;
 220
 221         /* Now write again with the volume update bit set */
 222         snd_soc_update_bits(codec, reg, 0x100, 0x100);
 223         snd_soc_update_bits(codec, reg2, 0x100, 0x100);
 224
 225         return 0;
 226 }
 227
 228 #define SOC_WM8580_OUT_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, \
 229                                     xinvert, tlv_array)                 \
 230 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
 231         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
 232                 SNDRV_CTL_ELEM_ACCESS_READWRITE,  \
 233         .tlv.p = (tlv_array), \
 234         .info = snd_soc_info_volsw_2r, \
 235         .get = snd_soc_get_volsw_2r, .put = wm8580_out_vu, \
 236         .private_value = (unsigned long)&(struct soc_mixer_control) \
 237                 {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
 238                 .max = xmax, .invert = xinvert} }
 239
 240 static const struct snd_kcontrol_new wm8580_snd_controls[] = {
 241 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC1 Playback Volume",
 242                             WM8580_DIGITAL_ATTENUATION_DACL1,
 243                             WM8580_DIGITAL_ATTENUATION_DACR1,
 244                             0, 0xff, 0, dac_tlv),
 245 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC2 Playback Volume",
 246                             WM8580_DIGITAL_ATTENUATION_DACL2,
 247                             WM8580_DIGITAL_ATTENUATION_DACR2,
 248                             0, 0xff, 0, dac_tlv),
 249 SOC_WM8580_OUT_DOUBLE_R_TLV("DAC3 Playback Volume",
 250                             WM8580_DIGITAL_ATTENUATION_DACL3,
 251                             WM8580_DIGITAL_ATTENUATION_DACR3,
 252                             0, 0xff, 0, dac_tlv),
 253
 254 SOC_SINGLE("DAC1 Deemphasis Switch", WM8580_DAC_CONTROL3, 0, 1, 0),
 255 SOC_SINGLE("DAC2 Deemphasis Switch", WM8580_DAC_CONTROL3, 1, 1, 0),
 256 SOC_SINGLE("DAC3 Deemphasis Switch", WM8580_DAC_CONTROL3, 2, 1, 0),
 257
 258 SOC_DOUBLE("DAC1 Invert Switch", WM8580_DAC_CONTROL4,  0, 1, 1, 0),
 259 SOC_DOUBLE("DAC2 Invert Switch", WM8580_DAC_CONTROL4,  2, 3, 1, 0),
 260 SOC_DOUBLE("DAC3 Invert Switch", WM8580_DAC_CONTROL4,  4, 5, 1, 0),
 261
 262 SOC_SINGLE("DAC ZC Switch", WM8580_DAC_CONTROL5, 5, 1, 0),
 263 SOC_SINGLE("DAC1 Switch", WM8580_DAC_CONTROL5, 0, 1, 1),
 264 SOC_SINGLE("DAC2 Switch", WM8580_DAC_CONTROL5, 1, 1, 1),
 265 SOC_SINGLE("DAC3 Switch", WM8580_DAC_CONTROL5, 2, 1, 1),
 266
 267 SOC_DOUBLE("Capture Switch", WM8580_ADC_CONTROL1, 0, 1, 1, 1),
 268 SOC_SINGLE("Capture High-Pass Filter Switch", WM8580_ADC_CONTROL1, 4, 1, 0),
 269 };
 270
 271 static const struct snd_soc_dapm_widget wm8580_dapm_widgets[] = {
 272 SND_SOC_DAPM_DAC("DAC1", "Playback", WM8580_PWRDN1, 2, 1),
 273 SND_SOC_DAPM_DAC("DAC2", "Playback", WM8580_PWRDN1, 3, 1),
 274 SND_SOC_DAPM_DAC("DAC3", "Playback", WM8580_PWRDN1, 4, 1),
 275
 276 SND_SOC_DAPM_OUTPUT("VOUT1L"),
 277 SND_SOC_DAPM_OUTPUT("VOUT1R"),
 278 SND_SOC_DAPM_OUTPUT("VOUT2L"),
 279 SND_SOC_DAPM_OUTPUT("VOUT2R"),
 280 SND_SOC_DAPM_OUTPUT("VOUT3L"),
 281 SND_SOC_DAPM_OUTPUT("VOUT3R"),
 282
 283 SND_SOC_DAPM_ADC("ADC", "Capture", WM8580_PWRDN1, 1, 1),
 284
 285 SND_SOC_DAPM_INPUT("AINL"),
 286 SND_SOC_DAPM_INPUT("AINR"),
 287 };
 288
 289 static const struct snd_soc_dapm_route audio_map[] = {
 290         { "VOUT1L", NULL, "DAC1" },
 291         { "VOUT1R", NULL, "DAC1" },
 292
 293         { "VOUT2L", NULL, "DAC2" },
 294         { "VOUT2R", NULL, "DAC2" },
 295
 296         { "VOUT3L", NULL, "DAC3" },
 297         { "VOUT3R", NULL, "DAC3" },
 298
 299         { "ADC", NULL, "AINL" },
 300         { "ADC", NULL, "AINR" },
 301 };
 302
 303 static int wm8580_add_widgets(struct snd_soc_codec *codec)
 304 {
 305         snd_soc_dapm_new_controls(codec, wm8580_dapm_widgets,
 306                                   ARRAY_SIZE(wm8580_dapm_widgets));
 307
 308         snd_soc_dapm_add_routes(codec, audio_map, ARRAY_SIZE(audio_map));
 309
 310         return 0;
 311 }
 312
 313 /* PLL divisors */
 314 struct _pll_div {
 315         u32 prescale:1;
 316         u32 postscale:1;
 317         u32 freqmode:2;
 318         u32 n:4;
 319         u32 k:24;
 320 };
 321
 322 /* The size in bits of the pll divide */
 323 #define FIXED_PLL_SIZE (1 << 22)
 324
 325 /* PLL rate to output rate divisions */
 326 static struct {
 327         unsigned int div;
 328         unsigned int freqmode;
 329         unsigned int postscale;
 330 } post_table[] = {
 331         {  2,  0, 0 },
 332         {  4,  0, 1 },
 333         {  4,  1, 0 },
 334         {  8,  1, 1 },
 335         {  8,  2, 0 },
 336         { 16,  2, 1 },
 337         { 12,  3, 0 },
 338         { 24,  3, 1 }
 339 };
 340
 341 static int pll_factors(struct _pll_div *pll_div, unsigned int target,
 342                        unsigned int source)
 343 {
 344         u64 Kpart;
 345         unsigned int K, Ndiv, Nmod;
 346         int i;
 347
 348         pr_debug("wm8580: PLL %uHz->%uHz\n", source, target);
 349
 350         /* Scale the output frequency up; the PLL should run in the
 351          * region of 90-100MHz.
 352          */
 353         for (i = 0; i < ARRAY_SIZE(post_table); i++) {
 354                 if (target * post_table[i].div >=  90000000 &&
 355                     target * post_table[i].div <= 100000000) {
 356                         pll_div->freqmode = post_table[i].freqmode;
 357                         pll_div->postscale = post_table[i].postscale;
 358                         target *= post_table[i].div;
 359                         break;
 360                 }
 361         }
 362
 363         if (i == ARRAY_SIZE(post_table)) {
 364                 printk(KERN_ERR "wm8580: Unable to scale output frequency "
 365                        "%u\n", target);
 366                 return -EINVAL;
 367         }
 368
 369         Ndiv = target / source;
 370
 371         if (Ndiv < 5) {
 372                 source /= 2;
 373                 pll_div->prescale = 1;
 374                 Ndiv = target / source;
 375         } else
 376                 pll_div->prescale = 0;
 377
 378         if ((Ndiv < 5) || (Ndiv > 13)) {
 379                 printk(KERN_ERR
 380                         "WM8580 N=%u outside supported range\n", Ndiv);
 381                 return -EINVAL;
 382         }
 383
 384         pll_div->n = Ndiv;
 385         Nmod = target % source;
 386         Kpart = FIXED_PLL_SIZE * (long long)Nmod;
 387
 388         do_div(Kpart, source);
 389
 390         K = Kpart & 0xFFFFFFFF;
 391
 392         pll_div->k = K;
 393
 394         pr_debug("PLL %x.%x prescale %d freqmode %d postscale %d\n",
 395                  pll_div->n, pll_div->k, pll_div->prescale, pll_div->freqmode,
 396                  pll_div->postscale);
 397
 398         return 0;
 399 }
 400
 401 static int wm8580_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 402                 int source, unsigned int freq_in, unsigned int freq_out)
 403 {
 404         int offset;
 405         struct snd_soc_codec *codec = codec_dai->codec;
 406         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 407         struct pll_state *state;
 408         struct _pll_div pll_div;
 409         unsigned int reg;
 410         unsigned int pwr_mask;
 411         int ret;
 412
 413         /* GCC isn't able to work out the ifs below for initialising/using
 414          * pll_div so suppress warnings.
 415          */
 416         memset(&pll_div, 0, sizeof(pll_div));
 417
 418         switch (pll_id) {
 419         case WM8580_PLLA:
 420                 state = &wm8580->a;
 421                 offset = 0;
 422                 pwr_mask = WM8580_PWRDN2_PLLAPD;
 423                 break;
 424         case WM8580_PLLB:
 425                 state = &wm8580->b;
 426                 offset = 4;
 427                 pwr_mask = WM8580_PWRDN2_PLLBPD;
 428                 break;
 429         default:
 430                 return -ENODEV;
 431         }
 432
 433         if (freq_in && freq_out) {
 434                 ret = pll_factors(&pll_div, freq_out, freq_in);
 435                 if (ret != 0)
 436                         return ret;
 437         }
 438
 439         state->in = freq_in;
 440         state->out = freq_out;
 441
 442         /* Always disable the PLL - it is not safe to leave it running
 443          * while reprogramming it.
 444          */
 445         reg = snd_soc_read(codec, WM8580_PWRDN2);
 446         snd_soc_write(codec, WM8580_PWRDN2, reg | pwr_mask);
 447
 448         if (!freq_in || !freq_out)
 449                 return 0;
 450
 451         snd_soc_write(codec, WM8580_PLLA1 + offset, pll_div.k & 0x1ff);
 452         snd_soc_write(codec, WM8580_PLLA2 + offset, (pll_div.k >> 9) & 0x1ff);
 453         snd_soc_write(codec, WM8580_PLLA3 + offset,
 454                      (pll_div.k >> 18 & 0xf) | (pll_div.n << 4));
 455
 456         reg = snd_soc_read(codec, WM8580_PLLA4 + offset);
 457         reg &= ~0x1b;
 458         reg |= pll_div.prescale | pll_div.postscale << 1 |
 459                 pll_div.freqmode << 3;
 460
 461         snd_soc_write(codec, WM8580_PLLA4 + offset, reg);
 462
 463         /* All done, turn it on */
 464         reg = snd_soc_read(codec, WM8580_PWRDN2);
 465         snd_soc_write(codec, WM8580_PWRDN2, reg & ~pwr_mask);
 466
 467         return 0;
 468 }
 469
 470 static const int wm8580_sysclk_ratios[] = {
 471         128, 192, 256, 384, 512, 768, 1152,
 472 };
 473
 474 /*
 475  * Set PCM DAI bit size and sample rate.
 476  */
 477 static int wm8580_paif_hw_params(struct snd_pcm_substream *substream,
 478                                  struct snd_pcm_hw_params *params,
 479                                  struct snd_soc_dai *dai)
 480 {
 481         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 482         struct snd_soc_codec *codec = rtd->codec;
 483         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 484         u16 paifa = 0;
 485         u16 paifb = 0;
 486         int i, ratio, osr;
 487
 488         /* bit size */
 489         switch (params_format(params)) {
 490         case SNDRV_PCM_FORMAT_S16_LE:
 491                 paifa |= 0x8;
 492                 break;
 493         case SNDRV_PCM_FORMAT_S20_3LE:
 494                 paifa |= 0x10;
 495                 paifb |= WM8580_AIF_LENGTH_20;
 496                 break;
 497         case SNDRV_PCM_FORMAT_S24_LE:
 498                 paifa |= 0x10;
 499                 paifb |= WM8580_AIF_LENGTH_24;
 500                 break;
 501         case SNDRV_PCM_FORMAT_S32_LE:
 502                 paifa |= 0x10;
 503                 paifb |= WM8580_AIF_LENGTH_24;
 504                 break;
 505         default:
 506                 return -EINVAL;
 507         }
 508
 509         /* Look up the SYSCLK ratio; accept only exact matches */
 510         ratio = wm8580->sysclk[dai->id] / params_rate(params);
 511         for (i = 0; i < ARRAY_SIZE(wm8580_sysclk_ratios); i++)
 512                 if (ratio == wm8580_sysclk_ratios[i])
 513                         break;
 514         if (i == ARRAY_SIZE(wm8580_sysclk_ratios)) {
 515                 dev_err(codec->dev, "Invalid clock ratio %d/%d\n",
 516                         wm8580->sysclk[dai->id], params_rate(params));
 517                 return -EINVAL;
 518         }
 519         paifa |= i;
 520         dev_dbg(codec->dev, "Running at %dfs with %dHz clock\n",
 521                 wm8580_sysclk_ratios[i], wm8580->sysclk[dai->driver->id]);
 522
 523         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 524                 switch (ratio) {
 525                 case 128:
 526                 case 192:
 527                         osr = WM8580_DACOSR;
 528                         dev_dbg(codec->dev, "Selecting 64x OSR\n");
 529                         break;
 530                 default:
 531                         osr = 0;
 532                         dev_dbg(codec->dev, "Selecting 128x OSR\n");
 533                         break;
 534                 }
 535
 536                 snd_soc_update_bits(codec, WM8580_PAIF3, WM8580_DACOSR, osr);
 537         }
 538
 539         snd_soc_update_bits(codec, WM8580_PAIF1 + dai->driver->id,
 540                             WM8580_AIF_RATE_MASK | WM8580_AIF_BCLKSEL_MASK,
 541                             paifa);
 542         snd_soc_update_bits(codec, WM8580_PAIF3 + dai->driver->id,
 543                             WM8580_AIF_LENGTH_MASK, paifb);
 544         return 0;
 545 }
 546
 547 static int wm8580_set_paif_dai_fmt(struct snd_soc_dai *codec_dai,
 548                                       unsigned int fmt)
 549 {
 550         struct snd_soc_codec *codec = codec_dai->codec;
 551         unsigned int aifa;
 552         unsigned int aifb;
 553         int can_invert_lrclk;
 554
 555         aifa = snd_soc_read(codec, WM8580_PAIF1 + codec_dai->driver->id);
 556         aifb = snd_soc_read(codec, WM8580_PAIF3 + codec_dai->driver->id);
 557
 558         aifb &= ~(WM8580_AIF_FMT_MASK | WM8580_AIF_LRP | WM8580_AIF_BCP);
 559
 560         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 561         case SND_SOC_DAIFMT_CBS_CFS:
 562                 aifa &= ~WM8580_AIF_MS;
 563                 break;
 564         case SND_SOC_DAIFMT_CBM_CFM:
 565                 aifa |= WM8580_AIF_MS;
 566                 break;
 567         default:
 568                 return -EINVAL;
 569         }
 570
 571         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 572         case SND_SOC_DAIFMT_I2S:
 573                 can_invert_lrclk = 1;
 574                 aifb |= WM8580_AIF_FMT_I2S;
 575                 break;
 576         case SND_SOC_DAIFMT_RIGHT_J:
 577                 can_invert_lrclk = 1;
 578                 aifb |= WM8580_AIF_FMT_RIGHTJ;
 579                 break;
 580         case SND_SOC_DAIFMT_LEFT_J:
 581                 can_invert_lrclk = 1;
 582                 aifb |= WM8580_AIF_FMT_LEFTJ;
 583                 break;
 584         case SND_SOC_DAIFMT_DSP_A:
 585                 can_invert_lrclk = 0;
 586                 aifb |= WM8580_AIF_FMT_DSP;
 587                 break;
 588         case SND_SOC_DAIFMT_DSP_B:
 589                 can_invert_lrclk = 0;
 590                 aifb |= WM8580_AIF_FMT_DSP;
 591                 aifb |= WM8580_AIF_LRP;
 592                 break;
 593         default:
 594                 return -EINVAL;
 595         }
 596
 597         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 598         case SND_SOC_DAIFMT_NB_NF:
 599                 break;
 600
 601         case SND_SOC_DAIFMT_IB_IF:
 602                 if (!can_invert_lrclk)
 603                         return -EINVAL;
 604                 aifb |= WM8580_AIF_BCP;
 605                 aifb |= WM8580_AIF_LRP;
 606                 break;
 607
 608         case SND_SOC_DAIFMT_IB_NF:
 609                 aifb |= WM8580_AIF_BCP;
 610                 break;
 611
 612         case SND_SOC_DAIFMT_NB_IF:
 613                 if (!can_invert_lrclk)
 614                         return -EINVAL;
 615                 aifb |= WM8580_AIF_LRP;
 616                 break;
 617
 618         default:
 619                 return -EINVAL;
 620         }
 621
 622         snd_soc_write(codec, WM8580_PAIF1 + codec_dai->driver->id, aifa);
 623         snd_soc_write(codec, WM8580_PAIF3 + codec_dai->driver->id, aifb);
 624
 625         return 0;
 626 }
 627
 628 static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
 629                                  int div_id, int div)
 630 {
 631         struct snd_soc_codec *codec = codec_dai->codec;
 632         unsigned int reg;
 633
 634         switch (div_id) {
 635         case WM8580_MCLK:
 636                 reg = snd_soc_read(codec, WM8580_PLLB4);
 637                 reg &= ~WM8580_PLLB4_MCLKOUTSRC_MASK;
 638
 639                 switch (div) {
 640                 case WM8580_CLKSRC_MCLK:
 641                         /* Input */
 642                         break;
 643
 644                 case WM8580_CLKSRC_PLLA:
 645                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLA;
 646                         break;
 647                 case WM8580_CLKSRC_PLLB:
 648                         reg |= WM8580_PLLB4_MCLKOUTSRC_PLLB;
 649                         break;
 650
 651                 case WM8580_CLKSRC_OSC:
 652                         reg |= WM8580_PLLB4_MCLKOUTSRC_OSC;
 653                         break;
 654
 655                 default:
 656                         return -EINVAL;
 657                 }
 658                 snd_soc_write(codec, WM8580_PLLB4, reg);
 659                 break;
 660
 661         case WM8580_CLKOUTSRC:
 662                 reg = snd_soc_read(codec, WM8580_PLLB4);
 663                 reg &= ~WM8580_PLLB4_CLKOUTSRC_MASK;
 664
 665                 switch (div) {
 666                 case WM8580_CLKSRC_NONE:
 667                         break;
 668
 669                 case WM8580_CLKSRC_PLLA:
 670                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLACLK;
 671                         break;
 672
 673                 case WM8580_CLKSRC_PLLB:
 674                         reg |= WM8580_PLLB4_CLKOUTSRC_PLLBCLK;
 675                         break;
 676
 677                 case WM8580_CLKSRC_OSC:
 678                         reg |= WM8580_PLLB4_CLKOUTSRC_OSCCLK;
 679                         break;
 680
 681                 default:
 682                         return -EINVAL;
 683                 }
 684                 snd_soc_write(codec, WM8580_PLLB4, reg);
 685                 break;
 686
 687         default:
 688                 return -EINVAL;
 689         }
 690
 691         return 0;
 692 }
 693
 694 static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
 695                              unsigned int freq, int dir)
 696 {
 697         struct snd_soc_codec *codec = dai->codec;
 698         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 699         int sel, sel_mask, sel_shift;
 700
 701         switch (dai->driver->id) {
 702         case WM8580_DAI_PAIFRX:
 703                 sel_mask = 0x3;
 704                 sel_shift = 0;
 705                 break;
 706
 707         case WM8580_DAI_PAIFTX:
 708                 sel_mask = 0xc;
 709                 sel_shift = 2;
 710                 break;
 711
 712         default:
 713                 BUG_ON("Unknown DAI driver ID\n");
 714                 return -EINVAL;
 715         }
 716
 717         switch (clk_id) {
 718         case WM8580_CLKSRC_ADCMCLK:
 719                 if (dai->id != WM8580_DAI_PAIFTX)
 720                         return -EINVAL;
 721                 sel = 0 << sel_shift;
 722                 break;
 723         case WM8580_CLKSRC_PLLA:
 724                 sel = 1 << sel_shift;
 725                 break;
 726         case WM8580_CLKSRC_PLLB:
 727                 sel = 2 << sel_shift;
 728                 break;
 729         case WM8580_CLKSRC_MCLK:
 730                 sel = 3 << sel_shift;
 731                 break;
 732         default:
 733                 dev_err(codec->dev, "Unknown clock %d\n", clk_id);
 734                 return -EINVAL;
 735         }
 736
 737         /* We really should validate PLL settings but not yet */
 738         wm8580->sysclk[dai->id] = freq;
 739
 740         return snd_soc_update_bits(codec, WM8580_CLKSEL, sel_mask, sel);
 741 }
 742
 743 static int wm8580_digital_mute(struct snd_soc_dai *codec_dai, int mute)
 744 {
 745         struct snd_soc_codec *codec = codec_dai->codec;
 746         unsigned int reg;
 747
 748         reg = snd_soc_read(codec, WM8580_DAC_CONTROL5);
 749
 750         if (mute)
 751                 reg |= WM8580_DAC_CONTROL5_MUTEALL;
 752         else
 753                 reg &= ~WM8580_DAC_CONTROL5_MUTEALL;
 754
 755         snd_soc_write(codec, WM8580_DAC_CONTROL5, reg);
 756
 757         return 0;
 758 }
 759
 760 static int wm8580_set_bias_level(struct snd_soc_codec *codec,
 761         enum snd_soc_bias_level level)
 762 {
 763         u16 reg;
 764         switch (level) {
 765         case SND_SOC_BIAS_ON:
 766         case SND_SOC_BIAS_PREPARE:
 767                 break;
 768
 769         case SND_SOC_BIAS_STANDBY:
 770                 if (codec->bias_level == SND_SOC_BIAS_OFF) {
 771                         /* Power up and get individual control of the DACs */
 772                         reg = snd_soc_read(codec, WM8580_PWRDN1);
 773                         reg &= ~(WM8580_PWRDN1_PWDN | WM8580_PWRDN1_ALLDACPD);
 774                         snd_soc_write(codec, WM8580_PWRDN1, reg);
 775
 776                         /* Make VMID high impedence */
 777                         reg = snd_soc_read(codec,  WM8580_ADC_CONTROL1);
 778                         reg &= ~0x100;
 779                         snd_soc_write(codec, WM8580_ADC_CONTROL1, reg);
 780                 }
 781                 break;
 782
 783         case SND_SOC_BIAS_OFF:
 784                 reg = snd_soc_read(codec, WM8580_PWRDN1);
 785                 snd_soc_write(codec, WM8580_PWRDN1, reg | WM8580_PWRDN1_PWDN);
 786                 break;
 787         }
 788         codec->bias_level = level;
 789         return 0;
 790 }
 791
 792 #define WM8580_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
 793                         SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
 794
 795 static struct snd_soc_dai_ops wm8580_dai_ops_playback = {
 796         .set_sysclk     = wm8580_set_sysclk,
 797         .hw_params      = wm8580_paif_hw_params,
 798         .set_fmt        = wm8580_set_paif_dai_fmt,
 799         .set_clkdiv     = wm8580_set_dai_clkdiv,
 800         .set_pll        = wm8580_set_dai_pll,
 801         .digital_mute   = wm8580_digital_mute,
 802 };
 803
 804 static struct snd_soc_dai_ops wm8580_dai_ops_capture = {
 805         .set_sysclk     = wm8580_set_sysclk,
 806         .hw_params      = wm8580_paif_hw_params,
 807         .set_fmt        = wm8580_set_paif_dai_fmt,
 808         .set_clkdiv     = wm8580_set_dai_clkdiv,
 809         .set_pll        = wm8580_set_dai_pll,
 810 };
 811
 812 static struct snd_soc_dai_driver wm8580_dai[] = {
 813         {
 814                 .name = "wm8580-hifi-playback",
 815                 .id     = WM8580_DAI_PAIFRX,
 816                 .playback = {
 817                         .stream_name = "Playback",
 818                         .channels_min = 1,
 819                         .channels_max = 6,
 820                         .rates = SNDRV_PCM_RATE_8000_192000,
 821                         .formats = WM8580_FORMATS,
 822                 },
 823                 .ops = &wm8580_dai_ops_playback,
 824         },
 825         {
 826                 .name = "wm8580-hifi-capture",
 827                 .id     =       WM8580_DAI_PAIFTX,
 828                 .capture = {
 829                         .stream_name = "Capture",
 830                         .channels_min = 2,
 831                         .channels_max = 2,
 832                         .rates = SNDRV_PCM_RATE_8000_192000,
 833                         .formats = WM8580_FORMATS,
 834                 },
 835                 .ops = &wm8580_dai_ops_capture,
 836         },
 837 };
 838
 839 static int wm8580_probe(struct snd_soc_codec *codec)
 840 {
 841         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 842         int ret = 0,i;
 843
 844         ret = snd_soc_codec_set_cache_io(codec, 7, 9, wm8580->control_type);
 845         if (ret < 0) {
 846                 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
 847                 return ret;
 848         }
 849
 850         for (i = 0; i < ARRAY_SIZE(wm8580->supplies); i++)
 851                 wm8580->supplies[i].supply = wm8580_supply_names[i];
 852
 853         ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(wm8580->supplies),
 854                                  wm8580->supplies);
 855         if (ret != 0) {
 856                 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
 857                 return ret;
 858         }
 859
 860         ret = regulator_bulk_enable(ARRAY_SIZE(wm8580->supplies),
 861                                     wm8580->supplies);
 862         if (ret != 0) {
 863                 dev_err(codec->dev, "Failed to enable supplies: %d\n", ret);
 864                 goto err_regulator_get;
 865         }
 866
 867         /* Get the codec into a known state */
 868         ret = snd_soc_write(codec, WM8580_RESET, 0);
 869         if (ret != 0) {
 870                 dev_err(codec->dev, "Failed to reset codec: %d\n", ret);
 871                 goto err_regulator_enable;
 872         }
 873
 874         wm8580_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
 875
 876         snd_soc_add_controls(codec, wm8580_snd_controls,
 877                              ARRAY_SIZE(wm8580_snd_controls));
 878         wm8580_add_widgets(codec);
 879
 880         return 0;
 881
 882 err_regulator_enable:
 883         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 884 err_regulator_get:
 885         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 886         return ret;
 887 }
 888
 889 /* power down chip */
 890 static int wm8580_remove(struct snd_soc_codec *codec)
 891 {
 892         struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
 893
 894         wm8580_set_bias_level(codec, SND_SOC_BIAS_OFF);
 895
 896         regulator_bulk_disable(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 897         regulator_bulk_free(ARRAY_SIZE(wm8580->supplies), wm8580->supplies);
 898
 899         return 0;
 900 }
 901
 902 static struct snd_soc_codec_driver soc_codec_dev_wm8580 = {
 903         .probe =        wm8580_probe,
 904         .remove =       wm8580_remove,
 905         .set_bias_level = wm8580_set_bias_level,
 906         .reg_cache_size = ARRAY_SIZE(wm8580_reg),
 907         .reg_word_size = sizeof(u16),
 908         .reg_cache_default = &wm8580_reg,
 909 };
 910
 911 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 912 static int wm8580_i2c_probe(struct i2c_client *i2c,
 913                             const struct i2c_device_id *id)
 914 {
 915         struct wm8580_priv *wm8580;
 916         int ret;
 917
 918         wm8580 = kzalloc(sizeof(struct wm8580_priv), GFP_KERNEL);
 919         if (wm8580 == NULL)
 920                 return -ENOMEM;
 921
 922         i2c_set_clientdata(i2c, wm8580);
 923         wm8580->control_type = SND_SOC_I2C;
 924
 925         ret =  snd_soc_register_codec(&i2c->dev,
 926                         &soc_codec_dev_wm8580, wm8580_dai, ARRAY_SIZE(wm8580_dai));
 927         if (ret < 0)
 928                 kfree(wm8580);
 929         return ret;
 930 }
 931
 932 static int wm8580_i2c_remove(struct i2c_client *client)
 933 {
 934         snd_soc_unregister_codec(&client->dev);
 935         kfree(i2c_get_clientdata(client));
 936         return 0;
 937 }
 938
 939 static const struct i2c_device_id wm8580_i2c_id[] = {
 940         { "wm8580", 0 },
 941         { }
 942 };
 943 MODULE_DEVICE_TABLE(i2c, wm8580_i2c_id);
 944
 945 static struct i2c_driver wm8580_i2c_driver = {
 946         .driver = {
 947                 .name = "wm8580-codec",
 948                 .owner = THIS_MODULE,
 949         },
 950         .probe =    wm8580_i2c_probe,
 951         .remove =   wm8580_i2c_remove,
 952         .id_table = wm8580_i2c_id,
 953 };
 954 #endif
 955
 956 static int __init wm8580_modinit(void)
 957 {
 958         int ret = 0;
 959
 960 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 961         ret = i2c_add_driver(&wm8580_i2c_driver);
 962         if (ret != 0) {
 963                 pr_err("Failed to register WM8580 I2C driver: %d\n", ret);
 964         }
 965 #endif
 966
 967         return ret;
 968 }
 969 module_init(wm8580_modinit);
 970
 971 static void __exit wm8580_exit(void)
 972 {
 973 #if defined(CONFIG_I2C) || defined(CONFIG_I2C_MODULE)
 974         i2c_del_driver(&wm8580_i2c_driver);
 975 #endif
 976 }
 977 module_exit(wm8580_exit);
 978
 979 MODULE_DESCRIPTION("ASoC WM8580 driver");
 980 MODULE_AUTHOR("Mark Brown <broonie@opensource.wolfsonmicro.com>");
 981 MODULE_LICENSE("GPL");