drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26
  27 #define RADEON_IDLE_LOOP_MS 100
  28 #define RADEON_RECLOCK_DELAY_MS 200
  29 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  30 #define RADEON_WAIT_IDLE_TIMEOUT 200
  31
  32 static void radeon_pm_idle_work_handler(struct work_struct *work);
  33 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  34
  35 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
  36 {
  37         struct radeon_bo *bo, *n;
  38
  39         if (list_empty(&rdev->gem.objects))
  40                 return;
  41
  42         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
  43                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
  44                         ttm_bo_unmap_virtual(&bo->tbo);
  45         }
  46
  47         if (rdev->gart.table.vram.robj)
  48                 ttm_bo_unmap_virtual(&rdev->gart.table.vram.robj->tbo);
  49
  50         if (rdev->stollen_vga_memory)
  51                 ttm_bo_unmap_virtual(&rdev->stollen_vga_memory->tbo);
  52
  53         if (rdev->r600_blit.shader_obj)
  54                 ttm_bo_unmap_virtual(&rdev->r600_blit.shader_obj->tbo);
  55 }
  56
  57 static void radeon_pm_set_clocks(struct radeon_device *rdev, int static_switch)
  58 {
  59         int i;
  60
  61         if (!static_switch)
  62                 radeon_get_power_state(rdev, rdev->pm.planned_action);
  63
  64         mutex_lock(&rdev->ddev->struct_mutex);
  65         mutex_lock(&rdev->vram_mutex);
  66         mutex_lock(&rdev->cp.mutex);
  67
  68         /* gui idle int has issues on older chips it seems */
  69         if (rdev->family >= CHIP_R600) {
  70                 /* wait for GPU idle */
  71                 rdev->pm.gui_idle = false;
  72                 rdev->irq.gui_idle = true;
  73                 radeon_irq_set(rdev);
  74                 wait_event_interruptible_timeout(
  75                         rdev->irq.idle_queue, rdev->pm.gui_idle,
  76                         msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
  77                 rdev->irq.gui_idle = false;
  78                 radeon_irq_set(rdev);
  79         } else {
  80                 struct radeon_fence *fence;
  81                 radeon_ring_alloc(rdev, 64);
  82                 radeon_fence_create(rdev, &fence);
  83                 radeon_fence_emit(rdev, fence);
  84                 radeon_ring_commit(rdev);
  85                 radeon_fence_wait(fence, false);
  86                 radeon_fence_unref(&fence);
  87         }
  88         radeon_unmap_vram_bos(rdev);
  89
  90         if (!static_switch) {
  91                 for (i = 0; i < rdev->num_crtc; i++) {
  92                         if (rdev->pm.active_crtcs & (1 << i)) {
  93                                 rdev->pm.req_vblank |= (1 << i);
  94                                 drm_vblank_get(rdev->ddev, i);
  95                         }
  96                 }
  97         }
  98
  99         radeon_set_power_state(rdev, static_switch);
 100
 101         if (!static_switch) {
 102                 for (i = 0; i < rdev->num_crtc; i++) {
 103                         if (rdev->pm.req_vblank & (1 << i)) {
 104                                 rdev->pm.req_vblank &= ~(1 << i);
 105                                 drm_vblank_put(rdev->ddev, i);
 106                         }
 107                 }
 108         }
 109
 110         /* update display watermarks based on new power state */
 111         radeon_update_bandwidth_info(rdev);
 112         if (rdev->pm.active_crtc_count)
 113                 radeon_bandwidth_update(rdev);
 114
 115         rdev->pm.planned_action = PM_ACTION_NONE;
 116
 117         mutex_unlock(&rdev->cp.mutex);
 118         mutex_unlock(&rdev->vram_mutex);
 119         mutex_unlock(&rdev->ddev->struct_mutex);
 120 }
 121
 122 static ssize_t radeon_get_power_state_static(struct device *dev,
 123                                              struct device_attribute *attr,
 124                                              char *buf)
 125 {
 126         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 127         struct radeon_device *rdev = ddev->dev_private;
 128
 129         return snprintf(buf, PAGE_SIZE, "%d.%d\n", rdev->pm.current_power_state_index,
 130                         rdev->pm.current_clock_mode_index);
 131 }
 132
 133 static ssize_t radeon_set_power_state_static(struct device *dev,
 134                                              struct device_attribute *attr,
 135                                              const char *buf,
 136                                              size_t count)
 137 {
 138         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 139         struct radeon_device *rdev = ddev->dev_private;
 140         int ps, cm;
 141
 142         if (sscanf(buf, "%u.%u", &ps, &cm) != 2) {
 143                 DRM_ERROR("Invalid power state!\n");
 144                 return count;
 145         }
 146
 147         mutex_lock(&rdev->pm.mutex);
 148         if ((ps >= 0) && (ps < rdev->pm.num_power_states) &&
 149             (cm >= 0) && (cm < rdev->pm.power_state[ps].num_clock_modes)) {
 150                 if ((rdev->pm.active_crtc_count > 1) &&
 151                     (rdev->pm.power_state[ps].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)) {
 152                         DRM_ERROR("Invalid power state for multi-head: %d.%d\n", ps, cm);
 153                 } else {
 154                         /* disable dynpm */
 155                         rdev->pm.state = PM_STATE_DISABLED;
 156                         rdev->pm.planned_action = PM_ACTION_NONE;
 157                         rdev->pm.requested_power_state_index = ps;
 158                         rdev->pm.requested_clock_mode_index = cm;
 159                         radeon_pm_set_clocks(rdev, true);
 160                 }
 161         } else
 162                 DRM_ERROR("Invalid power state: %d.%d\n\n", ps, cm);
 163         mutex_unlock(&rdev->pm.mutex);
 164
 165         return count;
 166 }
 167
 168 static ssize_t radeon_get_dynpm(struct device *dev,
 169                                 struct device_attribute *attr,
 170                                 char *buf)
 171 {
 172         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 173         struct radeon_device *rdev = ddev->dev_private;
 174
 175         return snprintf(buf, PAGE_SIZE, "%s\n",
 176                         (rdev->pm.state == PM_STATE_DISABLED) ? "disabled" : "enabled");
 177 }
 178
 179 static ssize_t radeon_set_dynpm(struct device *dev,
 180                                 struct device_attribute *attr,
 181                                 const char *buf,
 182                                 size_t count)
 183 {
 184         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 185         struct radeon_device *rdev = ddev->dev_private;
 186         int tmp = simple_strtoul(buf, NULL, 10);
 187
 188         if (tmp == 0) {
 189                 /* update power mode info */
 190                 radeon_pm_compute_clocks(rdev);
 191                 /* disable dynpm */
 192                 mutex_lock(&rdev->pm.mutex);
 193                 rdev->pm.state = PM_STATE_DISABLED;
 194                 rdev->pm.planned_action = PM_ACTION_NONE;
 195                 mutex_unlock(&rdev->pm.mutex);
 196                 DRM_INFO("radeon: dynamic power management disabled\n");
 197         } else if (tmp == 1) {
 198                 if (rdev->pm.num_power_states > 1) {
 199                         /* enable dynpm */
 200                         mutex_lock(&rdev->pm.mutex);
 201                         rdev->pm.state = PM_STATE_PAUSED;
 202                         rdev->pm.planned_action = PM_ACTION_DEFAULT;
 203                         radeon_get_power_state(rdev, rdev->pm.planned_action);
 204                         mutex_unlock(&rdev->pm.mutex);
 205                         /* update power mode info */
 206                         radeon_pm_compute_clocks(rdev);
 207                         DRM_INFO("radeon: dynamic power management enabled\n");
 208                 } else
 209                         DRM_ERROR("dynpm not valid on this system\n");
 210         } else
 211                 DRM_ERROR("Invalid setting: %d\n", tmp);
 212
 213         return count;
 214 }
 215
 216 static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR, radeon_get_power_state_static, radeon_set_power_state_static);
 217 static DEVICE_ATTR(dynpm, S_IRUGO | S_IWUSR, radeon_get_dynpm, radeon_set_dynpm);
 218
 219
 220 static const char *pm_state_names[4] = {
 221         "PM_STATE_DISABLED",
 222         "PM_STATE_MINIMUM",
 223         "PM_STATE_PAUSED",
 224         "PM_STATE_ACTIVE"
 225 };
 226
 227 static const char *pm_state_types[5] = {
 228         "",
 229         "Powersave",
 230         "Battery",
 231         "Balanced",
 232         "Performance",
 233 };
 234
 235 static void radeon_print_power_mode_info(struct radeon_device *rdev)
 236 {
 237         int i, j;
 238         bool is_default;
 239
 240         DRM_INFO("%d Power State(s)\n", rdev->pm.num_power_states);
 241         for (i = 0; i < rdev->pm.num_power_states; i++) {
 242                 if (rdev->pm.default_power_state_index == i)
 243                         is_default = true;
 244                 else
 245                         is_default = false;
 246                 DRM_INFO("State %d %s %s\n", i,
 247                          pm_state_types[rdev->pm.power_state[i].type],
 248                          is_default ? "(default)" : "");
 249                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 250                         DRM_INFO("\t%d PCIE Lanes\n", rdev->pm.power_state[i].pcie_lanes);
 251                 if (rdev->pm.power_state[i].flags & RADEON_PM_SINGLE_DISPLAY_ONLY)
 252                         DRM_INFO("\tSingle display only\n");
 253                 DRM_INFO("\t%d Clock Mode(s)\n", rdev->pm.power_state[i].num_clock_modes);
 254                 for (j = 0; j < rdev->pm.power_state[i].num_clock_modes; j++) {
 255                         if (rdev->flags & RADEON_IS_IGP)
 256                                 DRM_INFO("\t\t%d engine: %d\n",
 257                                          j,
 258                                          rdev->pm.power_state[i].clock_info[j].sclk * 10);
 259                         else
 260                                 DRM_INFO("\t\t%d engine/memory: %d/%d\n",
 261                                          j,
 262                                          rdev->pm.power_state[i].clock_info[j].sclk * 10,
 263                                          rdev->pm.power_state[i].clock_info[j].mclk * 10);
 264                 }
 265         }
 266 }
 267
 268 void radeon_sync_with_vblank(struct radeon_device *rdev)
 269 {
 270         if (rdev->pm.active_crtcs) {
 271                 rdev->pm.vblank_sync = false;
 272                 wait_event_timeout(
 273                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 274                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 275         }
 276 }
 277
 278 int radeon_pm_init(struct radeon_device *rdev)
 279 {
 280         rdev->pm.state = PM_STATE_DISABLED;
 281         rdev->pm.planned_action = PM_ACTION_NONE;
 282         rdev->pm.can_upclock = true;
 283         rdev->pm.can_downclock = true;
 284
 285         if (rdev->bios) {
 286                 if (rdev->is_atom_bios)
 287                         radeon_atombios_get_power_modes(rdev);
 288                 else
 289                         radeon_combios_get_power_modes(rdev);
 290                 radeon_print_power_mode_info(rdev);
 291         }
 292
 293         if (radeon_debugfs_pm_init(rdev)) {
 294                 DRM_ERROR("Failed to register debugfs file for PM!\n");
 295         }
 296
 297         /* where's the best place to put this? */
 298         device_create_file(rdev->dev, &dev_attr_power_state);
 299         device_create_file(rdev->dev, &dev_attr_dynpm);
 300
 301         INIT_DELAYED_WORK(&rdev->pm.idle_work, radeon_pm_idle_work_handler);
 302
 303         if ((radeon_dynpm != -1 && radeon_dynpm) && (rdev->pm.num_power_states > 1)) {
 304                 rdev->pm.state = PM_STATE_PAUSED;
 305                 DRM_INFO("radeon: dynamic power management enabled\n");
 306         }
 307
 308         DRM_INFO("radeon: power management initialized\n");
 309
 310         return 0;
 311 }
 312
 313 void radeon_pm_fini(struct radeon_device *rdev)
 314 {
 315         if (rdev->pm.state != PM_STATE_DISABLED) {
 316                 /* cancel work */
 317                 cancel_delayed_work_sync(&rdev->pm.idle_work);
 318                 /* reset default clocks */
 319                 rdev->pm.state = PM_STATE_DISABLED;
 320                 rdev->pm.planned_action = PM_ACTION_DEFAULT;
 321                 radeon_pm_set_clocks(rdev, false);
 322         } else if ((rdev->pm.current_power_state_index !=
 323                     rdev->pm.default_power_state_index) ||
 324                    (rdev->pm.current_clock_mode_index != 0)) {
 325                 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 326                 rdev->pm.requested_clock_mode_index = 0;
 327                 mutex_lock(&rdev->pm.mutex);
 328                 radeon_pm_set_clocks(rdev, true);
 329                 mutex_unlock(&rdev->pm.mutex);
 330         }
 331
 332         device_remove_file(rdev->dev, &dev_attr_power_state);
 333         device_remove_file(rdev->dev, &dev_attr_dynpm);
 334
 335         if (rdev->pm.i2c_bus)
 336                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 337 }
 338
 339 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 340 {
 341         struct drm_device *ddev = rdev->ddev;
 342         struct drm_crtc *crtc;
 343         struct radeon_crtc *radeon_crtc;
 344
 345         if (rdev->pm.state == PM_STATE_DISABLED)
 346                 return;
 347
 348         mutex_lock(&rdev->pm.mutex);
 349
 350         rdev->pm.active_crtcs = 0;
 351         rdev->pm.active_crtc_count = 0;
 352         list_for_each_entry(crtc,
 353                 &ddev->mode_config.crtc_list, head) {
 354                 radeon_crtc = to_radeon_crtc(crtc);
 355                 if (radeon_crtc->enabled) {
 356                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 357                         rdev->pm.active_crtc_count++;
 358                 }
 359         }
 360
 361         if (rdev->pm.active_crtc_count > 1) {
 362                 if (rdev->pm.state == PM_STATE_ACTIVE) {
 363                         cancel_delayed_work(&rdev->pm.idle_work);
 364
 365                         rdev->pm.state = PM_STATE_PAUSED;
 366                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 367                         radeon_pm_set_clocks(rdev, false);
 368
 369                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 370                 }
 371         } else if (rdev->pm.active_crtc_count == 1) {
 372                 /* TODO: Increase clocks if needed for current mode */
 373
 374                 if (rdev->pm.state == PM_STATE_MINIMUM) {
 375                         rdev->pm.state = PM_STATE_ACTIVE;
 376                         rdev->pm.planned_action = PM_ACTION_UPCLOCK;
 377                         radeon_pm_set_clocks(rdev, false);
 378
 379                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 380                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 381                 } else if (rdev->pm.state == PM_STATE_PAUSED) {
 382                         rdev->pm.state = PM_STATE_ACTIVE;
 383                         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 384                                 msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 385                         DRM_DEBUG("radeon: dynamic power management activated\n");
 386                 }
 387         } else { /* count == 0 */
 388                 if (rdev->pm.state != PM_STATE_MINIMUM) {
 389                         cancel_delayed_work(&rdev->pm.idle_work);
 390
 391                         rdev->pm.state = PM_STATE_MINIMUM;
 392                         rdev->pm.planned_action = PM_ACTION_MINIMUM;
 393                         radeon_pm_set_clocks(rdev, false);
 394                 }
 395         }
 396
 397         mutex_unlock(&rdev->pm.mutex);
 398 }
 399
 400 bool radeon_pm_in_vbl(struct radeon_device *rdev)
 401 {
 402         u32 stat_crtc = 0, vbl = 0, position = 0;
 403         bool in_vbl = true;
 404
 405         if (ASIC_IS_DCE4(rdev)) {
 406                 if (rdev->pm.active_crtcs & (1 << 0)) {
 407                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 408                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 409                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 410                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 411                 }
 412                 if (rdev->pm.active_crtcs & (1 << 1)) {
 413                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 414                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 415                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 416                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 417                 }
 418                 if (rdev->pm.active_crtcs & (1 << 2)) {
 419                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 420                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 421                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 422                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 423                 }
 424                 if (rdev->pm.active_crtcs & (1 << 3)) {
 425                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 426                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 427                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 428                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 429                 }
 430                 if (rdev->pm.active_crtcs & (1 << 4)) {
 431                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 432                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 433                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 434                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 435                 }
 436                 if (rdev->pm.active_crtcs & (1 << 5)) {
 437                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 438                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 439                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 440                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 441                 }
 442         } else if (ASIC_IS_AVIVO(rdev)) {
 443                 if (rdev->pm.active_crtcs & (1 << 0)) {
 444                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 445                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 446                 }
 447                 if (rdev->pm.active_crtcs & (1 << 1)) {
 448                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 449                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 450                 }
 451                 if (position < vbl && position > 1)
 452                         in_vbl = false;
 453         } else {
 454                 if (rdev->pm.active_crtcs & (1 << 0)) {
 455                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 456                         if (!(stat_crtc & 1))
 457                                 in_vbl = false;
 458                 }
 459                 if (rdev->pm.active_crtcs & (1 << 1)) {
 460                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 461                         if (!(stat_crtc & 1))
 462                                 in_vbl = false;
 463                 }
 464         }
 465
 466         if (position < vbl && position > 1)
 467                 in_vbl = false;
 468
 469         return in_vbl;
 470 }
 471
 472 bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 473 {
 474         u32 stat_crtc = 0;
 475         bool in_vbl = radeon_pm_in_vbl(rdev);
 476
 477         if (in_vbl == false)
 478                 DRM_INFO("not in vbl for pm change %08x at %s\n", stat_crtc,
 479                          finish ? "exit" : "entry");
 480         return in_vbl;
 481 }
 482
 483 static void radeon_pm_idle_work_handler(struct work_struct *work)
 484 {
 485         struct radeon_device *rdev;
 486         int resched;
 487         rdev = container_of(work, struct radeon_device,
 488                                 pm.idle_work.work);
 489
 490         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 491         mutex_lock(&rdev->pm.mutex);
 492         if (rdev->pm.state == PM_STATE_ACTIVE) {
 493                 unsigned long irq_flags;
 494                 int not_processed = 0;
 495
 496                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 497                 if (!list_empty(&rdev->fence_drv.emited)) {
 498                         struct list_head *ptr;
 499                         list_for_each(ptr, &rdev->fence_drv.emited) {
 500                                 /* count up to 3, that's enought info */
 501                                 if (++not_processed >= 3)
 502                                         break;
 503                         }
 504                 }
 505                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 506
 507                 if (not_processed >= 3) { /* should upclock */
 508                         if (rdev->pm.planned_action == PM_ACTION_DOWNCLOCK) {
 509                                 rdev->pm.planned_action = PM_ACTION_NONE;
 510                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 511                                    rdev->pm.can_upclock) {
 512                                 rdev->pm.planned_action =
 513                                         PM_ACTION_UPCLOCK;
 514                                 rdev->pm.action_timeout = jiffies +
 515                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 516                         }
 517                 } else if (not_processed == 0) { /* should downclock */
 518                         if (rdev->pm.planned_action == PM_ACTION_UPCLOCK) {
 519                                 rdev->pm.planned_action = PM_ACTION_NONE;
 520                         } else if (rdev->pm.planned_action == PM_ACTION_NONE &&
 521                                    rdev->pm.can_downclock) {
 522                                 rdev->pm.planned_action =
 523                                         PM_ACTION_DOWNCLOCK;
 524                                 rdev->pm.action_timeout = jiffies +
 525                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 526                         }
 527                 }
 528
 529                 if (rdev->pm.planned_action != PM_ACTION_NONE &&
 530                     jiffies > rdev->pm.action_timeout) {
 531                         radeon_pm_set_clocks(rdev, false);
 532                 }
 533         }
 534         mutex_unlock(&rdev->pm.mutex);
 535         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 536
 537         queue_delayed_work(rdev->wq, &rdev->pm.idle_work,
 538                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 539 }
 540
 541 /*
 542  * Debugfs info
 543  */
 544 #if defined(CONFIG_DEBUG_FS)
 545
 546 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 547 {
 548         struct drm_info_node *node = (struct drm_info_node *) m->private;
 549         struct drm_device *dev = node->minor->dev;
 550         struct radeon_device *rdev = dev->dev_private;
 551
 552         seq_printf(m, "state: %s\n", pm_state_names[rdev->pm.state]);
 553         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 554         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 555         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 556         if (rdev->asic->get_memory_clock)
 557                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 558         if (rdev->asic->get_pcie_lanes)
 559                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 560
 561         return 0;
 562 }
 563
 564 static struct drm_info_list radeon_pm_info_list[] = {
 565         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 566 };
 567 #endif
 568
 569 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 570 {
 571 #if defined(CONFIG_DEBUG_FS)
 572         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 573 #else
 574         return 0;
 575 #endif
 576 }