2 * PCI Bus Services, see include/linux/pci.h for further explanation.
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
10 #include <linux/kernel.h>
11 #include <linux/delay.h>
12 #include <linux/init.h>
13 #include <linux/pci.h>
15 #include <linux/module.h>
16 #include <linux/spinlock.h>
17 #include <linux/string.h>
18 #include <linux/log2.h>
19 #include <linux/pci-aspm.h>
20 #include <linux/pm_wakeup.h>
21 #include <linux/interrupt.h>
22 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 #include <linux/device.h>
24 #include <asm/setup.h>
27 const char *pci_power_names
[] = {
28 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
30 EXPORT_SYMBOL_GPL(pci_power_names
);
32 unsigned int pci_pm_d3_delay
= PCI_PM_D3_WAIT
;
34 #ifdef CONFIG_PCI_DOMAINS
35 int pci_domains_supported
= 1;
38 #define DEFAULT_CARDBUS_IO_SIZE (256)
39 #define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
40 /* pci=cbmemsize=nnM,cbiosize=nn can override this */
41 unsigned long pci_cardbus_io_size
= DEFAULT_CARDBUS_IO_SIZE
;
42 unsigned long pci_cardbus_mem_size
= DEFAULT_CARDBUS_MEM_SIZE
;
45 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
46 * @bus: pointer to PCI bus structure to search
48 * Given a PCI bus, returns the highest PCI bus number present in the set
49 * including the given PCI bus and its list of child PCI buses.
51 unsigned char pci_bus_max_busnr(struct pci_bus
* bus
)
53 struct list_head
*tmp
;
56 max
= bus
->subordinate
;
57 list_for_each(tmp
, &bus
->children
) {
58 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
64 EXPORT_SYMBOL_GPL(pci_bus_max_busnr
);
66 #ifdef CONFIG_HAS_IOMEM
67 void __iomem
*pci_ioremap_bar(struct pci_dev
*pdev
, int bar
)
70 * Make sure the BAR is actually a memory resource, not an IO resource
72 if (!(pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)) {
76 return ioremap_nocache(pci_resource_start(pdev
, bar
),
77 pci_resource_len(pdev
, bar
));
79 EXPORT_SYMBOL_GPL(pci_ioremap_bar
);
84 * pci_max_busnr - returns maximum PCI bus number
86 * Returns the highest PCI bus number present in the system global list of
89 unsigned char __devinit
92 struct pci_bus
*bus
= NULL
;
96 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
97 n
= pci_bus_max_busnr(bus
);
106 #define PCI_FIND_CAP_TTL 48
108 static int __pci_find_next_cap_ttl(struct pci_bus
*bus
, unsigned int devfn
,
109 u8 pos
, int cap
, int *ttl
)
114 pci_bus_read_config_byte(bus
, devfn
, pos
, &pos
);
118 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
,
124 pos
+= PCI_CAP_LIST_NEXT
;
129 static int __pci_find_next_cap(struct pci_bus
*bus
, unsigned int devfn
,
132 int ttl
= PCI_FIND_CAP_TTL
;
134 return __pci_find_next_cap_ttl(bus
, devfn
, pos
, cap
, &ttl
);
137 int pci_find_next_capability(struct pci_dev
*dev
, u8 pos
, int cap
)
139 return __pci_find_next_cap(dev
->bus
, dev
->devfn
,
140 pos
+ PCI_CAP_LIST_NEXT
, cap
);
142 EXPORT_SYMBOL_GPL(pci_find_next_capability
);
144 static int __pci_bus_find_cap_start(struct pci_bus
*bus
,
145 unsigned int devfn
, u8 hdr_type
)
149 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
150 if (!(status
& PCI_STATUS_CAP_LIST
))
154 case PCI_HEADER_TYPE_NORMAL
:
155 case PCI_HEADER_TYPE_BRIDGE
:
156 return PCI_CAPABILITY_LIST
;
157 case PCI_HEADER_TYPE_CARDBUS
:
158 return PCI_CB_CAPABILITY_LIST
;
167 * pci_find_capability - query for devices' capabilities
168 * @dev: PCI device to query
169 * @cap: capability code
171 * Tell if a device supports a given PCI capability.
172 * Returns the address of the requested capability structure within the
173 * device's PCI configuration space or 0 in case the device does not
174 * support it. Possible values for @cap:
176 * %PCI_CAP_ID_PM Power Management
177 * %PCI_CAP_ID_AGP Accelerated Graphics Port
178 * %PCI_CAP_ID_VPD Vital Product Data
179 * %PCI_CAP_ID_SLOTID Slot Identification
180 * %PCI_CAP_ID_MSI Message Signalled Interrupts
181 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
182 * %PCI_CAP_ID_PCIX PCI-X
183 * %PCI_CAP_ID_EXP PCI Express
185 int pci_find_capability(struct pci_dev
*dev
, int cap
)
189 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
191 pos
= __pci_find_next_cap(dev
->bus
, dev
->devfn
, pos
, cap
);
197 * pci_bus_find_capability - query for devices' capabilities
198 * @bus: the PCI bus to query
199 * @devfn: PCI device to query
200 * @cap: capability code
202 * Like pci_find_capability() but works for pci devices that do not have a
203 * pci_dev structure set up yet.
205 * Returns the address of the requested capability structure within the
206 * device's PCI configuration space or 0 in case the device does not
209 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
214 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
216 pos
= __pci_bus_find_cap_start(bus
, devfn
, hdr_type
& 0x7f);
218 pos
= __pci_find_next_cap(bus
, devfn
, pos
, cap
);
224 * pci_find_ext_capability - Find an extended capability
225 * @dev: PCI device to query
226 * @cap: capability code
228 * Returns the address of the requested extended capability structure
229 * within the device's PCI configuration space or 0 if the device does
230 * not support it. Possible values for @cap:
232 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
233 * %PCI_EXT_CAP_ID_VC Virtual Channel
234 * %PCI_EXT_CAP_ID_DSN Device Serial Number
235 * %PCI_EXT_CAP_ID_PWR Power Budgeting
237 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
241 int pos
= PCI_CFG_SPACE_SIZE
;
243 /* minimum 8 bytes per capability */
244 ttl
= (PCI_CFG_SPACE_EXP_SIZE
- PCI_CFG_SPACE_SIZE
) / 8;
246 if (dev
->cfg_size
<= PCI_CFG_SPACE_SIZE
)
249 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
253 * If we have no capabilities, this is indicated by cap ID,
254 * cap version and next pointer all being 0.
260 if (PCI_EXT_CAP_ID(header
) == cap
)
263 pos
= PCI_EXT_CAP_NEXT(header
);
264 if (pos
< PCI_CFG_SPACE_SIZE
)
267 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
273 EXPORT_SYMBOL_GPL(pci_find_ext_capability
);
275 static int __pci_find_next_ht_cap(struct pci_dev
*dev
, int pos
, int ht_cap
)
277 int rc
, ttl
= PCI_FIND_CAP_TTL
;
280 if (ht_cap
== HT_CAPTYPE_SLAVE
|| ht_cap
== HT_CAPTYPE_HOST
)
281 mask
= HT_3BIT_CAP_MASK
;
283 mask
= HT_5BIT_CAP_MASK
;
285 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
, pos
,
286 PCI_CAP_ID_HT
, &ttl
);
288 rc
= pci_read_config_byte(dev
, pos
+ 3, &cap
);
289 if (rc
!= PCIBIOS_SUCCESSFUL
)
292 if ((cap
& mask
) == ht_cap
)
295 pos
= __pci_find_next_cap_ttl(dev
->bus
, dev
->devfn
,
296 pos
+ PCI_CAP_LIST_NEXT
,
297 PCI_CAP_ID_HT
, &ttl
);
303 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
304 * @dev: PCI device to query
305 * @pos: Position from which to continue searching
306 * @ht_cap: Hypertransport capability code
308 * To be used in conjunction with pci_find_ht_capability() to search for
309 * all capabilities matching @ht_cap. @pos should always be a value returned
310 * from pci_find_ht_capability().
312 * NB. To be 100% safe against broken PCI devices, the caller should take
313 * steps to avoid an infinite loop.
315 int pci_find_next_ht_capability(struct pci_dev
*dev
, int pos
, int ht_cap
)
317 return __pci_find_next_ht_cap(dev
, pos
+ PCI_CAP_LIST_NEXT
, ht_cap
);
319 EXPORT_SYMBOL_GPL(pci_find_next_ht_capability
);
322 * pci_find_ht_capability - query a device's Hypertransport capabilities
323 * @dev: PCI device to query
324 * @ht_cap: Hypertransport capability code
326 * Tell if a device supports a given Hypertransport capability.
327 * Returns an address within the device's PCI configuration space
328 * or 0 in case the device does not support the request capability.
329 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
330 * which has a Hypertransport capability matching @ht_cap.
332 int pci_find_ht_capability(struct pci_dev
*dev
, int ht_cap
)
336 pos
= __pci_bus_find_cap_start(dev
->bus
, dev
->devfn
, dev
->hdr_type
);
338 pos
= __pci_find_next_ht_cap(dev
, pos
, ht_cap
);
342 EXPORT_SYMBOL_GPL(pci_find_ht_capability
);
345 * pci_find_parent_resource - return resource region of parent bus of given region
346 * @dev: PCI device structure contains resources to be searched
347 * @res: child resource record for which parent is sought
349 * For given resource region of given device, return the resource
350 * region of parent bus the given region is contained in or where
351 * it should be allocated from.
354 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
356 const struct pci_bus
*bus
= dev
->bus
;
358 struct resource
*best
= NULL
;
360 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
361 struct resource
*r
= bus
->resource
[i
];
364 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
365 continue; /* Not contained */
366 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
367 continue; /* Wrong type */
368 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
369 return r
; /* Exact match */
370 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
371 best
= r
; /* Approximating prefetchable by non-prefetchable */
377 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
378 * @dev: PCI device to have its BARs restored
380 * Restore the BAR values for a given device, so as to make it
381 * accessible by its driver.
384 pci_restore_bars(struct pci_dev
*dev
)
388 for (i
= 0; i
< PCI_BRIDGE_RESOURCES
; i
++)
389 pci_update_resource(dev
, i
);
392 static struct pci_platform_pm_ops
*pci_platform_pm
;
394 int pci_set_platform_pm(struct pci_platform_pm_ops
*ops
)
396 if (!ops
->is_manageable
|| !ops
->set_state
|| !ops
->choose_state
397 || !ops
->sleep_wake
|| !ops
->can_wakeup
)
399 pci_platform_pm
= ops
;
403 static inline bool platform_pci_power_manageable(struct pci_dev
*dev
)
405 return pci_platform_pm
? pci_platform_pm
->is_manageable(dev
) : false;
408 static inline int platform_pci_set_power_state(struct pci_dev
*dev
,
411 return pci_platform_pm
? pci_platform_pm
->set_state(dev
, t
) : -ENOSYS
;
414 static inline pci_power_t
platform_pci_choose_state(struct pci_dev
*dev
)
416 return pci_platform_pm
?
417 pci_platform_pm
->choose_state(dev
) : PCI_POWER_ERROR
;
420 static inline bool platform_pci_can_wakeup(struct pci_dev
*dev
)
422 return pci_platform_pm
? pci_platform_pm
->can_wakeup(dev
) : false;
425 static inline int platform_pci_sleep_wake(struct pci_dev
*dev
, bool enable
)
427 return pci_platform_pm
?
428 pci_platform_pm
->sleep_wake(dev
, enable
) : -ENODEV
;
432 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
434 * @dev: PCI device to handle.
435 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
438 * -EINVAL if the requested state is invalid.
439 * -EIO if device does not support PCI PM or its PM capabilities register has a
440 * wrong version, or device doesn't support the requested state.
441 * 0 if device already is in the requested state.
442 * 0 if device's power state has been successfully changed.
444 static int pci_raw_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
447 bool need_restore
= false;
449 /* Check if we're already there */
450 if (dev
->current_state
== state
)
456 if (state
< PCI_D0
|| state
> PCI_D3hot
)
459 /* Validate current state:
460 * Can enter D0 from any state, but if we can only go deeper
461 * to sleep if we're already in a low power state
463 if (state
!= PCI_D0
&& dev
->current_state
<= PCI_D3cold
464 && dev
->current_state
> state
) {
465 dev_err(&dev
->dev
, "invalid power transition "
466 "(from state %d to %d)\n", dev
->current_state
, state
);
470 /* check if this device supports the desired state */
471 if ((state
== PCI_D1
&& !dev
->d1_support
)
472 || (state
== PCI_D2
&& !dev
->d2_support
))
475 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
477 /* If we're (effectively) in D3, force entire word to 0.
478 * This doesn't affect PME_Status, disables PME_En, and
479 * sets PowerState to 0.
481 switch (dev
->current_state
) {
485 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
488 case PCI_UNKNOWN
: /* Boot-up */
489 if ((pmcsr
& PCI_PM_CTRL_STATE_MASK
) == PCI_D3hot
490 && !(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
492 /* Fall-through: force to D0 */
498 /* enter specified state */
499 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
501 /* Mandatory power management transition delays */
502 /* see PCI PM 1.1 5.6.1 table 18 */
503 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
504 msleep(pci_pm_d3_delay
);
505 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
506 udelay(PCI_PM_D2_DELAY
);
508 dev
->current_state
= state
;
510 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
511 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
512 * from D3hot to D0 _may_ perform an internal reset, thereby
513 * going to "D0 Uninitialized" rather than "D0 Initialized".
514 * For example, at least some versions of the 3c905B and the
515 * 3c556B exhibit this behaviour.
517 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
518 * devices in a D3hot state at boot. Consequently, we need to
519 * restore at least the BARs so that the device will be
520 * accessible to its driver.
523 pci_restore_bars(dev
);
526 pcie_aspm_pm_state_change(dev
->bus
->self
);
532 * pci_update_current_state - Read PCI power state of given device from its
533 * PCI PM registers and cache it
534 * @dev: PCI device to handle.
535 * @state: State to cache in case the device doesn't have the PM capability
537 void pci_update_current_state(struct pci_dev
*dev
, pci_power_t state
)
542 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
543 dev
->current_state
= (pmcsr
& PCI_PM_CTRL_STATE_MASK
);
545 dev
->current_state
= state
;
550 * pci_platform_power_transition - Use platform to change device power state
551 * @dev: PCI device to handle.
552 * @state: State to put the device into.
554 static int pci_platform_power_transition(struct pci_dev
*dev
, pci_power_t state
)
558 if (platform_pci_power_manageable(dev
)) {
559 error
= platform_pci_set_power_state(dev
, state
);
561 pci_update_current_state(dev
, state
);
564 /* Fall back to PCI_D0 if native PM is not supported */
566 dev
->current_state
= PCI_D0
;
573 * __pci_start_power_transition - Start power transition of a PCI device
574 * @dev: PCI device to handle.
575 * @state: State to put the device into.
577 static void __pci_start_power_transition(struct pci_dev
*dev
, pci_power_t state
)
580 pci_platform_power_transition(dev
, PCI_D0
);
584 * __pci_complete_power_transition - Complete power transition of a PCI device
585 * @dev: PCI device to handle.
586 * @state: State to put the device into.
588 * This function should not be called directly by device drivers.
590 int __pci_complete_power_transition(struct pci_dev
*dev
, pci_power_t state
)
592 return state
> PCI_D0
?
593 pci_platform_power_transition(dev
, state
) : -EINVAL
;
595 EXPORT_SYMBOL_GPL(__pci_complete_power_transition
);
598 * pci_set_power_state - Set the power state of a PCI device
599 * @dev: PCI device to handle.
600 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
602 * Transition a device to a new power state, using the platform firmware and/or
603 * the device's PCI PM registers.
606 * -EINVAL if the requested state is invalid.
607 * -EIO if device does not support PCI PM or its PM capabilities register has a
608 * wrong version, or device doesn't support the requested state.
609 * 0 if device already is in the requested state.
610 * 0 if device's power state has been successfully changed.
612 int pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
616 /* bound the state we're entering */
617 if (state
> PCI_D3hot
)
619 else if (state
< PCI_D0
)
621 else if ((state
== PCI_D1
|| state
== PCI_D2
) && pci_no_d1d2(dev
))
623 * If the device or the parent bridge do not support PCI PM,
624 * ignore the request if we're doing anything other than putting
625 * it into D0 (which would only happen on boot).
629 /* Check if we're already there */
630 if (dev
->current_state
== state
)
633 __pci_start_power_transition(dev
, state
);
635 /* This device is quirked not to be put into D3, so
636 don't put it in D3 */
637 if (state
== PCI_D3hot
&& (dev
->dev_flags
& PCI_DEV_FLAGS_NO_D3
))
640 error
= pci_raw_set_power_state(dev
, state
);
642 if (!__pci_complete_power_transition(dev
, state
))
649 * pci_choose_state - Choose the power state of a PCI device
650 * @dev: PCI device to be suspended
651 * @state: target sleep state for the whole system. This is the value
652 * that is passed to suspend() function.
654 * Returns PCI power state suitable for given device and given system
658 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
662 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
665 ret
= platform_pci_choose_state(dev
);
666 if (ret
!= PCI_POWER_ERROR
)
669 switch (state
.event
) {
672 case PM_EVENT_FREEZE
:
673 case PM_EVENT_PRETHAW
:
674 /* REVISIT both freeze and pre-thaw "should" use D0 */
675 case PM_EVENT_SUSPEND
:
676 case PM_EVENT_HIBERNATE
:
679 dev_info(&dev
->dev
, "unrecognized suspend event %d\n",
686 EXPORT_SYMBOL(pci_choose_state
);
688 #define PCI_EXP_SAVE_REGS 7
690 #define pcie_cap_has_devctl(type, flags) 1
691 #define pcie_cap_has_lnkctl(type, flags) \
692 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
693 (type == PCI_EXP_TYPE_ROOT_PORT || \
694 type == PCI_EXP_TYPE_ENDPOINT || \
695 type == PCI_EXP_TYPE_LEG_END))
696 #define pcie_cap_has_sltctl(type, flags) \
697 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
698 ((type == PCI_EXP_TYPE_ROOT_PORT) || \
699 (type == PCI_EXP_TYPE_DOWNSTREAM && \
700 (flags & PCI_EXP_FLAGS_SLOT))))
701 #define pcie_cap_has_rtctl(type, flags) \
702 ((flags & PCI_EXP_FLAGS_VERS) > 1 || \
703 (type == PCI_EXP_TYPE_ROOT_PORT || \
704 type == PCI_EXP_TYPE_RC_EC))
705 #define pcie_cap_has_devctl2(type, flags) \
706 ((flags & PCI_EXP_FLAGS_VERS) > 1)
707 #define pcie_cap_has_lnkctl2(type, flags) \
708 ((flags & PCI_EXP_FLAGS_VERS) > 1)
709 #define pcie_cap_has_sltctl2(type, flags) \
710 ((flags & PCI_EXP_FLAGS_VERS) > 1)
712 static int pci_save_pcie_state(struct pci_dev
*dev
)
715 struct pci_cap_saved_state
*save_state
;
719 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
723 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
725 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
728 cap
= (u16
*)&save_state
->data
[0];
730 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
732 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
733 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, &cap
[i
++]);
734 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
735 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, &cap
[i
++]);
736 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
737 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, &cap
[i
++]);
738 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
739 pci_read_config_word(dev
, pos
+ PCI_EXP_RTCTL
, &cap
[i
++]);
740 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
741 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, &cap
[i
++]);
742 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
743 pci_read_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, &cap
[i
++]);
744 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
745 pci_read_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, &cap
[i
++]);
750 static void pci_restore_pcie_state(struct pci_dev
*dev
)
753 struct pci_cap_saved_state
*save_state
;
757 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_EXP
);
758 pos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
759 if (!save_state
|| pos
<= 0)
761 cap
= (u16
*)&save_state
->data
[0];
763 pci_read_config_word(dev
, pos
+ PCI_EXP_FLAGS
, &flags
);
765 if (pcie_cap_has_devctl(dev
->pcie_type
, flags
))
766 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL
, cap
[i
++]);
767 if (pcie_cap_has_lnkctl(dev
->pcie_type
, flags
))
768 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL
, cap
[i
++]);
769 if (pcie_cap_has_sltctl(dev
->pcie_type
, flags
))
770 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL
, cap
[i
++]);
771 if (pcie_cap_has_rtctl(dev
->pcie_type
, flags
))
772 pci_write_config_word(dev
, pos
+ PCI_EXP_RTCTL
, cap
[i
++]);
773 if (pcie_cap_has_devctl2(dev
->pcie_type
, flags
))
774 pci_write_config_word(dev
, pos
+ PCI_EXP_DEVCTL2
, cap
[i
++]);
775 if (pcie_cap_has_lnkctl2(dev
->pcie_type
, flags
))
776 pci_write_config_word(dev
, pos
+ PCI_EXP_LNKCTL2
, cap
[i
++]);
777 if (pcie_cap_has_sltctl2(dev
->pcie_type
, flags
))
778 pci_write_config_word(dev
, pos
+ PCI_EXP_SLTCTL2
, cap
[i
++]);
782 static int pci_save_pcix_state(struct pci_dev
*dev
)
785 struct pci_cap_saved_state
*save_state
;
787 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
791 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
793 dev_err(&dev
->dev
, "buffer not found in %s\n", __func__
);
797 pci_read_config_word(dev
, pos
+ PCI_X_CMD
, (u16
*)save_state
->data
);
802 static void pci_restore_pcix_state(struct pci_dev
*dev
)
805 struct pci_cap_saved_state
*save_state
;
808 save_state
= pci_find_saved_cap(dev
, PCI_CAP_ID_PCIX
);
809 pos
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
810 if (!save_state
|| pos
<= 0)
812 cap
= (u16
*)&save_state
->data
[0];
814 pci_write_config_word(dev
, pos
+ PCI_X_CMD
, cap
[i
++]);
819 * pci_save_state - save the PCI configuration space of a device before suspending
820 * @dev: - PCI device that we're dealing with
823 pci_save_state(struct pci_dev
*dev
)
826 /* XXX: 100% dword access ok here? */
827 for (i
= 0; i
< 16; i
++)
828 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
829 dev
->state_saved
= true;
830 if ((i
= pci_save_pcie_state(dev
)) != 0)
832 if ((i
= pci_save_pcix_state(dev
)) != 0)
838 * pci_restore_state - Restore the saved state of a PCI device
839 * @dev: - PCI device that we're dealing with
842 pci_restore_state(struct pci_dev
*dev
)
847 /* PCI Express register must be restored first */
848 pci_restore_pcie_state(dev
);
851 * The Base Address register should be programmed before the command
854 for (i
= 15; i
>= 0; i
--) {
855 pci_read_config_dword(dev
, i
* 4, &val
);
856 if (val
!= dev
->saved_config_space
[i
]) {
857 dev_printk(KERN_DEBUG
, &dev
->dev
, "restoring config "
858 "space at offset %#x (was %#x, writing %#x)\n",
859 i
, val
, (int)dev
->saved_config_space
[i
]);
860 pci_write_config_dword(dev
,i
* 4,
861 dev
->saved_config_space
[i
]);
864 pci_restore_pcix_state(dev
);
865 pci_restore_msi_state(dev
);
866 pci_restore_iov_state(dev
);
871 static int do_pci_enable_device(struct pci_dev
*dev
, int bars
)
875 err
= pci_set_power_state(dev
, PCI_D0
);
876 if (err
< 0 && err
!= -EIO
)
878 err
= pcibios_enable_device(dev
, bars
);
881 pci_fixup_device(pci_fixup_enable
, dev
);
887 * pci_reenable_device - Resume abandoned device
888 * @dev: PCI device to be resumed
890 * Note this function is a backend of pci_default_resume and is not supposed
891 * to be called by normal code, write proper resume handler and use it instead.
893 int pci_reenable_device(struct pci_dev
*dev
)
895 if (pci_is_enabled(dev
))
896 return do_pci_enable_device(dev
, (1 << PCI_NUM_RESOURCES
) - 1);
900 static int __pci_enable_device_flags(struct pci_dev
*dev
,
901 resource_size_t flags
)
906 if (atomic_add_return(1, &dev
->enable_cnt
) > 1)
907 return 0; /* already enabled */
909 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
910 if (dev
->resource
[i
].flags
& flags
)
913 err
= do_pci_enable_device(dev
, bars
);
915 atomic_dec(&dev
->enable_cnt
);
920 * pci_enable_device_io - Initialize a device for use with IO space
921 * @dev: PCI device to be initialized
923 * Initialize device before it's used by a driver. Ask low-level code
924 * to enable I/O resources. Wake up the device if it was suspended.
925 * Beware, this function can fail.
927 int pci_enable_device_io(struct pci_dev
*dev
)
929 return __pci_enable_device_flags(dev
, IORESOURCE_IO
);
933 * pci_enable_device_mem - Initialize a device for use with Memory space
934 * @dev: PCI device to be initialized
936 * Initialize device before it's used by a driver. Ask low-level code
937 * to enable Memory resources. Wake up the device if it was suspended.
938 * Beware, this function can fail.
940 int pci_enable_device_mem(struct pci_dev
*dev
)
942 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
);
946 * pci_enable_device - Initialize device before it's used by a driver.
947 * @dev: PCI device to be initialized
949 * Initialize device before it's used by a driver. Ask low-level code
950 * to enable I/O and memory. Wake up the device if it was suspended.
951 * Beware, this function can fail.
953 * Note we don't actually enable the device many times if we call
954 * this function repeatedly (we just increment the count).
956 int pci_enable_device(struct pci_dev
*dev
)
958 return __pci_enable_device_flags(dev
, IORESOURCE_MEM
| IORESOURCE_IO
);
962 * Managed PCI resources. This manages device on/off, intx/msi/msix
963 * on/off and BAR regions. pci_dev itself records msi/msix status, so
964 * there's no need to track it separately. pci_devres is initialized
965 * when a device is enabled using managed PCI device enable interface.
968 unsigned int enabled
:1;
969 unsigned int pinned
:1;
970 unsigned int orig_intx
:1;
971 unsigned int restore_intx
:1;
975 static void pcim_release(struct device
*gendev
, void *res
)
977 struct pci_dev
*dev
= container_of(gendev
, struct pci_dev
, dev
);
978 struct pci_devres
*this = res
;
981 if (dev
->msi_enabled
)
982 pci_disable_msi(dev
);
983 if (dev
->msix_enabled
)
984 pci_disable_msix(dev
);
986 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++)
987 if (this->region_mask
& (1 << i
))
988 pci_release_region(dev
, i
);
990 if (this->restore_intx
)
991 pci_intx(dev
, this->orig_intx
);
993 if (this->enabled
&& !this->pinned
)
994 pci_disable_device(dev
);
997 static struct pci_devres
* get_pci_dr(struct pci_dev
*pdev
)
999 struct pci_devres
*dr
, *new_dr
;
1001 dr
= devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1005 new_dr
= devres_alloc(pcim_release
, sizeof(*new_dr
), GFP_KERNEL
);
1008 return devres_get(&pdev
->dev
, new_dr
, NULL
, NULL
);
1011 static struct pci_devres
* find_pci_dr(struct pci_dev
*pdev
)
1013 if (pci_is_managed(pdev
))
1014 return devres_find(&pdev
->dev
, pcim_release
, NULL
, NULL
);
1019 * pcim_enable_device - Managed pci_enable_device()
1020 * @pdev: PCI device to be initialized
1022 * Managed pci_enable_device().
1024 int pcim_enable_device(struct pci_dev
*pdev
)
1026 struct pci_devres
*dr
;
1029 dr
= get_pci_dr(pdev
);
1035 rc
= pci_enable_device(pdev
);
1037 pdev
->is_managed
= 1;
1044 * pcim_pin_device - Pin managed PCI device
1045 * @pdev: PCI device to pin
1047 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1048 * driver detach. @pdev must have been enabled with
1049 * pcim_enable_device().
1051 void pcim_pin_device(struct pci_dev
*pdev
)
1053 struct pci_devres
*dr
;
1055 dr
= find_pci_dr(pdev
);
1056 WARN_ON(!dr
|| !dr
->enabled
);
1062 * pcibios_disable_device - disable arch specific PCI resources for device dev
1063 * @dev: the PCI device to disable
1065 * Disables architecture specific PCI resources for the device. This
1066 * is the default implementation. Architecture implementations can
1069 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
1071 static void do_pci_disable_device(struct pci_dev
*dev
)
1075 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
1076 if (pci_command
& PCI_COMMAND_MASTER
) {
1077 pci_command
&= ~PCI_COMMAND_MASTER
;
1078 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
1081 pcibios_disable_device(dev
);
1085 * pci_disable_enabled_device - Disable device without updating enable_cnt
1086 * @dev: PCI device to disable
1088 * NOTE: This function is a backend of PCI power management routines and is
1089 * not supposed to be called drivers.
1091 void pci_disable_enabled_device(struct pci_dev
*dev
)
1093 if (pci_is_enabled(dev
))
1094 do_pci_disable_device(dev
);
1098 * pci_disable_device - Disable PCI device after use
1099 * @dev: PCI device to be disabled
1101 * Signal to the system that the PCI device is not in use by the system
1102 * anymore. This only involves disabling PCI bus-mastering, if active.
1104 * Note we don't actually disable the device until all callers of
1105 * pci_device_enable() have called pci_device_disable().
1108 pci_disable_device(struct pci_dev
*dev
)
1110 struct pci_devres
*dr
;
1112 dr
= find_pci_dr(dev
);
1116 if (atomic_sub_return(1, &dev
->enable_cnt
) != 0)
1119 do_pci_disable_device(dev
);
1121 dev
->is_busmaster
= 0;
1125 * pcibios_set_pcie_reset_state - set reset state for device dev
1126 * @dev: the PCI-E device reset
1127 * @state: Reset state to enter into
1130 * Sets the PCI-E reset state for the device. This is the default
1131 * implementation. Architecture implementations can override this.
1133 int __attribute__ ((weak
)) pcibios_set_pcie_reset_state(struct pci_dev
*dev
,
1134 enum pcie_reset_state state
)
1140 * pci_set_pcie_reset_state - set reset state for device dev
1141 * @dev: the PCI-E device reset
1142 * @state: Reset state to enter into
1145 * Sets the PCI reset state for the device.
1147 int pci_set_pcie_reset_state(struct pci_dev
*dev
, enum pcie_reset_state state
)
1149 return pcibios_set_pcie_reset_state(dev
, state
);
1153 * pci_pme_capable - check the capability of PCI device to generate PME#
1154 * @dev: PCI device to handle.
1155 * @state: PCI state from which device will issue PME#.
1157 bool pci_pme_capable(struct pci_dev
*dev
, pci_power_t state
)
1162 return !!(dev
->pme_support
& (1 << state
));
1166 * pci_pme_active - enable or disable PCI device's PME# function
1167 * @dev: PCI device to handle.
1168 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1170 * The caller must verify that the device is capable of generating PME# before
1171 * calling this function with @enable equal to 'true'.
1173 void pci_pme_active(struct pci_dev
*dev
, bool enable
)
1180 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pmcsr
);
1181 /* Clear PME_Status by writing 1 to it and enable PME# */
1182 pmcsr
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
1184 pmcsr
&= ~PCI_PM_CTRL_PME_ENABLE
;
1186 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
);
1188 dev_printk(KERN_INFO
, &dev
->dev
, "PME# %s\n",
1189 enable
? "enabled" : "disabled");
1193 * pci_enable_wake - enable PCI device as wakeup event source
1194 * @dev: PCI device affected
1195 * @state: PCI state from which device will issue wakeup events
1196 * @enable: True to enable event generation; false to disable
1198 * This enables the device as a wakeup event source, or disables it.
1199 * When such events involves platform-specific hooks, those hooks are
1200 * called automatically by this routine.
1202 * Devices with legacy power management (no standard PCI PM capabilities)
1203 * always require such platform hooks.
1206 * 0 is returned on success
1207 * -EINVAL is returned if device is not supposed to wake up the system
1208 * Error code depending on the platform is returned if both the platform and
1209 * the native mechanism fail to enable the generation of wake-up events
1211 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
1214 bool pme_done
= false;
1216 if (enable
&& !device_may_wakeup(&dev
->dev
))
1220 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1221 * Anderson we should be doing PME# wake enable followed by ACPI wake
1222 * enable. To disable wake-up we call the platform first, for symmetry.
1225 if (!enable
&& platform_pci_can_wakeup(dev
))
1226 error
= platform_pci_sleep_wake(dev
, false);
1228 if (!enable
|| pci_pme_capable(dev
, state
)) {
1229 pci_pme_active(dev
, enable
);
1233 if (enable
&& platform_pci_can_wakeup(dev
))
1234 error
= platform_pci_sleep_wake(dev
, true);
1236 return pme_done
? 0 : error
;
1240 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1241 * @dev: PCI device to prepare
1242 * @enable: True to enable wake-up event generation; false to disable
1244 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1245 * and this function allows them to set that up cleanly - pci_enable_wake()
1246 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1247 * ordering constraints.
1249 * This function only returns error code if the device is not capable of
1250 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1251 * enable wake-up power for it.
1253 int pci_wake_from_d3(struct pci_dev
*dev
, bool enable
)
1255 return pci_pme_capable(dev
, PCI_D3cold
) ?
1256 pci_enable_wake(dev
, PCI_D3cold
, enable
) :
1257 pci_enable_wake(dev
, PCI_D3hot
, enable
);
1261 * pci_target_state - find an appropriate low power state for a given PCI dev
1264 * Use underlying platform code to find a supported low power state for @dev.
1265 * If the platform can't manage @dev, return the deepest state from which it
1266 * can generate wake events, based on any available PME info.
1268 pci_power_t
pci_target_state(struct pci_dev
*dev
)
1270 pci_power_t target_state
= PCI_D3hot
;
1272 if (platform_pci_power_manageable(dev
)) {
1274 * Call the platform to choose the target state of the device
1275 * and enable wake-up from this state if supported.
1277 pci_power_t state
= platform_pci_choose_state(dev
);
1280 case PCI_POWER_ERROR
:
1285 if (pci_no_d1d2(dev
))
1288 target_state
= state
;
1290 } else if (device_may_wakeup(&dev
->dev
)) {
1292 * Find the deepest state from which the device can generate
1293 * wake-up events, make it the target state and enable device
1297 return PCI_POWER_ERROR
;
1299 if (dev
->pme_support
) {
1301 && !(dev
->pme_support
& (1 << target_state
)))
1306 return target_state
;
1310 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
1311 * @dev: Device to handle.
1313 * Choose the power state appropriate for the device depending on whether
1314 * it can wake up the system and/or is power manageable by the platform
1315 * (PCI_D3hot is the default) and put the device into that state.
1317 int pci_prepare_to_sleep(struct pci_dev
*dev
)
1319 pci_power_t target_state
= pci_target_state(dev
);
1322 if (target_state
== PCI_POWER_ERROR
)
1325 pci_enable_wake(dev
, target_state
, device_may_wakeup(&dev
->dev
));
1327 error
= pci_set_power_state(dev
, target_state
);
1330 pci_enable_wake(dev
, target_state
, false);
1336 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
1337 * @dev: Device to handle.
1339 * Disable device's sytem wake-up capability and put it into D0.
1341 int pci_back_from_sleep(struct pci_dev
*dev
)
1343 pci_enable_wake(dev
, PCI_D0
, false);
1344 return pci_set_power_state(dev
, PCI_D0
);
1348 * pci_pm_init - Initialize PM functions of given PCI device
1349 * @dev: PCI device to handle.
1351 void pci_pm_init(struct pci_dev
*dev
)
1358 /* find PCI PM capability in list */
1359 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
1362 /* Check device's ability to generate PME# */
1363 pci_read_config_word(dev
, pm
+ PCI_PM_PMC
, &pmc
);
1365 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 3) {
1366 dev_err(&dev
->dev
, "unsupported PM cap regs version (%u)\n",
1367 pmc
& PCI_PM_CAP_VER_MASK
);
1373 dev
->d1_support
= false;
1374 dev
->d2_support
= false;
1375 if (!pci_no_d1d2(dev
)) {
1376 if (pmc
& PCI_PM_CAP_D1
)
1377 dev
->d1_support
= true;
1378 if (pmc
& PCI_PM_CAP_D2
)
1379 dev
->d2_support
= true;
1381 if (dev
->d1_support
|| dev
->d2_support
)
1382 dev_printk(KERN_DEBUG
, &dev
->dev
, "supports%s%s\n",
1383 dev
->d1_support
? " D1" : "",
1384 dev
->d2_support
? " D2" : "");
1387 pmc
&= PCI_PM_CAP_PME_MASK
;
1389 dev_info(&dev
->dev
, "PME# supported from%s%s%s%s%s\n",
1390 (pmc
& PCI_PM_CAP_PME_D0
) ? " D0" : "",
1391 (pmc
& PCI_PM_CAP_PME_D1
) ? " D1" : "",
1392 (pmc
& PCI_PM_CAP_PME_D2
) ? " D2" : "",
1393 (pmc
& PCI_PM_CAP_PME_D3
) ? " D3hot" : "",
1394 (pmc
& PCI_PM_CAP_PME_D3cold
) ? " D3cold" : "");
1395 dev
->pme_support
= pmc
>> PCI_PM_CAP_PME_SHIFT
;
1397 * Make device's PM flags reflect the wake-up capability, but
1398 * let the user space enable it to wake up the system as needed.
1400 device_set_wakeup_capable(&dev
->dev
, true);
1401 device_set_wakeup_enable(&dev
->dev
, false);
1402 /* Disable the PME# generation functionality */
1403 pci_pme_active(dev
, false);
1405 dev
->pme_support
= 0;
1410 * platform_pci_wakeup_init - init platform wakeup if present
1413 * Some devices don't have PCI PM caps but can still generate wakeup
1414 * events through platform methods (like ACPI events). If @dev supports
1415 * platform wakeup events, set the device flag to indicate as much. This
1416 * may be redundant if the device also supports PCI PM caps, but double
1417 * initialization should be safe in that case.
1419 void platform_pci_wakeup_init(struct pci_dev
*dev
)
1421 if (!platform_pci_can_wakeup(dev
))
1424 device_set_wakeup_capable(&dev
->dev
, true);
1425 device_set_wakeup_enable(&dev
->dev
, false);
1426 platform_pci_sleep_wake(dev
, false);
1430 * pci_add_save_buffer - allocate buffer for saving given capability registers
1431 * @dev: the PCI device
1432 * @cap: the capability to allocate the buffer for
1433 * @size: requested size of the buffer
1435 static int pci_add_cap_save_buffer(
1436 struct pci_dev
*dev
, char cap
, unsigned int size
)
1439 struct pci_cap_saved_state
*save_state
;
1441 pos
= pci_find_capability(dev
, cap
);
1445 save_state
= kzalloc(sizeof(*save_state
) + size
, GFP_KERNEL
);
1449 save_state
->cap_nr
= cap
;
1450 pci_add_saved_cap(dev
, save_state
);
1456 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
1457 * @dev: the PCI device
1459 void pci_allocate_cap_save_buffers(struct pci_dev
*dev
)
1463 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_EXP
,
1464 PCI_EXP_SAVE_REGS
* sizeof(u16
));
1467 "unable to preallocate PCI Express save buffer\n");
1469 error
= pci_add_cap_save_buffer(dev
, PCI_CAP_ID_PCIX
, sizeof(u16
));
1472 "unable to preallocate PCI-X save buffer\n");
1476 * pci_enable_ari - enable ARI forwarding if hardware support it
1477 * @dev: the PCI device
1479 void pci_enable_ari(struct pci_dev
*dev
)
1484 struct pci_dev
*bridge
;
1486 if (!dev
->is_pcie
|| dev
->devfn
)
1489 pos
= pci_find_ext_capability(dev
, PCI_EXT_CAP_ID_ARI
);
1493 bridge
= dev
->bus
->self
;
1494 if (!bridge
|| !bridge
->is_pcie
)
1497 pos
= pci_find_capability(bridge
, PCI_CAP_ID_EXP
);
1501 pci_read_config_dword(bridge
, pos
+ PCI_EXP_DEVCAP2
, &cap
);
1502 if (!(cap
& PCI_EXP_DEVCAP2_ARI
))
1505 pci_read_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, &ctrl
);
1506 ctrl
|= PCI_EXP_DEVCTL2_ARI
;
1507 pci_write_config_word(bridge
, pos
+ PCI_EXP_DEVCTL2
, ctrl
);
1509 bridge
->ari_enabled
= 1;
1513 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
1514 * @dev: the PCI device
1515 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1517 * Perform INTx swizzling for a device behind one level of bridge. This is
1518 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
1519 * behind bridges on add-in cards.
1521 u8
pci_swizzle_interrupt_pin(struct pci_dev
*dev
, u8 pin
)
1523 return (((pin
- 1) + PCI_SLOT(dev
->devfn
)) % 4) + 1;
1527 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
1535 while (dev
->bus
->parent
) {
1536 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1537 dev
= dev
->bus
->self
;
1544 * pci_common_swizzle - swizzle INTx all the way to root bridge
1545 * @dev: the PCI device
1546 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
1548 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
1549 * bridges all the way up to a PCI root bus.
1551 u8
pci_common_swizzle(struct pci_dev
*dev
, u8
*pinp
)
1555 while (dev
->bus
->parent
) {
1556 pin
= pci_swizzle_interrupt_pin(dev
, pin
);
1557 dev
= dev
->bus
->self
;
1560 return PCI_SLOT(dev
->devfn
);
1564 * pci_release_region - Release a PCI bar
1565 * @pdev: PCI device whose resources were previously reserved by pci_request_region
1566 * @bar: BAR to release
1568 * Releases the PCI I/O and memory resources previously reserved by a
1569 * successful call to pci_request_region. Call this function only
1570 * after all use of the PCI regions has ceased.
1572 void pci_release_region(struct pci_dev
*pdev
, int bar
)
1574 struct pci_devres
*dr
;
1576 if (pci_resource_len(pdev
, bar
) == 0)
1578 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
1579 release_region(pci_resource_start(pdev
, bar
),
1580 pci_resource_len(pdev
, bar
));
1581 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
1582 release_mem_region(pci_resource_start(pdev
, bar
),
1583 pci_resource_len(pdev
, bar
));
1585 dr
= find_pci_dr(pdev
);
1587 dr
->region_mask
&= ~(1 << bar
);
1591 * __pci_request_region - Reserved PCI I/O and memory resource
1592 * @pdev: PCI device whose resources are to be reserved
1593 * @bar: BAR to be reserved
1594 * @res_name: Name to be associated with resource.
1595 * @exclusive: whether the region access is exclusive or not
1597 * Mark the PCI region associated with PCI device @pdev BR @bar as
1598 * being reserved by owner @res_name. Do not access any
1599 * address inside the PCI regions unless this call returns
1602 * If @exclusive is set, then the region is marked so that userspace
1603 * is explicitly not allowed to map the resource via /dev/mem or
1604 * sysfs MMIO access.
1606 * Returns 0 on success, or %EBUSY on error. A warning
1607 * message is also printed on failure.
1609 static int __pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
,
1612 struct pci_devres
*dr
;
1614 if (pci_resource_len(pdev
, bar
) == 0)
1617 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
1618 if (!request_region(pci_resource_start(pdev
, bar
),
1619 pci_resource_len(pdev
, bar
), res_name
))
1622 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
1623 if (!__request_mem_region(pci_resource_start(pdev
, bar
),
1624 pci_resource_len(pdev
, bar
), res_name
,
1629 dr
= find_pci_dr(pdev
);
1631 dr
->region_mask
|= 1 << bar
;
1636 dev_warn(&pdev
->dev
, "BAR %d: can't reserve %s region %pR\n",
1638 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
1639 &pdev
->resource
[bar
]);
1644 * pci_request_region - Reserve PCI I/O and memory resource
1645 * @pdev: PCI device whose resources are to be reserved
1646 * @bar: BAR to be reserved
1647 * @res_name: Name to be associated with resource
1649 * Mark the PCI region associated with PCI device @pdev BAR @bar as
1650 * being reserved by owner @res_name. Do not access any
1651 * address inside the PCI regions unless this call returns
1654 * Returns 0 on success, or %EBUSY on error. A warning
1655 * message is also printed on failure.
1657 int pci_request_region(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1659 return __pci_request_region(pdev
, bar
, res_name
, 0);
1663 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
1664 * @pdev: PCI device whose resources are to be reserved
1665 * @bar: BAR to be reserved
1666 * @res_name: Name to be associated with resource.
1668 * Mark the PCI region associated with PCI device @pdev BR @bar as
1669 * being reserved by owner @res_name. Do not access any
1670 * address inside the PCI regions unless this call returns
1673 * Returns 0 on success, or %EBUSY on error. A warning
1674 * message is also printed on failure.
1676 * The key difference that _exclusive makes it that userspace is
1677 * explicitly not allowed to map the resource via /dev/mem or
1680 int pci_request_region_exclusive(struct pci_dev
*pdev
, int bar
, const char *res_name
)
1682 return __pci_request_region(pdev
, bar
, res_name
, IORESOURCE_EXCLUSIVE
);
1685 * pci_release_selected_regions - Release selected PCI I/O and memory resources
1686 * @pdev: PCI device whose resources were previously reserved
1687 * @bars: Bitmask of BARs to be released
1689 * Release selected PCI I/O and memory resources previously reserved.
1690 * Call this function only after all use of the PCI regions has ceased.
1692 void pci_release_selected_regions(struct pci_dev
*pdev
, int bars
)
1696 for (i
= 0; i
< 6; i
++)
1697 if (bars
& (1 << i
))
1698 pci_release_region(pdev
, i
);
1701 int __pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1702 const char *res_name
, int excl
)
1706 for (i
= 0; i
< 6; i
++)
1707 if (bars
& (1 << i
))
1708 if (__pci_request_region(pdev
, i
, res_name
, excl
))
1714 if (bars
& (1 << i
))
1715 pci_release_region(pdev
, i
);
1722 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
1723 * @pdev: PCI device whose resources are to be reserved
1724 * @bars: Bitmask of BARs to be requested
1725 * @res_name: Name to be associated with resource
1727 int pci_request_selected_regions(struct pci_dev
*pdev
, int bars
,
1728 const char *res_name
)
1730 return __pci_request_selected_regions(pdev
, bars
, res_name
, 0);
1733 int pci_request_selected_regions_exclusive(struct pci_dev
*pdev
,
1734 int bars
, const char *res_name
)
1736 return __pci_request_selected_regions(pdev
, bars
, res_name
,
1737 IORESOURCE_EXCLUSIVE
);
1741 * pci_release_regions - Release reserved PCI I/O and memory resources
1742 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
1744 * Releases all PCI I/O and memory resources previously reserved by a
1745 * successful call to pci_request_regions. Call this function only
1746 * after all use of the PCI regions has ceased.
1749 void pci_release_regions(struct pci_dev
*pdev
)
1751 pci_release_selected_regions(pdev
, (1 << 6) - 1);
1755 * pci_request_regions - Reserved PCI I/O and memory resources
1756 * @pdev: PCI device whose resources are to be reserved
1757 * @res_name: Name to be associated with resource.
1759 * Mark all PCI regions associated with PCI device @pdev as
1760 * being reserved by owner @res_name. Do not access any
1761 * address inside the PCI regions unless this call returns
1764 * Returns 0 on success, or %EBUSY on error. A warning
1765 * message is also printed on failure.
1767 int pci_request_regions(struct pci_dev
*pdev
, const char *res_name
)
1769 return pci_request_selected_regions(pdev
, ((1 << 6) - 1), res_name
);
1773 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
1774 * @pdev: PCI device whose resources are to be reserved
1775 * @res_name: Name to be associated with resource.
1777 * Mark all PCI regions associated with PCI device @pdev as
1778 * being reserved by owner @res_name. Do not access any
1779 * address inside the PCI regions unless this call returns
1782 * pci_request_regions_exclusive() will mark the region so that
1783 * /dev/mem and the sysfs MMIO access will not be allowed.
1785 * Returns 0 on success, or %EBUSY on error. A warning
1786 * message is also printed on failure.
1788 int pci_request_regions_exclusive(struct pci_dev
*pdev
, const char *res_name
)
1790 return pci_request_selected_regions_exclusive(pdev
,
1791 ((1 << 6) - 1), res_name
);
1794 static void __pci_set_master(struct pci_dev
*dev
, bool enable
)
1798 pci_read_config_word(dev
, PCI_COMMAND
, &old_cmd
);
1800 cmd
= old_cmd
| PCI_COMMAND_MASTER
;
1802 cmd
= old_cmd
& ~PCI_COMMAND_MASTER
;
1803 if (cmd
!= old_cmd
) {
1804 dev_dbg(&dev
->dev
, "%s bus mastering\n",
1805 enable
? "enabling" : "disabling");
1806 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1808 dev
->is_busmaster
= enable
;
1812 * pci_set_master - enables bus-mastering for device dev
1813 * @dev: the PCI device to enable
1815 * Enables bus-mastering on the device and calls pcibios_set_master()
1816 * to do the needed arch specific settings.
1818 void pci_set_master(struct pci_dev
*dev
)
1820 __pci_set_master(dev
, true);
1821 pcibios_set_master(dev
);
1825 * pci_clear_master - disables bus-mastering for device dev
1826 * @dev: the PCI device to disable
1828 void pci_clear_master(struct pci_dev
*dev
)
1830 __pci_set_master(dev
, false);
1833 #ifdef PCI_DISABLE_MWI
1834 int pci_set_mwi(struct pci_dev
*dev
)
1839 int pci_try_set_mwi(struct pci_dev
*dev
)
1844 void pci_clear_mwi(struct pci_dev
*dev
)
1850 #ifndef PCI_CACHE_LINE_BYTES
1851 #define PCI_CACHE_LINE_BYTES L1_CACHE_BYTES
1854 /* This can be overridden by arch code. */
1855 /* Don't forget this is measured in 32-bit words, not bytes */
1856 u8 pci_cache_line_size
= PCI_CACHE_LINE_BYTES
/ 4;
1859 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
1860 * @dev: the PCI device for which MWI is to be enabled
1862 * Helper function for pci_set_mwi.
1863 * Originally copied from drivers/net/acenic.c.
1864 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
1866 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1869 pci_set_cacheline_size(struct pci_dev
*dev
)
1873 if (!pci_cache_line_size
)
1874 return -EINVAL
; /* The system doesn't support MWI. */
1876 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
1877 equal to or multiple of the right value. */
1878 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1879 if (cacheline_size
>= pci_cache_line_size
&&
1880 (cacheline_size
% pci_cache_line_size
) == 0)
1883 /* Write the correct value. */
1884 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
1886 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
1887 if (cacheline_size
== pci_cache_line_size
)
1890 dev_printk(KERN_DEBUG
, &dev
->dev
, "cache line size of %d is not "
1891 "supported\n", pci_cache_line_size
<< 2);
1897 * pci_set_mwi - enables memory-write-invalidate PCI transaction
1898 * @dev: the PCI device for which MWI is enabled
1900 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1902 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1905 pci_set_mwi(struct pci_dev
*dev
)
1910 rc
= pci_set_cacheline_size(dev
);
1914 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1915 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
1916 dev_dbg(&dev
->dev
, "enabling Mem-Wr-Inval\n");
1917 cmd
|= PCI_COMMAND_INVALIDATE
;
1918 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1925 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
1926 * @dev: the PCI device for which MWI is enabled
1928 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
1929 * Callers are not required to check the return value.
1931 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
1933 int pci_try_set_mwi(struct pci_dev
*dev
)
1935 int rc
= pci_set_mwi(dev
);
1940 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
1941 * @dev: the PCI device to disable
1943 * Disables PCI Memory-Write-Invalidate transaction on the device
1946 pci_clear_mwi(struct pci_dev
*dev
)
1950 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1951 if (cmd
& PCI_COMMAND_INVALIDATE
) {
1952 cmd
&= ~PCI_COMMAND_INVALIDATE
;
1953 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1956 #endif /* ! PCI_DISABLE_MWI */
1959 * pci_intx - enables/disables PCI INTx for device dev
1960 * @pdev: the PCI device to operate on
1961 * @enable: boolean: whether to enable or disable PCI INTx
1963 * Enables/disables PCI INTx for device dev
1966 pci_intx(struct pci_dev
*pdev
, int enable
)
1968 u16 pci_command
, new;
1970 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_command
);
1973 new = pci_command
& ~PCI_COMMAND_INTX_DISABLE
;
1975 new = pci_command
| PCI_COMMAND_INTX_DISABLE
;
1978 if (new != pci_command
) {
1979 struct pci_devres
*dr
;
1981 pci_write_config_word(pdev
, PCI_COMMAND
, new);
1983 dr
= find_pci_dr(pdev
);
1984 if (dr
&& !dr
->restore_intx
) {
1985 dr
->restore_intx
= 1;
1986 dr
->orig_intx
= !enable
;
1992 * pci_msi_off - disables any msi or msix capabilities
1993 * @dev: the PCI device to operate on
1995 * If you want to use msi see pci_enable_msi and friends.
1996 * This is a lower level primitive that allows us to disable
1997 * msi operation at the device level.
1999 void pci_msi_off(struct pci_dev
*dev
)
2004 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSI
);
2006 pci_read_config_word(dev
, pos
+ PCI_MSI_FLAGS
, &control
);
2007 control
&= ~PCI_MSI_FLAGS_ENABLE
;
2008 pci_write_config_word(dev
, pos
+ PCI_MSI_FLAGS
, control
);
2010 pos
= pci_find_capability(dev
, PCI_CAP_ID_MSIX
);
2012 pci_read_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, &control
);
2013 control
&= ~PCI_MSIX_FLAGS_ENABLE
;
2014 pci_write_config_word(dev
, pos
+ PCI_MSIX_FLAGS
, control
);
2018 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
2020 * These can be overridden by arch-specific implementations
2023 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
2025 if (!pci_dma_supported(dev
, mask
))
2028 dev
->dma_mask
= mask
;
2034 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
2036 if (!pci_dma_supported(dev
, mask
))
2039 dev
->dev
.coherent_dma_mask
= mask
;
2045 #ifndef HAVE_ARCH_PCI_SET_DMA_MAX_SEGMENT_SIZE
2046 int pci_set_dma_max_seg_size(struct pci_dev
*dev
, unsigned int size
)
2048 return dma_set_max_seg_size(&dev
->dev
, size
);
2050 EXPORT_SYMBOL(pci_set_dma_max_seg_size
);
2053 #ifndef HAVE_ARCH_PCI_SET_DMA_SEGMENT_BOUNDARY
2054 int pci_set_dma_seg_boundary(struct pci_dev
*dev
, unsigned long mask
)
2056 return dma_set_seg_boundary(&dev
->dev
, mask
);
2058 EXPORT_SYMBOL(pci_set_dma_seg_boundary
);
2061 static int __pcie_flr(struct pci_dev
*dev
, int probe
)
2065 int exppos
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2069 pci_read_config_dword(dev
, exppos
+ PCI_EXP_DEVCAP
, &cap
);
2070 if (!(cap
& PCI_EXP_DEVCAP_FLR
))
2076 pci_block_user_cfg_access(dev
);
2078 /* Wait for Transaction Pending bit clean */
2079 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2080 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2081 goto transaction_done
;
2084 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2085 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
2086 goto transaction_done
;
2088 dev_info(&dev
->dev
, "Busy after 100ms while trying to reset; "
2089 "sleeping for 1 second\n");
2091 pci_read_config_word(dev
, exppos
+ PCI_EXP_DEVSTA
, &status
);
2092 if (status
& PCI_EXP_DEVSTA_TRPND
)
2093 dev_info(&dev
->dev
, "Still busy after 1s; "
2094 "proceeding with reset anyway\n");
2097 pci_write_config_word(dev
, exppos
+ PCI_EXP_DEVCTL
,
2098 PCI_EXP_DEVCTL_BCR_FLR
);
2101 pci_unblock_user_cfg_access(dev
);
2105 static int __pci_af_flr(struct pci_dev
*dev
, int probe
)
2107 int cappos
= pci_find_capability(dev
, PCI_CAP_ID_AF
);
2113 pci_read_config_byte(dev
, cappos
+ PCI_AF_CAP
, &cap
);
2114 if (!(cap
& PCI_AF_CAP_TP
) || !(cap
& PCI_AF_CAP_FLR
))
2120 pci_block_user_cfg_access(dev
);
2122 /* Wait for Transaction Pending bit clean */
2123 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2124 if (!(status
& PCI_AF_STATUS_TP
))
2125 goto transaction_done
;
2128 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2129 if (!(status
& PCI_AF_STATUS_TP
))
2130 goto transaction_done
;
2132 dev_info(&dev
->dev
, "Busy after 100ms while trying to"
2133 " reset; sleeping for 1 second\n");
2135 pci_read_config_byte(dev
, cappos
+ PCI_AF_STATUS
, &status
);
2136 if (status
& PCI_AF_STATUS_TP
)
2137 dev_info(&dev
->dev
, "Still busy after 1s; "
2138 "proceeding with reset anyway\n");
2141 pci_write_config_byte(dev
, cappos
+ PCI_AF_CTRL
, PCI_AF_CTRL_FLR
);
2144 pci_unblock_user_cfg_access(dev
);
2148 static int __pci_reset_function(struct pci_dev
*pdev
, int probe
)
2152 res
= __pcie_flr(pdev
, probe
);
2156 res
= __pci_af_flr(pdev
, probe
);
2164 * pci_execute_reset_function() - Reset a PCI device function
2165 * @dev: Device function to reset
2167 * Some devices allow an individual function to be reset without affecting
2168 * other functions in the same device. The PCI device must be responsive
2169 * to PCI config space in order to use this function.
2171 * The device function is presumed to be unused when this function is called.
2172 * Resetting the device will make the contents of PCI configuration space
2173 * random, so any caller of this must be prepared to reinitialise the
2174 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
2177 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2178 * device doesn't support resetting a single function.
2180 int pci_execute_reset_function(struct pci_dev
*dev
)
2182 return __pci_reset_function(dev
, 0);
2184 EXPORT_SYMBOL_GPL(pci_execute_reset_function
);
2187 * pci_reset_function() - quiesce and reset a PCI device function
2188 * @dev: Device function to reset
2190 * Some devices allow an individual function to be reset without affecting
2191 * other functions in the same device. The PCI device must be responsive
2192 * to PCI config space in order to use this function.
2194 * This function does not just reset the PCI portion of a device, but
2195 * clears all the state associated with the device. This function differs
2196 * from pci_execute_reset_function in that it saves and restores device state
2199 * Returns 0 if the device function was successfully reset or -ENOTTY if the
2200 * device doesn't support resetting a single function.
2202 int pci_reset_function(struct pci_dev
*dev
)
2204 int r
= __pci_reset_function(dev
, 1);
2209 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2210 disable_irq(dev
->irq
);
2211 pci_save_state(dev
);
2213 pci_write_config_word(dev
, PCI_COMMAND
, PCI_COMMAND_INTX_DISABLE
);
2215 r
= pci_execute_reset_function(dev
);
2217 pci_restore_state(dev
);
2218 if (!dev
->msi_enabled
&& !dev
->msix_enabled
&& dev
->irq
!= 0)
2219 enable_irq(dev
->irq
);
2223 EXPORT_SYMBOL_GPL(pci_reset_function
);
2226 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
2227 * @dev: PCI device to query
2229 * Returns mmrbc: maximum designed memory read count in bytes
2230 * or appropriate error value.
2232 int pcix_get_max_mmrbc(struct pci_dev
*dev
)
2237 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2241 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2245 return (stat
& PCI_X_STATUS_MAX_READ
) >> 12;
2247 EXPORT_SYMBOL(pcix_get_max_mmrbc
);
2250 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
2251 * @dev: PCI device to query
2253 * Returns mmrbc: maximum memory read count in bytes
2254 * or appropriate error value.
2256 int pcix_get_mmrbc(struct pci_dev
*dev
)
2261 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2265 ret
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2267 ret
= 512 << ((cmd
& PCI_X_CMD_MAX_READ
) >> 2);
2271 EXPORT_SYMBOL(pcix_get_mmrbc
);
2274 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
2275 * @dev: PCI device to query
2276 * @mmrbc: maximum memory read count in bytes
2277 * valid values are 512, 1024, 2048, 4096
2279 * If possible sets maximum memory read byte count, some bridges have erratas
2280 * that prevent this.
2282 int pcix_set_mmrbc(struct pci_dev
*dev
, int mmrbc
)
2284 int cap
, err
= -EINVAL
;
2285 u32 stat
, cmd
, v
, o
;
2287 if (mmrbc
< 512 || mmrbc
> 4096 || !is_power_of_2(mmrbc
))
2290 v
= ffs(mmrbc
) - 10;
2292 cap
= pci_find_capability(dev
, PCI_CAP_ID_PCIX
);
2296 err
= pci_read_config_dword(dev
, cap
+ PCI_X_STATUS
, &stat
);
2300 if (v
> (stat
& PCI_X_STATUS_MAX_READ
) >> 21)
2303 err
= pci_read_config_dword(dev
, cap
+ PCI_X_CMD
, &cmd
);
2307 o
= (cmd
& PCI_X_CMD_MAX_READ
) >> 2;
2309 if (v
> o
&& dev
->bus
&&
2310 (dev
->bus
->bus_flags
& PCI_BUS_FLAGS_NO_MMRBC
))
2313 cmd
&= ~PCI_X_CMD_MAX_READ
;
2315 err
= pci_write_config_dword(dev
, cap
+ PCI_X_CMD
, cmd
);
2320 EXPORT_SYMBOL(pcix_set_mmrbc
);
2323 * pcie_get_readrq - get PCI Express read request size
2324 * @dev: PCI device to query
2326 * Returns maximum memory read request in bytes
2327 * or appropriate error value.
2329 int pcie_get_readrq(struct pci_dev
*dev
)
2334 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2338 ret
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2340 ret
= 128 << ((ctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
2344 EXPORT_SYMBOL(pcie_get_readrq
);
2347 * pcie_set_readrq - set PCI Express maximum memory read request
2348 * @dev: PCI device to query
2349 * @rq: maximum memory read count in bytes
2350 * valid values are 128, 256, 512, 1024, 2048, 4096
2352 * If possible sets maximum read byte count
2354 int pcie_set_readrq(struct pci_dev
*dev
, int rq
)
2356 int cap
, err
= -EINVAL
;
2359 if (rq
< 128 || rq
> 4096 || !is_power_of_2(rq
))
2362 v
= (ffs(rq
) - 8) << 12;
2364 cap
= pci_find_capability(dev
, PCI_CAP_ID_EXP
);
2368 err
= pci_read_config_word(dev
, cap
+ PCI_EXP_DEVCTL
, &ctl
);
2372 if ((ctl
& PCI_EXP_DEVCTL_READRQ
) != v
) {
2373 ctl
&= ~PCI_EXP_DEVCTL_READRQ
;
2375 err
= pci_write_config_dword(dev
, cap
+ PCI_EXP_DEVCTL
, ctl
);
2381 EXPORT_SYMBOL(pcie_set_readrq
);
2384 * pci_select_bars - Make BAR mask from the type of resource
2385 * @dev: the PCI device for which BAR mask is made
2386 * @flags: resource type mask to be selected
2388 * This helper routine makes bar mask from the type of resource.
2390 int pci_select_bars(struct pci_dev
*dev
, unsigned long flags
)
2393 for (i
= 0; i
< PCI_NUM_RESOURCES
; i
++)
2394 if (pci_resource_flags(dev
, i
) & flags
)
2400 * pci_resource_bar - get position of the BAR associated with a resource
2401 * @dev: the PCI device
2402 * @resno: the resource number
2403 * @type: the BAR type to be filled in
2405 * Returns BAR position in config space, or 0 if the BAR is invalid.
2407 int pci_resource_bar(struct pci_dev
*dev
, int resno
, enum pci_bar_type
*type
)
2411 if (resno
< PCI_ROM_RESOURCE
) {
2412 *type
= pci_bar_unknown
;
2413 return PCI_BASE_ADDRESS_0
+ 4 * resno
;
2414 } else if (resno
== PCI_ROM_RESOURCE
) {
2415 *type
= pci_bar_mem32
;
2416 return dev
->rom_base_reg
;
2417 } else if (resno
< PCI_BRIDGE_RESOURCES
) {
2418 /* device specific resource */
2419 reg
= pci_iov_resource_bar(dev
, resno
, type
);
2424 dev_err(&dev
->dev
, "BAR: invalid resource #%d\n", resno
);
2428 #define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
2429 static char resource_alignment_param
[RESOURCE_ALIGNMENT_PARAM_SIZE
] = {0};
2430 spinlock_t resource_alignment_lock
= SPIN_LOCK_UNLOCKED
;
2433 * pci_specified_resource_alignment - get resource alignment specified by user.
2434 * @dev: the PCI device to get
2436 * RETURNS: Resource alignment if it is specified.
2437 * Zero if it is not specified.
2439 resource_size_t
pci_specified_resource_alignment(struct pci_dev
*dev
)
2441 int seg
, bus
, slot
, func
, align_order
, count
;
2442 resource_size_t align
= 0;
2445 spin_lock(&resource_alignment_lock
);
2446 p
= resource_alignment_param
;
2449 if (sscanf(p
, "%d%n", &align_order
, &count
) == 1 &&
2455 if (sscanf(p
, "%x:%x:%x.%x%n",
2456 &seg
, &bus
, &slot
, &func
, &count
) != 4) {
2458 if (sscanf(p
, "%x:%x.%x%n",
2459 &bus
, &slot
, &func
, &count
) != 3) {
2460 /* Invalid format */
2461 printk(KERN_ERR
"PCI: Can't parse resource_alignment parameter: %s\n",
2467 if (seg
== pci_domain_nr(dev
->bus
) &&
2468 bus
== dev
->bus
->number
&&
2469 slot
== PCI_SLOT(dev
->devfn
) &&
2470 func
== PCI_FUNC(dev
->devfn
)) {
2471 if (align_order
== -1) {
2474 align
= 1 << align_order
;
2479 if (*p
!= ';' && *p
!= ',') {
2480 /* End of param or invalid format */
2485 spin_unlock(&resource_alignment_lock
);
2490 * pci_is_reassigndev - check if specified PCI is target device to reassign
2491 * @dev: the PCI device to check
2493 * RETURNS: non-zero for PCI device is a target device to reassign,
2496 int pci_is_reassigndev(struct pci_dev
*dev
)
2498 return (pci_specified_resource_alignment(dev
) != 0);
2501 ssize_t
pci_set_resource_alignment_param(const char *buf
, size_t count
)
2503 if (count
> RESOURCE_ALIGNMENT_PARAM_SIZE
- 1)
2504 count
= RESOURCE_ALIGNMENT_PARAM_SIZE
- 1;
2505 spin_lock(&resource_alignment_lock
);
2506 strncpy(resource_alignment_param
, buf
, count
);
2507 resource_alignment_param
[count
] = '\0';
2508 spin_unlock(&resource_alignment_lock
);
2512 ssize_t
pci_get_resource_alignment_param(char *buf
, size_t size
)
2515 spin_lock(&resource_alignment_lock
);
2516 count
= snprintf(buf
, size
, "%s", resource_alignment_param
);
2517 spin_unlock(&resource_alignment_lock
);
2521 static ssize_t
pci_resource_alignment_show(struct bus_type
*bus
, char *buf
)
2523 return pci_get_resource_alignment_param(buf
, PAGE_SIZE
);
2526 static ssize_t
pci_resource_alignment_store(struct bus_type
*bus
,
2527 const char *buf
, size_t count
)
2529 return pci_set_resource_alignment_param(buf
, count
);
2532 BUS_ATTR(resource_alignment
, 0644, pci_resource_alignment_show
,
2533 pci_resource_alignment_store
);
2535 static int __init
pci_resource_alignment_sysfs_init(void)
2537 return bus_create_file(&pci_bus_type
,
2538 &bus_attr_resource_alignment
);
2541 late_initcall(pci_resource_alignment_sysfs_init
);
2543 static void __devinit
pci_no_domains(void)
2545 #ifdef CONFIG_PCI_DOMAINS
2546 pci_domains_supported
= 0;
2551 * pci_ext_cfg_enabled - can we access extended PCI config space?
2552 * @dev: The PCI device of the root bridge.
2554 * Returns 1 if we can access PCI extended config space (offsets
2555 * greater than 0xff). This is the default implementation. Architecture
2556 * implementations can override this.
2558 int __attribute__ ((weak
)) pci_ext_cfg_avail(struct pci_dev
*dev
)
2563 static int __devinit
pci_init(void)
2565 struct pci_dev
*dev
= NULL
;
2567 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
2568 pci_fixup_device(pci_fixup_final
, dev
);
2574 static int __init
pci_setup(char *str
)
2577 char *k
= strchr(str
, ',');
2580 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
2581 if (!strcmp(str
, "nomsi")) {
2583 } else if (!strcmp(str
, "noaer")) {
2585 } else if (!strcmp(str
, "nodomains")) {
2587 } else if (!strncmp(str
, "cbiosize=", 9)) {
2588 pci_cardbus_io_size
= memparse(str
+ 9, &str
);
2589 } else if (!strncmp(str
, "cbmemsize=", 10)) {
2590 pci_cardbus_mem_size
= memparse(str
+ 10, &str
);
2591 } else if (!strncmp(str
, "resource_alignment=", 19)) {
2592 pci_set_resource_alignment_param(str
+ 19,
2595 printk(KERN_ERR
"PCI: Unknown option `%s'\n",
2603 early_param("pci", pci_setup
);
2605 device_initcall(pci_init
);
2607 EXPORT_SYMBOL(pci_reenable_device
);
2608 EXPORT_SYMBOL(pci_enable_device_io
);
2609 EXPORT_SYMBOL(pci_enable_device_mem
);
2610 EXPORT_SYMBOL(pci_enable_device
);
2611 EXPORT_SYMBOL(pcim_enable_device
);
2612 EXPORT_SYMBOL(pcim_pin_device
);
2613 EXPORT_SYMBOL(pci_disable_device
);
2614 EXPORT_SYMBOL(pci_find_capability
);
2615 EXPORT_SYMBOL(pci_bus_find_capability
);
2616 EXPORT_SYMBOL(pci_release_regions
);
2617 EXPORT_SYMBOL(pci_request_regions
);
2618 EXPORT_SYMBOL(pci_request_regions_exclusive
);
2619 EXPORT_SYMBOL(pci_release_region
);
2620 EXPORT_SYMBOL(pci_request_region
);
2621 EXPORT_SYMBOL(pci_request_region_exclusive
);
2622 EXPORT_SYMBOL(pci_release_selected_regions
);
2623 EXPORT_SYMBOL(pci_request_selected_regions
);
2624 EXPORT_SYMBOL(pci_request_selected_regions_exclusive
);
2625 EXPORT_SYMBOL(pci_set_master
);
2626 EXPORT_SYMBOL(pci_clear_master
);
2627 EXPORT_SYMBOL(pci_set_mwi
);
2628 EXPORT_SYMBOL(pci_try_set_mwi
);
2629 EXPORT_SYMBOL(pci_clear_mwi
);
2630 EXPORT_SYMBOL_GPL(pci_intx
);
2631 EXPORT_SYMBOL(pci_set_dma_mask
);
2632 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
2633 EXPORT_SYMBOL(pci_assign_resource
);
2634 EXPORT_SYMBOL(pci_find_parent_resource
);
2635 EXPORT_SYMBOL(pci_select_bars
);
2637 EXPORT_SYMBOL(pci_set_power_state
);
2638 EXPORT_SYMBOL(pci_save_state
);
2639 EXPORT_SYMBOL(pci_restore_state
);
2640 EXPORT_SYMBOL(pci_pme_capable
);
2641 EXPORT_SYMBOL(pci_pme_active
);
2642 EXPORT_SYMBOL(pci_enable_wake
);
2643 EXPORT_SYMBOL(pci_wake_from_d3
);
2644 EXPORT_SYMBOL(pci_target_state
);
2645 EXPORT_SYMBOL(pci_prepare_to_sleep
);
2646 EXPORT_SYMBOL(pci_back_from_sleep
);
2647 EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state
);