5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NO_MACH_MEMORY_H
217 Select this when mach/memory.h is removed.
220 hex "Physical address of main memory"
221 depends on !ARM_PATCH_PHYS_VIRT && NO_MACH_MEMORY_H
223 Please provide the physical address corresponding to the
224 location of main memory in your system.
226 source "init/Kconfig"
228 source "kernel/Kconfig.freezer"
233 bool "MMU-based Paged Memory Management Support"
236 Select if you want MMU-based virtualised addressing space
237 support by paged memory management. If unsure, say 'Y'.
240 # The "ARM system type" choice list is ordered alphabetically by option
241 # text. Please add new entries in the option alphabetic order.
244 prompt "ARM system type"
245 default ARCH_VERSATILE
247 config ARCH_INTEGRATOR
248 bool "ARM Ltd. Integrator family"
250 select ARCH_HAS_CPUFREQ
252 select HAVE_MACH_CLKDEV
254 select GENERIC_CLOCKEVENTS
255 select PLAT_VERSATILE
256 select PLAT_VERSATILE_FPGA_IRQ
258 Support for ARM's Integrator platform.
261 bool "ARM Ltd. RealView family"
264 select HAVE_MACH_CLKDEV
266 select GENERIC_CLOCKEVENTS
267 select ARCH_WANT_OPTIONAL_GPIOLIB
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_CLCD
270 select ARM_TIMER_SP804
271 select GPIO_PL061 if GPIOLIB
273 This enables support for ARM Ltd RealView boards.
275 config ARCH_VERSATILE
276 bool "ARM Ltd. Versatile family"
280 select HAVE_MACH_CLKDEV
282 select GENERIC_CLOCKEVENTS
283 select ARCH_WANT_OPTIONAL_GPIOLIB
284 select PLAT_VERSATILE
285 select PLAT_VERSATILE_CLCD
286 select PLAT_VERSATILE_FPGA_IRQ
287 select ARM_TIMER_SP804
288 select NO_MACH_MEMORY_H
290 This enables support for ARM Ltd Versatile board.
293 bool "ARM Ltd. Versatile Express family"
294 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select ARM_TIMER_SP804
298 select HAVE_MACH_CLKDEV
299 select GENERIC_CLOCKEVENTS
301 select HAVE_PATA_PLATFORM
303 select PLAT_VERSATILE
304 select PLAT_VERSATILE_CLCD
305 select NO_MACH_MEMORY_H
307 This enables support for the ARM Ltd Versatile Express boards.
311 select ARCH_REQUIRE_GPIOLIB
315 This enables support for systems based on the Atmel AT91RM9200,
316 AT91SAM9 and AT91CAP9 processors.
319 bool "Broadcom BCMRING"
323 select ARM_TIMER_SP804
325 select GENERIC_CLOCKEVENTS
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 Support for Broadcom's BCMRing platform.
331 bool "Cirrus Logic CLPS711x/EP721x-based"
333 select ARCH_USES_GETTIMEOFFSET
335 Support for Cirrus Logic 711x/721x based boards.
338 bool "Cavium Networks CNS3XXX family"
340 select GENERIC_CLOCKEVENTS
342 select MIGHT_HAVE_PCI
343 select PCI_DOMAINS if PCI
344 select NO_MACH_MEMORY_H
346 Support for Cavium Networks CNS3XXX platform.
349 bool "Cortina Systems Gemini"
351 select ARCH_REQUIRE_GPIOLIB
352 select ARCH_USES_GETTIMEOFFSET
353 select NO_MACH_MEMORY_H
355 Support for the Cortina Systems Gemini family SoCs
358 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
362 select GENERIC_CLOCKEVENTS
364 select GENERIC_IRQ_CHIP
368 Support for CSR SiRFSoC ARM Cortex A9 Platform
375 select ARCH_USES_GETTIMEOFFSET
377 This is an evaluation board for the StrongARM processor available
378 from Digital. It has limited hardware on-board, including an
379 Ethernet interface, two PCMCIA sockets, two serial ports and a
388 select ARCH_REQUIRE_GPIOLIB
389 select ARCH_HAS_HOLES_MEMORYMODEL
390 select ARCH_USES_GETTIMEOFFSET
392 This enables support for the Cirrus EP93xx series of CPUs.
394 config ARCH_FOOTBRIDGE
398 select GENERIC_CLOCKEVENTS
400 Support for systems based on the DC21285 companion chip
401 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
404 bool "Freescale MXC/iMX-based"
405 select GENERIC_CLOCKEVENTS
406 select ARCH_REQUIRE_GPIOLIB
409 select GENERIC_IRQ_CHIP
410 select HAVE_SCHED_CLOCK
412 Support for Freescale MXC/iMX-based family of processors
415 bool "Freescale MXS-based"
416 select GENERIC_CLOCKEVENTS
417 select ARCH_REQUIRE_GPIOLIB
420 select NO_MACH_MEMORY_H
422 Support for Freescale MXS-based family of processors
425 bool "Hilscher NetX based"
429 select GENERIC_CLOCKEVENTS
430 select NO_MACH_MEMORY_H
432 This enables support for systems based on the Hilscher NetX Soc
435 bool "Hynix HMS720x-based"
438 select ARCH_USES_GETTIMEOFFSET
439 select NO_MACH_MEMORY_H
441 This enables support for systems based on the Hynix HMS720x
449 select ARCH_SUPPORTS_MSI
452 Support for Intel's IOP13XX (XScale) family of processors.
460 select ARCH_REQUIRE_GPIOLIB
461 select NO_MACH_MEMORY_H
463 Support for Intel's 80219 and IOP32X (XScale) family of
472 select ARCH_REQUIRE_GPIOLIB
473 select NO_MACH_MEMORY_H
475 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_USES_GETTIMEOFFSET
484 Support for Intel's IXP23xx (XScale) family of processors.
487 bool "IXP2400/2800-based"
491 select ARCH_USES_GETTIMEOFFSET
493 Support for Intel's IXP2400/2800 (XScale) family of processors.
501 select GENERIC_CLOCKEVENTS
502 select HAVE_SCHED_CLOCK
503 select MIGHT_HAVE_PCI
504 select DMABOUNCE if PCI
505 select NO_MACH_MEMORY_H
507 Support for Intel's IXP4XX (XScale) family of processors.
513 select ARCH_REQUIRE_GPIOLIB
514 select GENERIC_CLOCKEVENTS
516 select NO_MACH_MEMORY_H
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
527 select NO_MACH_MEMORY_H
529 Support for the following Marvell Kirkwood series SoCs:
530 88F6180, 88F6192 and 88F6281.
536 select ARCH_REQUIRE_GPIOLIB
539 select USB_ARCH_HAS_OHCI
542 select GENERIC_CLOCKEVENTS
543 select NO_MACH_MEMORY_H
545 Support for the NXP LPC32XX family of processors
548 bool "Marvell MV78xx0"
551 select ARCH_REQUIRE_GPIOLIB
552 select GENERIC_CLOCKEVENTS
554 select NO_MACH_MEMORY_H
556 Support for the following Marvell MV78xx0 series SoCs:
564 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_CLOCKEVENTS
567 select NO_MACH_MEMORY_H
569 Support for the following Marvell Orion 5x series SoCs:
570 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
571 Orion-2 (5281), Orion-1-90 (6183).
574 bool "Marvell PXA168/910/MMP2"
576 select ARCH_REQUIRE_GPIOLIB
578 select GENERIC_CLOCKEVENTS
579 select HAVE_SCHED_CLOCK
583 select NO_MACH_MEMORY_H
585 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
588 bool "Micrel/Kendin KS8695"
590 select ARCH_REQUIRE_GPIOLIB
591 select ARCH_USES_GETTIMEOFFSET
593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
594 System-on-Chip devices.
597 bool "Nuvoton W90X900 CPU"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NO_MACH_MEMORY_H
605 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
606 At present, the w90x900 has been renamed nuc900, regarding
607 the ARM series product line, you can login the following
608 link address to know more.
610 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
611 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
614 bool "Nuvoton NUC93X CPU"
617 select NO_MACH_MEMORY_H
619 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
620 low-power and high performance MPEG-4/JPEG multimedia controller chip.
627 select GENERIC_CLOCKEVENTS
630 select HAVE_SCHED_CLOCK
631 select ARCH_HAS_CPUFREQ
632 select NO_MACH_MEMORY_H
634 This enables support for NVIDIA Tegra based systems (Tegra APX,
635 Tegra 6xx and Tegra 2 series).
638 bool "Philips Nexperia PNX4008 Mobile"
641 select ARCH_USES_GETTIMEOFFSET
642 select NO_MACH_MEMORY_H
644 This enables support for Philips PNX4008 mobile platform.
647 bool "PXA2xx/PXA3xx-based"
650 select ARCH_HAS_CPUFREQ
653 select ARCH_REQUIRE_GPIOLIB
654 select GENERIC_CLOCKEVENTS
655 select HAVE_SCHED_CLOCK
660 select MULTI_IRQ_HANDLER
661 select NO_MACH_MEMORY_H
663 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
668 select GENERIC_CLOCKEVENTS
669 select ARCH_REQUIRE_GPIOLIB
671 select NO_MACH_MEMORY_H
673 Support for Qualcomm MSM/QSD based systems. This runs on the
674 apps processor of the MSM/QSD and depends on a shared memory
675 interface to the modem processor which runs the baseband
676 stack and controls some vital subsystems
677 (clock and power control, etc).
680 bool "Renesas SH-Mobile / R-Mobile"
683 select HAVE_MACH_CLKDEV
684 select GENERIC_CLOCKEVENTS
687 select MULTI_IRQ_HANDLER
688 select PM_GENERIC_DOMAINS if PM
690 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
697 select ARCH_MAY_HAVE_PC_FDC
698 select HAVE_PATA_PLATFORM
701 select ARCH_SPARSEMEM_ENABLE
702 select ARCH_USES_GETTIMEOFFSET
704 On the Acorn Risc-PC, Linux can support the internal IDE disk and
705 CD-ROM interface, serial and parallel port, and the floppy drive.
712 select ARCH_SPARSEMEM_ENABLE
714 select ARCH_HAS_CPUFREQ
716 select GENERIC_CLOCKEVENTS
718 select HAVE_SCHED_CLOCK
720 select ARCH_REQUIRE_GPIOLIB
722 Support for StrongARM 11x0 based boards.
725 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
727 select ARCH_HAS_CPUFREQ
730 select ARCH_USES_GETTIMEOFFSET
731 select HAVE_S3C2410_I2C if I2C
732 select NO_MACH_MEMORY_H
734 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
735 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
736 the Samsung SMDK2410 development board (and derivatives).
738 Note, the S3C2416 and the S3C2450 are so close that they even share
739 the same SoC ID code. This means that there is no separate machine
740 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
743 bool "Samsung S3C64XX"
750 select ARCH_USES_GETTIMEOFFSET
751 select ARCH_HAS_CPUFREQ
752 select ARCH_REQUIRE_GPIOLIB
753 select SAMSUNG_CLKSRC
754 select SAMSUNG_IRQ_VIC_TIMER
755 select SAMSUNG_IRQ_UART
756 select S3C_GPIO_TRACK
757 select S3C_GPIO_PULL_UPDOWN
758 select S3C_GPIO_CFG_S3C24XX
759 select S3C_GPIO_CFG_S3C64XX
761 select USB_ARCH_HAS_OHCI
762 select SAMSUNG_GPIOLIB_4BIT
763 select HAVE_S3C2410_I2C if I2C
764 select HAVE_S3C2410_WATCHDOG if WATCHDOG
766 Samsung S3C64XX series based systems
769 bool "Samsung S5P6440 S5P6450"
775 select HAVE_S3C2410_WATCHDOG if WATCHDOG
776 select GENERIC_CLOCKEVENTS
777 select HAVE_SCHED_CLOCK
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C_RTC if RTC_CLASS
781 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
785 bool "Samsung S5PC100"
790 select ARM_L1_CACHE_SHIFT_6
791 select ARCH_USES_GETTIMEOFFSET
792 select HAVE_S3C2410_I2C if I2C
793 select HAVE_S3C_RTC if RTC_CLASS
794 select HAVE_S3C2410_WATCHDOG if WATCHDOG
795 select NO_MACH_MEMORY_H
797 Samsung S5PC100 series based systems
800 bool "Samsung S5PV210/S5PC110"
802 select ARCH_SPARSEMEM_ENABLE
803 select ARCH_HAS_HOLES_MEMORYMODEL
808 select ARM_L1_CACHE_SHIFT_6
809 select ARCH_HAS_CPUFREQ
810 select GENERIC_CLOCKEVENTS
811 select HAVE_SCHED_CLOCK
812 select HAVE_S3C2410_I2C if I2C
813 select HAVE_S3C_RTC if RTC_CLASS
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
816 Samsung S5PV210/S5PC110 series based systems
819 bool "Samsung EXYNOS4"
821 select ARCH_SPARSEMEM_ENABLE
822 select ARCH_HAS_HOLES_MEMORYMODEL
826 select ARCH_HAS_CPUFREQ
827 select GENERIC_CLOCKEVENTS
828 select HAVE_S3C_RTC if RTC_CLASS
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
832 Samsung EXYNOS4 series based systems
841 select ARCH_USES_GETTIMEOFFSET
843 Support for the StrongARM based Digital DNARD machine, also known
844 as "Shark" (<http://www.shark-linux.de/shark.html>).
847 bool "Telechips TCC ARM926-based systems"
852 select GENERIC_CLOCKEVENTS
853 select NO_MACH_MEMORY_H
855 Support for Telechips TCC ARM926-based systems.
858 bool "ST-Ericsson U300 Series"
862 select HAVE_SCHED_CLOCK
866 select GENERIC_CLOCKEVENTS
868 select HAVE_MACH_CLKDEV
871 Support for ST-Ericsson U300 series mobile platforms.
874 bool "ST-Ericsson U8500 Series"
877 select GENERIC_CLOCKEVENTS
879 select ARCH_REQUIRE_GPIOLIB
880 select ARCH_HAS_CPUFREQ
881 select NO_MACH_MEMORY_H
883 Support for ST-Ericsson's Ux500 architecture
886 bool "STMicroelectronics Nomadik"
891 select GENERIC_CLOCKEVENTS
892 select ARCH_REQUIRE_GPIOLIB
893 select NO_MACH_MEMORY_H
895 Support for the Nomadik platform by ST-Ericsson
899 select GENERIC_CLOCKEVENTS
900 select ARCH_REQUIRE_GPIOLIB
904 select GENERIC_ALLOCATOR
905 select GENERIC_IRQ_CHIP
906 select ARCH_HAS_HOLES_MEMORYMODEL
907 select NO_MACH_MEMORY_H
909 Support for TI's DaVinci platform.
914 select ARCH_REQUIRE_GPIOLIB
915 select ARCH_HAS_CPUFREQ
917 select GENERIC_CLOCKEVENTS
918 select HAVE_SCHED_CLOCK
919 select ARCH_HAS_HOLES_MEMORYMODEL
921 Support for TI's OMAP platform (OMAP1/2/3/4).
926 select ARCH_REQUIRE_GPIOLIB
929 select GENERIC_CLOCKEVENTS
931 select NO_MACH_MEMORY_H
933 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
936 bool "VIA/WonderMedia 85xx"
939 select ARCH_HAS_CPUFREQ
940 select GENERIC_CLOCKEVENTS
941 select ARCH_REQUIRE_GPIOLIB
943 select NO_MACH_MEMORY_H
945 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
948 bool "Xilinx Zynq ARM Cortex A9 Platform"
951 select GENERIC_CLOCKEVENTS
958 Support for Xilinx Zynq ARM Cortex A9 Platform
962 # This is sorted alphabetically by mach-* pathname. However, plat-*
963 # Kconfigs may be included either alphabetically (according to the
964 # plat- suffix) or along side the corresponding mach-* source.
966 source "arch/arm/mach-at91/Kconfig"
968 source "arch/arm/mach-bcmring/Kconfig"
970 source "arch/arm/mach-clps711x/Kconfig"
972 source "arch/arm/mach-cns3xxx/Kconfig"
974 source "arch/arm/mach-davinci/Kconfig"
976 source "arch/arm/mach-dove/Kconfig"
978 source "arch/arm/mach-ep93xx/Kconfig"
980 source "arch/arm/mach-footbridge/Kconfig"
982 source "arch/arm/mach-gemini/Kconfig"
984 source "arch/arm/mach-h720x/Kconfig"
986 source "arch/arm/mach-integrator/Kconfig"
988 source "arch/arm/mach-iop32x/Kconfig"
990 source "arch/arm/mach-iop33x/Kconfig"
992 source "arch/arm/mach-iop13xx/Kconfig"
994 source "arch/arm/mach-ixp4xx/Kconfig"
996 source "arch/arm/mach-ixp2000/Kconfig"
998 source "arch/arm/mach-ixp23xx/Kconfig"
1000 source "arch/arm/mach-kirkwood/Kconfig"
1002 source "arch/arm/mach-ks8695/Kconfig"
1004 source "arch/arm/mach-lpc32xx/Kconfig"
1006 source "arch/arm/mach-msm/Kconfig"
1008 source "arch/arm/mach-mv78xx0/Kconfig"
1010 source "arch/arm/plat-mxc/Kconfig"
1012 source "arch/arm/mach-mxs/Kconfig"
1014 source "arch/arm/mach-netx/Kconfig"
1016 source "arch/arm/mach-nomadik/Kconfig"
1017 source "arch/arm/plat-nomadik/Kconfig"
1019 source "arch/arm/mach-nuc93x/Kconfig"
1021 source "arch/arm/plat-omap/Kconfig"
1023 source "arch/arm/mach-omap1/Kconfig"
1025 source "arch/arm/mach-omap2/Kconfig"
1027 source "arch/arm/mach-orion5x/Kconfig"
1029 source "arch/arm/mach-pxa/Kconfig"
1030 source "arch/arm/plat-pxa/Kconfig"
1032 source "arch/arm/mach-mmp/Kconfig"
1034 source "arch/arm/mach-realview/Kconfig"
1036 source "arch/arm/mach-sa1100/Kconfig"
1038 source "arch/arm/plat-samsung/Kconfig"
1039 source "arch/arm/plat-s3c24xx/Kconfig"
1040 source "arch/arm/plat-s5p/Kconfig"
1042 source "arch/arm/plat-spear/Kconfig"
1044 source "arch/arm/plat-tcc/Kconfig"
1047 source "arch/arm/mach-s3c2410/Kconfig"
1048 source "arch/arm/mach-s3c2412/Kconfig"
1049 source "arch/arm/mach-s3c2416/Kconfig"
1050 source "arch/arm/mach-s3c2440/Kconfig"
1051 source "arch/arm/mach-s3c2443/Kconfig"
1055 source "arch/arm/mach-s3c64xx/Kconfig"
1058 source "arch/arm/mach-s5p64x0/Kconfig"
1060 source "arch/arm/mach-s5pc100/Kconfig"
1062 source "arch/arm/mach-s5pv210/Kconfig"
1064 source "arch/arm/mach-exynos4/Kconfig"
1066 source "arch/arm/mach-shmobile/Kconfig"
1068 source "arch/arm/mach-tegra/Kconfig"
1070 source "arch/arm/mach-u300/Kconfig"
1072 source "arch/arm/mach-ux500/Kconfig"
1074 source "arch/arm/mach-versatile/Kconfig"
1076 source "arch/arm/mach-vexpress/Kconfig"
1077 source "arch/arm/plat-versatile/Kconfig"
1079 source "arch/arm/mach-vt8500/Kconfig"
1081 source "arch/arm/mach-w90x900/Kconfig"
1083 # Definitions to make life easier
1089 select GENERIC_CLOCKEVENTS
1090 select HAVE_SCHED_CLOCK
1095 select GENERIC_IRQ_CHIP
1096 select HAVE_SCHED_CLOCK
1101 config PLAT_VERSATILE
1104 config ARM_TIMER_SP804
1108 source arch/arm/mm/Kconfig
1111 bool "Enable iWMMXt support"
1112 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1113 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1115 Enable support for iWMMXt context switching at run time if
1116 running on a CPU that supports it.
1118 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1121 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1125 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1126 (!ARCH_OMAP3 || OMAP3_EMU)
1130 config MULTI_IRQ_HANDLER
1133 Allow each machine to specify it's own IRQ handler at run time.
1136 source "arch/arm/Kconfig-nommu"
1139 config ARM_ERRATA_411920
1140 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1141 depends on CPU_V6 || CPU_V6K
1143 Invalidation of the Instruction Cache operation can
1144 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1145 It does not affect the MPCore. This option enables the ARM Ltd.
1146 recommended workaround.
1148 config ARM_ERRATA_430973
1149 bool "ARM errata: Stale prediction on replaced interworking branch"
1152 This option enables the workaround for the 430973 Cortex-A8
1153 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1154 interworking branch is replaced with another code sequence at the
1155 same virtual address, whether due to self-modifying code or virtual
1156 to physical address re-mapping, Cortex-A8 does not recover from the
1157 stale interworking branch prediction. This results in Cortex-A8
1158 executing the new code sequence in the incorrect ARM or Thumb state.
1159 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1160 and also flushes the branch target cache at every context switch.
1161 Note that setting specific bits in the ACTLR register may not be
1162 available in non-secure mode.
1164 config ARM_ERRATA_458693
1165 bool "ARM errata: Processor deadlock when a false hazard is created"
1168 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1169 erratum. For very specific sequences of memory operations, it is
1170 possible for a hazard condition intended for a cache line to instead
1171 be incorrectly associated with a different cache line. This false
1172 hazard might then cause a processor deadlock. The workaround enables
1173 the L1 caching of the NEON accesses and disables the PLD instruction
1174 in the ACTLR register. Note that setting specific bits in the ACTLR
1175 register may not be available in non-secure mode.
1177 config ARM_ERRATA_460075
1178 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1181 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1182 erratum. Any asynchronous access to the L2 cache may encounter a
1183 situation in which recent store transactions to the L2 cache are lost
1184 and overwritten with stale memory contents from external memory. The
1185 workaround disables the write-allocate mode for the L2 cache via the
1186 ACTLR register. Note that setting specific bits in the ACTLR register
1187 may not be available in non-secure mode.
1189 config ARM_ERRATA_742230
1190 bool "ARM errata: DMB operation may be faulty"
1191 depends on CPU_V7 && SMP
1193 This option enables the workaround for the 742230 Cortex-A9
1194 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1195 between two write operations may not ensure the correct visibility
1196 ordering of the two writes. This workaround sets a specific bit in
1197 the diagnostic register of the Cortex-A9 which causes the DMB
1198 instruction to behave as a DSB, ensuring the correct behaviour of
1201 config ARM_ERRATA_742231
1202 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1203 depends on CPU_V7 && SMP
1205 This option enables the workaround for the 742231 Cortex-A9
1206 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1207 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1208 accessing some data located in the same cache line, may get corrupted
1209 data due to bad handling of the address hazard when the line gets
1210 replaced from one of the CPUs at the same time as another CPU is
1211 accessing it. This workaround sets specific bits in the diagnostic
1212 register of the Cortex-A9 which reduces the linefill issuing
1213 capabilities of the processor.
1215 config PL310_ERRATA_588369
1216 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1217 depends on CACHE_L2X0
1219 The PL310 L2 cache controller implements three types of Clean &
1220 Invalidate maintenance operations: by Physical Address
1221 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1222 They are architecturally defined to behave as the execution of a
1223 clean operation followed immediately by an invalidate operation,
1224 both performing to the same memory location. This functionality
1225 is not correctly implemented in PL310 as clean lines are not
1226 invalidated as a result of these operations.
1228 config ARM_ERRATA_720789
1229 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1230 depends on CPU_V7 && SMP
1232 This option enables the workaround for the 720789 Cortex-A9 (prior to
1233 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1234 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1235 As a consequence of this erratum, some TLB entries which should be
1236 invalidated are not, resulting in an incoherency in the system page
1237 tables. The workaround changes the TLB flushing routines to invalidate
1238 entries regardless of the ASID.
1240 config PL310_ERRATA_727915
1241 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1242 depends on CACHE_L2X0
1244 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1245 operation (offset 0x7FC). This operation runs in background so that
1246 PL310 can handle normal accesses while it is in progress. Under very
1247 rare circumstances, due to this erratum, write data can be lost when
1248 PL310 treats a cacheable write transaction during a Clean &
1249 Invalidate by Way operation.
1251 config ARM_ERRATA_743622
1252 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1255 This option enables the workaround for the 743622 Cortex-A9
1256 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1257 optimisation in the Cortex-A9 Store Buffer may lead to data
1258 corruption. This workaround sets a specific bit in the diagnostic
1259 register of the Cortex-A9 which disables the Store Buffer
1260 optimisation, preventing the defect from occurring. This has no
1261 visible impact on the overall performance or power consumption of the
1264 config ARM_ERRATA_751472
1265 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 751472 Cortex-A9 (prior
1269 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1270 completion of a following broadcasted operation if the second
1271 operation is received by a CPU before the ICIALLUIS has completed,
1272 potentially leading to corrupted entries in the cache or TLB.
1274 config ARM_ERRATA_753970
1275 bool "ARM errata: cache sync operation may be faulty"
1276 depends on CACHE_PL310
1278 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1280 Under some condition the effect of cache sync operation on
1281 the store buffer still remains when the operation completes.
1282 This means that the store buffer is always asked to drain and
1283 this prevents it from merging any further writes. The workaround
1284 is to replace the normal offset of cache sync operation (0x730)
1285 by another offset targeting an unmapped PL310 register 0x740.
1286 This has the same effect as the cache sync operation: store buffer
1287 drain and waiting for all buffers empty.
1289 config ARM_ERRATA_754322
1290 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1293 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1294 r3p*) erratum. A speculative memory access may cause a page table walk
1295 which starts prior to an ASID switch but completes afterwards. This
1296 can populate the micro-TLB with a stale entry which may be hit with
1297 the new ASID. This workaround places two dsb instructions in the mm
1298 switching code so that no page table walks can cross the ASID switch.
1300 config ARM_ERRATA_754327
1301 bool "ARM errata: no automatic Store Buffer drain"
1302 depends on CPU_V7 && SMP
1304 This option enables the workaround for the 754327 Cortex-A9 (prior to
1305 r2p0) erratum. The Store Buffer does not have any automatic draining
1306 mechanism and therefore a livelock may occur if an external agent
1307 continuously polls a memory location waiting to observe an update.
1308 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1309 written polling loops from denying visibility of updates to memory.
1313 source "arch/arm/common/Kconfig"
1323 Find out whether you have ISA slots on your motherboard. ISA is the
1324 name of a bus system, i.e. the way the CPU talks to the other stuff
1325 inside your box. Other bus systems are PCI, EISA, MicroChannel
1326 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1327 newer boards don't support it. If you have ISA, say Y, otherwise N.
1329 # Select ISA DMA controller support
1334 # Select ISA DMA interface
1339 bool "PCI support" if MIGHT_HAVE_PCI
1341 Find out whether you have a PCI motherboard. PCI is the name of a
1342 bus system, i.e. the way the CPU talks to the other stuff inside
1343 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1344 VESA. If you have PCI, say Y, otherwise N.
1350 config PCI_NANOENGINE
1351 bool "BSE nanoEngine PCI support"
1352 depends on SA1100_NANOENGINE
1354 Enable PCI on the BSE nanoEngine board.
1359 # Select the host bridge type
1360 config PCI_HOST_VIA82C505
1362 depends on PCI && ARCH_SHARK
1365 config PCI_HOST_ITE8152
1367 depends on PCI && MACH_ARMCORE
1371 source "drivers/pci/Kconfig"
1373 source "drivers/pcmcia/Kconfig"
1377 menu "Kernel Features"
1379 source "kernel/time/Kconfig"
1382 bool "Symmetric Multi-Processing"
1383 depends on CPU_V6K || CPU_V7
1384 depends on GENERIC_CLOCKEVENTS
1385 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1386 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1387 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1388 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1389 select USE_GENERIC_SMP_HELPERS
1390 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1392 This enables support for systems with more than one CPU. If you have
1393 a system with only one CPU, like most personal computers, say N. If
1394 you have a system with more than one CPU, say Y.
1396 If you say N here, the kernel will run on single and multiprocessor
1397 machines, but will use only one CPU of a multiprocessor machine. If
1398 you say Y here, the kernel will run on many, but not all, single
1399 processor machines. On a single processor machine, the kernel will
1400 run faster if you say N here.
1402 See also <file:Documentation/i386/IO-APIC.txt>,
1403 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1404 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1406 If you don't know what to do here, say N.
1409 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1410 depends on EXPERIMENTAL
1411 depends on SMP && !XIP_KERNEL
1414 SMP kernels contain instructions which fail on non-SMP processors.
1415 Enabling this option allows the kernel to modify itself to make
1416 these instructions safe. Disabling it allows about 1K of space
1419 If you don't know what to do here, say Y.
1424 This option enables support for the ARM system coherency unit
1431 This options enables support for the ARM timer and watchdog unit
1434 prompt "Memory split"
1437 Select the desired split between kernel and user memory.
1439 If you are not absolutely sure what you are doing, leave this
1443 bool "3G/1G user/kernel split"
1445 bool "2G/2G user/kernel split"
1447 bool "1G/3G user/kernel split"
1452 default 0x40000000 if VMSPLIT_1G
1453 default 0x80000000 if VMSPLIT_2G
1457 int "Maximum number of CPUs (2-32)"
1463 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1464 depends on SMP && HOTPLUG && EXPERIMENTAL
1466 Say Y here to experiment with turning CPUs off and on. CPUs
1467 can be controlled through /sys/devices/system/cpu.
1470 bool "Use local timer interrupts"
1473 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1475 Enable support for local timers on SMP platforms, rather then the
1476 legacy IPI broadcast method. Local timers allows the system
1477 accounting to be spread across the timer interval, preventing a
1478 "thundering herd" at every timer tick.
1480 source kernel/Kconfig.preempt
1484 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1485 ARCH_S5PV210 || ARCH_EXYNOS4
1486 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1487 default AT91_TIMER_HZ if ARCH_AT91
1488 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1491 config THUMB2_KERNEL
1492 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1493 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1495 select ARM_ASM_UNIFIED
1497 By enabling this option, the kernel will be compiled in
1498 Thumb-2 mode. A compiler/assembler that understand the unified
1499 ARM-Thumb syntax is needed.
1503 config THUMB2_AVOID_R_ARM_THM_JUMP11
1504 bool "Work around buggy Thumb-2 short branch relocations in gas"
1505 depends on THUMB2_KERNEL && MODULES
1508 Various binutils versions can resolve Thumb-2 branches to
1509 locally-defined, preemptible global symbols as short-range "b.n"
1510 branch instructions.
1512 This is a problem, because there's no guarantee the final
1513 destination of the symbol, or any candidate locations for a
1514 trampoline, are within range of the branch. For this reason, the
1515 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1516 relocation in modules at all, and it makes little sense to add
1519 The symptom is that the kernel fails with an "unsupported
1520 relocation" error when loading some modules.
1522 Until fixed tools are available, passing
1523 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1524 code which hits this problem, at the cost of a bit of extra runtime
1525 stack usage in some cases.
1527 The problem is described in more detail at:
1528 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1530 Only Thumb-2 kernels are affected.
1532 Unless you are sure your tools don't have this problem, say Y.
1534 config ARM_ASM_UNIFIED
1538 bool "Use the ARM EABI to compile the kernel"
1540 This option allows for the kernel to be compiled using the latest
1541 ARM ABI (aka EABI). This is only useful if you are using a user
1542 space environment that is also compiled with EABI.
1544 Since there are major incompatibilities between the legacy ABI and
1545 EABI, especially with regard to structure member alignment, this
1546 option also changes the kernel syscall calling convention to
1547 disambiguate both ABIs and allow for backward compatibility support
1548 (selected with CONFIG_OABI_COMPAT).
1550 To use this you need GCC version 4.0.0 or later.
1553 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1554 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1557 This option preserves the old syscall interface along with the
1558 new (ARM EABI) one. It also provides a compatibility layer to
1559 intercept syscalls that have structure arguments which layout
1560 in memory differs between the legacy ABI and the new ARM EABI
1561 (only for non "thumb" binaries). This option adds a tiny
1562 overhead to all syscalls and produces a slightly larger kernel.
1563 If you know you'll be using only pure EABI user space then you
1564 can say N here. If this option is not selected and you attempt
1565 to execute a legacy ABI binary then the result will be
1566 UNPREDICTABLE (in fact it can be predicted that it won't work
1567 at all). If in doubt say Y.
1569 config ARCH_HAS_HOLES_MEMORYMODEL
1572 config ARCH_SPARSEMEM_ENABLE
1575 config ARCH_SPARSEMEM_DEFAULT
1576 def_bool ARCH_SPARSEMEM_ENABLE
1578 config ARCH_SELECT_MEMORY_MODEL
1579 def_bool ARCH_SPARSEMEM_ENABLE
1581 config HAVE_ARCH_PFN_VALID
1582 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1585 bool "High Memory Support"
1588 The address space of ARM processors is only 4 Gigabytes large
1589 and it has to accommodate user address space, kernel address
1590 space as well as some memory mapped IO. That means that, if you
1591 have a large amount of physical memory and/or IO, not all of the
1592 memory can be "permanently mapped" by the kernel. The physical
1593 memory that is not permanently mapped is called "high memory".
1595 Depending on the selected kernel/user memory split, minimum
1596 vmalloc space and actual amount of RAM, you may not need this
1597 option which should result in a slightly faster kernel.
1602 bool "Allocate 2nd-level pagetables from highmem"
1605 config HW_PERF_EVENTS
1606 bool "Enable hardware performance counter support for perf events"
1607 depends on PERF_EVENTS && CPU_HAS_PMU
1610 Enable hardware performance counter support for perf events. If
1611 disabled, perf events will use software events only.
1615 config FORCE_MAX_ZONEORDER
1616 int "Maximum zone order" if ARCH_SHMOBILE
1617 range 11 64 if ARCH_SHMOBILE
1618 default "9" if SA1111
1621 The kernel memory allocator divides physically contiguous memory
1622 blocks into "zones", where each zone is a power of two number of
1623 pages. This option selects the largest power of two that the kernel
1624 keeps in the memory allocator. If you need to allocate very large
1625 blocks of physically contiguous memory, then you may need to
1626 increase this value.
1628 This config option is actually maximum order plus one. For example,
1629 a value of 11 means that the largest free memory block is 2^10 pages.
1632 bool "Timer and CPU usage LEDs"
1633 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1634 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1635 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1636 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1637 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1638 ARCH_AT91 || ARCH_DAVINCI || \
1639 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1641 If you say Y here, the LEDs on your machine will be used
1642 to provide useful information about your current system status.
1644 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1645 be able to select which LEDs are active using the options below. If
1646 you are compiling a kernel for the EBSA-110 or the LART however, the
1647 red LED will simply flash regularly to indicate that the system is
1648 still functional. It is safe to say Y here if you have a CATS
1649 system, but the driver will do nothing.
1652 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1653 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1654 || MACH_OMAP_PERSEUS2
1656 depends on !GENERIC_CLOCKEVENTS
1657 default y if ARCH_EBSA110
1659 If you say Y here, one of the system LEDs (the green one on the
1660 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1661 will flash regularly to indicate that the system is still
1662 operational. This is mainly useful to kernel hackers who are
1663 debugging unstable kernels.
1665 The LART uses the same LED for both Timer LED and CPU usage LED
1666 functions. You may choose to use both, but the Timer LED function
1667 will overrule the CPU usage LED.
1670 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1672 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1673 || MACH_OMAP_PERSEUS2
1676 If you say Y here, the red LED will be used to give a good real
1677 time indication of CPU usage, by lighting whenever the idle task
1678 is not currently executing.
1680 The LART uses the same LED for both Timer LED and CPU usage LED
1681 functions. You may choose to use both, but the Timer LED function
1682 will overrule the CPU usage LED.
1684 config ALIGNMENT_TRAP
1686 depends on CPU_CP15_MMU
1687 default y if !ARCH_EBSA110
1688 select HAVE_PROC_CPU if PROC_FS
1690 ARM processors cannot fetch/store information which is not
1691 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1692 address divisible by 4. On 32-bit ARM processors, these non-aligned
1693 fetch/store instructions will be emulated in software if you say
1694 here, which has a severe performance impact. This is necessary for
1695 correct operation of some network protocols. With an IP-only
1696 configuration it is safe to say N, otherwise say Y.
1698 config UACCESS_WITH_MEMCPY
1699 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1700 depends on MMU && EXPERIMENTAL
1701 default y if CPU_FEROCEON
1703 Implement faster copy_to_user and clear_user methods for CPU
1704 cores where a 8-word STM instruction give significantly higher
1705 memory write throughput than a sequence of individual 32bit stores.
1707 A possible side effect is a slight increase in scheduling latency
1708 between threads sharing the same address space if they invoke
1709 such copy operations with large buffers.
1711 However, if the CPU data cache is using a write-allocate mode,
1712 this option is unlikely to provide any performance gain.
1716 prompt "Enable seccomp to safely compute untrusted bytecode"
1718 This kernel feature is useful for number crunching applications
1719 that may need to compute untrusted bytecode during their
1720 execution. By using pipes or other transports made available to
1721 the process as file descriptors supporting the read/write
1722 syscalls, it's possible to isolate those applications in
1723 their own address space using seccomp. Once seccomp is
1724 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1725 and the task is only allowed to execute a few safe syscalls
1726 defined by each seccomp mode.
1728 config CC_STACKPROTECTOR
1729 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1730 depends on EXPERIMENTAL
1732 This option turns on the -fstack-protector GCC feature. This
1733 feature puts, at the beginning of functions, a canary value on
1734 the stack just before the return address, and validates
1735 the value just before actually returning. Stack based buffer
1736 overflows (that need to overwrite this return address) now also
1737 overwrite the canary, which gets detected and the attack is then
1738 neutralized via a kernel panic.
1739 This feature requires gcc version 4.2 or above.
1741 config DEPRECATED_PARAM_STRUCT
1742 bool "Provide old way to pass kernel parameters"
1744 This was deprecated in 2001 and announced to live on for 5 years.
1745 Some old boot loaders still use this way.
1752 bool "Flattened Device Tree support"
1754 select OF_EARLY_FLATTREE
1757 Include support for flattened device tree machine descriptions.
1759 # Compressed boot loader in ROM. Yes, we really want to ask about
1760 # TEXT and BSS so we preserve their values in the config files.
1761 config ZBOOT_ROM_TEXT
1762 hex "Compressed ROM boot loader base address"
1765 The physical address at which the ROM-able zImage is to be
1766 placed in the target. Platforms which normally make use of
1767 ROM-able zImage formats normally set this to a suitable
1768 value in their defconfig file.
1770 If ZBOOT_ROM is not enabled, this has no effect.
1772 config ZBOOT_ROM_BSS
1773 hex "Compressed ROM boot loader BSS address"
1776 The base address of an area of read/write memory in the target
1777 for the ROM-able zImage which must be available while the
1778 decompressor is running. It must be large enough to hold the
1779 entire decompressed kernel plus an additional 128 KiB.
1780 Platforms which normally make use of ROM-able zImage formats
1781 normally set this to a suitable value in their defconfig file.
1783 If ZBOOT_ROM is not enabled, this has no effect.
1786 bool "Compressed boot loader in ROM/flash"
1787 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1789 Say Y here if you intend to execute your compressed kernel image
1790 (zImage) directly from ROM or flash. If unsure, say N.
1793 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1794 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1795 default ZBOOT_ROM_NONE
1797 Include experimental SD/MMC loading code in the ROM-able zImage.
1798 With this enabled it is possible to write the the ROM-able zImage
1799 kernel image to an MMC or SD card and boot the kernel straight
1800 from the reset vector. At reset the processor Mask ROM will load
1801 the first part of the the ROM-able zImage which in turn loads the
1802 rest the kernel image to RAM.
1804 config ZBOOT_ROM_NONE
1805 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1807 Do not load image from SD or MMC
1809 config ZBOOT_ROM_MMCIF
1810 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1812 Load image from MMCIF hardware block.
1814 config ZBOOT_ROM_SH_MOBILE_SDHI
1815 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1817 Load image from SDHI hardware block
1822 string "Default kernel command string"
1825 On some architectures (EBSA110 and CATS), there is currently no way
1826 for the boot loader to pass arguments to the kernel. For these
1827 architectures, you should supply some command-line options at build
1828 time by entering them here. As a minimum, you should specify the
1829 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1832 prompt "Kernel command line type" if CMDLINE != ""
1833 default CMDLINE_FROM_BOOTLOADER
1835 config CMDLINE_FROM_BOOTLOADER
1836 bool "Use bootloader kernel arguments if available"
1838 Uses the command-line options passed by the boot loader. If
1839 the boot loader doesn't provide any, the default kernel command
1840 string provided in CMDLINE will be used.
1842 config CMDLINE_EXTEND
1843 bool "Extend bootloader kernel arguments"
1845 The command-line arguments provided by the boot loader will be
1846 appended to the default kernel command string.
1848 config CMDLINE_FORCE
1849 bool "Always use the default kernel command string"
1851 Always use the default kernel command string, even if the boot
1852 loader passes other arguments to the kernel.
1853 This is useful if you cannot or don't want to change the
1854 command-line options your boot loader passes to the kernel.
1858 bool "Kernel Execute-In-Place from ROM"
1859 depends on !ZBOOT_ROM
1861 Execute-In-Place allows the kernel to run from non-volatile storage
1862 directly addressable by the CPU, such as NOR flash. This saves RAM
1863 space since the text section of the kernel is not loaded from flash
1864 to RAM. Read-write sections, such as the data section and stack,
1865 are still copied to RAM. The XIP kernel is not compressed since
1866 it has to run directly from flash, so it will take more space to
1867 store it. The flash address used to link the kernel object files,
1868 and for storing it, is configuration dependent. Therefore, if you
1869 say Y here, you must know the proper physical address where to
1870 store the kernel image depending on your own flash memory usage.
1872 Also note that the make target becomes "make xipImage" rather than
1873 "make zImage" or "make Image". The final kernel binary to put in
1874 ROM memory will be arch/arm/boot/xipImage.
1878 config XIP_PHYS_ADDR
1879 hex "XIP Kernel Physical Location"
1880 depends on XIP_KERNEL
1881 default "0x00080000"
1883 This is the physical address in your flash memory the kernel will
1884 be linked for and stored to. This address is dependent on your
1888 bool "Kexec system call (EXPERIMENTAL)"
1889 depends on EXPERIMENTAL
1891 kexec is a system call that implements the ability to shutdown your
1892 current kernel, and to start another kernel. It is like a reboot
1893 but it is independent of the system firmware. And like a reboot
1894 you can start any kernel with it, not just Linux.
1896 It is an ongoing process to be certain the hardware in a machine
1897 is properly shutdown, so do not be surprised if this code does not
1898 initially work for you. It may help to enable device hotplugging
1902 bool "Export atags in procfs"
1906 Should the atags used to boot the kernel be exported in an "atags"
1907 file in procfs. Useful with kexec.
1910 bool "Build kdump crash kernel (EXPERIMENTAL)"
1911 depends on EXPERIMENTAL
1913 Generate crash dump after being started by kexec. This should
1914 be normally only set in special crash dump kernels which are
1915 loaded in the main kernel with kexec-tools into a specially
1916 reserved region and then later executed after a crash by
1917 kdump/kexec. The crash dump kernel must be compiled to a
1918 memory address not used by the main kernel
1920 For more details see Documentation/kdump/kdump.txt
1922 config AUTO_ZRELADDR
1923 bool "Auto calculation of the decompressed kernel image address"
1924 depends on !ZBOOT_ROM && !ARCH_U300
1926 ZRELADDR is the physical address where the decompressed kernel
1927 image will be placed. If AUTO_ZRELADDR is selected, the address
1928 will be determined at run-time by masking the current IP with
1929 0xf8000000. This assumes the zImage being placed in the first 128MB
1930 from start of memory.
1934 menu "CPU Power Management"
1938 source "drivers/cpufreq/Kconfig"
1941 tristate "CPUfreq driver for i.MX CPUs"
1942 depends on ARCH_MXC && CPU_FREQ
1944 This enables the CPUfreq driver for i.MX CPUs.
1946 config CPU_FREQ_SA1100
1949 config CPU_FREQ_SA1110
1952 config CPU_FREQ_INTEGRATOR
1953 tristate "CPUfreq driver for ARM Integrator CPUs"
1954 depends on ARCH_INTEGRATOR && CPU_FREQ
1957 This enables the CPUfreq driver for ARM Integrator CPUs.
1959 For details, take a look at <file:Documentation/cpu-freq>.
1965 depends on CPU_FREQ && ARCH_PXA && PXA25x
1967 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1972 Internal configuration node for common cpufreq on Samsung SoC
1974 config CPU_FREQ_S3C24XX
1975 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1976 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1979 This enables the CPUfreq driver for the Samsung S3C24XX family
1982 For details, take a look at <file:Documentation/cpu-freq>.
1986 config CPU_FREQ_S3C24XX_PLL
1987 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
1988 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
1990 Compile in support for changing the PLL frequency from the
1991 S3C24XX series CPUfreq driver. The PLL takes time to settle
1992 after a frequency change, so by default it is not enabled.
1994 This also means that the PLL tables for the selected CPU(s) will
1995 be built which may increase the size of the kernel image.
1997 config CPU_FREQ_S3C24XX_DEBUG
1998 bool "Debug CPUfreq Samsung driver core"
1999 depends on CPU_FREQ_S3C24XX
2001 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2003 config CPU_FREQ_S3C24XX_IODEBUG
2004 bool "Debug CPUfreq Samsung driver IO timing"
2005 depends on CPU_FREQ_S3C24XX
2007 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2009 config CPU_FREQ_S3C24XX_DEBUGFS
2010 bool "Export debugfs for CPUFreq"
2011 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2013 Export status information via debugfs.
2017 source "drivers/cpuidle/Kconfig"
2021 menu "Floating point emulation"
2023 comment "At least one emulation must be selected"
2026 bool "NWFPE math emulation"
2027 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2029 Say Y to include the NWFPE floating point emulator in the kernel.
2030 This is necessary to run most binaries. Linux does not currently
2031 support floating point hardware so you need to say Y here even if
2032 your machine has an FPA or floating point co-processor podule.
2034 You may say N here if you are going to load the Acorn FPEmulator
2035 early in the bootup.
2038 bool "Support extended precision"
2039 depends on FPE_NWFPE
2041 Say Y to include 80-bit support in the kernel floating-point
2042 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2043 Note that gcc does not generate 80-bit operations by default,
2044 so in most cases this option only enlarges the size of the
2045 floating point emulator without any good reason.
2047 You almost surely want to say N here.
2050 bool "FastFPE math emulation (EXPERIMENTAL)"
2051 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2053 Say Y here to include the FAST floating point emulator in the kernel.
2054 This is an experimental much faster emulator which now also has full
2055 precision for the mantissa. It does not support any exceptions.
2056 It is very simple, and approximately 3-6 times faster than NWFPE.
2058 It should be sufficient for most programs. It may be not suitable
2059 for scientific calculations, but you have to check this for yourself.
2060 If you do not feel you need a faster FP emulation you should better
2064 bool "VFP-format floating point maths"
2065 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2067 Say Y to include VFP support code in the kernel. This is needed
2068 if your hardware includes a VFP unit.
2070 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2071 release notes and additional status information.
2073 Say N if your target does not have VFP hardware.
2081 bool "Advanced SIMD (NEON) Extension support"
2082 depends on VFPv3 && CPU_V7
2084 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2089 menu "Userspace binary formats"
2091 source "fs/Kconfig.binfmt"
2094 tristate "RISC OS personality"
2097 Say Y here to include the kernel code necessary if you want to run
2098 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2099 experimental; if this sounds frightening, say N and sleep in peace.
2100 You can also say M here to compile this support as a module (which
2101 will be called arthur).
2105 menu "Power management options"
2107 source "kernel/power/Kconfig"
2109 config ARCH_SUSPEND_POSSIBLE
2110 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2111 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2112 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2117 source "net/Kconfig"
2119 source "drivers/Kconfig"
2123 source "arch/arm/Kconfig.debug"
2125 source "security/Kconfig"
2127 source "crypto/Kconfig"
2129 source "lib/Kconfig"