2 * Alchemy/AMD/RMI DB1200 board setup.
4 * Licensed under the terms outlined in the file COPYING in the root of
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
11 #include <linux/kernel.h>
12 #include <asm/mach-au1x00/au1000.h>
13 #include <asm/mach-db1x00/bcsr.h>
14 #include <asm/mach-db1x00/db1200.h>
16 const char *get_system_type(void)
18 return "Alchemy Db1200";
21 void __init
board_setup(void)
23 unsigned long freq0
, clksrc
, div
, pfc
;
24 unsigned short whoami
;
26 bcsr_init(DB1200_BCSR_PHYS_ADDR
,
27 DB1200_BCSR_PHYS_ADDR
+ DB1200_BCSR_HEXLED_OFS
);
29 whoami
= bcsr_read(BCSR_WHOAMI
);
30 printk(KERN_INFO
"Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d"
31 " Board-ID %d Daughtercard ID %d\n",
32 (whoami
>> 4) & 0xf, (whoami
>> 8) & 0xf, whoami
& 0xf);
34 /* SMBus/SPI on PSC0, Audio on PSC1 */
35 pfc
= __raw_readl((void __iomem
*)SYS_PINFUNC
);
36 pfc
&= ~(SYS_PINFUNC_P0A
| SYS_PINFUNC_P0B
);
37 pfc
&= ~(SYS_PINFUNC_P1A
| SYS_PINFUNC_P1B
| SYS_PINFUNC_FS3
);
38 pfc
|= SYS_PINFUNC_P1C
; /* SPI is configured later */
39 __raw_writel(pfc
, (void __iomem
*)SYS_PINFUNC
);
42 /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from
43 * CPU clock; all other clock generators off/unused.
45 div
= (get_au1x00_speed() + 25000000) / 50000000;
48 div
= ((div
>> 1) - 1) & 0xff;
50 freq0
= div
<< SYS_FC_FRDIV0_BIT
;
51 __raw_writel(freq0
, (void __iomem
*)SYS_FREQCTRL0
);
53 freq0
|= SYS_FC_FE0
; /* enable F0 */
54 __raw_writel(freq0
, (void __iomem
*)SYS_FREQCTRL0
);
57 /* psc0_intclk comes 1:1 from F0 */
58 clksrc
= SYS_CS_MUX_FQ0
<< SYS_CS_ME0_BIT
;
59 __raw_writel(clksrc
, (void __iomem
*)SYS_CLKSRC
);
63 static int __init
db1200_arch_init(void)
65 /* GPIO7 is low-level triggered CPLD cascade */
66 set_irq_type(AU1200_GPIO7_INT
, IRQF_TRIGGER_LOW
);
67 bcsr_init_irq(DB1200_INT_BEGIN
, DB1200_INT_END
, AU1200_GPIO7_INT
);
69 /* insert/eject pairs: one of both is always screaming. To avoid
70 * issues they must not be automatically enabled when initially
73 irq_to_desc(DB1200_SD0_INSERT_INT
)->status
|= IRQ_NOAUTOEN
;
74 irq_to_desc(DB1200_SD0_EJECT_INT
)->status
|= IRQ_NOAUTOEN
;
75 irq_to_desc(DB1200_PC0_INSERT_INT
)->status
|= IRQ_NOAUTOEN
;
76 irq_to_desc(DB1200_PC0_EJECT_INT
)->status
|= IRQ_NOAUTOEN
;
77 irq_to_desc(DB1200_PC1_INSERT_INT
)->status
|= IRQ_NOAUTOEN
;
78 irq_to_desc(DB1200_PC1_EJECT_INT
)->status
|= IRQ_NOAUTOEN
;
82 arch_initcall(db1200_arch_init
);