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[S390] bug: use relative pointers in bug table entries
[linux-2.6/linux-2.6-ps3.git] / drivers / net / qlge / qlge.h
blob862c1aaf38608955600fc6728c45850083845a1c
1 /*
2 * QLogic QLA41xx NIC HBA Driver
3 * Copyright (c) 2003-2006 QLogic Corporation
4 *
5 * See LICENSE.qlge for copyright and licensing details.
6 */
7 #ifndef _QLGE_H_
8 #define _QLGE_H_
9
10 #include <linux/pci.h>
11 #include <linux/netdevice.h>
12 #include <linux/rtnetlink.h>
13
14 /*
15 * General definitions...
16 */
17 #define DRV_NAME "qlge"
18 #define DRV_STRING "QLogic 10 Gigabit PCI-E Ethernet Driver "
19 #define DRV_VERSION "v1.00.00.23.00.00-01"
20
21 #define PFX "qlge: "
22 #define QPRINTK(qdev, nlevel, klevel, fmt, args...) \
23 do { \
24 if (!((qdev)->msg_enable & NETIF_MSG_##nlevel)) \
25 ; \
26 else \
27 dev_printk(KERN_##klevel, &((qdev)->pdev->dev), \
28 "%s: " fmt, __func__, ##args); \
29 } while (0)
30
31 #define WQ_ADDR_ALIGN 0x3 /* 4 byte alignment */
32
33 #define QLGE_VENDOR_ID 0x1077
34 #define QLGE_DEVICE_ID_8012 0x8012
35 #define QLGE_DEVICE_ID_8000 0x8000
36 #define MAX_CPUS 8
37 #define MAX_TX_RINGS MAX_CPUS
38 #define MAX_RX_RINGS ((MAX_CPUS * 2) + 1)
39
40 #define NUM_TX_RING_ENTRIES 256
41 #define NUM_RX_RING_ENTRIES 256
42
43 #define NUM_SMALL_BUFFERS 512
44 #define NUM_LARGE_BUFFERS 512
45 #define DB_PAGE_SIZE 4096
46
47 /* Calculate the number of (4k) pages required to
48 * contain a buffer queue of the given length.
49 */
50 #define MAX_DB_PAGES_PER_BQ(x) \
51 (((x * sizeof(u64)) / DB_PAGE_SIZE) + \
52 (((x * sizeof(u64)) % DB_PAGE_SIZE) ? 1 : 0))
53
54 #define RX_RING_SHADOW_SPACE (sizeof(u64) + \
55 MAX_DB_PAGES_PER_BQ(NUM_SMALL_BUFFERS) * sizeof(u64) + \
56 MAX_DB_PAGES_PER_BQ(NUM_LARGE_BUFFERS) * sizeof(u64))
57 #define SMALL_BUFFER_SIZE 512
58 #define SMALL_BUF_MAP_SIZE (SMALL_BUFFER_SIZE / 2)
59 #define LARGE_BUFFER_MAX_SIZE 8192
60 #define LARGE_BUFFER_MIN_SIZE 2048
61 #define MAX_SPLIT_SIZE 1023
62 #define QLGE_SB_PAD 32
63
64 #define MAX_CQ 128
65 #define DFLT_COALESCE_WAIT 100 /* 100 usec wait for coalescing */
66 #define MAX_INTER_FRAME_WAIT 10 /* 10 usec max interframe-wait for coalescing */
67 #define DFLT_INTER_FRAME_WAIT (MAX_INTER_FRAME_WAIT/2)
68 #define UDELAY_COUNT 3
69 #define UDELAY_DELAY 100
70
71
72 #define TX_DESC_PER_IOCB 8
73 /* The maximum number of frags we handle is based
74 * on PAGE_SIZE...
75 */
76 #if (PAGE_SHIFT == 12) || (PAGE_SHIFT == 13) /* 4k & 8k pages */
77 #define TX_DESC_PER_OAL ((MAX_SKB_FRAGS - TX_DESC_PER_IOCB) + 2)
78 #else /* all other page sizes */
79 #define TX_DESC_PER_OAL 0
80 #endif
81
82 /* MPI test register definitions. This register
83 * is used for determining alternate NIC function's
84 * PCI->func number.
85 */
86 enum {
87 MPI_TEST_FUNC_PORT_CFG = 0x1002,
88 MPI_TEST_NIC1_FUNC_SHIFT = 1,
89 MPI_TEST_NIC2_FUNC_SHIFT = 5,
90 MPI_TEST_NIC_FUNC_MASK = 0x00000007,
91 };
92
93 /*
94 * Processor Address Register (PROC_ADDR) bit definitions.
95 */
96 enum {
97
98 /* Misc. stuff */
99 MAILBOX_COUNT = 16,
100 MAILBOX_TIMEOUT = 5,
101
102 PROC_ADDR_RDY = (1 << 31),
103 PROC_ADDR_R = (1 << 30),
104 PROC_ADDR_ERR = (1 << 29),
105 PROC_ADDR_DA = (1 << 28),
106 PROC_ADDR_FUNC0_MBI = 0x00001180,
107 PROC_ADDR_FUNC0_MBO = (PROC_ADDR_FUNC0_MBI + MAILBOX_COUNT),
108 PROC_ADDR_FUNC0_CTL = 0x000011a1,
109 PROC_ADDR_FUNC2_MBI = 0x00001280,
110 PROC_ADDR_FUNC2_MBO = (PROC_ADDR_FUNC2_MBI + MAILBOX_COUNT),
111 PROC_ADDR_FUNC2_CTL = 0x000012a1,
112 PROC_ADDR_MPI_RISC = 0x00000000,
113 PROC_ADDR_MDE = 0x00010000,
114 PROC_ADDR_REGBLOCK = 0x00020000,
115 PROC_ADDR_RISC_REG = 0x00030000,
116 };
117
118 /*
119 * System Register (SYS) bit definitions.
120 */
121 enum {
122 SYS_EFE = (1 << 0),
123 SYS_FAE = (1 << 1),
124 SYS_MDC = (1 << 2),
125 SYS_DST = (1 << 3),
126 SYS_DWC = (1 << 4),
127 SYS_EVW = (1 << 5),
128 SYS_OMP_DLY_MASK = 0x3f000000,
129 /*
130 * There are no values defined as of edit #15.
131 */
132 SYS_ODI = (1 << 14),
133 };
134
135 /*
136 * Reset/Failover Register (RST_FO) bit definitions.
137 */
138 enum {
139 RST_FO_TFO = (1 << 0),
140 RST_FO_RR_MASK = 0x00060000,
141 RST_FO_RR_CQ_CAM = 0x00000000,
142 RST_FO_RR_DROP = 0x00000002,
143 RST_FO_RR_DQ = 0x00000004,
144 RST_FO_RR_RCV_FUNC_CQ = 0x00000006,
145 RST_FO_FRB = (1 << 12),
146 RST_FO_MOP = (1 << 13),
147 RST_FO_REG = (1 << 14),
148 RST_FO_FR = (1 << 15),
149 };
150
151 /*
152 * Function Specific Control Register (FSC) bit definitions.
153 */
154 enum {
155 FSC_DBRST_MASK = 0x00070000,
156 FSC_DBRST_256 = 0x00000000,
157 FSC_DBRST_512 = 0x00000001,
158 FSC_DBRST_768 = 0x00000002,
159 FSC_DBRST_1024 = 0x00000003,
160 FSC_DBL_MASK = 0x00180000,
161 FSC_DBL_DBRST = 0x00000000,
162 FSC_DBL_MAX_PLD = 0x00000008,
163 FSC_DBL_MAX_BRST = 0x00000010,
164 FSC_DBL_128_BYTES = 0x00000018,
165 FSC_EC = (1 << 5),
166 FSC_EPC_MASK = 0x00c00000,
167 FSC_EPC_INBOUND = (1 << 6),
168 FSC_EPC_OUTBOUND = (1 << 7),
169 FSC_VM_PAGESIZE_MASK = 0x07000000,
170 FSC_VM_PAGE_2K = 0x00000100,
171 FSC_VM_PAGE_4K = 0x00000200,
172 FSC_VM_PAGE_8K = 0x00000300,
173 FSC_VM_PAGE_64K = 0x00000600,
174 FSC_SH = (1 << 11),
175 FSC_DSB = (1 << 12),
176 FSC_STE = (1 << 13),
177 FSC_FE = (1 << 15),
178 };
179
180 /*
181 * Host Command Status Register (CSR) bit definitions.
182 */
183 enum {
184 CSR_ERR_STS_MASK = 0x0000003f,
185 /*
186 * There are no valued defined as of edit #15.
187 */
188 CSR_RR = (1 << 8),
189 CSR_HRI = (1 << 9),
190 CSR_RP = (1 << 10),
191 CSR_CMD_PARM_SHIFT = 22,
192 CSR_CMD_NOP = 0x00000000,
193 CSR_CMD_SET_RST = 0x10000000,
194 CSR_CMD_CLR_RST = 0x20000000,
195 CSR_CMD_SET_PAUSE = 0x30000000,
196 CSR_CMD_CLR_PAUSE = 0x40000000,
197 CSR_CMD_SET_H2R_INT = 0x50000000,
198 CSR_CMD_CLR_H2R_INT = 0x60000000,
199 CSR_CMD_PAR_EN = 0x70000000,
200 CSR_CMD_SET_BAD_PAR = 0x80000000,
201 CSR_CMD_CLR_BAD_PAR = 0x90000000,
202 CSR_CMD_CLR_R2PCI_INT = 0xa0000000,
203 };
204
205 /*
206 * Configuration Register (CFG) bit definitions.
207 */
208 enum {
209 CFG_LRQ = (1 << 0),
210 CFG_DRQ = (1 << 1),
211 CFG_LR = (1 << 2),
212 CFG_DR = (1 << 3),
213 CFG_LE = (1 << 5),
214 CFG_LCQ = (1 << 6),
215 CFG_DCQ = (1 << 7),
216 CFG_Q_SHIFT = 8,
217 CFG_Q_MASK = 0x7f000000,
218 };
219
220 /*
221 * Status Register (STS) bit definitions.
222 */
223 enum {
224 STS_FE = (1 << 0),
225 STS_PI = (1 << 1),
226 STS_PL0 = (1 << 2),
227 STS_PL1 = (1 << 3),
228 STS_PI0 = (1 << 4),
229 STS_PI1 = (1 << 5),
230 STS_FUNC_ID_MASK = 0x000000c0,
231 STS_FUNC_ID_SHIFT = 6,
232 STS_F0E = (1 << 8),
233 STS_F1E = (1 << 9),
234 STS_F2E = (1 << 10),
235 STS_F3E = (1 << 11),
236 STS_NFE = (1 << 12),
237 };
238
239 /*
240 * Interrupt Enable Register (INTR_EN) bit definitions.
241 */
242 enum {
243 INTR_EN_INTR_MASK = 0x007f0000,
244 INTR_EN_TYPE_MASK = 0x03000000,
245 INTR_EN_TYPE_ENABLE = 0x00000100,
246 INTR_EN_TYPE_DISABLE = 0x00000200,
247 INTR_EN_TYPE_READ = 0x00000300,
248 INTR_EN_IHD = (1 << 13),
249 INTR_EN_IHD_MASK = (INTR_EN_IHD << 16),
250 INTR_EN_EI = (1 << 14),
251 INTR_EN_EN = (1 << 15),
252 };
253
254 /*
255 * Interrupt Mask Register (INTR_MASK) bit definitions.
256 */
257 enum {
258 INTR_MASK_PI = (1 << 0),
259 INTR_MASK_HL0 = (1 << 1),
260 INTR_MASK_LH0 = (1 << 2),
261 INTR_MASK_HL1 = (1 << 3),
262 INTR_MASK_LH1 = (1 << 4),
263 INTR_MASK_SE = (1 << 5),
264 INTR_MASK_LSC = (1 << 6),
265 INTR_MASK_MC = (1 << 7),
266 INTR_MASK_LINK_IRQS = INTR_MASK_LSC | INTR_MASK_SE | INTR_MASK_MC,
267 };
268
269 /*
270 * Register (REV_ID) bit definitions.
271 */
272 enum {
273 REV_ID_MASK = 0x0000000f,
274 REV_ID_NICROLL_SHIFT = 0,
275 REV_ID_NICREV_SHIFT = 4,
276 REV_ID_XGROLL_SHIFT = 8,
277 REV_ID_XGREV_SHIFT = 12,
278 REV_ID_CHIPREV_SHIFT = 28,
279 };
280
281 /*
282 * Force ECC Error Register (FRC_ECC_ERR) bit definitions.
283 */
284 enum {
285 FRC_ECC_ERR_VW = (1 << 12),
286 FRC_ECC_ERR_VB = (1 << 13),
287 FRC_ECC_ERR_NI = (1 << 14),
288 FRC_ECC_ERR_NO = (1 << 15),
289 FRC_ECC_PFE_SHIFT = 16,
290 FRC_ECC_ERR_DO = (1 << 18),
291 FRC_ECC_P14 = (1 << 19),
292 };
293
294 /*
295 * Error Status Register (ERR_STS) bit definitions.
296 */
297 enum {
298 ERR_STS_NOF = (1 << 0),
299 ERR_STS_NIF = (1 << 1),
300 ERR_STS_DRP = (1 << 2),
301 ERR_STS_XGP = (1 << 3),
302 ERR_STS_FOU = (1 << 4),
303 ERR_STS_FOC = (1 << 5),
304 ERR_STS_FOF = (1 << 6),
305 ERR_STS_FIU = (1 << 7),
306 ERR_STS_FIC = (1 << 8),
307 ERR_STS_FIF = (1 << 9),
308 ERR_STS_MOF = (1 << 10),
309 ERR_STS_TA = (1 << 11),
310 ERR_STS_MA = (1 << 12),
311 ERR_STS_MPE = (1 << 13),
312 ERR_STS_SCE = (1 << 14),
313 ERR_STS_STE = (1 << 15),
314 ERR_STS_FOW = (1 << 16),
315 ERR_STS_UE = (1 << 17),
316 ERR_STS_MCH = (1 << 26),
317 ERR_STS_LOC_SHIFT = 27,
318 };
319
320 /*
321 * RAM Debug Address Register (RAM_DBG_ADDR) bit definitions.
322 */
323 enum {
324 RAM_DBG_ADDR_FW = (1 << 30),
325 RAM_DBG_ADDR_FR = (1 << 31),
326 };
327
328 /*
329 * Semaphore Register (SEM) bit definitions.
330 */
331 enum {
332 /*
333 * Example:
334 * reg = SEM_XGMAC0_MASK | (SEM_SET << SEM_XGMAC0_SHIFT)
335 */
336 SEM_CLEAR = 0,
337 SEM_SET = 1,
338 SEM_FORCE = 3,
339 SEM_XGMAC0_SHIFT = 0,
340 SEM_XGMAC1_SHIFT = 2,
341 SEM_ICB_SHIFT = 4,
342 SEM_MAC_ADDR_SHIFT = 6,
343 SEM_FLASH_SHIFT = 8,
344 SEM_PROBE_SHIFT = 10,
345 SEM_RT_IDX_SHIFT = 12,
346 SEM_PROC_REG_SHIFT = 14,
347 SEM_XGMAC0_MASK = 0x00030000,
348 SEM_XGMAC1_MASK = 0x000c0000,
349 SEM_ICB_MASK = 0x00300000,
350 SEM_MAC_ADDR_MASK = 0x00c00000,
351 SEM_FLASH_MASK = 0x03000000,
352 SEM_PROBE_MASK = 0x0c000000,
353 SEM_RT_IDX_MASK = 0x30000000,
354 SEM_PROC_REG_MASK = 0xc0000000,
355 };
356
357 /*
358 * 10G MAC Address Register (XGMAC_ADDR) bit definitions.
359 */
360 enum {
361 XGMAC_ADDR_RDY = (1 << 31),
362 XGMAC_ADDR_R = (1 << 30),
363 XGMAC_ADDR_XME = (1 << 29),
364
365 /* XGMAC control registers */
366 PAUSE_SRC_LO = 0x00000100,
367 PAUSE_SRC_HI = 0x00000104,
368 GLOBAL_CFG = 0x00000108,
369 GLOBAL_CFG_RESET = (1 << 0),
370 GLOBAL_CFG_JUMBO = (1 << 6),
371 GLOBAL_CFG_TX_STAT_EN = (1 << 10),
372 GLOBAL_CFG_RX_STAT_EN = (1 << 11),
373 TX_CFG = 0x0000010c,
374 TX_CFG_RESET = (1 << 0),
375 TX_CFG_EN = (1 << 1),
376 TX_CFG_PREAM = (1 << 2),
377 RX_CFG = 0x00000110,
378 RX_CFG_RESET = (1 << 0),
379 RX_CFG_EN = (1 << 1),
380 RX_CFG_PREAM = (1 << 2),
381 FLOW_CTL = 0x0000011c,
382 PAUSE_OPCODE = 0x00000120,
383 PAUSE_TIMER = 0x00000124,
384 PAUSE_FRM_DEST_LO = 0x00000128,
385 PAUSE_FRM_DEST_HI = 0x0000012c,
386 MAC_TX_PARAMS = 0x00000134,
387 MAC_TX_PARAMS_JUMBO = (1 << 31),
388 MAC_TX_PARAMS_SIZE_SHIFT = 16,
389 MAC_RX_PARAMS = 0x00000138,
390 MAC_SYS_INT = 0x00000144,
391 MAC_SYS_INT_MASK = 0x00000148,
392 MAC_MGMT_INT = 0x0000014c,
393 MAC_MGMT_IN_MASK = 0x00000150,
394 EXT_ARB_MODE = 0x000001fc,
395
396 /* XGMAC TX statistics registers */
397 TX_PKTS = 0x00000200,
398 TX_BYTES = 0x00000208,
399 TX_MCAST_PKTS = 0x00000210,
400 TX_BCAST_PKTS = 0x00000218,
401 TX_UCAST_PKTS = 0x00000220,
402 TX_CTL_PKTS = 0x00000228,
403 TX_PAUSE_PKTS = 0x00000230,
404 TX_64_PKT = 0x00000238,
405 TX_65_TO_127_PKT = 0x00000240,
406 TX_128_TO_255_PKT = 0x00000248,
407 TX_256_511_PKT = 0x00000250,
408 TX_512_TO_1023_PKT = 0x00000258,
409 TX_1024_TO_1518_PKT = 0x00000260,
410 TX_1519_TO_MAX_PKT = 0x00000268,
411 TX_UNDERSIZE_PKT = 0x00000270,
412 TX_OVERSIZE_PKT = 0x00000278,
413
414 /* XGMAC statistics control registers */
415 RX_HALF_FULL_DET = 0x000002a0,
416 TX_HALF_FULL_DET = 0x000002a4,
417 RX_OVERFLOW_DET = 0x000002a8,
418 TX_OVERFLOW_DET = 0x000002ac,
419 RX_HALF_FULL_MASK = 0x000002b0,
420 TX_HALF_FULL_MASK = 0x000002b4,
421 RX_OVERFLOW_MASK = 0x000002b8,
422 TX_OVERFLOW_MASK = 0x000002bc,
423 STAT_CNT_CTL = 0x000002c0,
424 STAT_CNT_CTL_CLEAR_TX = (1 << 0),
425 STAT_CNT_CTL_CLEAR_RX = (1 << 1),
426 AUX_RX_HALF_FULL_DET = 0x000002d0,
427 AUX_TX_HALF_FULL_DET = 0x000002d4,
428 AUX_RX_OVERFLOW_DET = 0x000002d8,
429 AUX_TX_OVERFLOW_DET = 0x000002dc,
430 AUX_RX_HALF_FULL_MASK = 0x000002f0,
431 AUX_TX_HALF_FULL_MASK = 0x000002f4,
432 AUX_RX_OVERFLOW_MASK = 0x000002f8,
433 AUX_TX_OVERFLOW_MASK = 0x000002fc,
434
435 /* XGMAC RX statistics registers */
436 RX_BYTES = 0x00000300,
437 RX_BYTES_OK = 0x00000308,
438 RX_PKTS = 0x00000310,
439 RX_PKTS_OK = 0x00000318,
440 RX_BCAST_PKTS = 0x00000320,
441 RX_MCAST_PKTS = 0x00000328,
442 RX_UCAST_PKTS = 0x00000330,
443 RX_UNDERSIZE_PKTS = 0x00000338,
444 RX_OVERSIZE_PKTS = 0x00000340,
445 RX_JABBER_PKTS = 0x00000348,
446 RX_UNDERSIZE_FCERR_PKTS = 0x00000350,
447 RX_DROP_EVENTS = 0x00000358,
448 RX_FCERR_PKTS = 0x00000360,
449 RX_ALIGN_ERR = 0x00000368,
450 RX_SYMBOL_ERR = 0x00000370,
451 RX_MAC_ERR = 0x00000378,
452 RX_CTL_PKTS = 0x00000380,
453 RX_PAUSE_PKTS = 0x00000388,
454 RX_64_PKTS = 0x00000390,
455 RX_65_TO_127_PKTS = 0x00000398,
456 RX_128_255_PKTS = 0x000003a0,
457 RX_256_511_PKTS = 0x000003a8,
458 RX_512_TO_1023_PKTS = 0x000003b0,
459 RX_1024_TO_1518_PKTS = 0x000003b8,
460 RX_1519_TO_MAX_PKTS = 0x000003c0,
461 RX_LEN_ERR_PKTS = 0x000003c8,
462
463 /* XGMAC MDIO control registers */
464 MDIO_TX_DATA = 0x00000400,
465 MDIO_RX_DATA = 0x00000410,
466 MDIO_CMD = 0x00000420,
467 MDIO_PHY_ADDR = 0x00000430,
468 MDIO_PORT = 0x00000440,
469 MDIO_STATUS = 0x00000450,
470
471 /* XGMAC AUX statistics registers */
472 };
473
474 /*
475 * Enhanced Transmission Schedule Registers (NIC_ETS,CNA_ETS) bit definitions.
476 */
477 enum {
478 ETS_QUEUE_SHIFT = 29,
479 ETS_REF = (1 << 26),
480 ETS_RS = (1 << 27),
481 ETS_P = (1 << 28),
482 ETS_FC_COS_SHIFT = 23,
483 };
484
485 /*
486 * Flash Address Register (FLASH_ADDR) bit definitions.
487 */
488 enum {
489 FLASH_ADDR_RDY = (1 << 31),
490 FLASH_ADDR_R = (1 << 30),
491 FLASH_ADDR_ERR = (1 << 29),
492 };
493
494 /*
495 * Stop CQ Processing Register (CQ_STOP) bit definitions.
496 */
497 enum {
498 CQ_STOP_QUEUE_MASK = (0x007f0000),
499 CQ_STOP_TYPE_MASK = (0x03000000),
500 CQ_STOP_TYPE_START = 0x00000100,
501 CQ_STOP_TYPE_STOP = 0x00000200,
502 CQ_STOP_TYPE_READ = 0x00000300,
503 CQ_STOP_EN = (1 << 15),
504 };
505
506 /*
507 * MAC Protocol Address Index Register (MAC_ADDR_IDX) bit definitions.
508 */
509 enum {
510 MAC_ADDR_IDX_SHIFT = 4,
511 MAC_ADDR_TYPE_SHIFT = 16,
512 MAC_ADDR_TYPE_MASK = 0x000f0000,
513 MAC_ADDR_TYPE_CAM_MAC = 0x00000000,
514 MAC_ADDR_TYPE_MULTI_MAC = 0x00010000,
515 MAC_ADDR_TYPE_VLAN = 0x00020000,
516 MAC_ADDR_TYPE_MULTI_FLTR = 0x00030000,
517 MAC_ADDR_TYPE_FC_MAC = 0x00040000,
518 MAC_ADDR_TYPE_MGMT_MAC = 0x00050000,
519 MAC_ADDR_TYPE_MGMT_VLAN = 0x00060000,
520 MAC_ADDR_TYPE_MGMT_V4 = 0x00070000,
521 MAC_ADDR_TYPE_MGMT_V6 = 0x00080000,
522 MAC_ADDR_TYPE_MGMT_TU_DP = 0x00090000,
523 MAC_ADDR_ADR = (1 << 25),
524 MAC_ADDR_RS = (1 << 26),
525 MAC_ADDR_E = (1 << 27),
526 MAC_ADDR_MR = (1 << 30),
527 MAC_ADDR_MW = (1 << 31),
528 MAX_MULTICAST_ENTRIES = 32,
529 };
530
531 /*
532 * MAC Protocol Address Index Register (SPLT_HDR) bit definitions.
533 */
534 enum {
535 SPLT_HDR_EP = (1 << 31),
536 };
537
538 /*
539 * FCoE Receive Configuration Register (FC_RCV_CFG) bit definitions.
540 */
541 enum {
542 FC_RCV_CFG_ECT = (1 << 15),
543 FC_RCV_CFG_DFH = (1 << 20),
544 FC_RCV_CFG_DVF = (1 << 21),
545 FC_RCV_CFG_RCE = (1 << 27),
546 FC_RCV_CFG_RFE = (1 << 28),
547 FC_RCV_CFG_TEE = (1 << 29),
548 FC_RCV_CFG_TCE = (1 << 30),
549 FC_RCV_CFG_TFE = (1 << 31),
550 };
551
552 /*
553 * NIC Receive Configuration Register (NIC_RCV_CFG) bit definitions.
554 */
555 enum {
556 NIC_RCV_CFG_PPE = (1 << 0),
557 NIC_RCV_CFG_VLAN_MASK = 0x00060000,
558 NIC_RCV_CFG_VLAN_ALL = 0x00000000,
559 NIC_RCV_CFG_VLAN_MATCH_ONLY = 0x00000002,
560 NIC_RCV_CFG_VLAN_MATCH_AND_NON = 0x00000004,
561 NIC_RCV_CFG_VLAN_NONE_AND_NON = 0x00000006,
562 NIC_RCV_CFG_RV = (1 << 3),
563 NIC_RCV_CFG_DFQ_MASK = (0x7f000000),
564 NIC_RCV_CFG_DFQ_SHIFT = 8,
565 NIC_RCV_CFG_DFQ = 0, /* HARDCODE default queue to 0. */
566 };
567
568 /*
569 * Mgmt Receive Configuration Register (MGMT_RCV_CFG) bit definitions.
570 */
571 enum {
572 MGMT_RCV_CFG_ARP = (1 << 0),
573 MGMT_RCV_CFG_DHC = (1 << 1),
574 MGMT_RCV_CFG_DHS = (1 << 2),
575 MGMT_RCV_CFG_NP = (1 << 3),
576 MGMT_RCV_CFG_I6N = (1 << 4),
577 MGMT_RCV_CFG_I6R = (1 << 5),
578 MGMT_RCV_CFG_DH6 = (1 << 6),
579 MGMT_RCV_CFG_UD1 = (1 << 7),
580 MGMT_RCV_CFG_UD0 = (1 << 8),
581 MGMT_RCV_CFG_BCT = (1 << 9),
582 MGMT_RCV_CFG_MCT = (1 << 10),
583 MGMT_RCV_CFG_DM = (1 << 11),
584 MGMT_RCV_CFG_RM = (1 << 12),
585 MGMT_RCV_CFG_STL = (1 << 13),
586 MGMT_RCV_CFG_VLAN_MASK = 0xc0000000,
587 MGMT_RCV_CFG_VLAN_ALL = 0x00000000,
588 MGMT_RCV_CFG_VLAN_MATCH_ONLY = 0x00004000,
589 MGMT_RCV_CFG_VLAN_MATCH_AND_NON = 0x00008000,
590 MGMT_RCV_CFG_VLAN_NONE_AND_NON = 0x0000c000,
591 };
592
593 /*
594 * Routing Index Register (RT_IDX) bit definitions.
595 */
596 enum {
597 RT_IDX_IDX_SHIFT = 8,
598 RT_IDX_TYPE_MASK = 0x000f0000,
599 RT_IDX_TYPE_RT = 0x00000000,
600 RT_IDX_TYPE_RT_INV = 0x00010000,
601 RT_IDX_TYPE_NICQ = 0x00020000,
602 RT_IDX_TYPE_NICQ_INV = 0x00030000,
603 RT_IDX_DST_MASK = 0x00700000,
604 RT_IDX_DST_RSS = 0x00000000,
605 RT_IDX_DST_CAM_Q = 0x00100000,
606 RT_IDX_DST_COS_Q = 0x00200000,
607 RT_IDX_DST_DFLT_Q = 0x00300000,
608 RT_IDX_DST_DEST_Q = 0x00400000,
609 RT_IDX_RS = (1 << 26),
610 RT_IDX_E = (1 << 27),
611 RT_IDX_MR = (1 << 30),
612 RT_IDX_MW = (1 << 31),
613
614 /* Nic Queue format - type 2 bits */
615 RT_IDX_BCAST = (1 << 0),
616 RT_IDX_MCAST = (1 << 1),
617 RT_IDX_MCAST_MATCH = (1 << 2),
618 RT_IDX_MCAST_REG_MATCH = (1 << 3),
619 RT_IDX_MCAST_HASH_MATCH = (1 << 4),
620 RT_IDX_FC_MACH = (1 << 5),
621 RT_IDX_ETH_FCOE = (1 << 6),
622 RT_IDX_CAM_HIT = (1 << 7),
623 RT_IDX_CAM_BIT0 = (1 << 8),
624 RT_IDX_CAM_BIT1 = (1 << 9),
625 RT_IDX_VLAN_TAG = (1 << 10),
626 RT_IDX_VLAN_MATCH = (1 << 11),
627 RT_IDX_VLAN_FILTER = (1 << 12),
628 RT_IDX_ETH_SKIP1 = (1 << 13),
629 RT_IDX_ETH_SKIP2 = (1 << 14),
630 RT_IDX_BCAST_MCAST_MATCH = (1 << 15),
631 RT_IDX_802_3 = (1 << 16),
632 RT_IDX_LLDP = (1 << 17),
633 RT_IDX_UNUSED018 = (1 << 18),
634 RT_IDX_UNUSED019 = (1 << 19),
635 RT_IDX_UNUSED20 = (1 << 20),
636 RT_IDX_UNUSED21 = (1 << 21),
637 RT_IDX_ERR = (1 << 22),
638 RT_IDX_VALID = (1 << 23),
639 RT_IDX_TU_CSUM_ERR = (1 << 24),
640 RT_IDX_IP_CSUM_ERR = (1 << 25),
641 RT_IDX_MAC_ERR = (1 << 26),
642 RT_IDX_RSS_TCP6 = (1 << 27),
643 RT_IDX_RSS_TCP4 = (1 << 28),
644 RT_IDX_RSS_IPV6 = (1 << 29),
645 RT_IDX_RSS_IPV4 = (1 << 30),
646 RT_IDX_RSS_MATCH = (1 << 31),
647
648 /* Hierarchy for the NIC Queue Mask */
649 RT_IDX_ALL_ERR_SLOT = 0,
650 RT_IDX_MAC_ERR_SLOT = 0,
651 RT_IDX_IP_CSUM_ERR_SLOT = 1,
652 RT_IDX_TCP_UDP_CSUM_ERR_SLOT = 2,
653 RT_IDX_BCAST_SLOT = 3,
654 RT_IDX_MCAST_MATCH_SLOT = 4,
655 RT_IDX_ALLMULTI_SLOT = 5,
656 RT_IDX_UNUSED6_SLOT = 6,
657 RT_IDX_UNUSED7_SLOT = 7,
658 RT_IDX_RSS_MATCH_SLOT = 8,
659 RT_IDX_RSS_IPV4_SLOT = 8,
660 RT_IDX_RSS_IPV6_SLOT = 9,
661 RT_IDX_RSS_TCP4_SLOT = 10,
662 RT_IDX_RSS_TCP6_SLOT = 11,
663 RT_IDX_CAM_HIT_SLOT = 12,
664 RT_IDX_UNUSED013 = 13,
665 RT_IDX_UNUSED014 = 14,
666 RT_IDX_PROMISCUOUS_SLOT = 15,
667 RT_IDX_MAX_SLOTS = 16,
668 };
669
670 /*
671 * Control Register Set Map
672 */
673 enum {
674 PROC_ADDR = 0, /* Use semaphore */
675 PROC_DATA = 0x04, /* Use semaphore */
676 SYS = 0x08,
677 RST_FO = 0x0c,
678 FSC = 0x10,
679 CSR = 0x14,
680 LED = 0x18,
681 ICB_RID = 0x1c, /* Use semaphore */
682 ICB_L = 0x20, /* Use semaphore */
683 ICB_H = 0x24, /* Use semaphore */
684 CFG = 0x28,
685 BIOS_ADDR = 0x2c,
686 STS = 0x30,
687 INTR_EN = 0x34,
688 INTR_MASK = 0x38,
689 ISR1 = 0x3c,
690 ISR2 = 0x40,
691 ISR3 = 0x44,
692 ISR4 = 0x48,
693 REV_ID = 0x4c,
694 FRC_ECC_ERR = 0x50,
695 ERR_STS = 0x54,
696 RAM_DBG_ADDR = 0x58,
697 RAM_DBG_DATA = 0x5c,
698 ECC_ERR_CNT = 0x60,
699 SEM = 0x64,
700 GPIO_1 = 0x68, /* Use semaphore */
701 GPIO_2 = 0x6c, /* Use semaphore */
702 GPIO_3 = 0x70, /* Use semaphore */
703 RSVD2 = 0x74,
704 XGMAC_ADDR = 0x78, /* Use semaphore */
705 XGMAC_DATA = 0x7c, /* Use semaphore */
706 NIC_ETS = 0x80,
707 CNA_ETS = 0x84,
708 FLASH_ADDR = 0x88, /* Use semaphore */
709 FLASH_DATA = 0x8c, /* Use semaphore */
710 CQ_STOP = 0x90,
711 PAGE_TBL_RID = 0x94,
712 WQ_PAGE_TBL_LO = 0x98,
713 WQ_PAGE_TBL_HI = 0x9c,
714 CQ_PAGE_TBL_LO = 0xa0,
715 CQ_PAGE_TBL_HI = 0xa4,
716 MAC_ADDR_IDX = 0xa8, /* Use semaphore */
717 MAC_ADDR_DATA = 0xac, /* Use semaphore */
718 COS_DFLT_CQ1 = 0xb0,
719 COS_DFLT_CQ2 = 0xb4,
720 ETYPE_SKIP1 = 0xb8,
721 ETYPE_SKIP2 = 0xbc,
722 SPLT_HDR = 0xc0,
723 FC_PAUSE_THRES = 0xc4,
724 NIC_PAUSE_THRES = 0xc8,
725 FC_ETHERTYPE = 0xcc,
726 FC_RCV_CFG = 0xd0,
727 NIC_RCV_CFG = 0xd4,
728 FC_COS_TAGS = 0xd8,
729 NIC_COS_TAGS = 0xdc,
730 MGMT_RCV_CFG = 0xe0,
731 RT_IDX = 0xe4,
732 RT_DATA = 0xe8,
733 RSVD7 = 0xec,
734 XG_SERDES_ADDR = 0xf0,
735 XG_SERDES_DATA = 0xf4,
736 PRB_MX_ADDR = 0xf8, /* Use semaphore */
737 PRB_MX_DATA = 0xfc, /* Use semaphore */
738 };
739
740 /*
741 * CAM output format.
742 */
743 enum {
744 CAM_OUT_ROUTE_FC = 0,
745 CAM_OUT_ROUTE_NIC = 1,
746 CAM_OUT_FUNC_SHIFT = 2,
747 CAM_OUT_RV = (1 << 4),
748 CAM_OUT_SH = (1 << 15),
749 CAM_OUT_CQ_ID_SHIFT = 5,
750 };
751
752 /*
753 * Mailbox definitions
754 */
755 enum {
756 /* Asynchronous Event Notifications */
757 AEN_SYS_ERR = 0x00008002,
758 AEN_LINK_UP = 0x00008011,
759 AEN_LINK_DOWN = 0x00008012,
760 AEN_IDC_CMPLT = 0x00008100,
761 AEN_IDC_REQ = 0x00008101,
762 AEN_IDC_EXT = 0x00008102,
763 AEN_DCBX_CHG = 0x00008110,
764 AEN_AEN_LOST = 0x00008120,
765 AEN_AEN_SFP_IN = 0x00008130,
766 AEN_AEN_SFP_OUT = 0x00008131,
767 AEN_FW_INIT_DONE = 0x00008400,
768 AEN_FW_INIT_FAIL = 0x00008401,
769
770 /* Mailbox Command Opcodes. */
771 MB_CMD_NOP = 0x00000000,
772 MB_CMD_EX_FW = 0x00000002,
773 MB_CMD_MB_TEST = 0x00000006,
774 MB_CMD_CSUM_TEST = 0x00000007, /* Verify Checksum */
775 MB_CMD_ABOUT_FW = 0x00000008,
776 MB_CMD_COPY_RISC_RAM = 0x0000000a,
777 MB_CMD_LOAD_RISC_RAM = 0x0000000b,
778 MB_CMD_DUMP_RISC_RAM = 0x0000000c,
779 MB_CMD_WRITE_RAM = 0x0000000d,
780 MB_CMD_INIT_RISC_RAM = 0x0000000e,
781 MB_CMD_READ_RAM = 0x0000000f,
782 MB_CMD_STOP_FW = 0x00000014,
783 MB_CMD_MAKE_SYS_ERR = 0x0000002a,
784 MB_CMD_WRITE_SFP = 0x00000030,
785 MB_CMD_READ_SFP = 0x00000031,
786 MB_CMD_INIT_FW = 0x00000060,
787 MB_CMD_GET_IFCB = 0x00000061,
788 MB_CMD_GET_FW_STATE = 0x00000069,
789 MB_CMD_IDC_REQ = 0x00000100, /* Inter-Driver Communication */
790 MB_CMD_IDC_ACK = 0x00000101, /* Inter-Driver Communication */
791 MB_CMD_SET_WOL_MODE = 0x00000110, /* Wake On Lan */
792 MB_WOL_DISABLE = 0,
793 MB_WOL_MAGIC_PKT = (1 << 1),
794 MB_WOL_FLTR = (1 << 2),
795 MB_WOL_UCAST = (1 << 3),
796 MB_WOL_MCAST = (1 << 4),
797 MB_WOL_BCAST = (1 << 5),
798 MB_WOL_LINK_UP = (1 << 6),
799 MB_WOL_LINK_DOWN = (1 << 7),
800 MB_WOL_MODE_ON = (1 << 16), /* Wake on Lan Mode on */
801 MB_CMD_SET_WOL_FLTR = 0x00000111, /* Wake On Lan Filter */
802 MB_CMD_CLEAR_WOL_FLTR = 0x00000112, /* Wake On Lan Filter */
803 MB_CMD_SET_WOL_MAGIC = 0x00000113, /* Wake On Lan Magic Packet */
804 MB_CMD_CLEAR_WOL_MAGIC = 0x00000114,/* Wake On Lan Magic Packet */
805 MB_CMD_SET_WOL_IMMED = 0x00000115,
806 MB_CMD_PORT_RESET = 0x00000120,
807 MB_CMD_SET_PORT_CFG = 0x00000122,
808 MB_CMD_GET_PORT_CFG = 0x00000123,
809 MB_CMD_GET_LINK_STS = 0x00000124,
810 MB_CMD_SET_LED_CFG = 0x00000125, /* Set LED Configuration Register */
811 QL_LED_BLINK = 0x03e803e8,
812 MB_CMD_GET_LED_CFG = 0x00000126, /* Get LED Configuration Register */
813 MB_CMD_SET_MGMNT_TFK_CTL = 0x00000160, /* Set Mgmnt Traffic Control */
814 MB_SET_MPI_TFK_STOP = (1 << 0),
815 MB_SET_MPI_TFK_RESUME = (1 << 1),
816 MB_CMD_GET_MGMNT_TFK_CTL = 0x00000161, /* Get Mgmnt Traffic Control */
817 MB_GET_MPI_TFK_STOPPED = (1 << 0),
818 MB_GET_MPI_TFK_FIFO_EMPTY = (1 << 1),
819 /* Sub-commands for IDC request.
820 * This describes the reason for the
821 * IDC request.
822 */
823 MB_CMD_IOP_NONE = 0x0000,
824 MB_CMD_IOP_PREP_UPDATE_MPI = 0x0001,
825 MB_CMD_IOP_COMP_UPDATE_MPI = 0x0002,
826 MB_CMD_IOP_PREP_LINK_DOWN = 0x0010,
827 MB_CMD_IOP_DVR_START = 0x0100,
828 MB_CMD_IOP_FLASH_ACC = 0x0101,
829 MB_CMD_IOP_RESTART_MPI = 0x0102,
830 MB_CMD_IOP_CORE_DUMP_MPI = 0x0103,
831
832 /* Mailbox Command Status. */
833 MB_CMD_STS_GOOD = 0x00004000, /* Success. */
834 MB_CMD_STS_INTRMDT = 0x00001000, /* Intermediate Complete. */
835 MB_CMD_STS_INVLD_CMD = 0x00004001, /* Invalid. */
836 MB_CMD_STS_XFC_ERR = 0x00004002, /* Interface Error. */
837 MB_CMD_STS_CSUM_ERR = 0x00004003, /* Csum Error. */
838 MB_CMD_STS_ERR = 0x00004005, /* System Error. */
839 MB_CMD_STS_PARAM_ERR = 0x00004006, /* Parameter Error. */
840 };
841
842 struct mbox_params {
843 u32 mbox_in[MAILBOX_COUNT];
844 u32 mbox_out[MAILBOX_COUNT];
845 int in_count;
846 int out_count;
847 };
848
849 struct flash_params_8012 {
850 u8 dev_id_str[4];
851 __le16 size;
852 __le16 csum;
853 __le16 ver;
854 __le16 sub_dev_id;
855 u8 mac_addr[6];
856 __le16 res;
857 };
858
859 /* 8000 device's flash is a different structure
860 * at a different offset in flash.
861 */
862 #define FUNC0_FLASH_OFFSET 0x140200
863 #define FUNC1_FLASH_OFFSET 0x140600
864
865 /* Flash related data structures. */
866 struct flash_params_8000 {
867 u8 dev_id_str[4]; /* "8000" */
868 __le16 ver;
869 __le16 size;
870 __le16 csum;
871 __le16 reserved0;
872 __le16 total_size;
873 __le16 entry_count;
874 u8 data_type0;
875 u8 data_size0;
876 u8 mac_addr[6];
877 u8 data_type1;
878 u8 data_size1;
879 u8 mac_addr1[6];
880 u8 data_type2;
881 u8 data_size2;
882 __le16 vlan_id;
883 u8 data_type3;
884 u8 data_size3;
885 __le16 last;
886 u8 reserved1[464];
887 __le16 subsys_ven_id;
888 __le16 subsys_dev_id;
889 u8 reserved2[4];
890 };
891
892 union flash_params {
893 struct flash_params_8012 flash_params_8012;
894 struct flash_params_8000 flash_params_8000;
895 };
896
897 /*
898 * doorbell space for the rx ring context
899 */
900 struct rx_doorbell_context {
901 u32 cnsmr_idx; /* 0x00 */
902 u32 valid; /* 0x04 */
903 u32 reserved[4]; /* 0x08-0x14 */
904 u32 lbq_prod_idx; /* 0x18 */
905 u32 sbq_prod_idx; /* 0x1c */
906 };
907
908 /*
909 * doorbell space for the tx ring context
910 */
911 struct tx_doorbell_context {
912 u32 prod_idx; /* 0x00 */
913 u32 valid; /* 0x04 */
914 u32 reserved[4]; /* 0x08-0x14 */
915 u32 lbq_prod_idx; /* 0x18 */
916 u32 sbq_prod_idx; /* 0x1c */
917 };
918
919 /* DATA STRUCTURES SHARED WITH HARDWARE. */
920 struct tx_buf_desc {
921 __le64 addr;
922 __le32 len;
923 #define TX_DESC_LEN_MASK 0x000fffff
924 #define TX_DESC_C 0x40000000
925 #define TX_DESC_E 0x80000000
926 } __attribute((packed));
927
928 /*
929 * IOCB Definitions...
930 */
931
932 #define OPCODE_OB_MAC_IOCB 0x01
933 #define OPCODE_OB_MAC_TSO_IOCB 0x02
934 #define OPCODE_IB_MAC_IOCB 0x20
935 #define OPCODE_IB_MPI_IOCB 0x21
936 #define OPCODE_IB_AE_IOCB 0x3f
937
938 struct ob_mac_iocb_req {
939 u8 opcode;
940 u8 flags1;
941 #define OB_MAC_IOCB_REQ_OI 0x01
942 #define OB_MAC_IOCB_REQ_I 0x02
943 #define OB_MAC_IOCB_REQ_D 0x08
944 #define OB_MAC_IOCB_REQ_F 0x10
945 u8 flags2;
946 u8 flags3;
947 #define OB_MAC_IOCB_DFP 0x02
948 #define OB_MAC_IOCB_V 0x04
949 __le32 reserved1[2];
950 __le16 frame_len;
951 #define OB_MAC_IOCB_LEN_MASK 0x3ffff
952 __le16 reserved2;
953 u32 tid;
954 u32 txq_idx;
955 __le32 reserved3;
956 __le16 vlan_tci;
957 __le16 reserved4;
958 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
959 } __attribute((packed));
960
961 struct ob_mac_iocb_rsp {
962 u8 opcode; /* */
963 u8 flags1; /* */
964 #define OB_MAC_IOCB_RSP_OI 0x01 /* */
965 #define OB_MAC_IOCB_RSP_I 0x02 /* */
966 #define OB_MAC_IOCB_RSP_E 0x08 /* */
967 #define OB_MAC_IOCB_RSP_S 0x10 /* too Short */
968 #define OB_MAC_IOCB_RSP_L 0x20 /* too Large */
969 #define OB_MAC_IOCB_RSP_P 0x40 /* Padded */
970 u8 flags2; /* */
971 u8 flags3; /* */
972 #define OB_MAC_IOCB_RSP_B 0x80 /* */
973 u32 tid;
974 u32 txq_idx;
975 __le32 reserved[13];
976 } __attribute((packed));
977
978 struct ob_mac_tso_iocb_req {
979 u8 opcode;
980 u8 flags1;
981 #define OB_MAC_TSO_IOCB_OI 0x01
982 #define OB_MAC_TSO_IOCB_I 0x02
983 #define OB_MAC_TSO_IOCB_D 0x08
984 #define OB_MAC_TSO_IOCB_IP4 0x40
985 #define OB_MAC_TSO_IOCB_IP6 0x80
986 u8 flags2;
987 #define OB_MAC_TSO_IOCB_LSO 0x20
988 #define OB_MAC_TSO_IOCB_UC 0x40
989 #define OB_MAC_TSO_IOCB_TC 0x80
990 u8 flags3;
991 #define OB_MAC_TSO_IOCB_IC 0x01
992 #define OB_MAC_TSO_IOCB_DFP 0x02
993 #define OB_MAC_TSO_IOCB_V 0x04
994 __le32 reserved1[2];
995 __le32 frame_len;
996 u32 tid;
997 u32 txq_idx;
998 __le16 total_hdrs_len;
999 __le16 net_trans_offset;
1000 #define OB_MAC_TRANSPORT_HDR_SHIFT 6
1001 __le16 vlan_tci;
1002 __le16 mss;
1003 struct tx_buf_desc tbd[TX_DESC_PER_IOCB];
1004 } __attribute((packed));
1005
1006 struct ob_mac_tso_iocb_rsp {
1007 u8 opcode;
1008 u8 flags1;
1009 #define OB_MAC_TSO_IOCB_RSP_OI 0x01
1010 #define OB_MAC_TSO_IOCB_RSP_I 0x02
1011 #define OB_MAC_TSO_IOCB_RSP_E 0x08
1012 #define OB_MAC_TSO_IOCB_RSP_S 0x10
1013 #define OB_MAC_TSO_IOCB_RSP_L 0x20
1014 #define OB_MAC_TSO_IOCB_RSP_P 0x40
1015 u8 flags2; /* */
1016 u8 flags3; /* */
1017 #define OB_MAC_TSO_IOCB_RSP_B 0x8000
1018 u32 tid;
1019 u32 txq_idx;
1020 __le32 reserved2[13];
1021 } __attribute((packed));
1022
1023 struct ib_mac_iocb_rsp {
1024 u8 opcode; /* 0x20 */
1025 u8 flags1;
1026 #define IB_MAC_IOCB_RSP_OI 0x01 /* Overide intr delay */
1027 #define IB_MAC_IOCB_RSP_I 0x02 /* Disble Intr Generation */
1028 #define IB_MAC_CSUM_ERR_MASK 0x1c /* A mask to use for csum errs */
1029 #define IB_MAC_IOCB_RSP_TE 0x04 /* Checksum error */
1030 #define IB_MAC_IOCB_RSP_NU 0x08 /* No checksum rcvd */
1031 #define IB_MAC_IOCB_RSP_IE 0x10 /* IPv4 checksum error */
1032 #define IB_MAC_IOCB_RSP_M_MASK 0x60 /* Multicast info */
1033 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* Not mcast frame */
1034 #define IB_MAC_IOCB_RSP_M_HASH 0x20 /* HASH mcast frame */
1035 #define IB_MAC_IOCB_RSP_M_REG 0x40 /* Registered mcast frame */
1036 #define IB_MAC_IOCB_RSP_M_PROM 0x60 /* Promiscuous mcast frame */
1037 #define IB_MAC_IOCB_RSP_B 0x80 /* Broadcast frame */
1038 u8 flags2;
1039 #define IB_MAC_IOCB_RSP_P 0x01 /* Promiscuous frame */
1040 #define IB_MAC_IOCB_RSP_V 0x02 /* Vlan tag present */
1041 #define IB_MAC_IOCB_RSP_ERR_MASK 0x1c /* */
1042 #define IB_MAC_IOCB_RSP_ERR_CODE_ERR 0x04
1043 #define IB_MAC_IOCB_RSP_ERR_OVERSIZE 0x08
1044 #define IB_MAC_IOCB_RSP_ERR_UNDERSIZE 0x10
1045 #define IB_MAC_IOCB_RSP_ERR_PREAMBLE 0x14
1046 #define IB_MAC_IOCB_RSP_ERR_FRAME_LEN 0x18
1047 #define IB_MAC_IOCB_RSP_ERR_CRC 0x1c
1048 #define IB_MAC_IOCB_RSP_U 0x20 /* UDP packet */
1049 #define IB_MAC_IOCB_RSP_T 0x40 /* TCP packet */
1050 #define IB_MAC_IOCB_RSP_FO 0x80 /* Failover port */
1051 u8 flags3;
1052 #define IB_MAC_IOCB_RSP_RSS_MASK 0x07 /* RSS mask */
1053 #define IB_MAC_IOCB_RSP_M_NONE 0x00 /* No RSS match */
1054 #define IB_MAC_IOCB_RSP_M_IPV4 0x04 /* IPv4 RSS match */
1055 #define IB_MAC_IOCB_RSP_M_IPV6 0x02 /* IPv6 RSS match */
1056 #define IB_MAC_IOCB_RSP_M_TCP_V4 0x05 /* TCP with IPv4 */
1057 #define IB_MAC_IOCB_RSP_M_TCP_V6 0x03 /* TCP with IPv6 */
1058 #define IB_MAC_IOCB_RSP_V4 0x08 /* IPV4 */
1059 #define IB_MAC_IOCB_RSP_V6 0x10 /* IPV6 */
1060 #define IB_MAC_IOCB_RSP_IH 0x20 /* Split after IP header */
1061 #define IB_MAC_IOCB_RSP_DS 0x40 /* data is in small buffer */
1062 #define IB_MAC_IOCB_RSP_DL 0x80 /* data is in large buffer */
1063 __le32 data_len; /* */
1064 __le64 data_addr; /* */
1065 __le32 rss; /* */
1066 __le16 vlan_id; /* 12 bits */
1067 #define IB_MAC_IOCB_RSP_C 0x1000 /* VLAN CFI bit */
1068 #define IB_MAC_IOCB_RSP_COS_SHIFT 12 /* class of service value */
1069 #define IB_MAC_IOCB_RSP_VLAN_MASK 0x0ffff
1070
1071 __le16 reserved1;
1072 __le32 reserved2[6];
1073 u8 reserved3[3];
1074 u8 flags4;
1075 #define IB_MAC_IOCB_RSP_HV 0x20
1076 #define IB_MAC_IOCB_RSP_HS 0x40
1077 #define IB_MAC_IOCB_RSP_HL 0x80
1078 __le32 hdr_len; /* */
1079 __le64 hdr_addr; /* */
1080 } __attribute((packed));
1081
1082 struct ib_ae_iocb_rsp {
1083 u8 opcode;
1084 u8 flags1;
1085 #define IB_AE_IOCB_RSP_OI 0x01
1086 #define IB_AE_IOCB_RSP_I 0x02
1087 u8 event;
1088 #define LINK_UP_EVENT 0x00
1089 #define LINK_DOWN_EVENT 0x01
1090 #define CAM_LOOKUP_ERR_EVENT 0x06
1091 #define SOFT_ECC_ERROR_EVENT 0x07
1092 #define MGMT_ERR_EVENT 0x08
1093 #define TEN_GIG_MAC_EVENT 0x09
1094 #define GPI0_H2L_EVENT 0x10
1095 #define GPI0_L2H_EVENT 0x20
1096 #define GPI1_H2L_EVENT 0x11
1097 #define GPI1_L2H_EVENT 0x21
1098 #define PCI_ERR_ANON_BUF_RD 0x40
1099 u8 q_id;
1100 __le32 reserved[15];
1101 } __attribute((packed));
1102
1103 /*
1104 * These three structures are for generic
1105 * handling of ib and ob iocbs.
1106 */
1107 struct ql_net_rsp_iocb {
1108 u8 opcode;
1109 u8 flags0;
1110 __le16 length;
1111 __le32 tid;
1112 __le32 reserved[14];
1113 } __attribute((packed));
1114
1115 struct net_req_iocb {
1116 u8 opcode;
1117 u8 flags0;
1118 __le16 flags1;
1119 __le32 tid;
1120 __le32 reserved1[30];
1121 } __attribute((packed));
1122
1123 /*
1124 * tx ring initialization control block for chip.
1125 * It is defined as:
1126 * "Work Queue Initialization Control Block"
1127 */
1128 struct wqicb {
1129 __le16 len;
1130 #define Q_LEN_V (1 << 4)
1131 #define Q_LEN_CPP_CONT 0x0000
1132 #define Q_LEN_CPP_16 0x0001
1133 #define Q_LEN_CPP_32 0x0002
1134 #define Q_LEN_CPP_64 0x0003
1135 #define Q_LEN_CPP_512 0x0006
1136 __le16 flags;
1137 #define Q_PRI_SHIFT 1
1138 #define Q_FLAGS_LC 0x1000
1139 #define Q_FLAGS_LB 0x2000
1140 #define Q_FLAGS_LI 0x4000
1141 #define Q_FLAGS_LO 0x8000
1142 __le16 cq_id_rss;
1143 #define Q_CQ_ID_RSS_RV 0x8000
1144 __le16 rid;
1145 __le64 addr;
1146 __le64 cnsmr_idx_addr;
1147 } __attribute((packed));
1148
1149 /*
1150 * rx ring initialization control block for chip.
1151 * It is defined as:
1152 * "Completion Queue Initialization Control Block"
1153 */
1154 struct cqicb {
1155 u8 msix_vect;
1156 u8 reserved1;
1157 u8 reserved2;
1158 u8 flags;
1159 #define FLAGS_LV 0x08
1160 #define FLAGS_LS 0x10
1161 #define FLAGS_LL 0x20
1162 #define FLAGS_LI 0x40
1163 #define FLAGS_LC 0x80
1164 __le16 len;
1165 #define LEN_V (1 << 4)
1166 #define LEN_CPP_CONT 0x0000
1167 #define LEN_CPP_32 0x0001
1168 #define LEN_CPP_64 0x0002
1169 #define LEN_CPP_128 0x0003
1170 __le16 rid;
1171 __le64 addr;
1172 __le64 prod_idx_addr;
1173 __le16 pkt_delay;
1174 __le16 irq_delay;
1175 __le64 lbq_addr;
1176 __le16 lbq_buf_size;
1177 __le16 lbq_len; /* entry count */
1178 __le64 sbq_addr;
1179 __le16 sbq_buf_size;
1180 __le16 sbq_len; /* entry count */
1181 } __attribute((packed));
1182
1183 struct ricb {
1184 u8 base_cq;
1185 #define RSS_L4K 0x80
1186 u8 flags;
1187 #define RSS_L6K 0x01
1188 #define RSS_LI 0x02
1189 #define RSS_LB 0x04
1190 #define RSS_LM 0x08
1191 #define RSS_RI4 0x10
1192 #define RSS_RT4 0x20
1193 #define RSS_RI6 0x40
1194 #define RSS_RT6 0x80
1195 __le16 mask;
1196 u8 hash_cq_id[1024];
1197 __le32 ipv6_hash_key[10];
1198 __le32 ipv4_hash_key[4];
1199 } __attribute((packed));
1200
1201 /* SOFTWARE/DRIVER DATA STRUCTURES. */
1202
1203 struct oal {
1204 struct tx_buf_desc oal[TX_DESC_PER_OAL];
1205 };
1206
1207 struct map_list {
1208 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1209 DECLARE_PCI_UNMAP_LEN(maplen);
1210 };
1211
1212 struct tx_ring_desc {
1213 struct sk_buff *skb;
1214 struct ob_mac_iocb_req *queue_entry;
1215 u32 index;
1216 struct oal oal;
1217 struct map_list map[MAX_SKB_FRAGS + 1];
1218 int map_cnt;
1219 struct tx_ring_desc *next;
1220 };
1221
1222 struct page_chunk {
1223 struct page *page; /* master page */
1224 char *va; /* virt addr for this chunk */
1225 u64 map; /* mapping for master */
1226 unsigned int offset; /* offset for this chunk */
1227 unsigned int last_flag; /* flag set for last chunk in page */
1228 };
1229
1230 struct bq_desc {
1231 union {
1232 struct page_chunk pg_chunk;
1233 struct sk_buff *skb;
1234 } p;
1235 __le64 *addr;
1236 u32 index;
1237 DECLARE_PCI_UNMAP_ADDR(mapaddr);
1238 DECLARE_PCI_UNMAP_LEN(maplen);
1239 };
1240
1241 #define QL_TXQ_IDX(qdev, skb) (smp_processor_id()%(qdev->tx_ring_count))
1242
1243 struct tx_ring {
1244 /*
1245 * queue info.
1246 */
1247 struct wqicb wqicb; /* structure used to inform chip of new queue */
1248 void *wq_base; /* pci_alloc:virtual addr for tx */
1249 dma_addr_t wq_base_dma; /* pci_alloc:dma addr for tx */
1250 __le32 *cnsmr_idx_sh_reg; /* shadow copy of consumer idx */
1251 dma_addr_t cnsmr_idx_sh_reg_dma; /* dma-shadow copy of consumer */
1252 u32 wq_size; /* size in bytes of queue area */
1253 u32 wq_len; /* number of entries in queue */
1254 void __iomem *prod_idx_db_reg; /* doorbell area index reg at offset 0x00 */
1255 void __iomem *valid_db_reg; /* doorbell area valid reg at offset 0x04 */
1256 u16 prod_idx; /* current value for prod idx */
1257 u16 cq_id; /* completion (rx) queue for tx completions */
1258 u8 wq_id; /* queue id for this entry */
1259 u8 reserved1[3];
1260 struct tx_ring_desc *q; /* descriptor list for the queue */
1261 spinlock_t lock;
1262 atomic_t tx_count; /* counts down for every outstanding IO */
1263 atomic_t queue_stopped; /* Turns queue off when full. */
1264 struct delayed_work tx_work;
1265 struct ql_adapter *qdev;
1266 u64 tx_packets;
1267 u64 tx_bytes;
1268 u64 tx_errors;
1269 };
1270
1271 /*
1272 * Type of inbound queue.
1273 */
1274 enum {
1275 DEFAULT_Q = 2, /* Handles slow queue and chip/MPI events. */
1276 TX_Q = 3, /* Handles outbound completions. */
1277 RX_Q = 4, /* Handles inbound completions. */
1278 };
1279
1280 struct rx_ring {
1281 struct cqicb cqicb; /* The chip's completion queue init control block. */
1282
1283 /* Completion queue elements. */
1284 void *cq_base;
1285 dma_addr_t cq_base_dma;
1286 u32 cq_size;
1287 u32 cq_len;
1288 u16 cq_id;
1289 __le32 *prod_idx_sh_reg; /* Shadowed producer register. */
1290 dma_addr_t prod_idx_sh_reg_dma;
1291 void __iomem *cnsmr_idx_db_reg; /* PCI doorbell mem area + 0 */
1292 u32 cnsmr_idx; /* current sw idx */
1293 struct ql_net_rsp_iocb *curr_entry; /* next entry on queue */
1294 void __iomem *valid_db_reg; /* PCI doorbell mem area + 0x04 */
1295
1296 /* Large buffer queue elements. */
1297 u32 lbq_len; /* entry count */
1298 u32 lbq_size; /* size in bytes of queue */
1299 u32 lbq_buf_size;
1300 void *lbq_base;
1301 dma_addr_t lbq_base_dma;
1302 void *lbq_base_indirect;
1303 dma_addr_t lbq_base_indirect_dma;
1304 struct page_chunk pg_chunk; /* current page for chunks */
1305 struct bq_desc *lbq; /* array of control blocks */
1306 void __iomem *lbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x18 */
1307 u32 lbq_prod_idx; /* current sw prod idx */
1308 u32 lbq_curr_idx; /* next entry we expect */
1309 u32 lbq_clean_idx; /* beginning of new descs */
1310 u32 lbq_free_cnt; /* free buffer desc cnt */
1311
1312 /* Small buffer queue elements. */
1313 u32 sbq_len; /* entry count */
1314 u32 sbq_size; /* size in bytes of queue */
1315 u32 sbq_buf_size;
1316 void *sbq_base;
1317 dma_addr_t sbq_base_dma;
1318 void *sbq_base_indirect;
1319 dma_addr_t sbq_base_indirect_dma;
1320 struct bq_desc *sbq; /* array of control blocks */
1321 void __iomem *sbq_prod_idx_db_reg; /* PCI doorbell mem area + 0x1c */
1322 u32 sbq_prod_idx; /* current sw prod idx */
1323 u32 sbq_curr_idx; /* next entry we expect */
1324 u32 sbq_clean_idx; /* beginning of new descs */
1325 u32 sbq_free_cnt; /* free buffer desc cnt */
1326
1327 /* Misc. handler elements. */
1328 u32 type; /* Type of queue, tx, rx. */
1329 u32 irq; /* Which vector this ring is assigned. */
1330 u32 cpu; /* Which CPU this should run on. */
1331 char name[IFNAMSIZ + 5];
1332 struct napi_struct napi;
1333 u8 reserved;
1334 struct ql_adapter *qdev;
1335 u64 rx_packets;
1336 u64 rx_multicast;
1337 u64 rx_bytes;
1338 u64 rx_dropped;
1339 u64 rx_errors;
1340 };
1341
1342 /*
1343 * RSS Initialization Control Block
1344 */
1345 struct hash_id {
1346 u8 value[4];
1347 };
1348
1349 struct nic_stats {
1350 /*
1351 * These stats come from offset 200h to 278h
1352 * in the XGMAC register.
1353 */
1354 u64 tx_pkts;
1355 u64 tx_bytes;
1356 u64 tx_mcast_pkts;
1357 u64 tx_bcast_pkts;
1358 u64 tx_ucast_pkts;
1359 u64 tx_ctl_pkts;
1360 u64 tx_pause_pkts;
1361 u64 tx_64_pkt;
1362 u64 tx_65_to_127_pkt;
1363 u64 tx_128_to_255_pkt;
1364 u64 tx_256_511_pkt;
1365 u64 tx_512_to_1023_pkt;
1366 u64 tx_1024_to_1518_pkt;
1367 u64 tx_1519_to_max_pkt;
1368 u64 tx_undersize_pkt;
1369 u64 tx_oversize_pkt;
1370
1371 /*
1372 * These stats come from offset 300h to 3C8h
1373 * in the XGMAC register.
1374 */
1375 u64 rx_bytes;
1376 u64 rx_bytes_ok;
1377 u64 rx_pkts;
1378 u64 rx_pkts_ok;
1379 u64 rx_bcast_pkts;
1380 u64 rx_mcast_pkts;
1381 u64 rx_ucast_pkts;
1382 u64 rx_undersize_pkts;
1383 u64 rx_oversize_pkts;
1384 u64 rx_jabber_pkts;
1385 u64 rx_undersize_fcerr_pkts;
1386 u64 rx_drop_events;
1387 u64 rx_fcerr_pkts;
1388 u64 rx_align_err;
1389 u64 rx_symbol_err;
1390 u64 rx_mac_err;
1391 u64 rx_ctl_pkts;
1392 u64 rx_pause_pkts;
1393 u64 rx_64_pkts;
1394 u64 rx_65_to_127_pkts;
1395 u64 rx_128_255_pkts;
1396 u64 rx_256_511_pkts;
1397 u64 rx_512_to_1023_pkts;
1398 u64 rx_1024_to_1518_pkts;
1399 u64 rx_1519_to_max_pkts;
1400 u64 rx_len_err_pkts;
1401 /*
1402 * These stats come from offset 500h to 5C8h
1403 * in the XGMAC register.
1404 */
1405 u64 tx_cbfc_pause_frames0;
1406 u64 tx_cbfc_pause_frames1;
1407 u64 tx_cbfc_pause_frames2;
1408 u64 tx_cbfc_pause_frames3;
1409 u64 tx_cbfc_pause_frames4;
1410 u64 tx_cbfc_pause_frames5;
1411 u64 tx_cbfc_pause_frames6;
1412 u64 tx_cbfc_pause_frames7;
1413 u64 rx_cbfc_pause_frames0;
1414 u64 rx_cbfc_pause_frames1;
1415 u64 rx_cbfc_pause_frames2;
1416 u64 rx_cbfc_pause_frames3;
1417 u64 rx_cbfc_pause_frames4;
1418 u64 rx_cbfc_pause_frames5;
1419 u64 rx_cbfc_pause_frames6;
1420 u64 rx_cbfc_pause_frames7;
1421 u64 rx_nic_fifo_drop;
1422 };
1423
1424 /* Address/Length pairs for the coredump. */
1425 enum {
1426 MPI_CORE_REGS_ADDR = 0x00030000,
1427 MPI_CORE_REGS_CNT = 127,
1428 MPI_CORE_SH_REGS_CNT = 16,
1429 TEST_REGS_ADDR = 0x00001000,
1430 TEST_REGS_CNT = 23,
1431 RMII_REGS_ADDR = 0x00001040,
1432 RMII_REGS_CNT = 64,
1433 FCMAC1_REGS_ADDR = 0x00001080,
1434 FCMAC2_REGS_ADDR = 0x000010c0,
1435 FCMAC_REGS_CNT = 64,
1436 FC1_MBX_REGS_ADDR = 0x00001100,
1437 FC2_MBX_REGS_ADDR = 0x00001240,
1438 FC_MBX_REGS_CNT = 64,
1439 IDE_REGS_ADDR = 0x00001140,
1440 IDE_REGS_CNT = 64,
1441 NIC1_MBX_REGS_ADDR = 0x00001180,
1442 NIC2_MBX_REGS_ADDR = 0x00001280,
1443 NIC_MBX_REGS_CNT = 64,
1444 SMBUS_REGS_ADDR = 0x00001200,
1445 SMBUS_REGS_CNT = 64,
1446 I2C_REGS_ADDR = 0x00001fc0,
1447 I2C_REGS_CNT = 64,
1448 MEMC_REGS_ADDR = 0x00003000,
1449 MEMC_REGS_CNT = 256,
1450 PBUS_REGS_ADDR = 0x00007c00,
1451 PBUS_REGS_CNT = 256,
1452 MDE_REGS_ADDR = 0x00010000,
1453 MDE_REGS_CNT = 6,
1454 CODE_RAM_ADDR = 0x00020000,
1455 CODE_RAM_CNT = 0x2000,
1456 MEMC_RAM_ADDR = 0x00100000,
1457 MEMC_RAM_CNT = 0x2000,
1458 };
1459
1460 #define MPI_COREDUMP_COOKIE 0x5555aaaa
1461 struct mpi_coredump_global_header {
1462 u32 cookie;
1463 u8 idString[16];
1464 u32 timeLo;
1465 u32 timeHi;
1466 u32 imageSize;
1467 u32 headerSize;
1468 u8 info[220];
1469 };
1470
1471 struct mpi_coredump_segment_header {
1472 u32 cookie;
1473 u32 segNum;
1474 u32 segSize;
1475 u32 extra;
1476 u8 description[16];
1477 };
1478
1479 /* Reg dump segment numbers. */
1480 enum {
1481 CORE_SEG_NUM = 1,
1482 TEST_LOGIC_SEG_NUM = 2,
1483 RMII_SEG_NUM = 3,
1484 FCMAC1_SEG_NUM = 4,
1485 FCMAC2_SEG_NUM = 5,
1486 FC1_MBOX_SEG_NUM = 6,
1487 IDE_SEG_NUM = 7,
1488 NIC1_MBOX_SEG_NUM = 8,
1489 SMBUS_SEG_NUM = 9,
1490 FC2_MBOX_SEG_NUM = 10,
1491 NIC2_MBOX_SEG_NUM = 11,
1492 I2C_SEG_NUM = 12,
1493 MEMC_SEG_NUM = 13,
1494 PBUS_SEG_NUM = 14,
1495 MDE_SEG_NUM = 15,
1496 NIC1_CONTROL_SEG_NUM = 16,
1497 NIC2_CONTROL_SEG_NUM = 17,
1498 NIC1_XGMAC_SEG_NUM = 18,
1499 NIC2_XGMAC_SEG_NUM = 19,
1500 WCS_RAM_SEG_NUM = 20,
1501 MEMC_RAM_SEG_NUM = 21,
1502 XAUI_AN_SEG_NUM = 22,
1503 XAUI_HSS_PCS_SEG_NUM = 23,
1504 XFI_AN_SEG_NUM = 24,
1505 XFI_TRAIN_SEG_NUM = 25,
1506 XFI_HSS_PCS_SEG_NUM = 26,
1507 XFI_HSS_TX_SEG_NUM = 27,
1508 XFI_HSS_RX_SEG_NUM = 28,
1509 XFI_HSS_PLL_SEG_NUM = 29,
1510 MISC_NIC_INFO_SEG_NUM = 30,
1511 INTR_STATES_SEG_NUM = 31,
1512 CAM_ENTRIES_SEG_NUM = 32,
1513 ROUTING_WORDS_SEG_NUM = 33,
1514 ETS_SEG_NUM = 34,
1515 PROBE_DUMP_SEG_NUM = 35,
1516 ROUTING_INDEX_SEG_NUM = 36,
1517 MAC_PROTOCOL_SEG_NUM = 37,
1518 XAUI2_AN_SEG_NUM = 38,
1519 XAUI2_HSS_PCS_SEG_NUM = 39,
1520 XFI2_AN_SEG_NUM = 40,
1521 XFI2_TRAIN_SEG_NUM = 41,
1522 XFI2_HSS_PCS_SEG_NUM = 42,
1523 XFI2_HSS_TX_SEG_NUM = 43,
1524 XFI2_HSS_RX_SEG_NUM = 44,
1525 XFI2_HSS_PLL_SEG_NUM = 45,
1526 SEM_REGS_SEG_NUM = 50
1527
1528 };
1529
1530 struct ql_nic_misc {
1531 u32 rx_ring_count;
1532 u32 tx_ring_count;
1533 u32 intr_count;
1534 u32 function;
1535 };
1536
1537 struct ql_reg_dump {
1538
1539 /* segment 0 */
1540 struct mpi_coredump_global_header mpi_global_header;
1541
1542 /* segment 16 */
1543 struct mpi_coredump_segment_header nic_regs_seg_hdr;
1544 u32 nic_regs[64];
1545
1546 /* segment 30 */
1547 struct mpi_coredump_segment_header misc_nic_seg_hdr;
1548 struct ql_nic_misc misc_nic_info;
1549
1550 /* segment 31 */
1551 /* one interrupt state for each CQ */
1552 struct mpi_coredump_segment_header intr_states_seg_hdr;
1553 u32 intr_states[MAX_CPUS];
1554
1555 /* segment 32 */
1556 /* 3 cam words each for 16 unicast,
1557 * 2 cam words for each of 32 multicast.
1558 */
1559 struct mpi_coredump_segment_header cam_entries_seg_hdr;
1560 u32 cam_entries[(16 * 3) + (32 * 3)];
1561
1562 /* segment 33 */
1563 struct mpi_coredump_segment_header nic_routing_words_seg_hdr;
1564 u32 nic_routing_words[16];
1565
1566 /* segment 34 */
1567 struct mpi_coredump_segment_header ets_seg_hdr;
1568 u32 ets[8+2];
1569 };
1570
1571 /*
1572 * intr_context structure is used during initialization
1573 * to hook the interrupts. It is also used in a single
1574 * irq environment as a context to the ISR.
1575 */
1576 struct intr_context {
1577 struct ql_adapter *qdev;
1578 u32 intr;
1579 u32 irq_mask; /* Mask of which rings the vector services. */
1580 u32 hooked;
1581 u32 intr_en_mask; /* value/mask used to enable this intr */
1582 u32 intr_dis_mask; /* value/mask used to disable this intr */
1583 u32 intr_read_mask; /* value/mask used to read this intr */
1584 char name[IFNAMSIZ * 2];
1585 atomic_t irq_cnt; /* irq_cnt is used in single vector
1586 * environment. It's incremented for each
1587 * irq handler that is scheduled. When each
1588 * handler finishes it decrements irq_cnt and
1589 * enables interrupts if it's zero. */
1590 irq_handler_t handler;
1591 };
1592
1593 /* adapter flags definitions. */
1594 enum {
1595 QL_ADAPTER_UP = 0, /* Adapter has been brought up. */
1596 QL_LEGACY_ENABLED = 1,
1597 QL_MSI_ENABLED = 2,
1598 QL_MSIX_ENABLED = 3,
1599 QL_DMA64 = 4,
1600 QL_PROMISCUOUS = 5,
1601 QL_ALLMULTI = 6,
1602 QL_PORT_CFG = 7,
1603 QL_CAM_RT_SET = 8,
1604 QL_SELFTEST = 9,
1605 QL_LB_LINK_UP = 10,
1606 };
1607
1608 /* link_status bit definitions */
1609 enum {
1610 STS_LOOPBACK_MASK = 0x00000700,
1611 STS_LOOPBACK_PCS = 0x00000100,
1612 STS_LOOPBACK_HSS = 0x00000200,
1613 STS_LOOPBACK_EXT = 0x00000300,
1614 STS_PAUSE_MASK = 0x000000c0,
1615 STS_PAUSE_STD = 0x00000040,
1616 STS_PAUSE_PRI = 0x00000080,
1617 STS_SPEED_MASK = 0x00000038,
1618 STS_SPEED_100Mb = 0x00000000,
1619 STS_SPEED_1Gb = 0x00000008,
1620 STS_SPEED_10Gb = 0x00000010,
1621 STS_LINK_TYPE_MASK = 0x00000007,
1622 STS_LINK_TYPE_XFI = 0x00000001,
1623 STS_LINK_TYPE_XAUI = 0x00000002,
1624 STS_LINK_TYPE_XFI_BP = 0x00000003,
1625 STS_LINK_TYPE_XAUI_BP = 0x00000004,
1626 STS_LINK_TYPE_10GBASET = 0x00000005,
1627 };
1628
1629 /* link_config bit definitions */
1630 enum {
1631 CFG_JUMBO_FRAME_SIZE = 0x00010000,
1632 CFG_PAUSE_MASK = 0x00000060,
1633 CFG_PAUSE_STD = 0x00000020,
1634 CFG_PAUSE_PRI = 0x00000040,
1635 CFG_DCBX = 0x00000010,
1636 CFG_LOOPBACK_MASK = 0x00000007,
1637 CFG_LOOPBACK_PCS = 0x00000002,
1638 CFG_LOOPBACK_HSS = 0x00000004,
1639 CFG_LOOPBACK_EXT = 0x00000006,
1640 CFG_DEFAULT_MAX_FRAME_SIZE = 0x00002580,
1641 };
1642
1643 struct nic_operations {
1644
1645 int (*get_flash) (struct ql_adapter *);
1646 int (*port_initialize) (struct ql_adapter *);
1647 };
1648
1649 /*
1650 * The main Adapter structure definition.
1651 * This structure has all fields relevant to the hardware.
1652 */
1653 struct ql_adapter {
1654 struct ricb ricb;
1655 unsigned long flags;
1656 u32 wol;
1657
1658 struct nic_stats nic_stats;
1659
1660 struct vlan_group *vlgrp;
1661
1662 /* PCI Configuration information for this device */
1663 struct pci_dev *pdev;
1664 struct net_device *ndev; /* Parent NET device */
1665
1666 /* Hardware information */
1667 u32 chip_rev_id;
1668 u32 fw_rev_id;
1669 u32 func; /* PCI function for this adapter */
1670 u32 alt_func; /* PCI function for alternate adapter */
1671 u32 port; /* Port number this adapter */
1672
1673 spinlock_t adapter_lock;
1674 spinlock_t hw_lock;
1675 spinlock_t stats_lock;
1676
1677 /* PCI Bus Relative Register Addresses */
1678 void __iomem *reg_base;
1679 void __iomem *doorbell_area;
1680 u32 doorbell_area_size;
1681
1682 u32 msg_enable;
1683
1684 /* Page for Shadow Registers */
1685 void *rx_ring_shadow_reg_area;
1686 dma_addr_t rx_ring_shadow_reg_dma;
1687 void *tx_ring_shadow_reg_area;
1688 dma_addr_t tx_ring_shadow_reg_dma;
1689
1690 u32 mailbox_in;
1691 u32 mailbox_out;
1692 struct mbox_params idc_mbc;
1693
1694 int tx_ring_size;
1695 int rx_ring_size;
1696 u32 intr_count;
1697 struct msix_entry *msi_x_entry;
1698 struct intr_context intr_context[MAX_RX_RINGS];
1699
1700 int tx_ring_count; /* One per online CPU. */
1701 u32 rss_ring_count; /* One per irq vector. */
1702 /*
1703 * rx_ring_count =
1704 * (CPU count * outbound completion rx_ring) +
1705 * (irq_vector_cnt * inbound (RSS) completion rx_ring)
1706 */
1707 int rx_ring_count;
1708 int ring_mem_size;
1709 void *ring_mem;
1710
1711 struct rx_ring rx_ring[MAX_RX_RINGS];
1712 struct tx_ring tx_ring[MAX_TX_RINGS];
1713 unsigned int lbq_buf_order;
1714
1715 int rx_csum;
1716 u32 default_rx_queue;
1717
1718 u16 rx_coalesce_usecs; /* cqicb->int_delay */
1719 u16 rx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1720 u16 tx_coalesce_usecs; /* cqicb->int_delay */
1721 u16 tx_max_coalesced_frames; /* cqicb->pkt_int_delay */
1722
1723 u32 xg_sem_mask;
1724 u32 port_link_up;
1725 u32 port_init;
1726 u32 link_status;
1727 u32 link_config;
1728 u32 led_config;
1729 u32 max_frame_size;
1730
1731 union flash_params flash;
1732
1733 struct workqueue_struct *workqueue;
1734 struct delayed_work asic_reset_work;
1735 struct delayed_work mpi_reset_work;
1736 struct delayed_work mpi_work;
1737 struct delayed_work mpi_port_cfg_work;
1738 struct delayed_work mpi_idc_work;
1739 struct completion ide_completion;
1740 struct nic_operations *nic_ops;
1741 u16 device_id;
1742 atomic_t lb_count;
1743 };
1744
1745 /*
1746 * Typical Register accessor for memory mapped device.
1747 */
1748 static inline u32 ql_read32(const struct ql_adapter *qdev, int reg)
1749 {
1750 return readl(qdev->reg_base + reg);
1751 }
1752
1753 /*
1754 * Typical Register accessor for memory mapped device.
1755 */
1756 static inline void ql_write32(const struct ql_adapter *qdev, int reg, u32 val)
1757 {
1758 writel(val, qdev->reg_base + reg);
1759 }
1760
1761 /*
1762 * Doorbell Registers:
1763 * Doorbell registers are virtual registers in the PCI memory space.
1764 * The space is allocated by the chip during PCI initialization. The
1765 * device driver finds the doorbell address in BAR 3 in PCI config space.
1766 * The registers are used to control outbound and inbound queues. For
1767 * example, the producer index for an outbound queue. Each queue uses
1768 * 1 4k chunk of memory. The lower half of the space is for outbound
1769 * queues. The upper half is for inbound queues.
1770 */
1771 static inline void ql_write_db_reg(u32 val, void __iomem *addr)
1772 {
1773 writel(val, addr);
1774 mmiowb();
1775 }
1776
1777 /*
1778 * Shadow Registers:
1779 * Outbound queues have a consumer index that is maintained by the chip.
1780 * Inbound queues have a producer index that is maintained by the chip.
1781 * For lower overhead, these registers are "shadowed" to host memory
1782 * which allows the device driver to track the queue progress without
1783 * PCI reads. When an entry is placed on an inbound queue, the chip will
1784 * update the relevant index register and then copy the value to the
1785 * shadow register in host memory.
1786 */
1787 static inline u32 ql_read_sh_reg(__le32 *addr)
1788 {
1789 u32 reg;
1790 reg = le32_to_cpu(*addr);
1791 rmb();
1792 return reg;
1793 }
1794
1795 extern char qlge_driver_name[];
1796 extern const char qlge_driver_version[];
1797 extern const struct ethtool_ops qlge_ethtool_ops;
1798
1799 extern int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask);
1800 extern void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask);
1801 extern int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1802 extern int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
1803 u32 *value);
1804 extern int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value);
1805 extern int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
1806 u16 q_id);
1807 void ql_queue_fw_error(struct ql_adapter *qdev);
1808 void ql_mpi_work(struct work_struct *work);
1809 void ql_mpi_reset_work(struct work_struct *work);
1810 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 ebit);
1811 void ql_queue_asic_error(struct ql_adapter *qdev);
1812 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr);
1813 void ql_set_ethtool_ops(struct net_device *ndev);
1814 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data);
1815 void ql_mpi_idc_work(struct work_struct *work);
1816 void ql_mpi_port_cfg_work(struct work_struct *work);
1817 int ql_mb_get_fw_state(struct ql_adapter *qdev);
1818 int ql_cam_route_initialize(struct ql_adapter *qdev);
1819 int ql_read_mpi_reg(struct ql_adapter *qdev, u32 reg, u32 *data);
1820 int ql_mb_about_fw(struct ql_adapter *qdev);
1821 int ql_wol(struct ql_adapter *qdev);
1822 int ql_mb_wol_set_magic(struct ql_adapter *qdev, u32 enable_wol);
1823 int ql_mb_wol_mode(struct ql_adapter *qdev, u32 wol);
1824 int ql_mb_set_led_cfg(struct ql_adapter *qdev, u32 led_config);
1825 int ql_mb_get_led_cfg(struct ql_adapter *qdev);
1826 void ql_link_on(struct ql_adapter *qdev);
1827 void ql_link_off(struct ql_adapter *qdev);
1828 int ql_mb_set_mgmnt_traffic_ctl(struct ql_adapter *qdev, u32 control);
1829 int ql_mb_get_port_cfg(struct ql_adapter *qdev);
1830 int ql_mb_set_port_cfg(struct ql_adapter *qdev);
1831 int ql_wait_fifo_empty(struct ql_adapter *qdev);
1832 void ql_gen_reg_dump(struct ql_adapter *qdev,
1833 struct ql_reg_dump *mpi_coredump);
1834 netdev_tx_t ql_lb_send(struct sk_buff *skb, struct net_device *ndev);
1835 void ql_check_lb_frame(struct ql_adapter *, struct sk_buff *);
1836 int ql_clean_lb_rx_ring(struct rx_ring *rx_ring, int budget);
1837
1838 #if 1
1839 #define QL_ALL_DUMP
1840 #define QL_REG_DUMP
1841 #define QL_DEV_DUMP
1842 #define QL_CB_DUMP
1843 /* #define QL_IB_DUMP */
1844 /* #define QL_OB_DUMP */
1845 #endif
1846
1847 #ifdef QL_REG_DUMP
1848 extern void ql_dump_xgmac_control_regs(struct ql_adapter *qdev);
1849 extern void ql_dump_routing_entries(struct ql_adapter *qdev);
1850 extern void ql_dump_regs(struct ql_adapter *qdev);
1851 #define QL_DUMP_REGS(qdev) ql_dump_regs(qdev)
1852 #define QL_DUMP_ROUTE(qdev) ql_dump_routing_entries(qdev)
1853 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev) ql_dump_xgmac_control_regs(qdev)
1854 #else
1855 #define QL_DUMP_REGS(qdev)
1856 #define QL_DUMP_ROUTE(qdev)
1857 #define QL_DUMP_XGMAC_CONTROL_REGS(qdev)
1858 #endif
1859
1860 #ifdef QL_STAT_DUMP
1861 extern void ql_dump_stat(struct ql_adapter *qdev);
1862 #define QL_DUMP_STAT(qdev) ql_dump_stat(qdev)
1863 #else
1864 #define QL_DUMP_STAT(qdev)
1865 #endif
1866
1867 #ifdef QL_DEV_DUMP
1868 extern void ql_dump_qdev(struct ql_adapter *qdev);
1869 #define QL_DUMP_QDEV(qdev) ql_dump_qdev(qdev)
1870 #else
1871 #define QL_DUMP_QDEV(qdev)
1872 #endif
1873
1874 #ifdef QL_CB_DUMP
1875 extern void ql_dump_wqicb(struct wqicb *wqicb);
1876 extern void ql_dump_tx_ring(struct tx_ring *tx_ring);
1877 extern void ql_dump_ricb(struct ricb *ricb);
1878 extern void ql_dump_cqicb(struct cqicb *cqicb);
1879 extern void ql_dump_rx_ring(struct rx_ring *rx_ring);
1880 extern void ql_dump_hw_cb(struct ql_adapter *qdev, int size, u32 bit, u16 q_id);
1881 #define QL_DUMP_RICB(ricb) ql_dump_ricb(ricb)
1882 #define QL_DUMP_WQICB(wqicb) ql_dump_wqicb(wqicb)
1883 #define QL_DUMP_TX_RING(tx_ring) ql_dump_tx_ring(tx_ring)
1884 #define QL_DUMP_CQICB(cqicb) ql_dump_cqicb(cqicb)
1885 #define QL_DUMP_RX_RING(rx_ring) ql_dump_rx_ring(rx_ring)
1886 #define QL_DUMP_HW_CB(qdev, size, bit, q_id) \
1887 ql_dump_hw_cb(qdev, size, bit, q_id)
1888 #else
1889 #define QL_DUMP_RICB(ricb)
1890 #define QL_DUMP_WQICB(wqicb)
1891 #define QL_DUMP_TX_RING(tx_ring)
1892 #define QL_DUMP_CQICB(cqicb)
1893 #define QL_DUMP_RX_RING(rx_ring)
1894 #define QL_DUMP_HW_CB(qdev, size, bit, q_id)
1895 #endif
1896
1897 #ifdef QL_OB_DUMP
1898 extern void ql_dump_tx_desc(struct tx_buf_desc *tbd);
1899 extern void ql_dump_ob_mac_iocb(struct ob_mac_iocb_req *ob_mac_iocb);
1900 extern void ql_dump_ob_mac_rsp(struct ob_mac_iocb_rsp *ob_mac_rsp);
1901 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb) ql_dump_ob_mac_iocb(ob_mac_iocb)
1902 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp) ql_dump_ob_mac_rsp(ob_mac_rsp)
1903 #else
1904 #define QL_DUMP_OB_MAC_IOCB(ob_mac_iocb)
1905 #define QL_DUMP_OB_MAC_RSP(ob_mac_rsp)
1906 #endif
1907
1908 #ifdef QL_IB_DUMP
1909 extern void ql_dump_ib_mac_rsp(struct ib_mac_iocb_rsp *ib_mac_rsp);
1910 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp) ql_dump_ib_mac_rsp(ib_mac_rsp)
1911 #else
1912 #define QL_DUMP_IB_MAC_RSP(ib_mac_rsp)
1913 #endif
1914
1915 #ifdef QL_ALL_DUMP
1916 extern void ql_dump_all(struct ql_adapter *qdev);
1917 #define QL_DUMP_ALL(qdev) ql_dump_all(qdev)
1918 #else
1919 #define QL_DUMP_ALL(qdev)
1920 #endif
1921
1922 #endif /* _QLGE_H_ */
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