2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
12 #include <linux/kernel.h>
13 #include <linux/delay.h>
14 #include <linux/init.h>
15 #include <linux/pci.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <asm/dma.h> /* isa_dma_bridge_buggy */
23 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
24 * @bus: pointer to PCI bus structure to search
26 * Given a PCI bus, returns the highest PCI bus number present in the set
27 * including the given PCI bus and its list of child PCI buses.
29 unsigned char __devinit
30 pci_bus_max_busnr(struct pci_bus
* bus
)
32 struct list_head
*tmp
;
36 list_for_each(tmp
, &bus
->children
) {
37 n
= pci_bus_max_busnr(pci_bus_b(tmp
));
45 * pci_max_busnr - returns maximum PCI bus number
47 * Returns the highest PCI bus number present in the system global list of
50 unsigned char __devinit
53 struct pci_bus
*bus
= NULL
;
57 while ((bus
= pci_find_next_bus(bus
)) != NULL
) {
58 n
= pci_bus_max_busnr(bus
);
65 static int __pci_bus_find_cap(struct pci_bus
*bus
, unsigned int devfn
, u8 hdr_type
, int cap
)
71 pci_bus_read_config_word(bus
, devfn
, PCI_STATUS
, &status
);
72 if (!(status
& PCI_STATUS_CAP_LIST
))
76 case PCI_HEADER_TYPE_NORMAL
:
77 case PCI_HEADER_TYPE_BRIDGE
:
78 pci_bus_read_config_byte(bus
, devfn
, PCI_CAPABILITY_LIST
, &pos
);
80 case PCI_HEADER_TYPE_CARDBUS
:
81 pci_bus_read_config_byte(bus
, devfn
, PCI_CB_CAPABILITY_LIST
, &pos
);
86 while (ttl
-- && pos
>= 0x40) {
88 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_ID
, &id
);
93 pci_bus_read_config_byte(bus
, devfn
, pos
+ PCI_CAP_LIST_NEXT
, &pos
);
99 * pci_find_capability - query for devices' capabilities
100 * @dev: PCI device to query
101 * @cap: capability code
103 * Tell if a device supports a given PCI capability.
104 * Returns the address of the requested capability structure within the
105 * device's PCI configuration space or 0 in case the device does not
106 * support it. Possible values for @cap:
108 * %PCI_CAP_ID_PM Power Management
109 * %PCI_CAP_ID_AGP Accelerated Graphics Port
110 * %PCI_CAP_ID_VPD Vital Product Data
111 * %PCI_CAP_ID_SLOTID Slot Identification
112 * %PCI_CAP_ID_MSI Message Signalled Interrupts
113 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
114 * %PCI_CAP_ID_PCIX PCI-X
115 * %PCI_CAP_ID_EXP PCI Express
117 int pci_find_capability(struct pci_dev
*dev
, int cap
)
119 return __pci_bus_find_cap(dev
->bus
, dev
->devfn
, dev
->hdr_type
, cap
);
123 * pci_bus_find_capability - query for devices' capabilities
124 * @bus: the PCI bus to query
125 * @devfn: PCI device to query
126 * @cap: capability code
128 * Like pci_find_capability() but works for pci devices that do not have a
129 * pci_dev structure set up yet.
131 * Returns the address of the requested capability structure within the
132 * device's PCI configuration space or 0 in case the device does not
135 int pci_bus_find_capability(struct pci_bus
*bus
, unsigned int devfn
, int cap
)
139 pci_bus_read_config_byte(bus
, devfn
, PCI_HEADER_TYPE
, &hdr_type
);
141 return __pci_bus_find_cap(bus
, devfn
, hdr_type
& 0x7f, cap
);
145 * pci_find_ext_capability - Find an extended capability
146 * @dev: PCI device to query
147 * @cap: capability code
149 * Returns the address of the requested extended capability structure
150 * within the device's PCI configuration space or 0 if the device does
151 * not support it. Possible values for @cap:
153 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
154 * %PCI_EXT_CAP_ID_VC Virtual Channel
155 * %PCI_EXT_CAP_ID_DSN Device Serial Number
156 * %PCI_EXT_CAP_ID_PWR Power Budgeting
158 int pci_find_ext_capability(struct pci_dev
*dev
, int cap
)
161 int ttl
= 480; /* 3840 bytes, minimum 8 bytes per capability */
164 if (dev
->cfg_size
<= 256)
167 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
171 * If we have no capabilities, this is indicated by cap ID,
172 * cap version and next pointer all being 0.
178 if (PCI_EXT_CAP_ID(header
) == cap
)
181 pos
= PCI_EXT_CAP_NEXT(header
);
185 if (pci_read_config_dword(dev
, pos
, &header
) != PCIBIOS_SUCCESSFUL
)
193 * pci_find_parent_resource - return resource region of parent bus of given region
194 * @dev: PCI device structure contains resources to be searched
195 * @res: child resource record for which parent is sought
197 * For given resource region of given device, return the resource
198 * region of parent bus the given region is contained in or where
199 * it should be allocated from.
202 pci_find_parent_resource(const struct pci_dev
*dev
, struct resource
*res
)
204 const struct pci_bus
*bus
= dev
->bus
;
206 struct resource
*best
= NULL
;
208 for(i
= 0; i
< PCI_BUS_NUM_RESOURCES
; i
++) {
209 struct resource
*r
= bus
->resource
[i
];
212 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
213 continue; /* Not contained */
214 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
215 continue; /* Wrong type */
216 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
217 return r
; /* Exact match */
218 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
219 best
= r
; /* Approximating prefetchable by non-prefetchable */
225 * pci_restore_bars - restore a devices BAR values (e.g. after wake-up)
226 * @dev: PCI device to have its BARs restored
228 * Restore the BAR values for a given device, so as to make it
229 * accessible by its driver.
232 pci_restore_bars(struct pci_dev
*dev
)
236 switch (dev
->hdr_type
) {
237 case PCI_HEADER_TYPE_NORMAL
:
240 case PCI_HEADER_TYPE_BRIDGE
:
243 case PCI_HEADER_TYPE_CARDBUS
:
247 /* Should never get here, but just in case... */
251 for (i
= 0; i
< numres
; i
++)
252 pci_update_resource(dev
, &dev
->resource
[i
], i
);
256 * pci_set_power_state - Set the power state of a PCI device
257 * @dev: PCI device to be suspended
258 * @state: PCI power state (D0, D1, D2, D3hot, D3cold) we're entering
260 * Transition a device to a new power state, using the Power Management
261 * Capabilities in the device's config space.
264 * -EINVAL if trying to enter a lower state than we're already in.
265 * 0 if we're already in the requested state.
266 * -EIO if device does not support PCI PM.
267 * 0 if we can successfully change the power state.
269 int (*platform_pci_set_power_state
)(struct pci_dev
*dev
, pci_power_t t
);
271 pci_set_power_state(struct pci_dev
*dev
, pci_power_t state
)
273 int pm
, need_restore
= 0;
276 /* bound the state we're entering */
277 if (state
> PCI_D3hot
)
280 /* Validate current state:
281 * Can enter D0 from any state, but if we can only go deeper
282 * to sleep if we're already in a low power state
284 if (state
!= PCI_D0
&& dev
->current_state
> state
)
286 else if (dev
->current_state
== state
)
287 return 0; /* we're already there */
289 /* find PCI PM capability in list */
290 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
292 /* abort if the device doesn't support PM capabilities */
296 pci_read_config_word(dev
,pm
+ PCI_PM_PMC
,&pmc
);
297 if ((pmc
& PCI_PM_CAP_VER_MASK
) > 2) {
299 "PCI: %s has unsupported PM cap regs version (%u)\n",
300 pci_name(dev
), pmc
& PCI_PM_CAP_VER_MASK
);
304 /* check if this device supports the desired state */
305 if (state
== PCI_D1
|| state
== PCI_D2
) {
306 if (state
== PCI_D1
&& !(pmc
& PCI_PM_CAP_D1
))
308 else if (state
== PCI_D2
&& !(pmc
& PCI_PM_CAP_D2
))
312 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &pmcsr
);
314 /* If we're in D3, force entire word to 0.
315 * This doesn't affect PME_Status, disables PME_En, and
316 * sets PowerState to 0.
318 if (dev
->current_state
>= PCI_D3hot
) {
319 if (!(pmcsr
& PCI_PM_CTRL_NO_SOFT_RESET
))
323 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
327 /* enter specified state */
328 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, pmcsr
);
330 /* Mandatory power management transition delays */
331 /* see PCI PM 1.1 5.6.1 table 18 */
332 if (state
== PCI_D3hot
|| dev
->current_state
== PCI_D3hot
)
334 else if (state
== PCI_D2
|| dev
->current_state
== PCI_D2
)
338 * Give firmware a chance to be called, such as ACPI _PRx, _PSx
339 * Firmware method after natice method ?
341 if (platform_pci_set_power_state
)
342 platform_pci_set_power_state(dev
, state
);
344 dev
->current_state
= state
;
346 /* According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
347 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
348 * from D3hot to D0 _may_ perform an internal reset, thereby
349 * going to "D0 Uninitialized" rather than "D0 Initialized".
350 * For example, at least some versions of the 3c905B and the
351 * 3c556B exhibit this behaviour.
353 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
354 * devices in a D3hot state at boot. Consequently, we need to
355 * restore at least the BARs so that the device will be
356 * accessible to its driver.
359 pci_restore_bars(dev
);
364 int (*platform_pci_choose_state
)(struct pci_dev
*dev
, pm_message_t state
);
367 * pci_choose_state - Choose the power state of a PCI device
368 * @dev: PCI device to be suspended
369 * @state: target sleep state for the whole system. This is the value
370 * that is passed to suspend() function.
372 * Returns PCI power state suitable for given device and given system
376 pci_power_t
pci_choose_state(struct pci_dev
*dev
, pm_message_t state
)
380 if (!pci_find_capability(dev
, PCI_CAP_ID_PM
))
383 if (platform_pci_choose_state
) {
384 ret
= platform_pci_choose_state(dev
, state
);
389 case 0: return PCI_D0
;
390 case 3: return PCI_D3hot
;
392 printk("They asked me for state %d\n", state
);
398 EXPORT_SYMBOL(pci_choose_state
);
401 * pci_save_state - save the PCI configuration space of a device before suspending
402 * @dev: - PCI device that we're dealing with
405 pci_save_state(struct pci_dev
*dev
)
408 /* XXX: 100% dword access ok here? */
409 for (i
= 0; i
< 16; i
++)
410 pci_read_config_dword(dev
, i
* 4,&dev
->saved_config_space
[i
]);
415 * pci_restore_state - Restore the saved state of a PCI device
416 * @dev: - PCI device that we're dealing with
419 pci_restore_state(struct pci_dev
*dev
)
423 for (i
= 0; i
< 16; i
++)
424 pci_write_config_dword(dev
,i
* 4, dev
->saved_config_space
[i
]);
429 * pci_enable_device_bars - Initialize some of a device for use
430 * @dev: PCI device to be initialized
431 * @bars: bitmask of BAR's that must be configured
433 * Initialize device before it's used by a driver. Ask low-level code
434 * to enable selected I/O and memory resources. Wake up the device if it
435 * was suspended. Beware, this function can fail.
439 pci_enable_device_bars(struct pci_dev
*dev
, int bars
)
443 pci_set_power_state(dev
, PCI_D0
);
444 if ((err
= pcibios_enable_device(dev
, bars
)) < 0)
450 * pci_enable_device - Initialize device before it's used by a driver.
451 * @dev: PCI device to be initialized
453 * Initialize device before it's used by a driver. Ask low-level code
454 * to enable I/O and memory. Wake up the device if it was suspended.
455 * Beware, this function can fail.
458 pci_enable_device(struct pci_dev
*dev
)
462 if ((err
= pci_enable_device_bars(dev
, (1 << PCI_NUM_RESOURCES
) - 1)))
464 pci_fixup_device(pci_fixup_enable
, dev
);
470 * pcibios_disable_device - disable arch specific PCI resources for device dev
471 * @dev: the PCI device to disable
473 * Disables architecture specific PCI resources for the device. This
474 * is the default implementation. Architecture implementations can
477 void __attribute__ ((weak
)) pcibios_disable_device (struct pci_dev
*dev
) {}
480 * pci_disable_device - Disable PCI device after use
481 * @dev: PCI device to be disabled
483 * Signal to the system that the PCI device is not in use by the system
484 * anymore. This only involves disabling PCI bus-mastering, if active.
487 pci_disable_device(struct pci_dev
*dev
)
491 pci_read_config_word(dev
, PCI_COMMAND
, &pci_command
);
492 if (pci_command
& PCI_COMMAND_MASTER
) {
493 pci_command
&= ~PCI_COMMAND_MASTER
;
494 pci_write_config_word(dev
, PCI_COMMAND
, pci_command
);
496 dev
->is_busmaster
= 0;
498 pcibios_disable_device(dev
);
503 * pci_enable_wake - enable device to generate PME# when suspended
504 * @dev: - PCI device to operate on
505 * @state: - Current state of device.
506 * @enable: - Flag to enable or disable generation
508 * Set the bits in the device's PM Capabilities to generate PME# when
509 * the system is suspended.
511 * -EIO is returned if device doesn't have PM Capabilities.
512 * -EINVAL is returned if device supports it, but can't generate wake events.
513 * 0 if operation is successful.
516 int pci_enable_wake(struct pci_dev
*dev
, pci_power_t state
, int enable
)
521 /* find PCI PM capability in list */
522 pm
= pci_find_capability(dev
, PCI_CAP_ID_PM
);
524 /* If device doesn't support PM Capabilities, but request is to disable
525 * wake events, it's a nop; otherwise fail */
527 return enable
? -EIO
: 0;
529 /* Check device's ability to generate PME# */
530 pci_read_config_word(dev
,pm
+PCI_PM_PMC
,&value
);
532 value
&= PCI_PM_CAP_PME_MASK
;
533 value
>>= ffs(PCI_PM_CAP_PME_MASK
) - 1; /* First bit of mask */
535 /* Check if it can generate PME# from requested state. */
536 if (!value
|| !(value
& (1 << state
)))
537 return enable
? -EINVAL
: 0;
539 pci_read_config_word(dev
, pm
+ PCI_PM_CTRL
, &value
);
541 /* Clear PME_Status by writing 1 to it and enable PME# */
542 value
|= PCI_PM_CTRL_PME_STATUS
| PCI_PM_CTRL_PME_ENABLE
;
545 value
&= ~PCI_PM_CTRL_PME_ENABLE
;
547 pci_write_config_word(dev
, pm
+ PCI_PM_CTRL
, value
);
553 pci_get_interrupt_pin(struct pci_dev
*dev
, struct pci_dev
**bridge
)
557 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &pin
);
561 while (dev
->bus
->self
) {
562 pin
= (pin
+ PCI_SLOT(dev
->devfn
)) % 4;
563 dev
= dev
->bus
->self
;
570 * pci_release_region - Release a PCI bar
571 * @pdev: PCI device whose resources were previously reserved by pci_request_region
572 * @bar: BAR to release
574 * Releases the PCI I/O and memory resources previously reserved by a
575 * successful call to pci_request_region. Call this function only
576 * after all use of the PCI regions has ceased.
578 void pci_release_region(struct pci_dev
*pdev
, int bar
)
580 if (pci_resource_len(pdev
, bar
) == 0)
582 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
)
583 release_region(pci_resource_start(pdev
, bar
),
584 pci_resource_len(pdev
, bar
));
585 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
)
586 release_mem_region(pci_resource_start(pdev
, bar
),
587 pci_resource_len(pdev
, bar
));
591 * pci_request_region - Reserved PCI I/O and memory resource
592 * @pdev: PCI device whose resources are to be reserved
593 * @bar: BAR to be reserved
594 * @res_name: Name to be associated with resource.
596 * Mark the PCI region associated with PCI device @pdev BR @bar as
597 * being reserved by owner @res_name. Do not access any
598 * address inside the PCI regions unless this call returns
601 * Returns 0 on success, or %EBUSY on error. A warning
602 * message is also printed on failure.
604 int pci_request_region(struct pci_dev
*pdev
, int bar
, char *res_name
)
606 if (pci_resource_len(pdev
, bar
) == 0)
609 if (pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
) {
610 if (!request_region(pci_resource_start(pdev
, bar
),
611 pci_resource_len(pdev
, bar
), res_name
))
614 else if (pci_resource_flags(pdev
, bar
) & IORESOURCE_MEM
) {
615 if (!request_mem_region(pci_resource_start(pdev
, bar
),
616 pci_resource_len(pdev
, bar
), res_name
))
623 printk (KERN_WARNING
"PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n",
624 pci_resource_flags(pdev
, bar
) & IORESOURCE_IO
? "I/O" : "mem",
625 bar
+ 1, /* PCI BAR # */
626 pci_resource_len(pdev
, bar
), pci_resource_start(pdev
, bar
),
633 * pci_release_regions - Release reserved PCI I/O and memory resources
634 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
636 * Releases all PCI I/O and memory resources previously reserved by a
637 * successful call to pci_request_regions. Call this function only
638 * after all use of the PCI regions has ceased.
641 void pci_release_regions(struct pci_dev
*pdev
)
645 for (i
= 0; i
< 6; i
++)
646 pci_release_region(pdev
, i
);
650 * pci_request_regions - Reserved PCI I/O and memory resources
651 * @pdev: PCI device whose resources are to be reserved
652 * @res_name: Name to be associated with resource.
654 * Mark all PCI regions associated with PCI device @pdev as
655 * being reserved by owner @res_name. Do not access any
656 * address inside the PCI regions unless this call returns
659 * Returns 0 on success, or %EBUSY on error. A warning
660 * message is also printed on failure.
662 int pci_request_regions(struct pci_dev
*pdev
, char *res_name
)
666 for (i
= 0; i
< 6; i
++)
667 if(pci_request_region(pdev
, i
, res_name
))
673 pci_release_region(pdev
, i
);
679 * pci_set_master - enables bus-mastering for device dev
680 * @dev: the PCI device to enable
682 * Enables bus-mastering on the device and calls pcibios_set_master()
683 * to do the needed arch specific settings.
686 pci_set_master(struct pci_dev
*dev
)
690 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
691 if (! (cmd
& PCI_COMMAND_MASTER
)) {
692 pr_debug("PCI: Enabling bus mastering for device %s\n", pci_name(dev
));
693 cmd
|= PCI_COMMAND_MASTER
;
694 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
696 dev
->is_busmaster
= 1;
697 pcibios_set_master(dev
);
700 #ifndef HAVE_ARCH_PCI_MWI
701 /* This can be overridden by arch code. */
702 u8 pci_cache_line_size
= L1_CACHE_BYTES
>> 2;
705 * pci_generic_prep_mwi - helper function for pci_set_mwi
706 * @dev: the PCI device for which MWI is enabled
708 * Helper function for generic implementation of pcibios_prep_mwi
709 * function. Originally copied from drivers/net/acenic.c.
710 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
712 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
715 pci_generic_prep_mwi(struct pci_dev
*dev
)
719 if (!pci_cache_line_size
)
720 return -EINVAL
; /* The system doesn't support MWI. */
722 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
723 equal to or multiple of the right value. */
724 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
725 if (cacheline_size
>= pci_cache_line_size
&&
726 (cacheline_size
% pci_cache_line_size
) == 0)
729 /* Write the correct value. */
730 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
732 pci_read_config_byte(dev
, PCI_CACHE_LINE_SIZE
, &cacheline_size
);
733 if (cacheline_size
== pci_cache_line_size
)
736 printk(KERN_DEBUG
"PCI: cache line size of %d is not supported "
737 "by device %s\n", pci_cache_line_size
<< 2, pci_name(dev
));
741 #endif /* !HAVE_ARCH_PCI_MWI */
744 * pci_set_mwi - enables memory-write-invalidate PCI transaction
745 * @dev: the PCI device for which MWI is enabled
747 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND,
748 * and then calls @pcibios_set_mwi to do the needed arch specific
749 * operations or a generic mwi-prep function.
751 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
754 pci_set_mwi(struct pci_dev
*dev
)
759 #ifdef HAVE_ARCH_PCI_MWI
760 rc
= pcibios_prep_mwi(dev
);
762 rc
= pci_generic_prep_mwi(dev
);
768 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
769 if (! (cmd
& PCI_COMMAND_INVALIDATE
)) {
770 pr_debug("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev
));
771 cmd
|= PCI_COMMAND_INVALIDATE
;
772 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
779 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
780 * @dev: the PCI device to disable
782 * Disables PCI Memory-Write-Invalidate transaction on the device
785 pci_clear_mwi(struct pci_dev
*dev
)
789 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
790 if (cmd
& PCI_COMMAND_INVALIDATE
) {
791 cmd
&= ~PCI_COMMAND_INVALIDATE
;
792 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
796 #ifndef HAVE_ARCH_PCI_SET_DMA_MASK
798 * These can be overridden by arch-specific implementations
801 pci_set_dma_mask(struct pci_dev
*dev
, u64 mask
)
803 if (!pci_dma_supported(dev
, mask
))
806 dev
->dma_mask
= mask
;
812 pci_set_consistent_dma_mask(struct pci_dev
*dev
, u64 mask
)
814 if (!pci_dma_supported(dev
, mask
))
817 dev
->dev
.coherent_dma_mask
= mask
;
823 static int __devinit
pci_init(void)
825 struct pci_dev
*dev
= NULL
;
827 while ((dev
= pci_get_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
828 pci_fixup_device(pci_fixup_final
, dev
);
833 static int __devinit
pci_setup(char *str
)
836 char *k
= strchr(str
, ',');
839 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
840 /* PCI layer options should be handled here */
841 printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
848 device_initcall(pci_init
);
850 __setup("pci=", pci_setup
);
852 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
853 /* FIXME: Some boxes have multiple ISA bridges! */
854 struct pci_dev
*isa_bridge
;
855 EXPORT_SYMBOL(isa_bridge
);
858 EXPORT_SYMBOL_GPL(pci_restore_bars
);
859 EXPORT_SYMBOL(pci_enable_device_bars
);
860 EXPORT_SYMBOL(pci_enable_device
);
861 EXPORT_SYMBOL(pci_disable_device
);
862 EXPORT_SYMBOL(pci_max_busnr
);
863 EXPORT_SYMBOL(pci_bus_max_busnr
);
864 EXPORT_SYMBOL(pci_find_capability
);
865 EXPORT_SYMBOL(pci_bus_find_capability
);
866 EXPORT_SYMBOL(pci_release_regions
);
867 EXPORT_SYMBOL(pci_request_regions
);
868 EXPORT_SYMBOL(pci_release_region
);
869 EXPORT_SYMBOL(pci_request_region
);
870 EXPORT_SYMBOL(pci_set_master
);
871 EXPORT_SYMBOL(pci_set_mwi
);
872 EXPORT_SYMBOL(pci_clear_mwi
);
873 EXPORT_SYMBOL(pci_set_dma_mask
);
874 EXPORT_SYMBOL(pci_set_consistent_dma_mask
);
875 EXPORT_SYMBOL(pci_assign_resource
);
876 EXPORT_SYMBOL(pci_find_parent_resource
);
878 EXPORT_SYMBOL(pci_set_power_state
);
879 EXPORT_SYMBOL(pci_save_state
);
880 EXPORT_SYMBOL(pci_restore_state
);
881 EXPORT_SYMBOL(pci_enable_wake
);
885 EXPORT_SYMBOL(isa_dma_bridge_buggy
);
886 EXPORT_SYMBOL(pci_pci_problems
);