?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[Blackfin] arch: fix bug - Move IWR Enable All to the end of init_arch_irq otherwise...
[linux-2.6/linux-2.6-openrd.git] / arch / blackfin / mach-common / ints-priority.c
blobb321c4a92a67fae3fba3ce4d4dbc71535ab7fcaf
1 /*
2 * File: arch/blackfin/mach-common/ints-priority.c
3 * Based on:
4 * Author:
5 *
6 * Created: ?
7 * Description: Set up the interrupt priorities
8 *
9 * Modified:
10 * 1996 Roman Zippel
11 * 1999 D. Jeff Dionne <jeff@uclinux.org>
12 * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
13 * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
14 * 2003 Metrowerks/Motorola
15 * 2003 Bas Vermeulen <bas@buyways.nl>
16 * Copyright 2004-2008 Analog Devices Inc.
17 *
18 * Bugs: Enter bugs at http://blackfin.uclinux.org/
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, see the file COPYING, or write
32 * to the Free Software Foundation, Inc.,
33 * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel_stat.h>
38 #include <linux/seq_file.h>
39 #include <linux/irq.h>
40 #ifdef CONFIG_KGDB
41 #include <linux/kgdb.h>
42 #endif
43 #include <asm/traps.h>
44 #include <asm/blackfin.h>
45 #include <asm/gpio.h>
46 #include <asm/irq_handler.h>
47
48 #ifdef BF537_FAMILY
49 # define BF537_GENERIC_ERROR_INT_DEMUX
50 #else
51 # undef BF537_GENERIC_ERROR_INT_DEMUX
52 #endif
53
54 /*
55 * NOTES:
56 * - we have separated the physical Hardware interrupt from the
57 * levels that the LINUX kernel sees (see the description in irq.h)
58 * -
59 */
60
61 /* Initialize this to an actual value to force it into the .data
62 * section so that we know it is properly initialized at entry into
63 * the kernel but before bss is initialized to zero (which is where
64 * it would live otherwise). The 0x1f magic represents the IRQs we
65 * cannot actually mask out in hardware.
66 */
67 unsigned long irq_flags = 0x1f;
68
69 /* The number of spurious interrupts */
70 atomic_t num_spurious;
71
72 #ifdef CONFIG_PM
73 unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
74 #endif
75
76 struct ivgx {
77 /* irq number for request_irq, available in mach-bf533/irq.h */
78 unsigned int irqno;
79 /* corresponding bit in the SIC_ISR register */
80 unsigned int isrflag;
81 } ivg_table[NR_PERI_INTS];
82
83 struct ivg_slice {
84 /* position of first irq in ivg_table for given ivg */
85 struct ivgx *ifirst;
86 struct ivgx *istop;
87 } ivg7_13[IVG13 - IVG7 + 1];
88
89 static void search_IAR(void);
90
91 /*
92 * Search SIC_IAR and fill tables with the irqvalues
93 * and their positions in the SIC_ISR register.
94 */
95 static void __init search_IAR(void)
96 {
97 unsigned ivg, irq_pos = 0;
98 for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
99 int irqn;
100
101 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
102
103 for (irqn = 0; irqn < NR_PERI_INTS; irqn++) {
104 int iar_shift = (irqn & 7) * 4;
105 if (ivg == (0xf &
106 #ifndef CONFIG_BF52x
107 bfin_read32((unsigned long *)SIC_IAR0 +
108 (irqn >> 3)) >> iar_shift)) {
109 #else
110 bfin_read32((unsigned long *)SIC_IAR0 +
111 ((irqn%32) >> 3) + ((irqn / 32) * 16)) >> iar_shift)) {
112 #endif
113 ivg_table[irq_pos].irqno = IVG7 + irqn;
114 ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
115 ivg7_13[ivg].istop++;
116 irq_pos++;
117 }
118 }
119 }
120 }
121
122 /*
123 * This is for BF533 internal IRQs
124 */
125
126 static void ack_noop(unsigned int irq)
127 {
128 /* Dummy function. */
129 }
130
131 static void bfin_core_mask_irq(unsigned int irq)
132 {
133 irq_flags &= ~(1 << irq);
134 if (!irqs_disabled())
135 local_irq_enable();
136 }
137
138 static void bfin_core_unmask_irq(unsigned int irq)
139 {
140 irq_flags |= 1 << irq;
141 /*
142 * If interrupts are enabled, IMASK must contain the same value
143 * as irq_flags. Make sure that invariant holds. If interrupts
144 * are currently disabled we need not do anything; one of the
145 * callers will take care of setting IMASK to the proper value
146 * when reenabling interrupts.
147 * local_irq_enable just does "STI irq_flags", so it's exactly
148 * what we need.
149 */
150 if (!irqs_disabled())
151 local_irq_enable();
152 return;
153 }
154
155 static void bfin_internal_mask_irq(unsigned int irq)
156 {
157 #ifdef CONFIG_BF53x
158 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
159 ~(1 << (irq - (IRQ_CORETMR + 1))));
160 #else
161 unsigned mask_bank, mask_bit;
162 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
163 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
164 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
165 ~(1 << mask_bit));
166 #endif
167 SSYNC();
168 }
169
170 static void bfin_internal_unmask_irq(unsigned int irq)
171 {
172 #ifdef CONFIG_BF53x
173 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
174 (1 << (irq - (IRQ_CORETMR + 1))));
175 #else
176 unsigned mask_bank, mask_bit;
177 mask_bank = (irq - (IRQ_CORETMR + 1)) / 32;
178 mask_bit = (irq - (IRQ_CORETMR + 1)) % 32;
179 bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) |
180 (1 << mask_bit));
181 #endif
182 SSYNC();
183 }
184
185 #ifdef CONFIG_PM
186 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
187 {
188 unsigned bank, bit;
189 unsigned long flags;
190 bank = (irq - (IRQ_CORETMR + 1)) / 32;
191 bit = (irq - (IRQ_CORETMR + 1)) % 32;
192
193 local_irq_save(flags);
194
195 if (state)
196 bfin_sic_iwr[bank] |= (1 << bit);
197 else
198 bfin_sic_iwr[bank] &= ~(1 << bit);
199
200 local_irq_restore(flags);
201
202 return 0;
203 }
204 #endif
205
206 static struct irq_chip bfin_core_irqchip = {
207 .ack = ack_noop,
208 .mask = bfin_core_mask_irq,
209 .unmask = bfin_core_unmask_irq,
210 };
211
212 static struct irq_chip bfin_internal_irqchip = {
213 .ack = ack_noop,
214 .mask = bfin_internal_mask_irq,
215 .unmask = bfin_internal_unmask_irq,
216 #ifdef CONFIG_PM
217 .set_wake = bfin_internal_set_wake,
218 #endif
219 };
220
221 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
222 static int error_int_mask;
223
224 static void bfin_generic_error_ack_irq(unsigned int irq)
225 {
226
227 }
228
229 static void bfin_generic_error_mask_irq(unsigned int irq)
230 {
231 error_int_mask &= ~(1L << (irq - IRQ_PPI_ERROR));
232
233 if (!error_int_mask) {
234 local_irq_disable();
235 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
236 ~(1 << (IRQ_GENERIC_ERROR -
237 (IRQ_CORETMR + 1))));
238 SSYNC();
239 local_irq_enable();
240 }
241 }
242
243 static void bfin_generic_error_unmask_irq(unsigned int irq)
244 {
245 local_irq_disable();
246 bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | 1 <<
247 (IRQ_GENERIC_ERROR - (IRQ_CORETMR + 1)));
248 SSYNC();
249 local_irq_enable();
250
251 error_int_mask |= 1L << (irq - IRQ_PPI_ERROR);
252 }
253
254 static struct irq_chip bfin_generic_error_irqchip = {
255 .ack = bfin_generic_error_ack_irq,
256 .mask = bfin_generic_error_mask_irq,
257 .unmask = bfin_generic_error_unmask_irq,
258 };
259
260 static void bfin_demux_error_irq(unsigned int int_err_irq,
261 struct irq_desc *inta_desc)
262 {
263 int irq = 0;
264
265 SSYNC();
266
267 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
268 if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
269 irq = IRQ_MAC_ERROR;
270 else
271 #endif
272 if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
273 irq = IRQ_SPORT0_ERROR;
274 else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
275 irq = IRQ_SPORT1_ERROR;
276 else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
277 irq = IRQ_PPI_ERROR;
278 else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
279 irq = IRQ_CAN_ERROR;
280 else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
281 irq = IRQ_SPI_ERROR;
282 else if ((bfin_read_UART0_IIR() & UART_ERR_MASK_STAT1) &&
283 (bfin_read_UART0_IIR() & UART_ERR_MASK_STAT0))
284 irq = IRQ_UART0_ERROR;
285 else if ((bfin_read_UART1_IIR() & UART_ERR_MASK_STAT1) &&
286 (bfin_read_UART1_IIR() & UART_ERR_MASK_STAT0))
287 irq = IRQ_UART1_ERROR;
288
289 if (irq) {
290 if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR))) {
291 struct irq_desc *desc = irq_desc + irq;
292 desc->handle_irq(irq, desc);
293 } else {
294
295 switch (irq) {
296 case IRQ_PPI_ERROR:
297 bfin_write_PPI_STATUS(PPI_ERR_MASK);
298 break;
299 #if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
300 case IRQ_MAC_ERROR:
301 bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
302 break;
303 #endif
304 case IRQ_SPORT0_ERROR:
305 bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
306 break;
307
308 case IRQ_SPORT1_ERROR:
309 bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
310 break;
311
312 case IRQ_CAN_ERROR:
313 bfin_write_CAN_GIS(CAN_ERR_MASK);
314 break;
315
316 case IRQ_SPI_ERROR:
317 bfin_write_SPI_STAT(SPI_ERR_MASK);
318 break;
319
320 default:
321 break;
322 }
323
324 pr_debug("IRQ %d:"
325 " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
326 irq);
327 }
328 } else
329 printk(KERN_ERR
330 "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
331 " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
332 __FUNCTION__, __FILE__, __LINE__);
333
334 }
335 #endif /* BF537_GENERIC_ERROR_INT_DEMUX */
336
337 #if !defined(CONFIG_BF54x)
338
339 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
340 static unsigned short gpio_edge_triggered[gpio_bank(MAX_BLACKFIN_GPIOS)];
341
342
343 static void bfin_gpio_ack_irq(unsigned int irq)
344 {
345 u16 gpionr = irq - IRQ_PF0;
346
347 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
348 set_gpio_data(gpionr, 0);
349 SSYNC();
350 }
351 }
352
353 static void bfin_gpio_mask_ack_irq(unsigned int irq)
354 {
355 u16 gpionr = irq - IRQ_PF0;
356
357 if (gpio_edge_triggered[gpio_bank(gpionr)] & gpio_bit(gpionr)) {
358 set_gpio_data(gpionr, 0);
359 SSYNC();
360 }
361
362 set_gpio_maska(gpionr, 0);
363 SSYNC();
364 }
365
366 static void bfin_gpio_mask_irq(unsigned int irq)
367 {
368 set_gpio_maska(irq - IRQ_PF0, 0);
369 SSYNC();
370 }
371
372 static void bfin_gpio_unmask_irq(unsigned int irq)
373 {
374 set_gpio_maska(irq - IRQ_PF0, 1);
375 SSYNC();
376 }
377
378 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
379 {
380 unsigned int ret;
381 u16 gpionr = irq - IRQ_PF0;
382 char buf[8];
383
384 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
385 snprintf(buf, sizeof buf, "IRQ %d", irq);
386 ret = gpio_request(gpionr, buf);
387 if (ret)
388 return ret;
389 }
390
391 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
392 bfin_gpio_unmask_irq(irq);
393
394 return ret;
395 }
396
397 static void bfin_gpio_irq_shutdown(unsigned int irq)
398 {
399 bfin_gpio_mask_irq(irq);
400 gpio_free(irq - IRQ_PF0);
401 gpio_enabled[gpio_bank(irq - IRQ_PF0)] &= ~gpio_bit(irq - IRQ_PF0);
402 }
403
404 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
405 {
406
407 unsigned int ret;
408 char buf[8];
409 u16 gpionr = irq - IRQ_PF0;
410
411 if (type == IRQ_TYPE_PROBE) {
412 /* only probe unenabled GPIO interrupt lines */
413 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
414 return 0;
415 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
416 }
417
418 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
419 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
420 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
421 snprintf(buf, sizeof buf, "IRQ %d", irq);
422 ret = gpio_request(gpionr, buf);
423 if (ret)
424 return ret;
425 }
426
427 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
428 } else {
429 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
430 return 0;
431 }
432
433 set_gpio_inen(gpionr, 0);
434 set_gpio_dir(gpionr, 0);
435
436 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
437 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
438 set_gpio_both(gpionr, 1);
439 else
440 set_gpio_both(gpionr, 0);
441
442 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
443 set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */
444 else
445 set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */
446
447 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
448 set_gpio_edge(gpionr, 1);
449 set_gpio_inen(gpionr, 1);
450 gpio_edge_triggered[gpio_bank(gpionr)] |= gpio_bit(gpionr);
451 set_gpio_data(gpionr, 0);
452
453 } else {
454 set_gpio_edge(gpionr, 0);
455 gpio_edge_triggered[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
456 set_gpio_inen(gpionr, 1);
457 }
458
459 SSYNC();
460
461 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
462 set_irq_handler(irq, handle_edge_irq);
463 else
464 set_irq_handler(irq, handle_level_irq);
465
466 return 0;
467 }
468
469 #ifdef CONFIG_PM
470 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
471 {
472 unsigned gpio = irq_to_gpio(irq);
473
474 if (state)
475 gpio_pm_wakeup_request(gpio, PM_WAKE_IGNORE);
476 else
477 gpio_pm_wakeup_free(gpio);
478
479 return 0;
480 }
481 #endif
482
483 static struct irq_chip bfin_gpio_irqchip = {
484 .ack = bfin_gpio_ack_irq,
485 .mask = bfin_gpio_mask_irq,
486 .mask_ack = bfin_gpio_mask_ack_irq,
487 .unmask = bfin_gpio_unmask_irq,
488 .set_type = bfin_gpio_irq_type,
489 .startup = bfin_gpio_irq_startup,
490 .shutdown = bfin_gpio_irq_shutdown,
491 #ifdef CONFIG_PM
492 .set_wake = bfin_gpio_set_wake,
493 #endif
494 };
495
496 static void bfin_demux_gpio_irq(unsigned int inta_irq,
497 struct irq_desc *desc)
498 {
499 unsigned int i, gpio, mask, irq, search = 0;
500
501 switch (inta_irq) {
502 #if defined(CONFIG_BF53x)
503 case IRQ_PROG_INTA:
504 irq = IRQ_PF0;
505 search = 1;
506 break;
507 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
508 case IRQ_MAC_RX:
509 irq = IRQ_PH0;
510 break;
511 # endif
512 #elif defined(CONFIG_BF52x)
513 case IRQ_PORTF_INTA:
514 irq = IRQ_PF0;
515 break;
516 case IRQ_PORTG_INTA:
517 irq = IRQ_PG0;
518 break;
519 case IRQ_PORTH_INTA:
520 irq = IRQ_PH0;
521 break;
522 #elif defined(CONFIG_BF561)
523 case IRQ_PROG0_INTA:
524 irq = IRQ_PF0;
525 break;
526 case IRQ_PROG1_INTA:
527 irq = IRQ_PF16;
528 break;
529 case IRQ_PROG2_INTA:
530 irq = IRQ_PF32;
531 break;
532 #endif
533 default:
534 BUG();
535 return;
536 }
537
538 if (search) {
539 for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
540 irq += i;
541
542 mask = get_gpiop_data(i) &
543 (gpio_enabled[gpio_bank(i)] &
544 get_gpiop_maska(i));
545
546 while (mask) {
547 if (mask & 1) {
548 desc = irq_desc + irq;
549 desc->handle_irq(irq, desc);
550 }
551 irq++;
552 mask >>= 1;
553 }
554 }
555 } else {
556 gpio = irq_to_gpio(irq);
557 mask = get_gpiop_data(gpio) &
558 (gpio_enabled[gpio_bank(gpio)] &
559 get_gpiop_maska(gpio));
560
561 do {
562 if (mask & 1) {
563 desc = irq_desc + irq;
564 desc->handle_irq(irq, desc);
565 }
566 irq++;
567 mask >>= 1;
568 } while (mask);
569 }
570
571 }
572
573 #else /* CONFIG_BF54x */
574
575 #define NR_PINT_SYS_IRQS 4
576 #define NR_PINT_BITS 32
577 #define NR_PINTS 160
578 #define IRQ_NOT_AVAIL 0xFF
579
580 #define PINT_2_BANK(x) ((x) >> 5)
581 #define PINT_2_BIT(x) ((x) & 0x1F)
582 #define PINT_BIT(x) (1 << (PINT_2_BIT(x)))
583
584 static unsigned char irq2pint_lut[NR_PINTS];
585 static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS];
586
587 static unsigned int gpio_both_edge_triggered[NR_PINT_SYS_IRQS];
588 static unsigned short gpio_enabled[gpio_bank(MAX_BLACKFIN_GPIOS)];
589
590
591 struct pin_int_t {
592 unsigned int mask_set;
593 unsigned int mask_clear;
594 unsigned int request;
595 unsigned int assign;
596 unsigned int edge_set;
597 unsigned int edge_clear;
598 unsigned int invert_set;
599 unsigned int invert_clear;
600 unsigned int pinstate;
601 unsigned int latch;
602 };
603
604 static struct pin_int_t *pint[NR_PINT_SYS_IRQS] = {
605 (struct pin_int_t *)PINT0_MASK_SET,
606 (struct pin_int_t *)PINT1_MASK_SET,
607 (struct pin_int_t *)PINT2_MASK_SET,
608 (struct pin_int_t *)PINT3_MASK_SET,
609 };
610
611 unsigned short get_irq_base(u8 bank, u8 bmap)
612 {
613
614 u16 irq_base;
615
616 if (bank < 2) { /*PA-PB */
617 irq_base = IRQ_PA0 + bmap * 16;
618 } else { /*PC-PJ */
619 irq_base = IRQ_PC0 + bmap * 16;
620 }
621
622 return irq_base;
623
624 }
625
626 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
627 void init_pint_lut(void)
628 {
629 u16 bank, bit, irq_base, bit_pos;
630 u32 pint_assign;
631 u8 bmap;
632
633 memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut));
634
635 for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
636
637 pint_assign = pint[bank]->assign;
638
639 for (bit = 0; bit < NR_PINT_BITS; bit++) {
640
641 bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF;
642
643 irq_base = get_irq_base(bank, bmap);
644
645 irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0);
646 bit_pos = bit + bank * NR_PINT_BITS;
647
648 pint2irq_lut[bit_pos] = irq_base - SYS_IRQS;
649 irq2pint_lut[irq_base - SYS_IRQS] = bit_pos;
650
651 }
652
653 }
654
655 }
656
657 static void bfin_gpio_ack_irq(unsigned int irq)
658 {
659 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
660 u32 pintbit = PINT_BIT(pint_val);
661 u8 bank = PINT_2_BANK(pint_val);
662
663 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
664 if (pint[bank]->invert_set & pintbit)
665 pint[bank]->invert_clear = pintbit;
666 else
667 pint[bank]->invert_set = pintbit;
668 }
669 pint[bank]->request = pintbit;
670
671 SSYNC();
672 }
673
674 static void bfin_gpio_mask_ack_irq(unsigned int irq)
675 {
676 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
677 u32 pintbit = PINT_BIT(pint_val);
678 u8 bank = PINT_2_BANK(pint_val);
679
680 if (unlikely(gpio_both_edge_triggered[bank] & pintbit)) {
681 if (pint[bank]->invert_set & pintbit)
682 pint[bank]->invert_clear = pintbit;
683 else
684 pint[bank]->invert_set = pintbit;
685 }
686
687 pint[bank]->request = pintbit;
688 pint[bank]->mask_clear = pintbit;
689 SSYNC();
690 }
691
692 static void bfin_gpio_mask_irq(unsigned int irq)
693 {
694 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
695
696 pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val);
697 SSYNC();
698 }
699
700 static void bfin_gpio_unmask_irq(unsigned int irq)
701 {
702 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
703 u32 pintbit = PINT_BIT(pint_val);
704 u8 bank = PINT_2_BANK(pint_val);
705
706 pint[bank]->request = pintbit;
707 pint[bank]->mask_set = pintbit;
708 SSYNC();
709 }
710
711 static unsigned int bfin_gpio_irq_startup(unsigned int irq)
712 {
713 unsigned int ret;
714 char buf[8];
715 u16 gpionr = irq_to_gpio(irq);
716 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
717
718 if (pint_val == IRQ_NOT_AVAIL) {
719 printk(KERN_ERR
720 "GPIO IRQ %d :Not in PINT Assign table "
721 "Reconfigure Interrupt to Port Assignemt\n", irq);
722 return -ENODEV;
723 }
724
725 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
726 snprintf(buf, sizeof buf, "IRQ %d", irq);
727 ret = gpio_request(gpionr, buf);
728 if (ret)
729 return ret;
730 }
731
732 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
733 bfin_gpio_unmask_irq(irq);
734
735 return ret;
736 }
737
738 static void bfin_gpio_irq_shutdown(unsigned int irq)
739 {
740 u16 gpionr = irq_to_gpio(irq);
741
742 bfin_gpio_mask_irq(irq);
743 gpio_free(gpionr);
744 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
745 }
746
747 static int bfin_gpio_irq_type(unsigned int irq, unsigned int type)
748 {
749
750 unsigned int ret;
751 char buf[8];
752 u16 gpionr = irq_to_gpio(irq);
753 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
754 u32 pintbit = PINT_BIT(pint_val);
755 u8 bank = PINT_2_BANK(pint_val);
756
757 if (pint_val == IRQ_NOT_AVAIL)
758 return -ENODEV;
759
760 if (type == IRQ_TYPE_PROBE) {
761 /* only probe unenabled GPIO interrupt lines */
762 if (gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))
763 return 0;
764 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
765 }
766
767 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
768 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
769 if (!(gpio_enabled[gpio_bank(gpionr)] & gpio_bit(gpionr))) {
770 snprintf(buf, sizeof buf, "IRQ %d", irq);
771 ret = gpio_request(gpionr, buf);
772 if (ret)
773 return ret;
774 }
775
776 gpio_enabled[gpio_bank(gpionr)] |= gpio_bit(gpionr);
777 } else {
778 gpio_enabled[gpio_bank(gpionr)] &= ~gpio_bit(gpionr);
779 return 0;
780 }
781
782 gpio_direction_input(gpionr);
783
784 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
785 pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */
786 else
787 pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */
788
789 if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
790 == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
791
792 gpio_both_edge_triggered[bank] |= pintbit;
793
794 if (gpio_get_value(gpionr))
795 pint[bank]->invert_set = pintbit;
796 else
797 pint[bank]->invert_clear = pintbit;
798 } else {
799 gpio_both_edge_triggered[bank] &= ~pintbit;
800 }
801
802 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
803 pint[bank]->edge_set = pintbit;
804 set_irq_handler(irq, handle_edge_irq);
805 } else {
806 pint[bank]->edge_clear = pintbit;
807 set_irq_handler(irq, handle_level_irq);
808 }
809
810 SSYNC();
811
812 return 0;
813 }
814
815 #ifdef CONFIG_PM
816 u32 pint_saved_masks[NR_PINT_SYS_IRQS];
817 u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
818
819 int bfin_gpio_set_wake(unsigned int irq, unsigned int state)
820 {
821 u32 pint_irq;
822 u8 pint_val = irq2pint_lut[irq - SYS_IRQS];
823 u32 bank = PINT_2_BANK(pint_val);
824 u32 pintbit = PINT_BIT(pint_val);
825
826 switch (bank) {
827 case 0:
828 pint_irq = IRQ_PINT0;
829 break;
830 case 2:
831 pint_irq = IRQ_PINT2;
832 break;
833 case 3:
834 pint_irq = IRQ_PINT3;
835 break;
836 case 1:
837 pint_irq = IRQ_PINT1;
838 break;
839 default:
840 return -EINVAL;
841 }
842
843 bfin_internal_set_wake(pint_irq, state);
844
845 if (state)
846 pint_wakeup_masks[bank] |= pintbit;
847 else
848 pint_wakeup_masks[bank] &= ~pintbit;
849
850 return 0;
851 }
852
853 u32 bfin_pm_setup(void)
854 {
855 u32 val, i;
856
857 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
858 val = pint[i]->mask_clear;
859 pint_saved_masks[i] = val;
860 if (val ^ pint_wakeup_masks[i]) {
861 pint[i]->mask_clear = val;
862 pint[i]->mask_set = pint_wakeup_masks[i];
863 }
864 }
865
866 return 0;
867 }
868
869 void bfin_pm_restore(void)
870 {
871 u32 i, val;
872
873 for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
874 val = pint_saved_masks[i];
875 if (val ^ pint_wakeup_masks[i]) {
876 pint[i]->mask_clear = pint[i]->mask_clear;
877 pint[i]->mask_set = val;
878 }
879 }
880 }
881 #endif
882
883 static struct irq_chip bfin_gpio_irqchip = {
884 .ack = bfin_gpio_ack_irq,
885 .mask = bfin_gpio_mask_irq,
886 .mask_ack = bfin_gpio_mask_ack_irq,
887 .unmask = bfin_gpio_unmask_irq,
888 .set_type = bfin_gpio_irq_type,
889 .startup = bfin_gpio_irq_startup,
890 .shutdown = bfin_gpio_irq_shutdown,
891 #ifdef CONFIG_PM
892 .set_wake = bfin_gpio_set_wake,
893 #endif
894 };
895
896 static void bfin_demux_gpio_irq(unsigned int inta_irq,
897 struct irq_desc *desc)
898 {
899 u8 bank, pint_val;
900 u32 request, irq;
901
902 switch (inta_irq) {
903 case IRQ_PINT0:
904 bank = 0;
905 break;
906 case IRQ_PINT2:
907 bank = 2;
908 break;
909 case IRQ_PINT3:
910 bank = 3;
911 break;
912 case IRQ_PINT1:
913 bank = 1;
914 break;
915 default:
916 return;
917 }
918
919 pint_val = bank * NR_PINT_BITS;
920
921 request = pint[bank]->request;
922
923 while (request) {
924 if (request & 1) {
925 irq = pint2irq_lut[pint_val] + SYS_IRQS;
926 desc = irq_desc + irq;
927 desc->handle_irq(irq, desc);
928 }
929 pint_val++;
930 request >>= 1;
931 }
932
933 }
934 #endif
935
936 void __init init_exception_vectors(void)
937 {
938 SSYNC();
939
940 /* cannot program in software:
941 * evt0 - emulation (jtag)
942 * evt1 - reset
943 */
944 bfin_write_EVT2(evt_nmi);
945 bfin_write_EVT3(trap);
946 bfin_write_EVT5(evt_ivhw);
947 bfin_write_EVT6(evt_timer);
948 bfin_write_EVT7(evt_evt7);
949 bfin_write_EVT8(evt_evt8);
950 bfin_write_EVT9(evt_evt9);
951 bfin_write_EVT10(evt_evt10);
952 bfin_write_EVT11(evt_evt11);
953 bfin_write_EVT12(evt_evt12);
954 bfin_write_EVT13(evt_evt13);
955 bfin_write_EVT14(evt14_softirq);
956 bfin_write_EVT15(evt_system_call);
957 CSYNC();
958 }
959
960 /*
961 * This function should be called during kernel startup to initialize
962 * the BFin IRQ handling routines.
963 */
964 int __init init_arch_irq(void)
965 {
966 int irq;
967 unsigned long ilat = 0;
968 /* Disable all the peripheral intrs - page 4-29 HW Ref manual */
969 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
970 bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
971 bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
972 # ifdef CONFIG_BF54x
973 bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
974 # endif
975 #else
976 bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
977 #endif
978 SSYNC();
979
980 local_irq_disable();
981
982 init_exception_buff();
983
984 #ifdef CONFIG_BF54x
985 # ifdef CONFIG_PINTx_REASSIGN
986 pint[0]->assign = CONFIG_PINT0_ASSIGN;
987 pint[1]->assign = CONFIG_PINT1_ASSIGN;
988 pint[2]->assign = CONFIG_PINT2_ASSIGN;
989 pint[3]->assign = CONFIG_PINT3_ASSIGN;
990 # endif
991 /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
992 init_pint_lut();
993 #endif
994
995 for (irq = 0; irq <= SYS_IRQS; irq++) {
996 if (irq <= IRQ_CORETMR)
997 set_irq_chip(irq, &bfin_core_irqchip);
998 else
999 set_irq_chip(irq, &bfin_internal_irqchip);
1000 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1001 if (irq != IRQ_GENERIC_ERROR) {
1002 #endif
1003
1004 switch (irq) {
1005 #if defined(CONFIG_BF53x)
1006 case IRQ_PROG_INTA:
1007 set_irq_chained_handler(irq,
1008 bfin_demux_gpio_irq);
1009 break;
1010 # if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1011 case IRQ_MAC_RX:
1012 set_irq_chained_handler(irq,
1013 bfin_demux_gpio_irq);
1014 break;
1015 # endif
1016 #elif defined(CONFIG_BF54x)
1017 case IRQ_PINT0:
1018 set_irq_chained_handler(irq,
1019 bfin_demux_gpio_irq);
1020 break;
1021 case IRQ_PINT1:
1022 set_irq_chained_handler(irq,
1023 bfin_demux_gpio_irq);
1024 break;
1025 case IRQ_PINT2:
1026 set_irq_chained_handler(irq,
1027 bfin_demux_gpio_irq);
1028 break;
1029 case IRQ_PINT3:
1030 set_irq_chained_handler(irq,
1031 bfin_demux_gpio_irq);
1032 break;
1033 #elif defined(CONFIG_BF52x)
1034 case IRQ_PORTF_INTA:
1035 set_irq_chained_handler(irq,
1036 bfin_demux_gpio_irq);
1037 break;
1038 case IRQ_PORTG_INTA:
1039 set_irq_chained_handler(irq,
1040 bfin_demux_gpio_irq);
1041 break;
1042 case IRQ_PORTH_INTA:
1043 set_irq_chained_handler(irq,
1044 bfin_demux_gpio_irq);
1045 break;
1046 #elif defined(CONFIG_BF561)
1047 case IRQ_PROG0_INTA:
1048 set_irq_chained_handler(irq,
1049 bfin_demux_gpio_irq);
1050 break;
1051 case IRQ_PROG1_INTA:
1052 set_irq_chained_handler(irq,
1053 bfin_demux_gpio_irq);
1054 break;
1055 case IRQ_PROG2_INTA:
1056 set_irq_chained_handler(irq,
1057 bfin_demux_gpio_irq);
1058 break;
1059 #endif
1060 default:
1061 set_irq_handler(irq, handle_simple_irq);
1062 break;
1063 }
1064
1065 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1066 } else {
1067 set_irq_handler(irq, bfin_demux_error_irq);
1068 }
1069 #endif
1070 }
1071 #ifdef BF537_GENERIC_ERROR_INT_DEMUX
1072 for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++) {
1073 set_irq_chip(irq, &bfin_generic_error_irqchip);
1074 set_irq_handler(irq, handle_level_irq);
1075 }
1076 #endif
1077
1078 for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++) {
1079
1080 set_irq_chip(irq, &bfin_gpio_irqchip);
1081 /* if configured as edge, then will be changed to do_edge_IRQ */
1082 set_irq_handler(irq, handle_level_irq);
1083 }
1084
1085 bfin_write_IMASK(0);
1086 CSYNC();
1087 ilat = bfin_read_ILAT();
1088 CSYNC();
1089 bfin_write_ILAT(ilat);
1090 CSYNC();
1091
1092 printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1093 /* IMASK=xxx is equivalent to STI xx or irq_flags=xx,
1094 * local_irq_enable()
1095 */
1096 program_IAR();
1097 /* Therefore it's better to setup IARs before interrupts enabled */
1098 search_IAR();
1099
1100 /* Enable interrupts IVG7-15 */
1101 irq_flags = irq_flags | IMASK_IVG15 |
1102 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1103 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1104
1105 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1106 bfin_write_SIC_IWR0(IWR_ENABLE_ALL);
1107 bfin_write_SIC_IWR1(IWR_ENABLE_ALL);
1108 # ifdef CONFIG_BF54x
1109 bfin_write_SIC_IWR2(IWR_ENABLE_ALL);
1110 # endif
1111 #else
1112 bfin_write_SIC_IWR(IWR_ENABLE_ALL);
1113 #endif
1114
1115 return 0;
1116 }
1117
1118 #ifdef CONFIG_DO_IRQ_L1
1119 __attribute__((l1_text))
1120 #endif
1121 void do_irq(int vec, struct pt_regs *fp)
1122 {
1123 if (vec == EVT_IVTMR_P) {
1124 vec = IRQ_CORETMR;
1125 } else {
1126 struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1127 struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1128 #if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561)
1129 unsigned long sic_status[3];
1130
1131 SSYNC();
1132 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1133 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1134 #ifdef CONFIG_BF54x
1135 sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1136 #endif
1137 for (;; ivg++) {
1138 if (ivg >= ivg_stop) {
1139 atomic_inc(&num_spurious);
1140 return;
1141 }
1142 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1143 break;
1144 }
1145 #else
1146 unsigned long sic_status;
1147 SSYNC();
1148 sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1149
1150 for (;; ivg++) {
1151 if (ivg >= ivg_stop) {
1152 atomic_inc(&num_spurious);
1153 return;
1154 } else if (sic_status & ivg->isrflag)
1155 break;
1156 }
1157 #endif
1158 vec = ivg->irqno;
1159 }
1160 asm_do_IRQ(vec, fp);
1161
1162 #ifdef CONFIG_KGDB
1163 kgdb_process_breakpoint();
1164 #endif
1165 }
linux 2.6 git repository for openrd