2 * drivers/i2c/busses/i2c-bfin-twi.c
4 * Description: Driver for Blackfin Two Wire Interface
6 * Author: sonicz <sonic.zhang@analog.com>
8 * Copyright (c) 2005-2007 Analog Devices, Inc.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/module.h>
26 #include <linux/kernel.h>
27 #include <linux/init.h>
28 #include <linux/i2c.h>
30 #include <linux/timer.h>
31 #include <linux/spinlock.h>
32 #include <linux/completion.h>
33 #include <linux/interrupt.h>
34 #include <linux/platform_device.h>
36 #include <asm/blackfin.h>
37 #include <asm/portmux.h>
40 #define POLL_TIMEOUT (2 * HZ)
43 #define TWI_I2C_MODE_STANDARD 1
44 #define TWI_I2C_MODE_STANDARDSUB 2
45 #define TWI_I2C_MODE_COMBINED 3
46 #define TWI_I2C_MODE_REPEAT 4
48 struct bfin_twi_iface
{
60 struct timer_list timeout_timer
;
61 struct i2c_adapter adap
;
62 struct completion complete
;
66 void __iomem
*regs_base
;
70 #define DEFINE_TWI_REG(reg, off) \
71 static inline u16 read_##reg(struct bfin_twi_iface *iface) \
72 { return bfin_read16(iface->regs_base + (off)); } \
73 static inline void write_##reg(struct bfin_twi_iface *iface, u16 v) \
74 { bfin_write16(iface->regs_base + (off), v); }
76 DEFINE_TWI_REG(CLKDIV
, 0x00)
77 DEFINE_TWI_REG(CONTROL
, 0x04)
78 DEFINE_TWI_REG(SLAVE_CTL
, 0x08)
79 DEFINE_TWI_REG(SLAVE_STAT
, 0x0C)
80 DEFINE_TWI_REG(SLAVE_ADDR
, 0x10)
81 DEFINE_TWI_REG(MASTER_CTL
, 0x14)
82 DEFINE_TWI_REG(MASTER_STAT
, 0x18)
83 DEFINE_TWI_REG(MASTER_ADDR
, 0x1C)
84 DEFINE_TWI_REG(INT_STAT
, 0x20)
85 DEFINE_TWI_REG(INT_MASK
, 0x24)
86 DEFINE_TWI_REG(FIFO_CTL
, 0x28)
87 DEFINE_TWI_REG(FIFO_STAT
, 0x2C)
88 DEFINE_TWI_REG(XMT_DATA8
, 0x80)
89 DEFINE_TWI_REG(XMT_DATA16
, 0x84)
90 DEFINE_TWI_REG(RCV_DATA8
, 0x88)
91 DEFINE_TWI_REG(RCV_DATA16
, 0x8C)
93 static const u16 pin_req
[2][3] = {
94 {P_TWI0_SCL
, P_TWI0_SDA
, 0},
95 {P_TWI1_SCL
, P_TWI1_SDA
, 0},
98 static void bfin_twi_handle_interrupt(struct bfin_twi_iface
*iface
)
100 unsigned short twi_int_status
= read_INT_STAT(iface
);
101 unsigned short mast_stat
= read_MASTER_STAT(iface
);
103 if (twi_int_status
& XMTSERV
) {
104 /* Transmit next data */
105 if (iface
->writeNum
> 0) {
106 write_XMT_DATA8(iface
, *(iface
->transPtr
++));
109 /* start receive immediately after complete sending in
112 else if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
)
113 write_MASTER_CTL(iface
,
114 read_MASTER_CTL(iface
) | MDIR
| RSTART
);
115 else if (iface
->manual_stop
)
116 write_MASTER_CTL(iface
,
117 read_MASTER_CTL(iface
) | STOP
);
118 else if (iface
->cur_mode
== TWI_I2C_MODE_REPEAT
&&
119 iface
->cur_msg
+1 < iface
->msg_num
)
120 write_MASTER_CTL(iface
,
121 read_MASTER_CTL(iface
) | RSTART
);
124 write_INT_STAT(iface
, XMTSERV
);
127 if (twi_int_status
& RCVSERV
) {
128 if (iface
->readNum
> 0) {
129 /* Receive next data */
130 *(iface
->transPtr
) = read_RCV_DATA8(iface
);
131 if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
) {
132 /* Change combine mode into sub mode after
135 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
136 /* Get read number from first byte in block
139 if (iface
->readNum
== 1 && iface
->manual_stop
)
140 iface
->readNum
= *iface
->transPtr
+ 1;
144 } else if (iface
->manual_stop
) {
145 write_MASTER_CTL(iface
,
146 read_MASTER_CTL(iface
) | STOP
);
148 } else if (iface
->cur_mode
== TWI_I2C_MODE_REPEAT
&&
149 iface
->cur_msg
+1 < iface
->msg_num
) {
150 write_MASTER_CTL(iface
,
151 read_MASTER_CTL(iface
) | RSTART
);
154 /* Clear interrupt source */
155 write_INT_STAT(iface
, RCVSERV
);
158 if (twi_int_status
& MERR
) {
159 write_INT_STAT(iface
, MERR
);
160 write_INT_MASK(iface
, 0);
161 write_MASTER_STAT(iface
, 0x3e);
162 write_MASTER_CTL(iface
, 0);
164 iface
->result
= -EIO
;
165 /* if both err and complete int stats are set, return proper
168 if (twi_int_status
& MCOMP
) {
169 write_INT_STAT(iface
, MCOMP
);
170 write_INT_MASK(iface
, 0);
171 write_MASTER_CTL(iface
, 0);
173 /* If it is a quick transfer, only address bug no data,
174 * not an err, return 1.
176 if (iface
->writeNum
== 0 && (mast_stat
& BUFRDERR
))
178 /* If address not acknowledged return -1,
181 else if (!(mast_stat
& ANAK
))
184 complete(&iface
->complete
);
187 if (twi_int_status
& MCOMP
) {
188 write_INT_STAT(iface
, MCOMP
);
190 if (iface
->cur_mode
== TWI_I2C_MODE_COMBINED
) {
191 if (iface
->readNum
== 0) {
192 /* set the read number to 1 and ask for manual
193 * stop in block combine mode
196 iface
->manual_stop
= 1;
197 write_MASTER_CTL(iface
,
198 read_MASTER_CTL(iface
) | (0xff << 6));
200 /* set the readd number in other
203 write_MASTER_CTL(iface
,
204 (read_MASTER_CTL(iface
) &
206 (iface
->readNum
<< 6));
208 /* remove restart bit and enable master receive */
209 write_MASTER_CTL(iface
,
210 read_MASTER_CTL(iface
) & ~RSTART
);
211 write_MASTER_CTL(iface
,
212 read_MASTER_CTL(iface
) | MEN
| MDIR
);
214 } else if (iface
->cur_mode
== TWI_I2C_MODE_REPEAT
&&
215 iface
->cur_msg
+1 < iface
->msg_num
) {
217 iface
->transPtr
= iface
->pmsg
[iface
->cur_msg
].buf
;
218 iface
->writeNum
= iface
->readNum
=
219 iface
->pmsg
[iface
->cur_msg
].len
;
220 /* Set Transmit device address */
221 write_MASTER_ADDR(iface
,
222 iface
->pmsg
[iface
->cur_msg
].addr
);
223 if (iface
->pmsg
[iface
->cur_msg
].flags
& I2C_M_RD
)
224 iface
->read_write
= I2C_SMBUS_READ
;
226 iface
->read_write
= I2C_SMBUS_WRITE
;
227 /* Transmit first data */
228 if (iface
->writeNum
> 0) {
229 write_XMT_DATA8(iface
,
230 *(iface
->transPtr
++));
236 if (iface
->pmsg
[iface
->cur_msg
].len
<= 255)
237 write_MASTER_CTL(iface
,
238 iface
->pmsg
[iface
->cur_msg
].len
<< 6);
240 write_MASTER_CTL(iface
, 0xff << 6);
241 iface
->manual_stop
= 1;
243 /* remove restart bit and enable master receive */
244 write_MASTER_CTL(iface
,
245 read_MASTER_CTL(iface
) & ~RSTART
);
246 write_MASTER_CTL(iface
, read_MASTER_CTL(iface
) |
247 MEN
| ((iface
->read_write
== I2C_SMBUS_READ
) ?
252 write_INT_MASK(iface
, 0);
253 write_MASTER_CTL(iface
, 0);
255 complete(&iface
->complete
);
260 /* Interrupt handler */
261 static irqreturn_t
bfin_twi_interrupt_entry(int irq
, void *dev_id
)
263 struct bfin_twi_iface
*iface
= dev_id
;
266 spin_lock_irqsave(&iface
->lock
, flags
);
267 del_timer(&iface
->timeout_timer
);
268 bfin_twi_handle_interrupt(iface
);
269 spin_unlock_irqrestore(&iface
->lock
, flags
);
273 static void bfin_twi_timeout(unsigned long data
)
275 struct bfin_twi_iface
*iface
= (struct bfin_twi_iface
*)data
;
278 spin_lock_irqsave(&iface
->lock
, flags
);
279 bfin_twi_handle_interrupt(iface
);
280 if (iface
->result
== 0) {
281 iface
->timeout_count
--;
282 if (iface
->timeout_count
> 0) {
283 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
284 add_timer(&iface
->timeout_timer
);
287 complete(&iface
->complete
);
290 spin_unlock_irqrestore(&iface
->lock
, flags
);
294 * Generic i2c master transfer entrypoint
296 static int bfin_twi_master_xfer(struct i2c_adapter
*adap
,
297 struct i2c_msg
*msgs
, int num
)
299 struct bfin_twi_iface
*iface
= adap
->algo_data
;
300 struct i2c_msg
*pmsg
;
303 if (!(read_CONTROL(iface
) & TWI_ENA
))
306 while (read_MASTER_STAT(iface
) & BUSBUSY
)
310 iface
->msg_num
= num
;
314 if (pmsg
->flags
& I2C_M_TEN
) {
315 dev_err(&adap
->dev
, "10 bits addr not supported!\n");
319 iface
->cur_mode
= TWI_I2C_MODE_REPEAT
;
320 iface
->manual_stop
= 0;
321 iface
->transPtr
= pmsg
->buf
;
322 iface
->writeNum
= iface
->readNum
= pmsg
->len
;
324 iface
->timeout_count
= 10;
325 /* Set Transmit device address */
326 write_MASTER_ADDR(iface
, pmsg
->addr
);
328 /* FIFO Initiation. Data in FIFO should be
329 * discarded before start a new operation.
331 write_FIFO_CTL(iface
, 0x3);
333 write_FIFO_CTL(iface
, 0);
336 if (pmsg
->flags
& I2C_M_RD
)
337 iface
->read_write
= I2C_SMBUS_READ
;
339 iface
->read_write
= I2C_SMBUS_WRITE
;
340 /* Transmit first data */
341 if (iface
->writeNum
> 0) {
342 write_XMT_DATA8(iface
, *(iface
->transPtr
++));
349 write_INT_STAT(iface
, MERR
| MCOMP
| XMTSERV
| RCVSERV
);
351 /* Interrupt mask . Enable XMT, RCV interrupt */
352 write_INT_MASK(iface
, MCOMP
| MERR
| RCVSERV
| XMTSERV
);
355 if (pmsg
->len
<= 255)
356 write_MASTER_CTL(iface
, pmsg
->len
<< 6);
358 write_MASTER_CTL(iface
, 0xff << 6);
359 iface
->manual_stop
= 1;
362 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
363 add_timer(&iface
->timeout_timer
);
366 write_MASTER_CTL(iface
, read_MASTER_CTL(iface
) | MEN
|
367 ((iface
->read_write
== I2C_SMBUS_READ
) ? MDIR
: 0) |
368 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
> 100) ? FAST
: 0));
371 wait_for_completion(&iface
->complete
);
382 * SMBus type transfer entrypoint
385 int bfin_twi_smbus_xfer(struct i2c_adapter
*adap
, u16 addr
,
386 unsigned short flags
, char read_write
,
387 u8 command
, int size
, union i2c_smbus_data
*data
)
389 struct bfin_twi_iface
*iface
= adap
->algo_data
;
392 if (!(read_CONTROL(iface
) & TWI_ENA
))
395 while (read_MASTER_STAT(iface
) & BUSBUSY
)
401 /* Prepare datas & select mode */
403 case I2C_SMBUS_QUICK
:
404 iface
->transPtr
= NULL
;
405 iface
->cur_mode
= TWI_I2C_MODE_STANDARD
;
409 iface
->transPtr
= NULL
;
411 if (read_write
== I2C_SMBUS_READ
)
415 iface
->transPtr
= &data
->byte
;
417 iface
->cur_mode
= TWI_I2C_MODE_STANDARD
;
419 case I2C_SMBUS_BYTE_DATA
:
420 if (read_write
== I2C_SMBUS_READ
) {
422 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
425 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
427 iface
->transPtr
= &data
->byte
;
429 case I2C_SMBUS_WORD_DATA
:
430 if (read_write
== I2C_SMBUS_READ
) {
432 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
435 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
437 iface
->transPtr
= (u8
*)&data
->word
;
439 case I2C_SMBUS_PROC_CALL
:
442 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
443 iface
->transPtr
= (u8
*)&data
->word
;
445 case I2C_SMBUS_BLOCK_DATA
:
446 if (read_write
== I2C_SMBUS_READ
) {
448 iface
->cur_mode
= TWI_I2C_MODE_COMBINED
;
450 iface
->writeNum
= data
->block
[0] + 1;
451 iface
->cur_mode
= TWI_I2C_MODE_STANDARDSUB
;
453 iface
->transPtr
= data
->block
;
460 iface
->manual_stop
= 0;
461 iface
->read_write
= read_write
;
462 iface
->command
= command
;
463 iface
->timeout_count
= 10;
465 /* FIFO Initiation. Data in FIFO should be discarded before
466 * start a new operation.
468 write_FIFO_CTL(iface
, 0x3);
470 write_FIFO_CTL(iface
, 0);
473 write_INT_STAT(iface
, MERR
| MCOMP
| XMTSERV
| RCVSERV
);
475 /* Set Transmit device address */
476 write_MASTER_ADDR(iface
, addr
);
479 iface
->timeout_timer
.expires
= jiffies
+ POLL_TIMEOUT
;
480 add_timer(&iface
->timeout_timer
);
482 switch (iface
->cur_mode
) {
483 case TWI_I2C_MODE_STANDARDSUB
:
484 write_XMT_DATA8(iface
, iface
->command
);
485 write_INT_MASK(iface
, MCOMP
| MERR
|
486 ((iface
->read_write
== I2C_SMBUS_READ
) ?
490 if (iface
->writeNum
+ 1 <= 255)
491 write_MASTER_CTL(iface
, (iface
->writeNum
+ 1) << 6);
493 write_MASTER_CTL(iface
, 0xff << 6);
494 iface
->manual_stop
= 1;
497 write_MASTER_CTL(iface
, read_MASTER_CTL(iface
) | MEN
|
498 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
>100) ? FAST
: 0));
500 case TWI_I2C_MODE_COMBINED
:
501 write_XMT_DATA8(iface
, iface
->command
);
502 write_INT_MASK(iface
, MCOMP
| MERR
| RCVSERV
| XMTSERV
);
505 if (iface
->writeNum
> 0)
506 write_MASTER_CTL(iface
, (iface
->writeNum
+ 1) << 6);
508 write_MASTER_CTL(iface
, 0x1 << 6);
510 write_MASTER_CTL(iface
, read_MASTER_CTL(iface
) | MEN
|
511 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
>100) ? FAST
: 0));
514 write_MASTER_CTL(iface
, 0);
515 if (size
!= I2C_SMBUS_QUICK
) {
516 /* Don't access xmit data register when this is a
519 if (iface
->read_write
!= I2C_SMBUS_READ
) {
520 if (iface
->writeNum
> 0) {
521 write_XMT_DATA8(iface
,
522 *(iface
->transPtr
++));
523 if (iface
->writeNum
<= 255)
524 write_MASTER_CTL(iface
,
525 iface
->writeNum
<< 6);
527 write_MASTER_CTL(iface
,
529 iface
->manual_stop
= 1;
533 write_XMT_DATA8(iface
, iface
->command
);
534 write_MASTER_CTL(iface
, 1 << 6);
537 if (iface
->readNum
> 0 && iface
->readNum
<= 255)
538 write_MASTER_CTL(iface
,
539 iface
->readNum
<< 6);
540 else if (iface
->readNum
> 255) {
541 write_MASTER_CTL(iface
, 0xff << 6);
542 iface
->manual_stop
= 1;
544 del_timer(&iface
->timeout_timer
);
549 write_INT_MASK(iface
, MCOMP
| MERR
|
550 ((iface
->read_write
== I2C_SMBUS_READ
) ?
555 write_MASTER_CTL(iface
, read_MASTER_CTL(iface
) | MEN
|
556 ((iface
->read_write
== I2C_SMBUS_READ
) ? MDIR
: 0) |
557 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
> 100) ? FAST
: 0));
562 wait_for_completion(&iface
->complete
);
564 rc
= (iface
->result
>= 0) ? 0 : -1;
570 * Return what the adapter supports
572 static u32
bfin_twi_functionality(struct i2c_adapter
*adap
)
574 return I2C_FUNC_SMBUS_QUICK
| I2C_FUNC_SMBUS_BYTE
|
575 I2C_FUNC_SMBUS_BYTE_DATA
| I2C_FUNC_SMBUS_WORD_DATA
|
576 I2C_FUNC_SMBUS_BLOCK_DATA
| I2C_FUNC_SMBUS_PROC_CALL
|
581 static struct i2c_algorithm bfin_twi_algorithm
= {
582 .master_xfer
= bfin_twi_master_xfer
,
583 .smbus_xfer
= bfin_twi_smbus_xfer
,
584 .functionality
= bfin_twi_functionality
,
588 static int i2c_bfin_twi_suspend(struct platform_device
*dev
, pm_message_t state
)
590 struct bfin_twi_iface
*iface
= platform_get_drvdata(dev
);
593 write_CONTROL(iface
, read_CONTROL(iface
) & ~TWI_ENA
);
599 static int i2c_bfin_twi_resume(struct platform_device
*dev
)
601 struct bfin_twi_iface
*iface
= platform_get_drvdata(dev
);
604 write_CONTROL(iface
, read_CONTROL(iface
) | TWI_ENA
);
610 static int i2c_bfin_twi_probe(struct platform_device
*pdev
)
612 struct bfin_twi_iface
*iface
;
613 struct i2c_adapter
*p_adap
;
614 struct resource
*res
;
617 iface
= kzalloc(sizeof(struct bfin_twi_iface
), GFP_KERNEL
);
619 dev_err(&pdev
->dev
, "Cannot allocate memory\n");
621 goto out_error_nomem
;
624 spin_lock_init(&(iface
->lock
));
625 init_completion(&(iface
->complete
));
627 /* Find and map our resources */
628 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
630 dev_err(&pdev
->dev
, "Cannot get IORESOURCE_MEM\n");
632 goto out_error_get_res
;
635 iface
->regs_base
= ioremap(res
->start
, res
->end
- res
->start
+ 1);
636 if (iface
->regs_base
== NULL
) {
637 dev_err(&pdev
->dev
, "Cannot map IO\n");
639 goto out_error_ioremap
;
642 iface
->irq
= platform_get_irq(pdev
, 0);
643 if (iface
->irq
< 0) {
644 dev_err(&pdev
->dev
, "No IRQ specified\n");
646 goto out_error_no_irq
;
649 init_timer(&(iface
->timeout_timer
));
650 iface
->timeout_timer
.function
= bfin_twi_timeout
;
651 iface
->timeout_timer
.data
= (unsigned long)iface
;
653 p_adap
= &iface
->adap
;
654 p_adap
->id
= I2C_HW_BLACKFIN
;
655 p_adap
->nr
= pdev
->id
;
656 strlcpy(p_adap
->name
, pdev
->name
, sizeof(p_adap
->name
));
657 p_adap
->algo
= &bfin_twi_algorithm
;
658 p_adap
->algo_data
= iface
;
659 p_adap
->class = I2C_CLASS_ALL
;
660 p_adap
->dev
.parent
= &pdev
->dev
;
662 rc
= peripheral_request_list(pin_req
[pdev
->id
], "i2c-bfin-twi");
664 dev_err(&pdev
->dev
, "Can't setup pin mux!\n");
665 goto out_error_pin_mux
;
668 rc
= request_irq(iface
->irq
, bfin_twi_interrupt_entry
,
669 IRQF_DISABLED
, pdev
->name
, iface
);
671 dev_err(&pdev
->dev
, "Can't get IRQ %d !\n", iface
->irq
);
673 goto out_error_req_irq
;
676 /* Set TWI internal clock as 10MHz */
677 write_CONTROL(iface
, ((get_sclk() / 1024 / 1024 + 5) / 10) & 0x7F);
679 /* Set Twi interface clock as specified */
680 write_CLKDIV(iface
, ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
)
681 << 8) | ((5*1024 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ
)
685 write_CONTROL(iface
, read_CONTROL(iface
) | TWI_ENA
);
688 rc
= i2c_add_numbered_adapter(p_adap
);
690 dev_err(&pdev
->dev
, "Can't add i2c adapter!\n");
691 goto out_error_add_adapter
;
694 platform_set_drvdata(pdev
, iface
);
696 dev_info(&pdev
->dev
, "Blackfin BF5xx on-chip I2C TWI Contoller, "
697 "regs_base@%p\n", iface
->regs_base
);
701 out_error_add_adapter
:
702 free_irq(iface
->irq
, iface
);
705 peripheral_free_list(pin_req
[pdev
->id
]);
707 iounmap(iface
->regs_base
);
715 static int i2c_bfin_twi_remove(struct platform_device
*pdev
)
717 struct bfin_twi_iface
*iface
= platform_get_drvdata(pdev
);
719 platform_set_drvdata(pdev
, NULL
);
721 i2c_del_adapter(&(iface
->adap
));
722 free_irq(iface
->irq
, iface
);
723 peripheral_free_list(pin_req
[pdev
->id
]);
724 iounmap(iface
->regs_base
);
730 static struct platform_driver i2c_bfin_twi_driver
= {
731 .probe
= i2c_bfin_twi_probe
,
732 .remove
= i2c_bfin_twi_remove
,
733 .suspend
= i2c_bfin_twi_suspend
,
734 .resume
= i2c_bfin_twi_resume
,
736 .name
= "i2c-bfin-twi",
737 .owner
= THIS_MODULE
,
741 static int __init
i2c_bfin_twi_init(void)
743 return platform_driver_register(&i2c_bfin_twi_driver
);
746 static void __exit
i2c_bfin_twi_exit(void)
748 platform_driver_unregister(&i2c_bfin_twi_driver
);
751 module_init(i2c_bfin_twi_init
);
752 module_exit(i2c_bfin_twi_exit
);
754 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
755 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Contoller Driver");
756 MODULE_LICENSE("GPL");