drivers/net/netxen/netxen_nic.h

   1 /*
   2  * Copyright (C) 2003 - 2009 NetXen, Inc.
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
  18  * MA  02111-1307, USA.
  19  *
  20  * The full GNU General Public License is included in this distribution
  21  * in the file called LICENSE.
  22  *
  23  * Contact Information:
  24  *    info@netxen.com
  25  * NetXen Inc,
  26  * 18922 Forge Drive
  27  * Cupertino, CA 95014-0701
  28  *
  29  */
  30
  31 #ifndef _NETXEN_NIC_H_
  32 #define _NETXEN_NIC_H_
  33
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/types.h>
  37 #include <linux/ioport.h>
  38 #include <linux/pci.h>
  39 #include <linux/netdevice.h>
  40 #include <linux/etherdevice.h>
  41 #include <linux/ip.h>
  42 #include <linux/in.h>
  43 #include <linux/tcp.h>
  44 #include <linux/skbuff.h>
  45
  46 #include <linux/ethtool.h>
  47 #include <linux/mii.h>
  48 #include <linux/timer.h>
  49
  50 #include <linux/vmalloc.h>
  51
  52 #include <asm/io.h>
  53 #include <asm/byteorder.h>
  54
  55 #include "netxen_nic_hw.h"
  56
  57 #define _NETXEN_NIC_LINUX_MAJOR 4
  58 #define _NETXEN_NIC_LINUX_MINOR 0
  59 #define _NETXEN_NIC_LINUX_SUBVERSION 30
  60 #define NETXEN_NIC_LINUX_VERSIONID  "4.0.30"
  61
  62 #define NETXEN_VERSION_CODE(a, b, c)    (((a) << 16) + ((b) << 8) + (c))
  63
  64 #define NETXEN_NUM_FLASH_SECTORS (64)
  65 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024)
  66 #define NETXEN_FLASH_TOTAL_SIZE  (NETXEN_NUM_FLASH_SECTORS \
  67                                         * NETXEN_FLASH_SECTOR_SIZE)
  68
  69 #define PHAN_VENDOR_ID 0x4040
  70
  71 #define RCV_DESC_RINGSIZE(rds_ring)     \
  72         (sizeof(struct rcv_desc) * (rds_ring)->num_desc)
  73 #define RCV_BUFF_RINGSIZE(rds_ring)     \
  74         (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc)
  75 #define STATUS_DESC_RINGSIZE(sds_ring)  \
  76         (sizeof(struct status_desc) * (sds_ring)->num_desc)
  77 #define TX_BUFF_RINGSIZE(tx_ring)       \
  78         (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc)
  79 #define TX_DESC_RINGSIZE(tx_ring)       \
  80         (sizeof(struct cmd_desc_type0) * tx_ring->num_desc)
  81
  82 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a)))
  83
  84 #define NETXEN_RCV_PRODUCER_OFFSET      0
  85 #define NETXEN_RCV_PEG_DB_ID            2
  86 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024
  87 #define FLASH_SUCCESS 0
  88
  89 #define ADDR_IN_WINDOW1(off)    \
  90         ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0
  91
  92 /*
  93  * normalize a 64MB crb address to 32MB PCI window
  94  * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1
  95  */
  96 #define NETXEN_CRB_NORMAL(reg)  \
  97         ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST)
  98
  99 #define NETXEN_CRB_NORMALIZE(adapter, reg) \
 100         pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg))
 101
 102 #define DB_NORMALIZE(adapter, off) \
 103         (adapter->ahw.db_base + (off))
 104
 105 #define NX_P2_C0                0x24
 106 #define NX_P2_C1                0x25
 107 #define NX_P3_A0                0x30
 108 #define NX_P3_A2                0x30
 109 #define NX_P3_B0                0x40
 110 #define NX_P3_B1                0x41
 111 #define NX_P3_B2                0x42
 112
 113 #define NX_IS_REVISION_P2(REVISION)     (REVISION <= NX_P2_C1)
 114 #define NX_IS_REVISION_P3(REVISION)     (REVISION >= NX_P3_A0)
 115
 116 #define FIRST_PAGE_GROUP_START  0
 117 #define FIRST_PAGE_GROUP_END    0x100000
 118
 119 #define SECOND_PAGE_GROUP_START 0x6000000
 120 #define SECOND_PAGE_GROUP_END   0x68BC000
 121
 122 #define THIRD_PAGE_GROUP_START  0x70E4000
 123 #define THIRD_PAGE_GROUP_END    0x8000000
 124
 125 #define FIRST_PAGE_GROUP_SIZE  FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START
 126 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START
 127 #define THIRD_PAGE_GROUP_SIZE  THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START
 128
 129 #define P2_MAX_MTU                     (8000)
 130 #define P3_MAX_MTU                     (9600)
 131 #define NX_ETHERMTU                    1500
 132 #define NX_MAX_ETHERHDR                32 /* This contains some padding */
 133
 134 #define NX_RX_NORMAL_BUF_MAX_LEN       (NX_MAX_ETHERHDR + NX_ETHERMTU)
 135 #define NX_P2_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P2_MAX_MTU)
 136 #define NX_P3_RX_JUMBO_BUF_MAX_LEN     (NX_MAX_ETHERHDR + P3_MAX_MTU)
 137 #define NX_CT_DEFAULT_RX_BUF_LEN        2048
 138
 139 #define MAX_RX_BUFFER_LENGTH            1760
 140 #define MAX_RX_JUMBO_BUFFER_LENGTH      8062
 141 #define MAX_RX_LRO_BUFFER_LENGTH        (8062)
 142 #define RX_DMA_MAP_LEN                  (MAX_RX_BUFFER_LENGTH - 2)
 143 #define RX_JUMBO_DMA_MAP_LEN    \
 144         (MAX_RX_JUMBO_BUFFER_LENGTH - 2)
 145 #define RX_LRO_DMA_MAP_LEN              (MAX_RX_LRO_BUFFER_LENGTH - 2)
 146
 147 /*
 148  * Maximum number of ring contexts
 149  */
 150 #define MAX_RING_CTX 1
 151
 152 /* Opcodes to be used with the commands */
 153 #define TX_ETHER_PKT    0x01
 154 #define TX_TCP_PKT      0x02
 155 #define TX_UDP_PKT      0x03
 156 #define TX_IP_PKT       0x04
 157 #define TX_TCP_LSO      0x05
 158 #define TX_TCP_LSO6     0x06
 159 #define TX_IPSEC        0x07
 160 #define TX_IPSEC_CMD    0x0a
 161 #define TX_TCPV6_PKT    0x0b
 162 #define TX_UDPV6_PKT    0x0c
 163
 164 /* The following opcodes are for internal consumption. */
 165 #define NETXEN_CONTROL_OP       0x10
 166 #define PEGNET_REQUEST          0x11
 167
 168 #define MAX_NUM_CARDS           4
 169
 170 #define MAX_BUFFERS_PER_CMD     32
 171
 172 /*
 173  * Following are the states of the Phantom. Phantom will set them and
 174  * Host will read to check if the fields are correct.
 175  */
 176 #define PHAN_INITIALIZE_START           0xff00
 177 #define PHAN_INITIALIZE_FAILED          0xffff
 178 #define PHAN_INITIALIZE_COMPLETE        0xff01
 179
 180 /* Host writes the following to notify that it has done the init-handshake */
 181 #define PHAN_INITIALIZE_ACK     0xf00f
 182
 183 #define NUM_RCV_DESC_RINGS      3
 184 #define NUM_STS_DESC_RINGS      4
 185
 186 #define RCV_RING_NORMAL 0
 187 #define RCV_RING_JUMBO  1
 188 #define RCV_RING_LRO    2
 189
 190 #define MAX_CMD_DESCRIPTORS             4096
 191 #define MAX_RCV_DESCRIPTORS             16384
 192 #define MAX_CMD_DESCRIPTORS_HOST        1024
 193 #define MAX_RCV_DESCRIPTORS_1G          2048
 194 #define MAX_RCV_DESCRIPTORS_10G         4096
 195 #define MAX_JUMBO_RCV_DESCRIPTORS       1024
 196 #define MAX_LRO_RCV_DESCRIPTORS         8
 197 #define NETXEN_CTX_SIGNATURE    0xdee0
 198 #define NETXEN_RCV_PRODUCER(ringid)     (ringid)
 199
 200 #define PHAN_PEG_RCV_INITIALIZED        0xff01
 201 #define PHAN_PEG_RCV_START_INITIALIZE   0xff00
 202
 203 #define get_next_index(index, length)   \
 204         (((index) + 1) & ((length) - 1))
 205
 206 #define get_index_range(index,length,count)     \
 207         (((index) + (count)) & ((length) - 1))
 208
 209 #define MPORT_SINGLE_FUNCTION_MODE 0x1111
 210 #define MPORT_MULTI_FUNCTION_MODE 0x2222
 211
 212 #include "netxen_nic_phan_reg.h"
 213
 214 /*
 215  * NetXen host-peg signal message structure
 216  *
 217  *      Bit 0-1         : peg_id => 0x2 for tx and 01 for rx
 218  *      Bit 2           : priv_id => must be 1
 219  *      Bit 3-17        : count => for doorbell
 220  *      Bit 18-27       : ctx_id => Context id
 221  *      Bit 28-31       : opcode
 222  */
 223
 224 typedef u32 netxen_ctx_msg;
 225
 226 #define netxen_set_msg_peg_id(config_word, val) \
 227         ((config_word) &= ~3, (config_word) |= val & 3)
 228 #define netxen_set_msg_privid(config_word)      \
 229         ((config_word) |= 1 << 2)
 230 #define netxen_set_msg_count(config_word, val)  \
 231         ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3)
 232 #define netxen_set_msg_ctxid(config_word, val)  \
 233         ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18)
 234 #define netxen_set_msg_opcode(config_word, val) \
 235         ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28)
 236
 237 struct netxen_rcv_context {
 238         __le64 rcv_ring_addr;
 239         __le32 rcv_ring_size;
 240         __le32 rsrvd;
 241 };
 242
 243 struct netxen_ring_ctx {
 244
 245         /* one command ring */
 246         __le64 cmd_consumer_offset;
 247         __le64 cmd_ring_addr;
 248         __le32 cmd_ring_size;
 249         __le32 rsrvd;
 250
 251         /* three receive rings */
 252         struct netxen_rcv_context rcv_ctx[3];
 253
 254         /* one status ring */
 255         __le64 sts_ring_addr;
 256         __le32 sts_ring_size;
 257
 258         __le32 ctx_id;
 259 } __attribute__ ((aligned(64)));
 260
 261 /*
 262  * Following data structures describe the descriptors that will be used.
 263  * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when
 264  * we are doing LSO (above the 1500 size packet) only.
 265  */
 266
 267 /*
 268  * The size of reference handle been changed to 16 bits to pass the MSS fields
 269  * for the LSO packet
 270  */
 271
 272 #define FLAGS_CHECKSUM_ENABLED  0x01
 273 #define FLAGS_LSO_ENABLED       0x02
 274 #define FLAGS_IPSEC_SA_ADD      0x04
 275 #define FLAGS_IPSEC_SA_DELETE   0x08
 276 #define FLAGS_VLAN_TAGGED       0x10
 277
 278 #define netxen_set_cmd_desc_port(cmd_desc, var) \
 279         ((cmd_desc)->port_ctxid |= ((var) & 0x0F))
 280 #define netxen_set_cmd_desc_ctxid(cmd_desc, var)        \
 281         ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0))
 282
 283 #define netxen_set_tx_port(_desc, _port) \
 284         (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0)
 285
 286 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \
 287         (_desc)->flags_opcode = \
 288         cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7))
 289
 290 #define netxen_set_tx_frags_len(_desc, _frags, _len) \
 291         (_desc)->num_of_buffers_total_length = \
 292         cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8))
 293
 294 struct cmd_desc_type0 {
 295         u8 tcp_hdr_offset;      /* For LSO only */
 296         u8 ip_hdr_offset;       /* For LSO only */
 297         /* Bit pattern: 0-6 flags, 7-12 opcode, 13-15 unused */
 298         __le16 flags_opcode;
 299         /* Bit pattern: 0-7 total number of segments,
 300            8-31 Total size of the packet */
 301         __le32 num_of_buffers_total_length;
 302         union {
 303                 struct {
 304                         __le32 addr_low_part2;
 305                         __le32 addr_high_part2;
 306                 };
 307                 __le64 addr_buffer2;
 308         };
 309
 310         __le16 reference_handle;        /* changed to u16 to add mss */
 311         __le16 mss;             /* passed by NDIS_PACKET for LSO */
 312         /* Bit pattern 0-3 port, 0-3 ctx id */
 313         u8 port_ctxid;
 314         u8 total_hdr_length;    /* LSO only : MAC+IP+TCP Hdr size */
 315         __le16 conn_id;         /* IPSec offoad only */
 316
 317         union {
 318                 struct {
 319                         __le32 addr_low_part3;
 320                         __le32 addr_high_part3;
 321                 };
 322                 __le64 addr_buffer3;
 323         };
 324         union {
 325                 struct {
 326                         __le32 addr_low_part1;
 327                         __le32 addr_high_part1;
 328                 };
 329                 __le64 addr_buffer1;
 330         };
 331
 332         __le16 buffer_length[4];
 333
 334         union {
 335                 struct {
 336                         __le32 addr_low_part4;
 337                         __le32 addr_high_part4;
 338                 };
 339                 __le64 addr_buffer4;
 340         };
 341
 342         __le64 unused;
 343
 344 } __attribute__ ((aligned(64)));
 345
 346 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
 347 struct rcv_desc {
 348         __le16 reference_handle;
 349         __le16 reserved;
 350         __le32 buffer_length;   /* allocated buffer length (usually 2K) */
 351         __le64 addr_buffer;
 352 };
 353
 354 /* opcode field in status_desc */
 355 #define NETXEN_NIC_RXPKT_DESC  0x04
 356 #define NETXEN_OLD_RXPKT_DESC  0x3f
 357 #define NETXEN_NIC_RESPONSE_DESC 0x05
 358
 359 /* for status field in status_desc */
 360 #define STATUS_NEED_CKSUM       (1)
 361 #define STATUS_CKSUM_OK         (2)
 362
 363 /* owner bits of status_desc */
 364 #define STATUS_OWNER_HOST       (0x1ULL << 56)
 365 #define STATUS_OWNER_PHANTOM    (0x2ULL << 56)
 366
 367 /* Status descriptor:
 368    0-3 port, 4-7 status, 8-11 type, 12-27 total_length
 369    28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset
 370    53-55 desc_cnt, 56-57 owner, 58-63 opcode
 371  */
 372 #define netxen_get_sts_port(sts_data)   \
 373         ((sts_data) & 0x0F)
 374 #define netxen_get_sts_status(sts_data) \
 375         (((sts_data) >> 4) & 0x0F)
 376 #define netxen_get_sts_type(sts_data)   \
 377         (((sts_data) >> 8) & 0x0F)
 378 #define netxen_get_sts_totallength(sts_data)    \
 379         (((sts_data) >> 12) & 0xFFFF)
 380 #define netxen_get_sts_refhandle(sts_data)      \
 381         (((sts_data) >> 28) & 0xFFFF)
 382 #define netxen_get_sts_prot(sts_data)   \
 383         (((sts_data) >> 44) & 0x0F)
 384 #define netxen_get_sts_pkt_offset(sts_data)     \
 385         (((sts_data) >> 48) & 0x1F)
 386 #define netxen_get_sts_desc_cnt(sts_data)       \
 387         (((sts_data) >> 53) & 0x7)
 388 #define netxen_get_sts_opcode(sts_data) \
 389         (((sts_data) >> 58) & 0x03F)
 390
 391 struct status_desc {
 392         __le64 status_desc_data[2];
 393 } __attribute__ ((aligned(16)));
 394
 395 /* The version of the main data structure */
 396 #define NETXEN_BDINFO_VERSION 1
 397
 398 /* Magic number to let user know flash is programmed */
 399 #define NETXEN_BDINFO_MAGIC 0x12345678
 400
 401 /* Max number of Gig ports on a Phantom board */
 402 #define NETXEN_MAX_PORTS 4
 403
 404 #define NETXEN_BRDTYPE_P1_BD            0x0000
 405 #define NETXEN_BRDTYPE_P1_SB            0x0001
 406 #define NETXEN_BRDTYPE_P1_SMAX          0x0002
 407 #define NETXEN_BRDTYPE_P1_SOCK          0x0003
 408
 409 #define NETXEN_BRDTYPE_P2_SOCK_31       0x0008
 410 #define NETXEN_BRDTYPE_P2_SOCK_35       0x0009
 411 #define NETXEN_BRDTYPE_P2_SB35_4G       0x000a
 412 #define NETXEN_BRDTYPE_P2_SB31_10G      0x000b
 413 #define NETXEN_BRDTYPE_P2_SB31_2G       0x000c
 414
 415 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ         0x000d
 416 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ         0x000e
 417 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4          0x000f
 418
 419 #define NETXEN_BRDTYPE_P3_REF_QG        0x0021
 420 #define NETXEN_BRDTYPE_P3_HMEZ          0x0022
 421 #define NETXEN_BRDTYPE_P3_10G_CX4_LP    0x0023
 422 #define NETXEN_BRDTYPE_P3_4_GB          0x0024
 423 #define NETXEN_BRDTYPE_P3_IMEZ          0x0025
 424 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS  0x0026
 425 #define NETXEN_BRDTYPE_P3_10000_BASE_T  0x0027
 426 #define NETXEN_BRDTYPE_P3_XG_LOM        0x0028
 427 #define NETXEN_BRDTYPE_P3_4_GB_MM       0x0029
 428 #define NETXEN_BRDTYPE_P3_10G_SFP_CT    0x002a
 429 #define NETXEN_BRDTYPE_P3_10G_SFP_QT    0x002b
 430 #define NETXEN_BRDTYPE_P3_10G_CX4       0x0031
 431 #define NETXEN_BRDTYPE_P3_10G_XFP       0x0032
 432 #define NETXEN_BRDTYPE_P3_10G_TP        0x0080
 433
 434 struct netxen_board_info {
 435         u32 header_version;
 436
 437         u32 board_mfg;
 438         u32 board_type;
 439         u32 board_num;
 440         u32 chip_id;
 441         u32 chip_minor;
 442         u32 chip_major;
 443         u32 chip_pkg;
 444         u32 chip_lot;
 445
 446         u32 port_mask;          /* available niu ports */
 447         u32 peg_mask;           /* available pegs */
 448         u32 icache_ok;          /* can we run with icache? */
 449         u32 dcache_ok;          /* can we run with dcache? */
 450         u32 casper_ok;
 451
 452         u32 mac_addr_lo_0;
 453         u32 mac_addr_lo_1;
 454         u32 mac_addr_lo_2;
 455         u32 mac_addr_lo_3;
 456
 457         /* MN-related config */
 458         u32 mn_sync_mode;       /* enable/ sync shift cclk/ sync shift mclk */
 459         u32 mn_sync_shift_cclk;
 460         u32 mn_sync_shift_mclk;
 461         u32 mn_wb_en;
 462         u32 mn_crystal_freq;    /* in MHz */
 463         u32 mn_speed;           /* in MHz */
 464         u32 mn_org;
 465         u32 mn_depth;
 466         u32 mn_ranks_0;         /* ranks per slot */
 467         u32 mn_ranks_1;         /* ranks per slot */
 468         u32 mn_rd_latency_0;
 469         u32 mn_rd_latency_1;
 470         u32 mn_rd_latency_2;
 471         u32 mn_rd_latency_3;
 472         u32 mn_rd_latency_4;
 473         u32 mn_rd_latency_5;
 474         u32 mn_rd_latency_6;
 475         u32 mn_rd_latency_7;
 476         u32 mn_rd_latency_8;
 477         u32 mn_dll_val[18];
 478         u32 mn_mode_reg;        /* MIU DDR Mode Register */
 479         u32 mn_ext_mode_reg;    /* MIU DDR Extended Mode Register */
 480         u32 mn_timing_0;        /* MIU Memory Control Timing Rgister */
 481         u32 mn_timing_1;        /* MIU Extended Memory Ctrl Timing Register */
 482         u32 mn_timing_2;        /* MIU Extended Memory Ctrl Timing2 Register */
 483
 484         /* SN-related config */
 485         u32 sn_sync_mode;       /* enable/ sync shift cclk / sync shift mclk */
 486         u32 sn_pt_mode;         /* pass through mode */
 487         u32 sn_ecc_en;
 488         u32 sn_wb_en;
 489         u32 sn_crystal_freq;
 490         u32 sn_speed;
 491         u32 sn_org;
 492         u32 sn_depth;
 493         u32 sn_dll_tap;
 494         u32 sn_rd_latency;
 495
 496         u32 mac_addr_hi_0;
 497         u32 mac_addr_hi_1;
 498         u32 mac_addr_hi_2;
 499         u32 mac_addr_hi_3;
 500
 501         u32 magic;              /* indicates flash has been initialized */
 502
 503         u32 mn_rdimm;
 504         u32 mn_dll_override;
 505
 506 };
 507
 508 #define FLASH_NUM_PORTS         (4)
 509
 510 struct netxen_flash_mac_addr {
 511         u32 flash_addr[32];
 512 };
 513
 514 struct netxen_user_old_info {
 515         u8 flash_md5[16];
 516         u8 crbinit_md5[16];
 517         u8 brdcfg_md5[16];
 518         /* bootloader */
 519         u32 bootld_version;
 520         u32 bootld_size;
 521         u8 bootld_md5[16];
 522         /* image */
 523         u32 image_version;
 524         u32 image_size;
 525         u8 image_md5[16];
 526         /* primary image status */
 527         u32 primary_status;
 528         u32 secondary_present;
 529
 530         /* MAC address , 4 ports */
 531         struct netxen_flash_mac_addr mac_addr[FLASH_NUM_PORTS];
 532 };
 533 #define FLASH_NUM_MAC_PER_PORT  32
 534 struct netxen_user_info {
 535         u8 flash_md5[16 * 64];
 536         /* bootloader */
 537         u32 bootld_version;
 538         u32 bootld_size;
 539         /* image */
 540         u32 image_version;
 541         u32 image_size;
 542         /* primary image status */
 543         u32 primary_status;
 544         u32 secondary_present;
 545
 546         /* MAC address , 4 ports, 32 address per port */
 547         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 548         u32 sub_sys_id;
 549         u8 serial_num[32];
 550
 551         /* Any user defined data */
 552 };
 553
 554 /*
 555  * Flash Layout - new format.
 556  */
 557 struct netxen_new_user_info {
 558         u8 flash_md5[16 * 64];
 559         /* bootloader */
 560         u32 bootld_version;
 561         u32 bootld_size;
 562         /* image */
 563         u32 image_version;
 564         u32 image_size;
 565         /* primary image status */
 566         u32 primary_status;
 567         u32 secondary_present;
 568
 569         /* MAC address , 4 ports, 32 address per port */
 570         u64 mac_addr[FLASH_NUM_PORTS * FLASH_NUM_MAC_PER_PORT];
 571         u32 sub_sys_id;
 572         u8 serial_num[32];
 573
 574         /* Any user defined data */
 575 };
 576
 577 #define SECONDARY_IMAGE_PRESENT 0xb3b4b5b6
 578 #define SECONDARY_IMAGE_ABSENT  0xffffffff
 579 #define PRIMARY_IMAGE_GOOD      0x5a5a5a5a
 580 #define PRIMARY_IMAGE_BAD       0xffffffff
 581
 582 /* Flash memory map */
 583 #define NETXEN_CRBINIT_START    0       /* crbinit section */
 584 #define NETXEN_BRDCFG_START     0x4000  /* board config */
 585 #define NETXEN_INITCODE_START   0x6000  /* pegtune code */
 586 #define NETXEN_BOOTLD_START     0x10000 /* bootld */
 587 #define NETXEN_IMAGE_START      0x43000 /* compressed image */
 588 #define NETXEN_SECONDARY_START  0x200000        /* backup images */
 589 #define NETXEN_PXE_START        0x3E0000        /* PXE boot rom */
 590 #define NETXEN_USER_START       0x3E8000        /* Firmare info */
 591 #define NETXEN_FIXED_START      0x3F0000        /* backup of crbinit */
 592
 593 #define NX_FW_VERSION_OFFSET    (NETXEN_USER_START+0x408)
 594 #define NX_FW_SIZE_OFFSET       (NETXEN_USER_START+0x40c)
 595 #define NX_BIOS_VERSION_OFFSET  (NETXEN_USER_START+0x83c)
 596 #define NX_FW_MAGIC_OFFSET      (NETXEN_BRDCFG_START+0x128)
 597 #define NX_FW_MIN_SIZE          (0x3fffff)
 598 #define NX_P2_MN_ROMIMAGE       0
 599 #define NX_P3_CT_ROMIMAGE       1
 600 #define NX_P3_MN_ROMIMAGE       2
 601
 602 #define NETXEN_USER_START_OLD NETXEN_PXE_START  /* for backward compatibility */
 603
 604 #define NETXEN_FLASH_START              (NETXEN_CRBINIT_START)
 605 #define NETXEN_INIT_SECTOR              (0)
 606 #define NETXEN_PRIMARY_START            (NETXEN_BOOTLD_START)
 607 #define NETXEN_FLASH_CRBINIT_SIZE       (0x4000)
 608 #define NETXEN_FLASH_BRDCFG_SIZE        (sizeof(struct netxen_board_info))
 609 #define NETXEN_FLASH_USER_SIZE          (sizeof(struct netxen_user_info)/sizeof(u32))
 610 #define NETXEN_FLASH_SECONDARY_SIZE     (NETXEN_USER_START-NETXEN_SECONDARY_START)
 611 #define NETXEN_NUM_PRIMARY_SECTORS      (0x20)
 612 #define NETXEN_NUM_CONFIG_SECTORS       (1)
 613 extern char netxen_nic_driver_name[];
 614
 615 /* Number of status descriptors to handle per interrupt */
 616 #define MAX_STATUS_HANDLE       (64)
 617
 618 /*
 619  * netxen_skb_frag{} is to contain mapping info for each SG list. This
 620  * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}.
 621  */
 622 struct netxen_skb_frag {
 623         u64 dma;
 624         u64 length;
 625 };
 626
 627 #define _netxen_set_bits(config_word, start, bits, val) {\
 628         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));\
 629         unsigned long long __tvalue = (val);    \
 630         (config_word) &= ~__tmask;      \
 631         (config_word) |= (((__tvalue) << (start)) & __tmask); \
 632 }
 633
 634 #define _netxen_clear_bits(config_word, start, bits) {\
 635         unsigned long long __tmask = (((1ULL << (bits)) - 1) << (start));  \
 636         (config_word) &= ~__tmask; \
 637 }
 638
 639 /*    Following defines are for the state of the buffers    */
 640 #define NETXEN_BUFFER_FREE      0
 641 #define NETXEN_BUFFER_BUSY      1
 642
 643 /*
 644  * There will be one netxen_buffer per skb packet.    These will be
 645  * used to save the dma info for pci_unmap_page()
 646  */
 647 struct netxen_cmd_buffer {
 648         struct sk_buff *skb;
 649         struct netxen_skb_frag frag_array[MAX_BUFFERS_PER_CMD + 1];
 650         u32 frag_count;
 651 };
 652
 653 /* In rx_buffer, we do not need multiple fragments as is a single buffer */
 654 struct netxen_rx_buffer {
 655         struct list_head list;
 656         struct sk_buff *skb;
 657         u64 dma;
 658         u16 ref_handle;
 659         u16 state;
 660 };
 661
 662 /* Board types */
 663 #define NETXEN_NIC_GBE  0x01
 664 #define NETXEN_NIC_XGBE 0x02
 665
 666 /*
 667  * One hardware_context{} per adapter
 668  * contains interrupt info as well shared hardware info.
 669  */
 670 struct netxen_hardware_context {
 671         void __iomem *pci_base0;
 672         void __iomem *pci_base1;
 673         void __iomem *pci_base2;
 674         void __iomem *db_base;
 675         unsigned long db_len;
 676         unsigned long pci_len0;
 677
 678         int qdr_sn_window;
 679         int ddr_mn_window;
 680         unsigned long mn_win_crb;
 681         unsigned long ms_win_crb;
 682
 683         u8 cut_through;
 684         u8 revision_id;
 685         u8 pci_func;
 686         u8 linkup;
 687         u16 port_type;
 688         u16 board_type;
 689 };
 690
 691 #define MINIMUM_ETHERNET_FRAME_SIZE     64      /* With FCS */
 692 #define ETHERNET_FCS_SIZE               4
 693
 694 struct netxen_adapter_stats {
 695         u64  xmitcalled;
 696         u64  xmitfinished;
 697         u64  rxdropped;
 698         u64  txdropped;
 699         u64  csummed;
 700         u64  no_rcv;
 701         u64  rxbytes;
 702         u64  txbytes;
 703 };
 704
 705 /*
 706  * Rcv Descriptor Context. One such per Rcv Descriptor. There may
 707  * be one Rcv Descriptor for normal packets, one for jumbo and may be others.
 708  */
 709 struct nx_host_rds_ring {
 710         u32 producer;
 711         u32 crb_rcv_producer;
 712         u32 num_desc;
 713         u32 dma_size;
 714         u32 skb_size;
 715         u32 flags;
 716         struct rcv_desc *desc_head;
 717         struct netxen_rx_buffer *rx_buf_arr;
 718         struct list_head free_list;
 719         spinlock_t lock;
 720         dma_addr_t phys_addr;
 721 };
 722
 723 struct nx_host_sds_ring {
 724         u32 consumer;
 725         u32 crb_sts_consumer;
 726         u32 crb_intr_mask;
 727         u32 num_desc;
 728
 729         struct status_desc *desc_head;
 730         struct netxen_adapter *adapter;
 731         struct napi_struct napi;
 732         struct list_head free_list[NUM_RCV_DESC_RINGS];
 733
 734         int irq;
 735
 736         dma_addr_t phys_addr;
 737         char name[IFNAMSIZ+4];
 738 };
 739
 740 struct nx_host_tx_ring {
 741         u32 producer;
 742         __le32 *hw_consumer;
 743         u32 sw_consumer;
 744         u32 crb_cmd_producer;
 745         u32 crb_cmd_consumer;
 746         u32 num_desc;
 747
 748         struct netxen_cmd_buffer *cmd_buf_arr;
 749         struct cmd_desc_type0 *desc_head;
 750         dma_addr_t phys_addr;
 751 };
 752
 753 /*
 754  * Receive context. There is one such structure per instance of the
 755  * receive processing. Any state information that is relevant to
 756  * the receive, and is must be in this structure. The global data may be
 757  * present elsewhere.
 758  */
 759 struct netxen_recv_context {
 760         u32 state;
 761         u16 context_id;
 762         u16 virt_port;
 763
 764         struct nx_host_rds_ring rds_rings[NUM_RCV_DESC_RINGS];
 765         struct nx_host_sds_ring *sds_rings;
 766 };
 767
 768 /* New HW context creation */
 769
 770 #define NX_OS_CRB_RETRY_COUNT   4000
 771 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \
 772         (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16))
 773
 774 #define NX_CDRP_CLEAR           0x00000000
 775 #define NX_CDRP_CMD_BIT         0x80000000
 776
 777 /*
 778  * All responses must have the NX_CDRP_CMD_BIT cleared
 779  * in the crb NX_CDRP_CRB_OFFSET.
 780  */
 781 #define NX_CDRP_FORM_RSP(rsp)   (rsp)
 782 #define NX_CDRP_IS_RSP(rsp)     (((rsp) & NX_CDRP_CMD_BIT) == 0)
 783
 784 #define NX_CDRP_RSP_OK          0x00000001
 785 #define NX_CDRP_RSP_FAIL        0x00000002
 786 #define NX_CDRP_RSP_TIMEOUT     0x00000003
 787
 788 /*
 789  * All commands must have the NX_CDRP_CMD_BIT set in
 790  * the crb NX_CDRP_CRB_OFFSET.
 791  */
 792 #define NX_CDRP_FORM_CMD(cmd)   (NX_CDRP_CMD_BIT | (cmd))
 793 #define NX_CDRP_IS_CMD(cmd)     (((cmd) & NX_CDRP_CMD_BIT) != 0)
 794
 795 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES     0x00000001
 796 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX    0x00000002
 797 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX    0x00000003
 798 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX  0x00000004
 799 #define NX_CDRP_CMD_READ_MAX_RX_CTX         0x00000005
 800 #define NX_CDRP_CMD_READ_MAX_TX_CTX         0x00000006
 801 #define NX_CDRP_CMD_CREATE_RX_CTX           0x00000007
 802 #define NX_CDRP_CMD_DESTROY_RX_CTX          0x00000008
 803 #define NX_CDRP_CMD_CREATE_TX_CTX           0x00000009
 804 #define NX_CDRP_CMD_DESTROY_TX_CTX          0x0000000a
 805 #define NX_CDRP_CMD_SETUP_STATISTICS        0x0000000e
 806 #define NX_CDRP_CMD_GET_STATISTICS          0x0000000f
 807 #define NX_CDRP_CMD_DELETE_STATISTICS       0x00000010
 808 #define NX_CDRP_CMD_SET_MTU                 0x00000012
 809 #define NX_CDRP_CMD_MAX                     0x00000013
 810
 811 #define NX_RCODE_SUCCESS                0
 812 #define NX_RCODE_NO_HOST_MEM            1
 813 #define NX_RCODE_NO_HOST_RESOURCE       2
 814 #define NX_RCODE_NO_CARD_CRB            3
 815 #define NX_RCODE_NO_CARD_MEM            4
 816 #define NX_RCODE_NO_CARD_RESOURCE       5
 817 #define NX_RCODE_INVALID_ARGS           6
 818 #define NX_RCODE_INVALID_ACTION         7
 819 #define NX_RCODE_INVALID_STATE          8
 820 #define NX_RCODE_NOT_SUPPORTED          9
 821 #define NX_RCODE_NOT_PERMITTED          10
 822 #define NX_RCODE_NOT_READY              11
 823 #define NX_RCODE_DOES_NOT_EXIST         12
 824 #define NX_RCODE_ALREADY_EXISTS         13
 825 #define NX_RCODE_BAD_SIGNATURE          14
 826 #define NX_RCODE_CMD_NOT_IMPL           15
 827 #define NX_RCODE_CMD_INVALID            16
 828 #define NX_RCODE_TIMEOUT                17
 829 #define NX_RCODE_CMD_FAILED             18
 830 #define NX_RCODE_MAX_EXCEEDED           19
 831 #define NX_RCODE_MAX                    20
 832
 833 #define NX_DESTROY_CTX_RESET            0
 834 #define NX_DESTROY_CTX_D3_RESET         1
 835 #define NX_DESTROY_CTX_MAX              2
 836
 837 /*
 838  * Capabilities
 839  */
 840 #define NX_CAP_BIT(class, bit)          (1 << bit)
 841 #define NX_CAP0_LEGACY_CONTEXT          NX_CAP_BIT(0, 0)
 842 #define NX_CAP0_MULTI_CONTEXT           NX_CAP_BIT(0, 1)
 843 #define NX_CAP0_LEGACY_MN               NX_CAP_BIT(0, 2)
 844 #define NX_CAP0_LEGACY_MS               NX_CAP_BIT(0, 3)
 845 #define NX_CAP0_CUT_THROUGH             NX_CAP_BIT(0, 4)
 846 #define NX_CAP0_LRO                     NX_CAP_BIT(0, 5)
 847 #define NX_CAP0_LSO                     NX_CAP_BIT(0, 6)
 848 #define NX_CAP0_JUMBO_CONTIGUOUS        NX_CAP_BIT(0, 7)
 849 #define NX_CAP0_LRO_CONTIGUOUS          NX_CAP_BIT(0, 8)
 850
 851 /*
 852  * Context state
 853  */
 854 #define NX_HOST_CTX_STATE_FREED         0
 855 #define NX_HOST_CTX_STATE_ALLOCATED     1
 856 #define NX_HOST_CTX_STATE_ACTIVE        2
 857 #define NX_HOST_CTX_STATE_DISABLED      3
 858 #define NX_HOST_CTX_STATE_QUIESCED      4
 859 #define NX_HOST_CTX_STATE_MAX           5
 860
 861 /*
 862  * Rx context
 863  */
 864
 865 typedef struct {
 866         __le64 host_phys_addr;  /* Ring base addr */
 867         __le32 ring_size;               /* Ring entries */
 868         __le16 msi_index;
 869         __le16 rsvd;            /* Padding */
 870 } nx_hostrq_sds_ring_t;
 871
 872 typedef struct {
 873         __le64 host_phys_addr;  /* Ring base addr */
 874         __le64 buff_size;               /* Packet buffer size */
 875         __le32 ring_size;               /* Ring entries */
 876         __le32 ring_kind;               /* Class of ring */
 877 } nx_hostrq_rds_ring_t;
 878
 879 typedef struct {
 880         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 881         __le32 capabilities[4]; /* Flag bit vector */
 882         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 883         __le32 host_rds_crb_mode;       /* RDS crb usage */
 884         /* These ring offsets are relative to data[0] below */
 885         __le32 rds_ring_offset; /* Offset to RDS config */
 886         __le32 sds_ring_offset; /* Offset to SDS config */
 887         __le16 num_rds_rings;   /* Count of RDS rings */
 888         __le16 num_sds_rings;   /* Count of SDS rings */
 889         __le16 rsvd1;           /* Padding */
 890         __le16 rsvd2;           /* Padding */
 891         u8  reserved[128];      /* reserve space for future expansion*/
 892         /* MUST BE 64-bit aligned.
 893            The following is packed:
 894            - N hostrq_rds_rings
 895            - N hostrq_sds_rings */
 896         char data[0];
 897 } nx_hostrq_rx_ctx_t;
 898
 899 typedef struct {
 900         __le32 host_producer_crb;       /* Crb to use */
 901         __le32 rsvd1;           /* Padding */
 902 } nx_cardrsp_rds_ring_t;
 903
 904 typedef struct {
 905         __le32 host_consumer_crb;       /* Crb to use */
 906         __le32 interrupt_crb;   /* Crb to use */
 907 } nx_cardrsp_sds_ring_t;
 908
 909 typedef struct {
 910         /* These ring offsets are relative to data[0] below */
 911         __le32 rds_ring_offset; /* Offset to RDS config */
 912         __le32 sds_ring_offset; /* Offset to SDS config */
 913         __le32 host_ctx_state;  /* Starting State */
 914         __le32 num_fn_per_port; /* How many PCI fn share the port */
 915         __le16 num_rds_rings;   /* Count of RDS rings */
 916         __le16 num_sds_rings;   /* Count of SDS rings */
 917         __le16 context_id;              /* Handle for context */
 918         u8  phys_port;          /* Physical id of port */
 919         u8  virt_port;          /* Virtual/Logical id of port */
 920         u8  reserved[128];      /* save space for future expansion */
 921         /*  MUST BE 64-bit aligned.
 922            The following is packed:
 923            - N cardrsp_rds_rings
 924            - N cardrs_sds_rings */
 925         char data[0];
 926 } nx_cardrsp_rx_ctx_t;
 927
 928 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings)       \
 929         (sizeof(HOSTRQ_RX) +                                    \
 930         (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) +            \
 931         (sds_rings)*(sizeof(nx_hostrq_sds_ring_t)))
 932
 933 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings)     \
 934         (sizeof(CARDRSP_RX) +                                   \
 935         (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) +           \
 936         (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t)))
 937
 938 /*
 939  * Tx context
 940  */
 941
 942 typedef struct {
 943         __le64 host_phys_addr;  /* Ring base addr */
 944         __le32 ring_size;               /* Ring entries */
 945         __le32 rsvd;            /* Padding */
 946 } nx_hostrq_cds_ring_t;
 947
 948 typedef struct {
 949         __le64 host_rsp_dma_addr;       /* Response dma'd here */
 950         __le64 cmd_cons_dma_addr;       /*  */
 951         __le64 dummy_dma_addr;  /*  */
 952         __le32 capabilities[4]; /* Flag bit vector */
 953         __le32 host_int_crb_mode;       /* Interrupt crb usage */
 954         __le32 rsvd1;           /* Padding */
 955         __le16 rsvd2;           /* Padding */
 956         __le16 interrupt_ctl;
 957         __le16 msi_index;
 958         __le16 rsvd3;           /* Padding */
 959         nx_hostrq_cds_ring_t cds_ring;  /* Desc of cds ring */
 960         u8  reserved[128];      /* future expansion */
 961 } nx_hostrq_tx_ctx_t;
 962
 963 typedef struct {
 964         __le32 host_producer_crb;       /* Crb to use */
 965         __le32 interrupt_crb;   /* Crb to use */
 966 } nx_cardrsp_cds_ring_t;
 967
 968 typedef struct {
 969         __le32 host_ctx_state;  /* Starting state */
 970         __le16 context_id;              /* Handle for context */
 971         u8  phys_port;          /* Physical id of port */
 972         u8  virt_port;          /* Virtual/Logical id of port */
 973         nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */
 974         u8  reserved[128];      /* future expansion */
 975 } nx_cardrsp_tx_ctx_t;
 976
 977 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX)     (sizeof(HOSTRQ_TX))
 978 #define SIZEOF_CARDRSP_TX(CARDRSP_TX)   (sizeof(CARDRSP_TX))
 979
 980 /* CRB */
 981
 982 #define NX_HOST_RDS_CRB_MODE_UNIQUE     0
 983 #define NX_HOST_RDS_CRB_MODE_SHARED     1
 984 #define NX_HOST_RDS_CRB_MODE_CUSTOM     2
 985 #define NX_HOST_RDS_CRB_MODE_MAX        3
 986
 987 #define NX_HOST_INT_CRB_MODE_UNIQUE     0
 988 #define NX_HOST_INT_CRB_MODE_SHARED     1
 989 #define NX_HOST_INT_CRB_MODE_NORX       2
 990 #define NX_HOST_INT_CRB_MODE_NOTX       3
 991 #define NX_HOST_INT_CRB_MODE_NORXTX     4
 992
 993
 994 /* MAC */
 995
 996 #define MC_COUNT_P2     16
 997 #define MC_COUNT_P3     38
 998
 999 #define NETXEN_MAC_NOOP 0
1000 #define NETXEN_MAC_ADD  1
1001 #define NETXEN_MAC_DEL  2
1002
1003 typedef struct nx_mac_list_s {
1004         struct nx_mac_list_s *next;
1005         uint8_t mac_addr[MAX_ADDR_LEN];
1006 } nx_mac_list_t;
1007
1008 /*
1009  * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is
1010  * adjusted based on configured MTU.
1011  */
1012 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3
1013 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256
1014 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64
1015 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4
1016
1017 #define NETXEN_NIC_INTR_DEFAULT                 0x04
1018
1019 typedef union {
1020         struct {
1021                 uint16_t        rx_packets;
1022                 uint16_t        rx_time_us;
1023                 uint16_t        tx_packets;
1024                 uint16_t        tx_time_us;
1025         } data;
1026         uint64_t                word;
1027 } nx_nic_intr_coalesce_data_t;
1028
1029 typedef struct {
1030         uint16_t                        stats_time_us;
1031         uint16_t                        rate_sample_time;
1032         uint16_t                        flags;
1033         uint16_t                        rsvd_1;
1034         uint32_t                        low_threshold;
1035         uint32_t                        high_threshold;
1036         nx_nic_intr_coalesce_data_t     normal;
1037         nx_nic_intr_coalesce_data_t     low;
1038         nx_nic_intr_coalesce_data_t     high;
1039         nx_nic_intr_coalesce_data_t     irq;
1040 } nx_nic_intr_coalesce_t;
1041
1042 #define NX_HOST_REQUEST         0x13
1043 #define NX_NIC_REQUEST          0x14
1044
1045 #define NX_MAC_EVENT            0x1
1046
1047 /*
1048  * Driver --> Firmware
1049  */
1050 #define NX_NIC_H2C_OPCODE_START                         0
1051 #define NX_NIC_H2C_OPCODE_CONFIG_RSS                    1
1052 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL                2
1053 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE          3
1054 #define NX_NIC_H2C_OPCODE_CONFIG_LED                    4
1055 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS            5
1056 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC                 6
1057 #define NX_NIC_H2C_OPCODE_LRO_REQUEST                   7
1058 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS                8
1059 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST           9
1060 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST            10
1061 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU                 11
1062 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE     12
1063 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST      13
1064 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST       14
1065 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST        15
1066 #define NX_NIC_H2C_OPCODE_GET_NET_STATS                 16
1067 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V              17
1068 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR                 18
1069 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK               19
1070 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE               20
1071 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT                 21
1072 #define NX_NIC_C2C_OPCODE                               22
1073 #define NX_NIC_H2C_OPCODE_LAST                          23
1074
1075 /*
1076  * Firmware --> Driver
1077  */
1078
1079 #define NX_NIC_C2H_OPCODE_START                         128
1080 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE           129
1081 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE       130
1082 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE           131
1083 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE   132
1084 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE        133
1085 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE           134
1086 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE      135
1087 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS                136
1088 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY        137
1089 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY         138
1090 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139
1091 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE        140
1092 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE        141
1093 #define NX_NIC_C2H_OPCODE_LAST                          142
1094
1095 #define VPORT_MISS_MODE_DROP            0 /* drop all unmatched */
1096 #define VPORT_MISS_MODE_ACCEPT_ALL      1 /* accept all packets */
1097 #define VPORT_MISS_MODE_ACCEPT_MULTI    2 /* accept unmatched multicast */
1098
1099 #define NX_FW_CAPABILITY_LINK_NOTIFICATION      (1 << 5)
1100 #define NX_FW_CAPABILITY_SWITCHING              (1 << 6)
1101
1102 /* module types */
1103 #define LINKEVENT_MODULE_NOT_PRESENT                    1
1104 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN                2
1105 #define LINKEVENT_MODULE_OPTICAL_SRLR                   3
1106 #define LINKEVENT_MODULE_OPTICAL_LRM                    4
1107 #define LINKEVENT_MODULE_OPTICAL_SFP_1G                 5
1108 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE       6
1109 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN    7
1110 #define LINKEVENT_MODULE_TWINAX                         8
1111
1112 #define LINKSPEED_10GBPS        10000
1113 #define LINKSPEED_1GBPS         1000
1114 #define LINKSPEED_100MBPS       100
1115 #define LINKSPEED_10MBPS        10
1116
1117 #define LINKSPEED_ENCODED_10MBPS        0
1118 #define LINKSPEED_ENCODED_100MBPS       1
1119 #define LINKSPEED_ENCODED_1GBPS         2
1120
1121 #define LINKEVENT_AUTONEG_DISABLED      0
1122 #define LINKEVENT_AUTONEG_ENABLED       1
1123
1124 #define LINKEVENT_HALF_DUPLEX           0
1125 #define LINKEVENT_FULL_DUPLEX           1
1126
1127 #define LINKEVENT_LINKSPEED_MBPS        0
1128 #define LINKEVENT_LINKSPEED_ENCODED     1
1129
1130 /* firmware response header:
1131  *      63:58 - message type
1132  *      57:56 - owner
1133  *      55:53 - desc count
1134  *      52:48 - reserved
1135  *      47:40 - completion id
1136  *      39:32 - opcode
1137  *      31:16 - error code
1138  *      15:00 - reserved
1139  */
1140 #define netxen_get_nic_msgtype(msg_hdr) \
1141         ((msg_hdr >> 58) & 0x3F)
1142 #define netxen_get_nic_msg_compid(msg_hdr)      \
1143         ((msg_hdr >> 40) & 0xFF)
1144 #define netxen_get_nic_msg_opcode(msg_hdr)      \
1145         ((msg_hdr >> 32) & 0xFF)
1146 #define netxen_get_nic_msg_errcode(msg_hdr)     \
1147         ((msg_hdr >> 16) & 0xFFFF)
1148
1149 typedef struct {
1150         union {
1151                 struct {
1152                         u64 hdr;
1153                         u64 body[7];
1154                 };
1155                 u64 words[8];
1156         };
1157 } nx_fw_msg_t;
1158
1159 typedef struct {
1160         __le64 qhdr;
1161         __le64 req_hdr;
1162         __le64 words[6];
1163 } nx_nic_req_t;
1164
1165 typedef struct {
1166         u8 op;
1167         u8 tag;
1168         u8 mac_addr[6];
1169 } nx_mac_req_t;
1170
1171 #define MAX_PENDING_DESC_BLOCK_SIZE     64
1172
1173 #define NETXEN_NIC_MSI_ENABLED          0x02
1174 #define NETXEN_NIC_MSIX_ENABLED         0x04
1175 #define NETXEN_IS_MSI_FAMILY(adapter) \
1176         ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED))
1177
1178 #define MSIX_ENTRIES_PER_ADAPTER        NUM_STS_DESC_RINGS
1179 #define NETXEN_MSIX_TBL_SPACE           8192
1180 #define NETXEN_PCI_REG_MSIX_TBL         0x44
1181
1182 #define NETXEN_DB_MAPSIZE_BYTES         0x1000
1183
1184 #define NETXEN_NETDEV_WEIGHT 128
1185 #define NETXEN_ADAPTER_UP_MAGIC 777
1186 #define NETXEN_NIC_PEG_TUNE 0
1187
1188 struct netxen_dummy_dma {
1189         void *addr;
1190         dma_addr_t phys_addr;
1191 };
1192
1193 struct netxen_adapter {
1194         struct netxen_hardware_context ahw;
1195
1196         struct net_device *netdev;
1197         struct pci_dev *pdev;
1198         nx_mac_list_t   *mac_list;
1199
1200         u32 curr_window;
1201         u32 crb_win;
1202         rwlock_t adapter_lock;
1203
1204         spinlock_t tx_clean_lock;
1205
1206         u16 num_txd;
1207         u16 num_rxd;
1208         u16 num_jumbo_rxd;
1209         u16 num_lro_rxd;
1210
1211         u8 max_rds_rings;
1212         u8 max_sds_rings;
1213         u8 driver_mismatch;
1214         u8 msix_supported;
1215         u8 rx_csum;
1216         u8 pci_using_dac;
1217         u8 portnum;
1218         u8 physical_port;
1219
1220         u8 mc_enabled;
1221         u8 max_mc_count;
1222         u16 resv2;
1223         u32 resv3;
1224
1225         u8 has_link_events;
1226         u8 resv1;
1227         u16 tx_context_id;
1228         u16 mtu;
1229         u16 is_up;
1230
1231         u16 link_speed;
1232         u16 link_duplex;
1233         u16 link_autoneg;
1234         u16 module_type;
1235
1236         u32 capabilities;
1237         u32 flags;
1238         u32 irq;
1239         u32 temp;
1240         u32 fw_major;
1241         u32 fw_version;
1242
1243         struct netxen_adapter_stats stats;
1244
1245         struct netxen_recv_context recv_ctx;
1246         struct nx_host_tx_ring tx_ring;
1247
1248         /* Context interface shared between card and host */
1249         struct netxen_ring_ctx *ctx_desc;
1250         dma_addr_t ctx_desc_phys_addr;
1251         int (*enable_phy_interrupts) (struct netxen_adapter *);
1252         int (*disable_phy_interrupts) (struct netxen_adapter *);
1253         int (*macaddr_set) (struct netxen_adapter *, netxen_ethernet_macaddr_t);
1254         int (*set_mtu) (struct netxen_adapter *, int);
1255         int (*set_promisc) (struct netxen_adapter *, u32);
1256         int (*phy_read) (struct netxen_adapter *, long reg, u32 *);
1257         int (*phy_write) (struct netxen_adapter *, long reg, u32 val);
1258         int (*init_port) (struct netxen_adapter *, int);
1259         int (*stop_port) (struct netxen_adapter *);
1260
1261         u32 (*hw_read_wx)(struct netxen_adapter *, ulong);
1262         int (*hw_write_wx)(struct netxen_adapter *, ulong, u32);
1263         int (*pci_mem_read)(struct netxen_adapter *, u64, void *, int);
1264         int (*pci_mem_write)(struct netxen_adapter *, u64, void *, int);
1265         int (*pci_write_immediate)(struct netxen_adapter *, u64, u32);
1266         u32 (*pci_read_immediate)(struct netxen_adapter *, u64);
1267         unsigned long (*pci_set_window)(struct netxen_adapter *,
1268                         unsigned long long);
1269
1270         struct netxen_legacy_intr_set legacy_intr;
1271
1272         struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER];
1273
1274         struct netxen_dummy_dma dummy_dma;
1275
1276         struct work_struct watchdog_task;
1277         struct timer_list watchdog_timer;
1278         struct work_struct  tx_timeout_task;
1279
1280         struct net_device_stats net_stats;
1281
1282         nx_nic_intr_coalesce_t coal;
1283 };
1284
1285 /*
1286  * NetXen dma watchdog control structure
1287  *
1288  *      Bit 0           : enabled => R/O: 1 watchdog active, 0 inactive
1289  *      Bit 1           : disable_request => 1 req disable dma watchdog
1290  *      Bit 2           : enable_request =>  1 req enable dma watchdog
1291  *      Bit 3-31        : unused
1292  */
1293
1294 #define netxen_set_dma_watchdog_disable_req(config_word) \
1295         _netxen_set_bits(config_word, 1, 1, 1)
1296 #define netxen_set_dma_watchdog_enable_req(config_word) \
1297         _netxen_set_bits(config_word, 2, 1, 1)
1298 #define netxen_get_dma_watchdog_enabled(config_word) \
1299         ((config_word) & 0x1)
1300 #define netxen_get_dma_watchdog_disabled(config_word) \
1301         (((config_word) >> 1) & 0x1)
1302
1303 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1304 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter);
1305 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1306 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter);
1307 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
1308                             __u32 * readval);
1309 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter,
1310                              long reg, __u32 val);
1311
1312 /* Functions available from netxen_nic_hw.c */
1313 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
1314 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu);
1315
1316 #define NXRD32(adapter, off) \
1317         (adapter->hw_read_wx(adapter, off))
1318 #define NXWR32(adapter, off, val) \
1319         (adapter->hw_write_wx(adapter, off, val))
1320
1321 int netxen_nic_get_board_info(struct netxen_adapter *adapter);
1322 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter);
1323 int netxen_nic_wol_supported(struct netxen_adapter *adapter);
1324
1325 u32 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off);
1326 int netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
1327                 ulong off, u32 data);
1328 int netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1329                 u64 off, void *data, int size);
1330 int netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1331                 u64 off, void *data, int size);
1332 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1333                 u64 off, u32 data);
1334 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off);
1335 void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1336                 u64 off, u32 data);
1337 u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off);
1338 unsigned long netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1339                 unsigned long long addr);
1340 void netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter,
1341                 u32 wndw);
1342
1343 u32 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off);
1344 int netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1345                 ulong off, u32 data);
1346 int netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1347                 u64 off, void *data, int size);
1348 int netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1349                 u64 off, void *data, int size);
1350 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1351                 u64 off, u32 data);
1352 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off);
1353 void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1354                 u64 off, u32 data);
1355 u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off);
1356 unsigned long netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1357                 unsigned long long addr);
1358
1359 /* Functions from netxen_nic_init.c */
1360 void netxen_free_adapter_offload(struct netxen_adapter *adapter);
1361 int netxen_initialize_adapter_offload(struct netxen_adapter *adapter);
1362 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val);
1363 int netxen_load_firmware(struct netxen_adapter *adapter);
1364 int netxen_pinit_from_rom(struct netxen_adapter *adapter, int verbose);
1365
1366 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp);
1367 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr,
1368                                 u8 *bytes, size_t size);
1369 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr,
1370                                 u8 *bytes, size_t size);
1371 int netxen_flash_unlock(struct netxen_adapter *adapter);
1372 int netxen_backup_crbinit(struct netxen_adapter *adapter);
1373 int netxen_flash_erase_secondary(struct netxen_adapter *adapter);
1374 int netxen_flash_erase_primary(struct netxen_adapter *adapter);
1375 void netxen_halt_pegs(struct netxen_adapter *adapter);
1376
1377 int netxen_rom_se(struct netxen_adapter *adapter, int addr);
1378
1379 int netxen_alloc_sw_resources(struct netxen_adapter *adapter);
1380 void netxen_free_sw_resources(struct netxen_adapter *adapter);
1381
1382 int netxen_alloc_hw_resources(struct netxen_adapter *adapter);
1383 void netxen_free_hw_resources(struct netxen_adapter *adapter);
1384
1385 void netxen_release_rx_buffers(struct netxen_adapter *adapter);
1386 void netxen_release_tx_buffers(struct netxen_adapter *adapter);
1387
1388 void netxen_initialize_adapter_ops(struct netxen_adapter *adapter);
1389 int netxen_init_firmware(struct netxen_adapter *adapter);
1390 void netxen_nic_clear_stats(struct netxen_adapter *adapter);
1391 void netxen_watchdog_task(struct work_struct *work);
1392 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid,
1393                 struct nx_host_rds_ring *rds_ring);
1394 int netxen_process_cmd_ring(struct netxen_adapter *adapter);
1395 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max);
1396 void netxen_p2_nic_set_multi(struct net_device *netdev);
1397 void netxen_p3_nic_set_multi(struct net_device *netdev);
1398 void netxen_p3_free_mac_list(struct netxen_adapter *adapter);
1399 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32);
1400 int netxen_config_intr_coalesce(struct netxen_adapter *adapter);
1401 int netxen_config_rss(struct netxen_adapter *adapter, int enable);
1402 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable);
1403 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup);
1404
1405 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu);
1406 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu);
1407
1408 int netxen_nic_set_mac(struct net_device *netdev, void *p);
1409 struct net_device_stats *netxen_nic_get_stats(struct net_device *netdev);
1410
1411 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter,
1412                 struct nx_host_tx_ring *tx_ring, uint32_t crb_producer);
1413
1414 /*
1415  * NetXen Board information
1416  */
1417
1418 #define NETXEN_MAX_SHORT_NAME 32
1419 struct netxen_brdinfo {
1420         int brdtype;    /* type of board */
1421         long ports;             /* max no of physical ports */
1422         char short_name[NETXEN_MAX_SHORT_NAME];
1423 };
1424
1425 static const struct netxen_brdinfo netxen_boards[] = {
1426         {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"},
1427         {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"},
1428         {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"},
1429         {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"},
1430         {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"},
1431         {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"},
1432         {NETXEN_BRDTYPE_P3_REF_QG,  4, "Reference Quad Gig "},
1433         {NETXEN_BRDTYPE_P3_HMEZ,    2, "Dual XGb HMEZ"},
1434         {NETXEN_BRDTYPE_P3_10G_CX4_LP,   2, "Dual XGb CX4 LP"},
1435         {NETXEN_BRDTYPE_P3_4_GB,    4, "Quad Gig LP"},
1436         {NETXEN_BRDTYPE_P3_IMEZ,    2, "Dual XGb IMEZ"},
1437         {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"},
1438         {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"},
1439         {NETXEN_BRDTYPE_P3_XG_LOM,  2, "Dual XGb LOM"},
1440         {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"},
1441         {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"},
1442         {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"},
1443         {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"},
1444         {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"}
1445 };
1446
1447 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards)
1448
1449 static inline void get_brd_name_by_type(u32 type, char *name)
1450 {
1451         int i, found = 0;
1452         for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) {
1453                 if (netxen_boards[i].brdtype == type) {
1454                         strcpy(name, netxen_boards[i].short_name);
1455                         found = 1;
1456                         break;
1457                 }
1458
1459         }
1460         if (!found)
1461                 name = "Unknown";
1462 }
1463
1464 static inline int
1465 dma_watchdog_shutdown_request(struct netxen_adapter *adapter)
1466 {
1467         u32 ctrl;
1468
1469         /* check if already inactive */
1470         ctrl = adapter->hw_read_wx(adapter,
1471                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1472
1473         if (netxen_get_dma_watchdog_enabled(ctrl) == 0)
1474                 return 1;
1475
1476         /* Send the disable request */
1477         netxen_set_dma_watchdog_disable_req(ctrl);
1478         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1479
1480         return 0;
1481 }
1482
1483 static inline int
1484 dma_watchdog_shutdown_poll_result(struct netxen_adapter *adapter)
1485 {
1486         u32 ctrl;
1487
1488         ctrl = adapter->hw_read_wx(adapter,
1489                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1490
1491         return (netxen_get_dma_watchdog_enabled(ctrl) == 0);
1492 }
1493
1494 static inline int
1495 dma_watchdog_wakeup(struct netxen_adapter *adapter)
1496 {
1497         u32 ctrl;
1498
1499         ctrl = adapter->hw_read_wx(adapter,
1500                         NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL));
1501
1502         if (netxen_get_dma_watchdog_enabled(ctrl))
1503                 return 1;
1504
1505         /* send the wakeup request */
1506         netxen_set_dma_watchdog_enable_req(ctrl);
1507
1508         NXWR32(adapter, NETXEN_CAM_RAM(NETXEN_CAM_RAM_DMA_WATCHDOG_CTRL), ctrl);
1509
1510         return 0;
1511 }
1512
1513
1514 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1515 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac);
1516 extern void netxen_change_ringparam(struct netxen_adapter *adapter);
1517 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr,
1518                                 int *valp);
1519
1520 extern struct ethtool_ops netxen_nic_ethtool_ops;
1521
1522 #endif                          /* __NETXEN_NIC_H_ */