2 * drivers/net/gianfar.c
4 * Gianfar Ethernet Driver
5 * This driver is designed for the non-CPM ethernet controllers
6 * on the 85xx and 83xx family of integrated processors
7 * Based on 8260_io/fcc_enet.c
10 * Maintainer: Kumar Gala
12 * Copyright (c) 2002-2006 Freescale Semiconductor, Inc.
13 * Copyright (c) 2007 MontaVista Software, Inc.
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 * Gianfar: AKA Lambda Draconis, "Dragon"
28 * The driver is initialized through platform_device. Structures which
29 * define the configuration needed by the board are defined in a
30 * board structure in arch/ppc/platforms (though I do not
31 * discount the possibility that other architectures could one
34 * The Gianfar Ethernet Controller uses a ring of buffer
35 * descriptors. The beginning is indicated by a register
36 * pointing to the physical address of the start of the ring.
37 * The end is determined by a "wrap" bit being set in the
38 * last descriptor of the ring.
40 * When a packet is received, the RXF bit in the
41 * IEVENT register is set, triggering an interrupt when the
42 * corresponding bit in the IMASK register is also set (if
43 * interrupt coalescing is active, then the interrupt may not
44 * happen immediately, but will wait until either a set number
45 * of frames or amount of time have passed). In NAPI, the
46 * interrupt handler will signal there is work to be done, and
47 * exit. This method will start at the last known empty
48 * descriptor, and process every subsequent descriptor until there
49 * are none left with data (NAPI will stop after a set number of
50 * packets to give time to other tasks, but will eventually
51 * process all the packets). The data arrives inside a
52 * pre-allocated skb, and so after the skb is passed up to the
53 * stack, a new skb must be allocated, and the address field in
54 * the buffer descriptor must be updated to indicate this new
57 * When the kernel requests that a packet be transmitted, the
58 * driver starts where it left off last time, and points the
59 * descriptor at the buffer which was passed in. The driver
60 * then informs the DMA engine that there are packets ready to
61 * be transmitted. Once the controller is finished transmitting
62 * the packet, an interrupt may be triggered (under the same
63 * conditions as for reception, but depending on the TXF bit).
64 * The driver then cleans up the buffer.
67 #include <linux/kernel.h>
68 #include <linux/string.h>
69 #include <linux/errno.h>
70 #include <linux/unistd.h>
71 #include <linux/slab.h>
72 #include <linux/interrupt.h>
73 #include <linux/init.h>
74 #include <linux/delay.h>
75 #include <linux/netdevice.h>
76 #include <linux/etherdevice.h>
77 #include <linux/skbuff.h>
78 #include <linux/if_vlan.h>
79 #include <linux/spinlock.h>
81 #include <linux/platform_device.h>
83 #include <linux/tcp.h>
84 #include <linux/udp.h>
89 #include <asm/uaccess.h>
90 #include <linux/module.h>
91 #include <linux/dma-mapping.h>
92 #include <linux/crc32.h>
93 #include <linux/mii.h>
94 #include <linux/phy.h>
97 #include "gianfar_mii.h"
99 #define TX_TIMEOUT (1*HZ)
100 #undef BRIEF_GFAR_ERRORS
101 #undef VERBOSE_GFAR_ERRORS
103 const char gfar_driver_name
[] = "Gianfar Ethernet";
104 const char gfar_driver_version
[] = "1.3";
106 static int gfar_enet_open(struct net_device
*dev
);
107 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
);
108 static void gfar_timeout(struct net_device
*dev
);
109 static int gfar_close(struct net_device
*dev
);
110 struct sk_buff
*gfar_new_skb(struct net_device
*dev
);
111 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
112 struct sk_buff
*skb
);
113 static int gfar_set_mac_address(struct net_device
*dev
);
114 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
);
115 static irqreturn_t
gfar_error(int irq
, void *dev_id
);
116 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
);
117 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
);
118 static void adjust_link(struct net_device
*dev
);
119 static void init_registers(struct net_device
*dev
);
120 static int init_phy(struct net_device
*dev
);
121 static int gfar_probe(struct platform_device
*pdev
);
122 static int gfar_remove(struct platform_device
*pdev
);
123 static void free_skb_resources(struct gfar_private
*priv
);
124 static void gfar_set_multi(struct net_device
*dev
);
125 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
);
126 static void gfar_configure_serdes(struct net_device
*dev
);
127 static int gfar_poll(struct napi_struct
*napi
, int budget
);
128 #ifdef CONFIG_NET_POLL_CONTROLLER
129 static void gfar_netpoll(struct net_device
*dev
);
131 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
);
132 static int gfar_clean_tx_ring(struct net_device
*dev
);
133 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
, int length
);
134 static void gfar_vlan_rx_register(struct net_device
*netdev
,
135 struct vlan_group
*grp
);
136 void gfar_halt(struct net_device
*dev
);
137 void gfar_start(struct net_device
*dev
);
138 static void gfar_clear_exact_match(struct net_device
*dev
);
139 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
);
141 extern const struct ethtool_ops gfar_ethtool_ops
;
143 MODULE_AUTHOR("Freescale Semiconductor, Inc");
144 MODULE_DESCRIPTION("Gianfar Ethernet Driver");
145 MODULE_LICENSE("GPL");
147 /* Returns 1 if incoming frames use an FCB */
148 static inline int gfar_uses_fcb(struct gfar_private
*priv
)
150 return (priv
->vlan_enable
|| priv
->rx_csum_enable
);
153 /* Set up the ethernet device structure, private data,
154 * and anything else we need before we start */
155 static int gfar_probe(struct platform_device
*pdev
)
158 struct net_device
*dev
= NULL
;
159 struct gfar_private
*priv
= NULL
;
160 struct gianfar_platform_data
*einfo
;
163 DECLARE_MAC_BUF(mac
);
165 einfo
= (struct gianfar_platform_data
*) pdev
->dev
.platform_data
;
168 printk(KERN_ERR
"gfar %d: Missing additional data!\n",
174 /* Create an ethernet device instance */
175 dev
= alloc_etherdev(sizeof (*priv
));
180 priv
= netdev_priv(dev
);
183 /* Set the info in the priv to the current info */
186 /* fill out IRQ fields */
187 if (einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
188 priv
->interruptTransmit
= platform_get_irq_byname(pdev
, "tx");
189 priv
->interruptReceive
= platform_get_irq_byname(pdev
, "rx");
190 priv
->interruptError
= platform_get_irq_byname(pdev
, "error");
191 if (priv
->interruptTransmit
< 0 || priv
->interruptReceive
< 0 || priv
->interruptError
< 0)
194 priv
->interruptTransmit
= platform_get_irq(pdev
, 0);
195 if (priv
->interruptTransmit
< 0)
199 /* get a pointer to the register memory */
200 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
201 priv
->regs
= ioremap(r
->start
, sizeof (struct gfar
));
203 if (NULL
== priv
->regs
) {
208 spin_lock_init(&priv
->txlock
);
209 spin_lock_init(&priv
->rxlock
);
211 platform_set_drvdata(pdev
, dev
);
213 /* Stop the DMA engine now, in case it was running before */
214 /* (The firmware could have used it, and left it running). */
215 /* To do this, we write Graceful Receive Stop and Graceful */
216 /* Transmit Stop, and then wait until the corresponding bits */
217 /* in IEVENT indicate the stops have completed. */
218 tempval
= gfar_read(&priv
->regs
->dmactrl
);
219 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
220 gfar_write(&priv
->regs
->dmactrl
, tempval
);
222 tempval
= gfar_read(&priv
->regs
->dmactrl
);
223 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
224 gfar_write(&priv
->regs
->dmactrl
, tempval
);
226 while (!(gfar_read(&priv
->regs
->ievent
) & (IEVENT_GRSC
| IEVENT_GTSC
)))
229 /* Reset MAC layer */
230 gfar_write(&priv
->regs
->maccfg1
, MACCFG1_SOFT_RESET
);
232 tempval
= (MACCFG1_TX_FLOW
| MACCFG1_RX_FLOW
);
233 gfar_write(&priv
->regs
->maccfg1
, tempval
);
235 /* Initialize MACCFG2. */
236 gfar_write(&priv
->regs
->maccfg2
, MACCFG2_INIT_SETTINGS
);
238 /* Initialize ECNTRL */
239 gfar_write(&priv
->regs
->ecntrl
, ECNTRL_INIT_SETTINGS
);
241 /* Copy the station address into the dev structure, */
242 memcpy(dev
->dev_addr
, einfo
->mac_addr
, MAC_ADDR_LEN
);
244 /* Set the dev->base_addr to the gfar reg region */
245 dev
->base_addr
= (unsigned long) (priv
->regs
);
247 SET_NETDEV_DEV(dev
, &pdev
->dev
);
249 /* Fill in the dev structure */
250 dev
->open
= gfar_enet_open
;
251 dev
->hard_start_xmit
= gfar_start_xmit
;
252 dev
->tx_timeout
= gfar_timeout
;
253 dev
->watchdog_timeo
= TX_TIMEOUT
;
254 netif_napi_add(dev
, &priv
->napi
, gfar_poll
, GFAR_DEV_WEIGHT
);
255 #ifdef CONFIG_NET_POLL_CONTROLLER
256 dev
->poll_controller
= gfar_netpoll
;
258 dev
->stop
= gfar_close
;
259 dev
->change_mtu
= gfar_change_mtu
;
261 dev
->set_multicast_list
= gfar_set_multi
;
263 dev
->ethtool_ops
= &gfar_ethtool_ops
;
265 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_CSUM
) {
266 priv
->rx_csum_enable
= 1;
267 dev
->features
|= NETIF_F_IP_CSUM
;
269 priv
->rx_csum_enable
= 0;
273 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_VLAN
) {
274 dev
->vlan_rx_register
= gfar_vlan_rx_register
;
276 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
278 priv
->vlan_enable
= 1;
281 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_EXTENDED_HASH
) {
282 priv
->extended_hash
= 1;
283 priv
->hash_width
= 9;
285 priv
->hash_regs
[0] = &priv
->regs
->igaddr0
;
286 priv
->hash_regs
[1] = &priv
->regs
->igaddr1
;
287 priv
->hash_regs
[2] = &priv
->regs
->igaddr2
;
288 priv
->hash_regs
[3] = &priv
->regs
->igaddr3
;
289 priv
->hash_regs
[4] = &priv
->regs
->igaddr4
;
290 priv
->hash_regs
[5] = &priv
->regs
->igaddr5
;
291 priv
->hash_regs
[6] = &priv
->regs
->igaddr6
;
292 priv
->hash_regs
[7] = &priv
->regs
->igaddr7
;
293 priv
->hash_regs
[8] = &priv
->regs
->gaddr0
;
294 priv
->hash_regs
[9] = &priv
->regs
->gaddr1
;
295 priv
->hash_regs
[10] = &priv
->regs
->gaddr2
;
296 priv
->hash_regs
[11] = &priv
->regs
->gaddr3
;
297 priv
->hash_regs
[12] = &priv
->regs
->gaddr4
;
298 priv
->hash_regs
[13] = &priv
->regs
->gaddr5
;
299 priv
->hash_regs
[14] = &priv
->regs
->gaddr6
;
300 priv
->hash_regs
[15] = &priv
->regs
->gaddr7
;
303 priv
->extended_hash
= 0;
304 priv
->hash_width
= 8;
306 priv
->hash_regs
[0] = &priv
->regs
->gaddr0
;
307 priv
->hash_regs
[1] = &priv
->regs
->gaddr1
;
308 priv
->hash_regs
[2] = &priv
->regs
->gaddr2
;
309 priv
->hash_regs
[3] = &priv
->regs
->gaddr3
;
310 priv
->hash_regs
[4] = &priv
->regs
->gaddr4
;
311 priv
->hash_regs
[5] = &priv
->regs
->gaddr5
;
312 priv
->hash_regs
[6] = &priv
->regs
->gaddr6
;
313 priv
->hash_regs
[7] = &priv
->regs
->gaddr7
;
316 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_PADDING
)
317 priv
->padding
= DEFAULT_PADDING
;
321 if (dev
->features
& NETIF_F_IP_CSUM
)
322 dev
->hard_header_len
+= GMAC_FCB_LEN
;
324 priv
->rx_buffer_size
= DEFAULT_RX_BUFFER_SIZE
;
325 priv
->tx_ring_size
= DEFAULT_TX_RING_SIZE
;
326 priv
->rx_ring_size
= DEFAULT_RX_RING_SIZE
;
328 priv
->txcoalescing
= DEFAULT_TX_COALESCE
;
329 priv
->txcount
= DEFAULT_TXCOUNT
;
330 priv
->txtime
= DEFAULT_TXTIME
;
331 priv
->rxcoalescing
= DEFAULT_RX_COALESCE
;
332 priv
->rxcount
= DEFAULT_RXCOUNT
;
333 priv
->rxtime
= DEFAULT_RXTIME
;
335 /* Enable most messages by default */
336 priv
->msg_enable
= (NETIF_MSG_IFUP
<< 1 ) - 1;
338 err
= register_netdev(dev
);
341 printk(KERN_ERR
"%s: Cannot register net device, aborting.\n",
346 /* Create all the sysfs files */
347 gfar_init_sysfs(dev
);
349 /* Print out the device info */
350 printk(KERN_INFO DEVICE_NAME
"%s\n",
351 dev
->name
, print_mac(mac
, dev
->dev_addr
));
353 /* Even more device info helps when determining which kernel */
354 /* provided which set of benchmarks. */
355 printk(KERN_INFO
"%s: Running with NAPI enabled\n", dev
->name
);
356 printk(KERN_INFO
"%s: %d/%d RX/TX BD ring size\n",
357 dev
->name
, priv
->rx_ring_size
, priv
->tx_ring_size
);
368 static int gfar_remove(struct platform_device
*pdev
)
370 struct net_device
*dev
= platform_get_drvdata(pdev
);
371 struct gfar_private
*priv
= netdev_priv(dev
);
373 platform_set_drvdata(pdev
, NULL
);
382 /* Reads the controller's registers to determine what interface
383 * connects it to the PHY.
385 static phy_interface_t
gfar_get_interface(struct net_device
*dev
)
387 struct gfar_private
*priv
= netdev_priv(dev
);
388 u32 ecntrl
= gfar_read(&priv
->regs
->ecntrl
);
390 if (ecntrl
& ECNTRL_SGMII_MODE
)
391 return PHY_INTERFACE_MODE_SGMII
;
393 if (ecntrl
& ECNTRL_TBI_MODE
) {
394 if (ecntrl
& ECNTRL_REDUCED_MODE
)
395 return PHY_INTERFACE_MODE_RTBI
;
397 return PHY_INTERFACE_MODE_TBI
;
400 if (ecntrl
& ECNTRL_REDUCED_MODE
) {
401 if (ecntrl
& ECNTRL_REDUCED_MII_MODE
)
402 return PHY_INTERFACE_MODE_RMII
;
404 phy_interface_t interface
= priv
->einfo
->interface
;
407 * This isn't autodetected right now, so it must
408 * be set by the device tree or platform code.
410 if (interface
== PHY_INTERFACE_MODE_RGMII_ID
)
411 return PHY_INTERFACE_MODE_RGMII_ID
;
413 return PHY_INTERFACE_MODE_RGMII
;
417 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
)
418 return PHY_INTERFACE_MODE_GMII
;
420 return PHY_INTERFACE_MODE_MII
;
424 /* Initializes driver's PHY state, and attaches to the PHY.
425 * Returns 0 on success.
427 static int init_phy(struct net_device
*dev
)
429 struct gfar_private
*priv
= netdev_priv(dev
);
430 uint gigabit_support
=
431 priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_GIGABIT
?
432 SUPPORTED_1000baseT_Full
: 0;
433 struct phy_device
*phydev
;
434 char phy_id
[BUS_ID_SIZE
];
435 phy_interface_t interface
;
439 priv
->oldduplex
= -1;
441 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->einfo
->bus_id
, priv
->einfo
->phy_id
);
443 interface
= gfar_get_interface(dev
);
445 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, interface
);
447 if (interface
== PHY_INTERFACE_MODE_SGMII
)
448 gfar_configure_serdes(dev
);
450 if (IS_ERR(phydev
)) {
451 printk(KERN_ERR
"%s: Could not attach to PHY\n", dev
->name
);
452 return PTR_ERR(phydev
);
455 /* Remove any features not supported by the controller */
456 phydev
->supported
&= (GFAR_SUPPORTED
| gigabit_support
);
457 phydev
->advertising
= phydev
->supported
;
459 priv
->phydev
= phydev
;
465 * Initialize TBI PHY interface for communicating with the
466 * SERDES lynx PHY on the chip. We communicate with this PHY
467 * through the MDIO bus on each controller, treating it as a
468 * "normal" PHY at the address found in the TBIPA register. We assume
469 * that the TBIPA register is valid. Either the MDIO bus code will set
470 * it to a value that doesn't conflict with other PHYs on the bus, or the
471 * value doesn't matter, as there are no other PHYs on the bus.
473 static void gfar_configure_serdes(struct net_device
*dev
)
475 struct gfar_private
*priv
= netdev_priv(dev
);
476 struct gfar_mii __iomem
*regs
=
477 (void __iomem
*)&priv
->regs
->gfar_mii_regs
;
478 int tbipa
= gfar_read(&priv
->regs
->tbipa
);
480 /* Single clk mode, mii mode off(for serdes communication) */
481 gfar_local_mdio_write(regs
, tbipa
, MII_TBICON
, TBICON_CLK_SELECT
);
483 gfar_local_mdio_write(regs
, tbipa
, MII_ADVERTISE
,
484 ADVERTISE_1000XFULL
| ADVERTISE_1000XPAUSE
|
485 ADVERTISE_1000XPSE_ASYM
);
487 gfar_local_mdio_write(regs
, tbipa
, MII_BMCR
, BMCR_ANENABLE
|
488 BMCR_ANRESTART
| BMCR_FULLDPLX
| BMCR_SPEED1000
);
491 static void init_registers(struct net_device
*dev
)
493 struct gfar_private
*priv
= netdev_priv(dev
);
496 gfar_write(&priv
->regs
->ievent
, IEVENT_INIT_CLEAR
);
498 /* Initialize IMASK */
499 gfar_write(&priv
->regs
->imask
, IMASK_INIT_CLEAR
);
501 /* Init hash registers to zero */
502 gfar_write(&priv
->regs
->igaddr0
, 0);
503 gfar_write(&priv
->regs
->igaddr1
, 0);
504 gfar_write(&priv
->regs
->igaddr2
, 0);
505 gfar_write(&priv
->regs
->igaddr3
, 0);
506 gfar_write(&priv
->regs
->igaddr4
, 0);
507 gfar_write(&priv
->regs
->igaddr5
, 0);
508 gfar_write(&priv
->regs
->igaddr6
, 0);
509 gfar_write(&priv
->regs
->igaddr7
, 0);
511 gfar_write(&priv
->regs
->gaddr0
, 0);
512 gfar_write(&priv
->regs
->gaddr1
, 0);
513 gfar_write(&priv
->regs
->gaddr2
, 0);
514 gfar_write(&priv
->regs
->gaddr3
, 0);
515 gfar_write(&priv
->regs
->gaddr4
, 0);
516 gfar_write(&priv
->regs
->gaddr5
, 0);
517 gfar_write(&priv
->regs
->gaddr6
, 0);
518 gfar_write(&priv
->regs
->gaddr7
, 0);
520 /* Zero out the rmon mib registers if it has them */
521 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_RMON
) {
522 memset_io(&(priv
->regs
->rmon
), 0, sizeof (struct rmon_mib
));
524 /* Mask off the CAM interrupts */
525 gfar_write(&priv
->regs
->rmon
.cam1
, 0xffffffff);
526 gfar_write(&priv
->regs
->rmon
.cam2
, 0xffffffff);
529 /* Initialize the max receive buffer length */
530 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
532 /* Initialize the Minimum Frame Length Register */
533 gfar_write(&priv
->regs
->minflr
, MINFLR_INIT_SETTINGS
);
537 /* Halt the receive and transmit queues */
538 void gfar_halt(struct net_device
*dev
)
540 struct gfar_private
*priv
= netdev_priv(dev
);
541 struct gfar __iomem
*regs
= priv
->regs
;
544 /* Mask all interrupts */
545 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
547 /* Clear all interrupts */
548 gfar_write(®s
->ievent
, IEVENT_INIT_CLEAR
);
550 /* Stop the DMA, and wait for it to stop */
551 tempval
= gfar_read(&priv
->regs
->dmactrl
);
552 if ((tempval
& (DMACTRL_GRS
| DMACTRL_GTS
))
553 != (DMACTRL_GRS
| DMACTRL_GTS
)) {
554 tempval
|= (DMACTRL_GRS
| DMACTRL_GTS
);
555 gfar_write(&priv
->regs
->dmactrl
, tempval
);
557 while (!(gfar_read(&priv
->regs
->ievent
) &
558 (IEVENT_GRSC
| IEVENT_GTSC
)))
562 /* Disable Rx and Tx */
563 tempval
= gfar_read(®s
->maccfg1
);
564 tempval
&= ~(MACCFG1_RX_EN
| MACCFG1_TX_EN
);
565 gfar_write(®s
->maccfg1
, tempval
);
568 void stop_gfar(struct net_device
*dev
)
570 struct gfar_private
*priv
= netdev_priv(dev
);
571 struct gfar __iomem
*regs
= priv
->regs
;
574 phy_stop(priv
->phydev
);
577 spin_lock_irqsave(&priv
->txlock
, flags
);
578 spin_lock(&priv
->rxlock
);
582 spin_unlock(&priv
->rxlock
);
583 spin_unlock_irqrestore(&priv
->txlock
, flags
);
586 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
587 free_irq(priv
->interruptError
, dev
);
588 free_irq(priv
->interruptTransmit
, dev
);
589 free_irq(priv
->interruptReceive
, dev
);
591 free_irq(priv
->interruptTransmit
, dev
);
594 free_skb_resources(priv
);
596 dma_free_coherent(&dev
->dev
,
597 sizeof(struct txbd8
)*priv
->tx_ring_size
598 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
600 gfar_read(®s
->tbase0
));
603 /* If there are any tx skbs or rx skbs still around, free them.
604 * Then free tx_skbuff and rx_skbuff */
605 static void free_skb_resources(struct gfar_private
*priv
)
611 /* Go through all the buffer descriptors and free their data buffers */
612 txbdp
= priv
->tx_bd_base
;
614 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
616 if (priv
->tx_skbuff
[i
]) {
617 dma_unmap_single(&priv
->dev
->dev
, txbdp
->bufPtr
,
620 dev_kfree_skb_any(priv
->tx_skbuff
[i
]);
621 priv
->tx_skbuff
[i
] = NULL
;
627 kfree(priv
->tx_skbuff
);
629 rxbdp
= priv
->rx_bd_base
;
631 /* rx_skbuff is not guaranteed to be allocated, so only
632 * free it and its contents if it is allocated */
633 if(priv
->rx_skbuff
!= NULL
) {
634 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
635 if (priv
->rx_skbuff
[i
]) {
636 dma_unmap_single(&priv
->dev
->dev
, rxbdp
->bufPtr
,
637 priv
->rx_buffer_size
,
640 dev_kfree_skb_any(priv
->rx_skbuff
[i
]);
641 priv
->rx_skbuff
[i
] = NULL
;
651 kfree(priv
->rx_skbuff
);
655 void gfar_start(struct net_device
*dev
)
657 struct gfar_private
*priv
= netdev_priv(dev
);
658 struct gfar __iomem
*regs
= priv
->regs
;
661 /* Enable Rx and Tx in MACCFG1 */
662 tempval
= gfar_read(®s
->maccfg1
);
663 tempval
|= (MACCFG1_RX_EN
| MACCFG1_TX_EN
);
664 gfar_write(®s
->maccfg1
, tempval
);
666 /* Initialize DMACTRL to have WWR and WOP */
667 tempval
= gfar_read(&priv
->regs
->dmactrl
);
668 tempval
|= DMACTRL_INIT_SETTINGS
;
669 gfar_write(&priv
->regs
->dmactrl
, tempval
);
671 /* Make sure we aren't stopped */
672 tempval
= gfar_read(&priv
->regs
->dmactrl
);
673 tempval
&= ~(DMACTRL_GRS
| DMACTRL_GTS
);
674 gfar_write(&priv
->regs
->dmactrl
, tempval
);
676 /* Clear THLT/RHLT, so that the DMA starts polling now */
677 gfar_write(®s
->tstat
, TSTAT_CLEAR_THALT
);
678 gfar_write(®s
->rstat
, RSTAT_CLEAR_RHALT
);
680 /* Unmask the interrupts we look for */
681 gfar_write(®s
->imask
, IMASK_DEFAULT
);
684 /* Bring the controller up and running */
685 int startup_gfar(struct net_device
*dev
)
692 struct gfar_private
*priv
= netdev_priv(dev
);
693 struct gfar __iomem
*regs
= priv
->regs
;
698 gfar_write(®s
->imask
, IMASK_INIT_CLEAR
);
700 /* Allocate memory for the buffer descriptors */
701 vaddr
= (unsigned long) dma_alloc_coherent(&dev
->dev
,
702 sizeof (struct txbd8
) * priv
->tx_ring_size
+
703 sizeof (struct rxbd8
) * priv
->rx_ring_size
,
707 if (netif_msg_ifup(priv
))
708 printk(KERN_ERR
"%s: Could not allocate buffer descriptors!\n",
713 priv
->tx_bd_base
= (struct txbd8
*) vaddr
;
715 /* enet DMA only understands physical addresses */
716 gfar_write(®s
->tbase0
, addr
);
718 /* Start the rx descriptor ring where the tx ring leaves off */
719 addr
= addr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
720 vaddr
= vaddr
+ sizeof (struct txbd8
) * priv
->tx_ring_size
;
721 priv
->rx_bd_base
= (struct rxbd8
*) vaddr
;
722 gfar_write(®s
->rbase0
, addr
);
724 /* Setup the skbuff rings */
726 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
727 priv
->tx_ring_size
, GFP_KERNEL
);
729 if (NULL
== priv
->tx_skbuff
) {
730 if (netif_msg_ifup(priv
))
731 printk(KERN_ERR
"%s: Could not allocate tx_skbuff\n",
737 for (i
= 0; i
< priv
->tx_ring_size
; i
++)
738 priv
->tx_skbuff
[i
] = NULL
;
741 (struct sk_buff
**) kmalloc(sizeof (struct sk_buff
*) *
742 priv
->rx_ring_size
, GFP_KERNEL
);
744 if (NULL
== priv
->rx_skbuff
) {
745 if (netif_msg_ifup(priv
))
746 printk(KERN_ERR
"%s: Could not allocate rx_skbuff\n",
752 for (i
= 0; i
< priv
->rx_ring_size
; i
++)
753 priv
->rx_skbuff
[i
] = NULL
;
755 /* Initialize some variables in our dev structure */
756 priv
->dirty_tx
= priv
->cur_tx
= priv
->tx_bd_base
;
757 priv
->cur_rx
= priv
->rx_bd_base
;
758 priv
->skb_curtx
= priv
->skb_dirtytx
= 0;
761 /* Initialize Transmit Descriptor Ring */
762 txbdp
= priv
->tx_bd_base
;
763 for (i
= 0; i
< priv
->tx_ring_size
; i
++) {
770 /* Set the last descriptor in the ring to indicate wrap */
772 txbdp
->status
|= TXBD_WRAP
;
774 rxbdp
= priv
->rx_bd_base
;
775 for (i
= 0; i
< priv
->rx_ring_size
; i
++) {
778 skb
= gfar_new_skb(dev
);
781 printk(KERN_ERR
"%s: Can't allocate RX buffers\n",
784 goto err_rxalloc_fail
;
787 priv
->rx_skbuff
[i
] = skb
;
789 gfar_new_rxbdp(dev
, rxbdp
, skb
);
794 /* Set the last descriptor in the ring to wrap */
796 rxbdp
->status
|= RXBD_WRAP
;
798 /* If the device has multiple interrupts, register for
799 * them. Otherwise, only register for the one */
800 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
801 /* Install our interrupt handlers for Error,
802 * Transmit, and Receive */
803 if (request_irq(priv
->interruptError
, gfar_error
,
804 0, "enet_error", dev
) < 0) {
805 if (netif_msg_intr(priv
))
806 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
807 dev
->name
, priv
->interruptError
);
813 if (request_irq(priv
->interruptTransmit
, gfar_transmit
,
814 0, "enet_tx", dev
) < 0) {
815 if (netif_msg_intr(priv
))
816 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
817 dev
->name
, priv
->interruptTransmit
);
824 if (request_irq(priv
->interruptReceive
, gfar_receive
,
825 0, "enet_rx", dev
) < 0) {
826 if (netif_msg_intr(priv
))
827 printk(KERN_ERR
"%s: Can't get IRQ %d (receive0)\n",
828 dev
->name
, priv
->interruptReceive
);
834 if (request_irq(priv
->interruptTransmit
, gfar_interrupt
,
835 0, "gfar_interrupt", dev
) < 0) {
836 if (netif_msg_intr(priv
))
837 printk(KERN_ERR
"%s: Can't get IRQ %d\n",
838 dev
->name
, priv
->interruptError
);
845 phy_start(priv
->phydev
);
847 /* Configure the coalescing support */
848 if (priv
->txcoalescing
)
849 gfar_write(®s
->txic
,
850 mk_ic_value(priv
->txcount
, priv
->txtime
));
852 gfar_write(®s
->txic
, 0);
854 if (priv
->rxcoalescing
)
855 gfar_write(®s
->rxic
,
856 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
858 gfar_write(®s
->rxic
, 0);
860 if (priv
->rx_csum_enable
)
861 rctrl
|= RCTRL_CHECKSUMMING
;
863 if (priv
->extended_hash
) {
864 rctrl
|= RCTRL_EXTHASH
;
866 gfar_clear_exact_match(dev
);
870 if (priv
->vlan_enable
)
874 rctrl
&= ~RCTRL_PAL_MASK
;
875 rctrl
|= RCTRL_PADDING(priv
->padding
);
878 /* Init rctrl based on our settings */
879 gfar_write(&priv
->regs
->rctrl
, rctrl
);
881 if (dev
->features
& NETIF_F_IP_CSUM
)
882 gfar_write(&priv
->regs
->tctrl
, TCTRL_INIT_CSUM
);
884 /* Set the extraction length and index */
885 attrs
= ATTRELI_EL(priv
->rx_stash_size
) |
886 ATTRELI_EI(priv
->rx_stash_index
);
888 gfar_write(&priv
->regs
->attreli
, attrs
);
890 /* Start with defaults, and add stashing or locking
891 * depending on the approprate variables */
892 attrs
= ATTR_INIT_SETTINGS
;
894 if (priv
->bd_stash_en
)
895 attrs
|= ATTR_BDSTASH
;
897 if (priv
->rx_stash_size
!= 0)
898 attrs
|= ATTR_BUFSTASH
;
900 gfar_write(&priv
->regs
->attr
, attrs
);
902 gfar_write(&priv
->regs
->fifo_tx_thr
, priv
->fifo_threshold
);
903 gfar_write(&priv
->regs
->fifo_tx_starve
, priv
->fifo_starve
);
904 gfar_write(&priv
->regs
->fifo_tx_starve_shutoff
, priv
->fifo_starve_off
);
906 /* Start the controller */
912 free_irq(priv
->interruptTransmit
, dev
);
914 free_irq(priv
->interruptError
, dev
);
918 free_skb_resources(priv
);
920 dma_free_coherent(&dev
->dev
,
921 sizeof(struct txbd8
)*priv
->tx_ring_size
922 + sizeof(struct rxbd8
)*priv
->rx_ring_size
,
924 gfar_read(®s
->tbase0
));
929 /* Called when something needs to use the ethernet device */
930 /* Returns 0 for success. */
931 static int gfar_enet_open(struct net_device
*dev
)
933 struct gfar_private
*priv
= netdev_priv(dev
);
936 napi_enable(&priv
->napi
);
938 /* Initialize a bunch of registers */
941 gfar_set_mac_address(dev
);
946 napi_disable(&priv
->napi
);
950 err
= startup_gfar(dev
);
952 napi_disable(&priv
->napi
);
956 netif_start_queue(dev
);
961 static inline struct txfcb
*gfar_add_fcb(struct sk_buff
*skb
, struct txbd8
*bdp
)
963 struct txfcb
*fcb
= (struct txfcb
*)skb_push (skb
, GMAC_FCB_LEN
);
965 memset(fcb
, 0, GMAC_FCB_LEN
);
970 static inline void gfar_tx_checksum(struct sk_buff
*skb
, struct txfcb
*fcb
)
974 /* If we're here, it's a IP packet with a TCP or UDP
975 * payload. We set it to checksum, using a pseudo-header
978 flags
= TXFCB_DEFAULT
;
980 /* Tell the controller what the protocol is */
981 /* And provide the already calculated phcs */
982 if (ip_hdr(skb
)->protocol
== IPPROTO_UDP
) {
984 fcb
->phcs
= udp_hdr(skb
)->check
;
986 fcb
->phcs
= tcp_hdr(skb
)->check
;
988 /* l3os is the distance between the start of the
989 * frame (skb->data) and the start of the IP hdr.
990 * l4os is the distance between the start of the
991 * l3 hdr and the l4 hdr */
992 fcb
->l3os
= (u16
)(skb_network_offset(skb
) - GMAC_FCB_LEN
);
993 fcb
->l4os
= skb_network_header_len(skb
);
998 void inline gfar_tx_vlan(struct sk_buff
*skb
, struct txfcb
*fcb
)
1000 fcb
->flags
|= TXFCB_VLN
;
1001 fcb
->vlctl
= vlan_tx_tag_get(skb
);
1004 /* This is called by the kernel when a frame is ready for transmission. */
1005 /* It is pointed to by the dev->hard_start_xmit function pointer */
1006 static int gfar_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1008 struct gfar_private
*priv
= netdev_priv(dev
);
1009 struct txfcb
*fcb
= NULL
;
1010 struct txbd8
*txbdp
;
1012 unsigned long flags
;
1014 /* Update transmit stats */
1015 dev
->stats
.tx_bytes
+= skb
->len
;
1018 spin_lock_irqsave(&priv
->txlock
, flags
);
1020 /* Point at the first free tx descriptor */
1021 txbdp
= priv
->cur_tx
;
1023 /* Clear all but the WRAP status flags */
1024 status
= txbdp
->status
& TXBD_WRAP
;
1026 /* Set up checksumming */
1027 if (likely((dev
->features
& NETIF_F_IP_CSUM
)
1028 && (CHECKSUM_PARTIAL
== skb
->ip_summed
))) {
1029 fcb
= gfar_add_fcb(skb
, txbdp
);
1031 gfar_tx_checksum(skb
, fcb
);
1034 if (priv
->vlan_enable
&&
1035 unlikely(priv
->vlgrp
&& vlan_tx_tag_present(skb
))) {
1036 if (unlikely(NULL
== fcb
)) {
1037 fcb
= gfar_add_fcb(skb
, txbdp
);
1041 gfar_tx_vlan(skb
, fcb
);
1044 /* Set buffer length and pointer */
1045 txbdp
->length
= skb
->len
;
1046 txbdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1047 skb
->len
, DMA_TO_DEVICE
);
1049 /* Save the skb pointer so we can free it later */
1050 priv
->tx_skbuff
[priv
->skb_curtx
] = skb
;
1052 /* Update the current skb pointer (wrapping if this was the last) */
1054 (priv
->skb_curtx
+ 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1056 /* Flag the BD as interrupt-causing */
1057 status
|= TXBD_INTERRUPT
;
1059 /* Flag the BD as ready to go, last in frame, and */
1060 /* in need of CRC */
1061 status
|= (TXBD_READY
| TXBD_LAST
| TXBD_CRC
);
1063 dev
->trans_start
= jiffies
;
1065 /* The powerpc-specific eieio() is used, as wmb() has too strong
1066 * semantics (it requires synchronization between cacheable and
1067 * uncacheable mappings, which eieio doesn't provide and which we
1068 * don't need), thus requiring a more expensive sync instruction. At
1069 * some point, the set of architecture-independent barrier functions
1070 * should be expanded to include weaker barriers.
1074 txbdp
->status
= status
;
1076 /* If this was the last BD in the ring, the next one */
1077 /* is at the beginning of the ring */
1078 if (txbdp
->status
& TXBD_WRAP
)
1079 txbdp
= priv
->tx_bd_base
;
1083 /* If the next BD still needs to be cleaned up, then the bds
1084 are full. We need to tell the kernel to stop sending us stuff. */
1085 if (txbdp
== priv
->dirty_tx
) {
1086 netif_stop_queue(dev
);
1088 dev
->stats
.tx_fifo_errors
++;
1091 /* Update the current txbd to the next one */
1092 priv
->cur_tx
= txbdp
;
1094 /* Tell the DMA to go go go */
1095 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1098 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1103 /* Stops the kernel queue, and halts the controller */
1104 static int gfar_close(struct net_device
*dev
)
1106 struct gfar_private
*priv
= netdev_priv(dev
);
1108 napi_disable(&priv
->napi
);
1112 /* Disconnect from the PHY */
1113 phy_disconnect(priv
->phydev
);
1114 priv
->phydev
= NULL
;
1116 netif_stop_queue(dev
);
1121 /* Changes the mac address if the controller is not running. */
1122 static int gfar_set_mac_address(struct net_device
*dev
)
1124 gfar_set_mac_for_addr(dev
, 0, dev
->dev_addr
);
1130 /* Enables and disables VLAN insertion/extraction */
1131 static void gfar_vlan_rx_register(struct net_device
*dev
,
1132 struct vlan_group
*grp
)
1134 struct gfar_private
*priv
= netdev_priv(dev
);
1135 unsigned long flags
;
1138 spin_lock_irqsave(&priv
->rxlock
, flags
);
1143 /* Enable VLAN tag insertion */
1144 tempval
= gfar_read(&priv
->regs
->tctrl
);
1145 tempval
|= TCTRL_VLINS
;
1147 gfar_write(&priv
->regs
->tctrl
, tempval
);
1149 /* Enable VLAN tag extraction */
1150 tempval
= gfar_read(&priv
->regs
->rctrl
);
1151 tempval
|= RCTRL_VLEX
;
1152 gfar_write(&priv
->regs
->rctrl
, tempval
);
1154 /* Disable VLAN tag insertion */
1155 tempval
= gfar_read(&priv
->regs
->tctrl
);
1156 tempval
&= ~TCTRL_VLINS
;
1157 gfar_write(&priv
->regs
->tctrl
, tempval
);
1159 /* Disable VLAN tag extraction */
1160 tempval
= gfar_read(&priv
->regs
->rctrl
);
1161 tempval
&= ~RCTRL_VLEX
;
1162 gfar_write(&priv
->regs
->rctrl
, tempval
);
1165 spin_unlock_irqrestore(&priv
->rxlock
, flags
);
1168 static int gfar_change_mtu(struct net_device
*dev
, int new_mtu
)
1170 int tempsize
, tempval
;
1171 struct gfar_private
*priv
= netdev_priv(dev
);
1172 int oldsize
= priv
->rx_buffer_size
;
1173 int frame_size
= new_mtu
+ ETH_HLEN
;
1175 if (priv
->vlan_enable
)
1176 frame_size
+= VLAN_HLEN
;
1178 if (gfar_uses_fcb(priv
))
1179 frame_size
+= GMAC_FCB_LEN
;
1181 frame_size
+= priv
->padding
;
1183 if ((frame_size
< 64) || (frame_size
> JUMBO_FRAME_SIZE
)) {
1184 if (netif_msg_drv(priv
))
1185 printk(KERN_ERR
"%s: Invalid MTU setting\n",
1191 (frame_size
& ~(INCREMENTAL_BUFFER_SIZE
- 1)) +
1192 INCREMENTAL_BUFFER_SIZE
;
1194 /* Only stop and start the controller if it isn't already
1195 * stopped, and we changed something */
1196 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1199 priv
->rx_buffer_size
= tempsize
;
1203 gfar_write(&priv
->regs
->mrblr
, priv
->rx_buffer_size
);
1204 gfar_write(&priv
->regs
->maxfrm
, priv
->rx_buffer_size
);
1206 /* If the mtu is larger than the max size for standard
1207 * ethernet frames (ie, a jumbo frame), then set maccfg2
1208 * to allow huge frames, and to check the length */
1209 tempval
= gfar_read(&priv
->regs
->maccfg2
);
1211 if (priv
->rx_buffer_size
> DEFAULT_RX_BUFFER_SIZE
)
1212 tempval
|= (MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1214 tempval
&= ~(MACCFG2_HUGEFRAME
| MACCFG2_LENGTHCHECK
);
1216 gfar_write(&priv
->regs
->maccfg2
, tempval
);
1218 if ((oldsize
!= tempsize
) && (dev
->flags
& IFF_UP
))
1224 /* gfar_timeout gets called when a packet has not been
1225 * transmitted after a set amount of time.
1226 * For now, assume that clearing out all the structures, and
1227 * starting over will fix the problem. */
1228 static void gfar_timeout(struct net_device
*dev
)
1230 dev
->stats
.tx_errors
++;
1232 if (dev
->flags
& IFF_UP
) {
1237 netif_tx_schedule_all(dev
);
1240 /* Interrupt Handler for Transmit complete */
1241 static int gfar_clean_tx_ring(struct net_device
*dev
)
1244 struct gfar_private
*priv
= netdev_priv(dev
);
1247 bdp
= priv
->dirty_tx
;
1248 while ((bdp
->status
& TXBD_READY
) == 0) {
1249 /* If dirty_tx and cur_tx are the same, then either the */
1250 /* ring is empty or full now (it could only be full in the beginning, */
1251 /* obviously). If it is empty, we are done. */
1252 if ((bdp
== priv
->cur_tx
) && (netif_queue_stopped(dev
) == 0))
1257 /* Deferred means some collisions occurred during transmit, */
1258 /* but we eventually sent the packet. */
1259 if (bdp
->status
& TXBD_DEF
)
1260 dev
->stats
.collisions
++;
1262 /* Free the sk buffer associated with this TxBD */
1263 dev_kfree_skb_irq(priv
->tx_skbuff
[priv
->skb_dirtytx
]);
1265 priv
->tx_skbuff
[priv
->skb_dirtytx
] = NULL
;
1267 (priv
->skb_dirtytx
+
1268 1) & TX_RING_MOD_MASK(priv
->tx_ring_size
);
1270 /* Clean BD length for empty detection */
1273 /* update bdp to point at next bd in the ring (wrapping if necessary) */
1274 if (bdp
->status
& TXBD_WRAP
)
1275 bdp
= priv
->tx_bd_base
;
1279 /* Move dirty_tx to be the next bd */
1280 priv
->dirty_tx
= bdp
;
1282 /* We freed a buffer, so now we can restart transmission */
1283 if (netif_queue_stopped(dev
))
1284 netif_wake_queue(dev
);
1285 } /* while ((bdp->status & TXBD_READY) == 0) */
1287 dev
->stats
.tx_packets
+= howmany
;
1292 /* Interrupt Handler for Transmit complete */
1293 static irqreturn_t
gfar_transmit(int irq
, void *dev_id
)
1295 struct net_device
*dev
= (struct net_device
*) dev_id
;
1296 struct gfar_private
*priv
= netdev_priv(dev
);
1299 gfar_write(&priv
->regs
->ievent
, IEVENT_TX_MASK
);
1302 spin_lock(&priv
->txlock
);
1304 gfar_clean_tx_ring(dev
);
1306 /* If we are coalescing the interrupts, reset the timer */
1307 /* Otherwise, clear it */
1308 if (likely(priv
->txcoalescing
)) {
1309 gfar_write(&priv
->regs
->txic
, 0);
1310 gfar_write(&priv
->regs
->txic
,
1311 mk_ic_value(priv
->txcount
, priv
->txtime
));
1314 spin_unlock(&priv
->txlock
);
1319 static void gfar_new_rxbdp(struct net_device
*dev
, struct rxbd8
*bdp
,
1320 struct sk_buff
*skb
)
1322 struct gfar_private
*priv
= netdev_priv(dev
);
1323 u32
* status_len
= (u32
*)bdp
;
1326 bdp
->bufPtr
= dma_map_single(&dev
->dev
, skb
->data
,
1327 priv
->rx_buffer_size
, DMA_FROM_DEVICE
);
1329 flags
= RXBD_EMPTY
| RXBD_INTERRUPT
;
1331 if (bdp
== priv
->rx_bd_base
+ priv
->rx_ring_size
- 1)
1336 *status_len
= (u32
)flags
<< 16;
1340 struct sk_buff
* gfar_new_skb(struct net_device
*dev
)
1342 unsigned int alignamount
;
1343 struct gfar_private
*priv
= netdev_priv(dev
);
1344 struct sk_buff
*skb
= NULL
;
1346 /* We have to allocate the skb, so keep trying till we succeed */
1347 skb
= netdev_alloc_skb(dev
, priv
->rx_buffer_size
+ RXBUF_ALIGNMENT
);
1352 alignamount
= RXBUF_ALIGNMENT
-
1353 (((unsigned long) skb
->data
) & (RXBUF_ALIGNMENT
- 1));
1355 /* We need the data buffer to be aligned properly. We will reserve
1356 * as many bytes as needed to align the data properly
1358 skb_reserve(skb
, alignamount
);
1363 static inline void count_errors(unsigned short status
, struct net_device
*dev
)
1365 struct gfar_private
*priv
= netdev_priv(dev
);
1366 struct net_device_stats
*stats
= &dev
->stats
;
1367 struct gfar_extra_stats
*estats
= &priv
->extra_stats
;
1369 /* If the packet was truncated, none of the other errors
1371 if (status
& RXBD_TRUNCATED
) {
1372 stats
->rx_length_errors
++;
1378 /* Count the errors, if there were any */
1379 if (status
& (RXBD_LARGE
| RXBD_SHORT
)) {
1380 stats
->rx_length_errors
++;
1382 if (status
& RXBD_LARGE
)
1387 if (status
& RXBD_NONOCTET
) {
1388 stats
->rx_frame_errors
++;
1389 estats
->rx_nonoctet
++;
1391 if (status
& RXBD_CRCERR
) {
1392 estats
->rx_crcerr
++;
1393 stats
->rx_crc_errors
++;
1395 if (status
& RXBD_OVERRUN
) {
1396 estats
->rx_overrun
++;
1397 stats
->rx_crc_errors
++;
1401 irqreturn_t
gfar_receive(int irq
, void *dev_id
)
1403 struct net_device
*dev
= (struct net_device
*) dev_id
;
1404 struct gfar_private
*priv
= netdev_priv(dev
);
1408 /* Clear IEVENT, so interrupts aren't called again
1409 * because of the packets that have already arrived */
1410 gfar_write(&priv
->regs
->ievent
, IEVENT_RTX_MASK
);
1412 if (netif_rx_schedule_prep(dev
, &priv
->napi
)) {
1413 tempval
= gfar_read(&priv
->regs
->imask
);
1414 tempval
&= IMASK_RTX_DISABLED
;
1415 gfar_write(&priv
->regs
->imask
, tempval
);
1417 __netif_rx_schedule(dev
, &priv
->napi
);
1419 if (netif_msg_rx_err(priv
))
1420 printk(KERN_DEBUG
"%s: receive called twice (%x)[%x]\n",
1421 dev
->name
, gfar_read(&priv
->regs
->ievent
),
1422 gfar_read(&priv
->regs
->imask
));
1428 static inline void gfar_rx_checksum(struct sk_buff
*skb
, struct rxfcb
*fcb
)
1430 /* If valid headers were found, and valid sums
1431 * were verified, then we tell the kernel that no
1432 * checksumming is necessary. Otherwise, it is */
1433 if ((fcb
->flags
& RXFCB_CSUM_MASK
) == (RXFCB_CIP
| RXFCB_CTU
))
1434 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1436 skb
->ip_summed
= CHECKSUM_NONE
;
1440 static inline struct rxfcb
*gfar_get_fcb(struct sk_buff
*skb
)
1442 struct rxfcb
*fcb
= (struct rxfcb
*)skb
->data
;
1444 /* Remove the FCB from the skb */
1445 skb_pull(skb
, GMAC_FCB_LEN
);
1450 /* gfar_process_frame() -- handle one incoming packet if skb
1452 static int gfar_process_frame(struct net_device
*dev
, struct sk_buff
*skb
,
1455 struct gfar_private
*priv
= netdev_priv(dev
);
1456 struct rxfcb
*fcb
= NULL
;
1459 if (netif_msg_rx_err(priv
))
1460 printk(KERN_WARNING
"%s: Missing skb!!.\n", dev
->name
);
1461 dev
->stats
.rx_dropped
++;
1462 priv
->extra_stats
.rx_skbmissing
++;
1466 /* Prep the skb for the packet */
1467 skb_put(skb
, length
);
1469 /* Grab the FCB if there is one */
1470 if (gfar_uses_fcb(priv
))
1471 fcb
= gfar_get_fcb(skb
);
1473 /* Remove the padded bytes, if there are any */
1475 skb_pull(skb
, priv
->padding
);
1477 if (priv
->rx_csum_enable
)
1478 gfar_rx_checksum(skb
, fcb
);
1480 /* Tell the skb what kind of packet this is */
1481 skb
->protocol
= eth_type_trans(skb
, dev
);
1483 /* Send the packet up the stack */
1484 if (unlikely(priv
->vlgrp
&& (fcb
->flags
& RXFCB_VLN
))) {
1485 ret
= vlan_hwaccel_receive_skb(skb
, priv
->vlgrp
,
1488 ret
= netif_receive_skb(skb
);
1490 if (NET_RX_DROP
== ret
)
1491 priv
->extra_stats
.kernel_dropped
++;
1497 /* gfar_clean_rx_ring() -- Processes each frame in the rx ring
1498 * until the budget/quota has been reached. Returns the number
1501 int gfar_clean_rx_ring(struct net_device
*dev
, int rx_work_limit
)
1504 struct sk_buff
*skb
;
1507 struct gfar_private
*priv
= netdev_priv(dev
);
1509 /* Get the first full descriptor */
1512 while (!((bdp
->status
& RXBD_EMPTY
) || (--rx_work_limit
< 0))) {
1513 struct sk_buff
*newskb
;
1516 /* Add another skb for the future */
1517 newskb
= gfar_new_skb(dev
);
1519 skb
= priv
->rx_skbuff
[priv
->skb_currx
];
1521 /* We drop the frame if we failed to allocate a new buffer */
1522 if (unlikely(!newskb
|| !(bdp
->status
& RXBD_LAST
) ||
1523 bdp
->status
& RXBD_ERR
)) {
1524 count_errors(bdp
->status
, dev
);
1526 if (unlikely(!newskb
))
1530 dma_unmap_single(&priv
->dev
->dev
,
1532 priv
->rx_buffer_size
,
1535 dev_kfree_skb_any(skb
);
1538 /* Increment the number of packets */
1539 dev
->stats
.rx_packets
++;
1542 /* Remove the FCS from the packet length */
1543 pkt_len
= bdp
->length
- 4;
1545 gfar_process_frame(dev
, skb
, pkt_len
);
1547 dev
->stats
.rx_bytes
+= pkt_len
;
1550 dev
->last_rx
= jiffies
;
1552 priv
->rx_skbuff
[priv
->skb_currx
] = newskb
;
1554 /* Setup the new bdp */
1555 gfar_new_rxbdp(dev
, bdp
, newskb
);
1557 /* Update to the next pointer */
1558 if (bdp
->status
& RXBD_WRAP
)
1559 bdp
= priv
->rx_bd_base
;
1563 /* update to point at the next skb */
1565 (priv
->skb_currx
+ 1) &
1566 RX_RING_MOD_MASK(priv
->rx_ring_size
);
1569 /* Update the current rxbd pointer to be the next one */
1575 static int gfar_poll(struct napi_struct
*napi
, int budget
)
1577 struct gfar_private
*priv
= container_of(napi
, struct gfar_private
, napi
);
1578 struct net_device
*dev
= priv
->dev
;
1580 unsigned long flags
;
1582 /* If we fail to get the lock, don't bother with the TX BDs */
1583 if (spin_trylock_irqsave(&priv
->txlock
, flags
)) {
1584 gfar_clean_tx_ring(dev
);
1585 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1588 howmany
= gfar_clean_rx_ring(dev
, budget
);
1590 if (howmany
< budget
) {
1591 netif_rx_complete(dev
, napi
);
1593 /* Clear the halt bit in RSTAT */
1594 gfar_write(&priv
->regs
->rstat
, RSTAT_CLEAR_RHALT
);
1596 gfar_write(&priv
->regs
->imask
, IMASK_DEFAULT
);
1598 /* If we are coalescing interrupts, update the timer */
1599 /* Otherwise, clear it */
1600 if (likely(priv
->rxcoalescing
)) {
1601 gfar_write(&priv
->regs
->rxic
, 0);
1602 gfar_write(&priv
->regs
->rxic
,
1603 mk_ic_value(priv
->rxcount
, priv
->rxtime
));
1610 #ifdef CONFIG_NET_POLL_CONTROLLER
1612 * Polling 'interrupt' - used by things like netconsole to send skbs
1613 * without having to re-enable interrupts. It's not called while
1614 * the interrupt routine is executing.
1616 static void gfar_netpoll(struct net_device
*dev
)
1618 struct gfar_private
*priv
= netdev_priv(dev
);
1620 /* If the device has multiple interrupts, run tx/rx */
1621 if (priv
->einfo
->device_flags
& FSL_GIANFAR_DEV_HAS_MULTI_INTR
) {
1622 disable_irq(priv
->interruptTransmit
);
1623 disable_irq(priv
->interruptReceive
);
1624 disable_irq(priv
->interruptError
);
1625 gfar_interrupt(priv
->interruptTransmit
, dev
);
1626 enable_irq(priv
->interruptError
);
1627 enable_irq(priv
->interruptReceive
);
1628 enable_irq(priv
->interruptTransmit
);
1630 disable_irq(priv
->interruptTransmit
);
1631 gfar_interrupt(priv
->interruptTransmit
, dev
);
1632 enable_irq(priv
->interruptTransmit
);
1637 /* The interrupt handler for devices with one interrupt */
1638 static irqreturn_t
gfar_interrupt(int irq
, void *dev_id
)
1640 struct net_device
*dev
= dev_id
;
1641 struct gfar_private
*priv
= netdev_priv(dev
);
1643 /* Save ievent for future reference */
1644 u32 events
= gfar_read(&priv
->regs
->ievent
);
1646 /* Check for reception */
1647 if (events
& IEVENT_RX_MASK
)
1648 gfar_receive(irq
, dev_id
);
1650 /* Check for transmit completion */
1651 if (events
& IEVENT_TX_MASK
)
1652 gfar_transmit(irq
, dev_id
);
1654 /* Check for errors */
1655 if (events
& IEVENT_ERR_MASK
)
1656 gfar_error(irq
, dev_id
);
1661 /* Called every time the controller might need to be made
1662 * aware of new link state. The PHY code conveys this
1663 * information through variables in the phydev structure, and this
1664 * function converts those variables into the appropriate
1665 * register values, and can bring down the device if needed.
1667 static void adjust_link(struct net_device
*dev
)
1669 struct gfar_private
*priv
= netdev_priv(dev
);
1670 struct gfar __iomem
*regs
= priv
->regs
;
1671 unsigned long flags
;
1672 struct phy_device
*phydev
= priv
->phydev
;
1675 spin_lock_irqsave(&priv
->txlock
, flags
);
1677 u32 tempval
= gfar_read(®s
->maccfg2
);
1678 u32 ecntrl
= gfar_read(®s
->ecntrl
);
1680 /* Now we make sure that we can be in full duplex mode.
1681 * If not, we operate in half-duplex mode. */
1682 if (phydev
->duplex
!= priv
->oldduplex
) {
1684 if (!(phydev
->duplex
))
1685 tempval
&= ~(MACCFG2_FULL_DUPLEX
);
1687 tempval
|= MACCFG2_FULL_DUPLEX
;
1689 priv
->oldduplex
= phydev
->duplex
;
1692 if (phydev
->speed
!= priv
->oldspeed
) {
1694 switch (phydev
->speed
) {
1697 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_GMII
);
1702 ((tempval
& ~(MACCFG2_IF
)) | MACCFG2_MII
);
1704 /* Reduced mode distinguishes
1705 * between 10 and 100 */
1706 if (phydev
->speed
== SPEED_100
)
1707 ecntrl
|= ECNTRL_R100
;
1709 ecntrl
&= ~(ECNTRL_R100
);
1712 if (netif_msg_link(priv
))
1714 "%s: Ack! Speed (%d) is not 10/100/1000!\n",
1715 dev
->name
, phydev
->speed
);
1719 priv
->oldspeed
= phydev
->speed
;
1722 gfar_write(®s
->maccfg2
, tempval
);
1723 gfar_write(®s
->ecntrl
, ecntrl
);
1725 if (!priv
->oldlink
) {
1729 } else if (priv
->oldlink
) {
1733 priv
->oldduplex
= -1;
1736 if (new_state
&& netif_msg_link(priv
))
1737 phy_print_status(phydev
);
1739 spin_unlock_irqrestore(&priv
->txlock
, flags
);
1742 /* Update the hash table based on the current list of multicast
1743 * addresses we subscribe to. Also, change the promiscuity of
1744 * the device based on the flags (this function is called
1745 * whenever dev->flags is changed */
1746 static void gfar_set_multi(struct net_device
*dev
)
1748 struct dev_mc_list
*mc_ptr
;
1749 struct gfar_private
*priv
= netdev_priv(dev
);
1750 struct gfar __iomem
*regs
= priv
->regs
;
1753 if(dev
->flags
& IFF_PROMISC
) {
1754 /* Set RCTRL to PROM */
1755 tempval
= gfar_read(®s
->rctrl
);
1756 tempval
|= RCTRL_PROM
;
1757 gfar_write(®s
->rctrl
, tempval
);
1759 /* Set RCTRL to not PROM */
1760 tempval
= gfar_read(®s
->rctrl
);
1761 tempval
&= ~(RCTRL_PROM
);
1762 gfar_write(®s
->rctrl
, tempval
);
1765 if(dev
->flags
& IFF_ALLMULTI
) {
1766 /* Set the hash to rx all multicast frames */
1767 gfar_write(®s
->igaddr0
, 0xffffffff);
1768 gfar_write(®s
->igaddr1
, 0xffffffff);
1769 gfar_write(®s
->igaddr2
, 0xffffffff);
1770 gfar_write(®s
->igaddr3
, 0xffffffff);
1771 gfar_write(®s
->igaddr4
, 0xffffffff);
1772 gfar_write(®s
->igaddr5
, 0xffffffff);
1773 gfar_write(®s
->igaddr6
, 0xffffffff);
1774 gfar_write(®s
->igaddr7
, 0xffffffff);
1775 gfar_write(®s
->gaddr0
, 0xffffffff);
1776 gfar_write(®s
->gaddr1
, 0xffffffff);
1777 gfar_write(®s
->gaddr2
, 0xffffffff);
1778 gfar_write(®s
->gaddr3
, 0xffffffff);
1779 gfar_write(®s
->gaddr4
, 0xffffffff);
1780 gfar_write(®s
->gaddr5
, 0xffffffff);
1781 gfar_write(®s
->gaddr6
, 0xffffffff);
1782 gfar_write(®s
->gaddr7
, 0xffffffff);
1787 /* zero out the hash */
1788 gfar_write(®s
->igaddr0
, 0x0);
1789 gfar_write(®s
->igaddr1
, 0x0);
1790 gfar_write(®s
->igaddr2
, 0x0);
1791 gfar_write(®s
->igaddr3
, 0x0);
1792 gfar_write(®s
->igaddr4
, 0x0);
1793 gfar_write(®s
->igaddr5
, 0x0);
1794 gfar_write(®s
->igaddr6
, 0x0);
1795 gfar_write(®s
->igaddr7
, 0x0);
1796 gfar_write(®s
->gaddr0
, 0x0);
1797 gfar_write(®s
->gaddr1
, 0x0);
1798 gfar_write(®s
->gaddr2
, 0x0);
1799 gfar_write(®s
->gaddr3
, 0x0);
1800 gfar_write(®s
->gaddr4
, 0x0);
1801 gfar_write(®s
->gaddr5
, 0x0);
1802 gfar_write(®s
->gaddr6
, 0x0);
1803 gfar_write(®s
->gaddr7
, 0x0);
1805 /* If we have extended hash tables, we need to
1806 * clear the exact match registers to prepare for
1808 if (priv
->extended_hash
) {
1809 em_num
= GFAR_EM_NUM
+ 1;
1810 gfar_clear_exact_match(dev
);
1817 if(dev
->mc_count
== 0)
1820 /* Parse the list, and set the appropriate bits */
1821 for(mc_ptr
= dev
->mc_list
; mc_ptr
; mc_ptr
= mc_ptr
->next
) {
1823 gfar_set_mac_for_addr(dev
, idx
,
1827 gfar_set_hash_for_addr(dev
, mc_ptr
->dmi_addr
);
1835 /* Clears each of the exact match registers to zero, so they
1836 * don't interfere with normal reception */
1837 static void gfar_clear_exact_match(struct net_device
*dev
)
1840 u8 zero_arr
[MAC_ADDR_LEN
] = {0,0,0,0,0,0};
1842 for(idx
= 1;idx
< GFAR_EM_NUM
+ 1;idx
++)
1843 gfar_set_mac_for_addr(dev
, idx
, (u8
*)zero_arr
);
1846 /* Set the appropriate hash bit for the given addr */
1847 /* The algorithm works like so:
1848 * 1) Take the Destination Address (ie the multicast address), and
1849 * do a CRC on it (little endian), and reverse the bits of the
1851 * 2) Use the 8 most significant bits as a hash into a 256-entry
1852 * table. The table is controlled through 8 32-bit registers:
1853 * gaddr0-7. gaddr0's MSB is entry 0, and gaddr7's LSB is
1854 * gaddr7. This means that the 3 most significant bits in the
1855 * hash index which gaddr register to use, and the 5 other bits
1856 * indicate which bit (assuming an IBM numbering scheme, which
1857 * for PowerPC (tm) is usually the case) in the register holds
1859 static void gfar_set_hash_for_addr(struct net_device
*dev
, u8
*addr
)
1862 struct gfar_private
*priv
= netdev_priv(dev
);
1863 u32 result
= ether_crc(MAC_ADDR_LEN
, addr
);
1864 int width
= priv
->hash_width
;
1865 u8 whichbit
= (result
>> (32 - width
)) & 0x1f;
1866 u8 whichreg
= result
>> (32 - width
+ 5);
1867 u32 value
= (1 << (31-whichbit
));
1869 tempval
= gfar_read(priv
->hash_regs
[whichreg
]);
1871 gfar_write(priv
->hash_regs
[whichreg
], tempval
);
1877 /* There are multiple MAC Address register pairs on some controllers
1878 * This function sets the numth pair to a given address
1880 static void gfar_set_mac_for_addr(struct net_device
*dev
, int num
, u8
*addr
)
1882 struct gfar_private
*priv
= netdev_priv(dev
);
1884 char tmpbuf
[MAC_ADDR_LEN
];
1886 u32 __iomem
*macptr
= &priv
->regs
->macstnaddr1
;
1890 /* Now copy it into the mac registers backwards, cuz */
1891 /* little endian is silly */
1892 for (idx
= 0; idx
< MAC_ADDR_LEN
; idx
++)
1893 tmpbuf
[MAC_ADDR_LEN
- 1 - idx
] = addr
[idx
];
1895 gfar_write(macptr
, *((u32
*) (tmpbuf
)));
1897 tempval
= *((u32
*) (tmpbuf
+ 4));
1899 gfar_write(macptr
+1, tempval
);
1902 /* GFAR error interrupt handler */
1903 static irqreturn_t
gfar_error(int irq
, void *dev_id
)
1905 struct net_device
*dev
= dev_id
;
1906 struct gfar_private
*priv
= netdev_priv(dev
);
1908 /* Save ievent for future reference */
1909 u32 events
= gfar_read(&priv
->regs
->ievent
);
1912 gfar_write(&priv
->regs
->ievent
, IEVENT_ERR_MASK
);
1915 if (netif_msg_rx_err(priv
) || netif_msg_tx_err(priv
))
1916 printk(KERN_DEBUG
"%s: error interrupt (ievent=0x%08x imask=0x%08x)\n",
1917 dev
->name
, events
, gfar_read(&priv
->regs
->imask
));
1919 /* Update the error counters */
1920 if (events
& IEVENT_TXE
) {
1921 dev
->stats
.tx_errors
++;
1923 if (events
& IEVENT_LC
)
1924 dev
->stats
.tx_window_errors
++;
1925 if (events
& IEVENT_CRL
)
1926 dev
->stats
.tx_aborted_errors
++;
1927 if (events
& IEVENT_XFUN
) {
1928 if (netif_msg_tx_err(priv
))
1929 printk(KERN_DEBUG
"%s: TX FIFO underrun, "
1930 "packet dropped.\n", dev
->name
);
1931 dev
->stats
.tx_dropped
++;
1932 priv
->extra_stats
.tx_underrun
++;
1934 /* Reactivate the Tx Queues */
1935 gfar_write(&priv
->regs
->tstat
, TSTAT_CLEAR_THALT
);
1937 if (netif_msg_tx_err(priv
))
1938 printk(KERN_DEBUG
"%s: Transmit Error\n", dev
->name
);
1940 if (events
& IEVENT_BSY
) {
1941 dev
->stats
.rx_errors
++;
1942 priv
->extra_stats
.rx_bsy
++;
1944 gfar_receive(irq
, dev_id
);
1946 if (netif_msg_rx_err(priv
))
1947 printk(KERN_DEBUG
"%s: busy error (rstat: %x)\n",
1948 dev
->name
, gfar_read(&priv
->regs
->rstat
));
1950 if (events
& IEVENT_BABR
) {
1951 dev
->stats
.rx_errors
++;
1952 priv
->extra_stats
.rx_babr
++;
1954 if (netif_msg_rx_err(priv
))
1955 printk(KERN_DEBUG
"%s: babbling RX error\n", dev
->name
);
1957 if (events
& IEVENT_EBERR
) {
1958 priv
->extra_stats
.eberr
++;
1959 if (netif_msg_rx_err(priv
))
1960 printk(KERN_DEBUG
"%s: bus error\n", dev
->name
);
1962 if ((events
& IEVENT_RXC
) && netif_msg_rx_status(priv
))
1963 printk(KERN_DEBUG
"%s: control frame\n", dev
->name
);
1965 if (events
& IEVENT_BABT
) {
1966 priv
->extra_stats
.tx_babt
++;
1967 if (netif_msg_tx_err(priv
))
1968 printk(KERN_DEBUG
"%s: babbling TX error\n", dev
->name
);
1973 /* work with hotplug and coldplug */
1974 MODULE_ALIAS("platform:fsl-gianfar");
1976 /* Structure for a device driver */
1977 static struct platform_driver gfar_driver
= {
1978 .probe
= gfar_probe
,
1979 .remove
= gfar_remove
,
1981 .name
= "fsl-gianfar",
1982 .owner
= THIS_MODULE
,
1986 static int __init
gfar_init(void)
1988 int err
= gfar_mdio_init();
1993 err
= platform_driver_register(&gfar_driver
);
2001 static void __exit
gfar_exit(void)
2003 platform_driver_unregister(&gfar_driver
);
2007 module_init(gfar_init
);
2008 module_exit(gfar_exit
);