2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Ring initialization rules:
25 * 1. Each segment is initialized to zero, except for link TRBs.
26 * 2. Ring cycle state = 0. This represents Producer Cycle State (PCS) or
27 * Consumer Cycle State (CCS), depending on ring function.
28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
30 * Ring behavior rules:
31 * 1. A ring is empty if enqueue == dequeue. This means there will always be at
32 * least one free TRB in the ring. This is useful if you want to turn that
33 * into a link TRB and expand the ring.
34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
35 * link TRB, then load the pointer with the address in the link TRB. If the
36 * link TRB had its toggle bit set, you may need to update the ring cycle
37 * state (see cycle bit rules). You may have to do this multiple times
38 * until you reach a non-link TRB.
39 * 3. A ring is full if enqueue++ (for the definition of increment above)
40 * equals the dequeue pointer.
43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
44 * in a link TRB, it must toggle the ring cycle state.
45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
46 * in a link TRB, it must toggle the ring cycle state.
49 * 1. Check if ring is full before you enqueue.
50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
51 * Update enqueue pointer between each write (which may update the ring
53 * 3. Notify consumer. If SW is producer, it rings the doorbell for command
54 * and endpoint rings. If HC is the producer for the event ring,
55 * and it generates an interrupt according to interrupt modulation rules.
58 * 1. Check if TRB belongs to you. If the cycle bit == your ring cycle state,
59 * the TRB is owned by the consumer.
60 * 2. Update dequeue pointer (which may update the ring cycle state) and
61 * continue processing TRBs until you reach a TRB which is not owned by you.
62 * 3. Notify the producer. SW is the consumer for the event ring, and it
63 * updates event ring dequeue pointer. HC is the consumer for the command and
64 * endpoint rings; it generates events on the event ring for these.
67 #include <linux/scatterlist.h>
71 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
74 dma_addr_t
xhci_trb_virt_to_dma(struct xhci_segment
*seg
,
77 unsigned long segment_offset
;
79 if (!seg
|| !trb
|| trb
< seg
->trbs
)
82 segment_offset
= trb
- seg
->trbs
;
83 if (segment_offset
> TRBS_PER_SEGMENT
)
85 return seg
->dma
+ (segment_offset
* sizeof(*trb
));
88 /* Does this link TRB point to the first segment in a ring,
89 * or was the previous TRB the last TRB on the last segment in the ERST?
91 static inline bool last_trb_on_last_seg(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
92 struct xhci_segment
*seg
, union xhci_trb
*trb
)
94 if (ring
== xhci
->event_ring
)
95 return (trb
== &seg
->trbs
[TRBS_PER_SEGMENT
]) &&
96 (seg
->next
== xhci
->event_ring
->first_seg
);
98 return trb
->link
.control
& LINK_TOGGLE
;
101 /* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
102 * segment? I.e. would the updated event TRB pointer step off the end of the
105 static inline int last_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
106 struct xhci_segment
*seg
, union xhci_trb
*trb
)
108 if (ring
== xhci
->event_ring
)
109 return trb
== &seg
->trbs
[TRBS_PER_SEGMENT
];
111 return (trb
->link
.control
& TRB_TYPE_BITMASK
) == TRB_TYPE(TRB_LINK
);
114 /* Updates trb to point to the next TRB in the ring, and updates seg if the next
115 * TRB is in a new segment. This does not skip over link TRBs, and it does not
116 * effect the ring dequeue or enqueue pointers.
118 static void next_trb(struct xhci_hcd
*xhci
,
119 struct xhci_ring
*ring
,
120 struct xhci_segment
**seg
,
121 union xhci_trb
**trb
)
123 if (last_trb(xhci
, ring
, *seg
, *trb
)) {
125 *trb
= ((*seg
)->trbs
);
132 * See Cycle bit rules. SW is the consumer for the event ring only.
133 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
135 static void inc_deq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
137 union xhci_trb
*next
= ++(ring
->dequeue
);
138 unsigned long long addr
;
141 /* Update the dequeue pointer further if that was a link TRB or we're at
142 * the end of an event ring segment (which doesn't have link TRBS)
144 while (last_trb(xhci
, ring
, ring
->deq_seg
, next
)) {
145 if (consumer
&& last_trb_on_last_seg(xhci
, ring
, ring
->deq_seg
, next
)) {
146 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
148 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
150 (unsigned int) ring
->cycle_state
);
152 ring
->deq_seg
= ring
->deq_seg
->next
;
153 ring
->dequeue
= ring
->deq_seg
->trbs
;
154 next
= ring
->dequeue
;
156 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->deq_seg
, ring
->dequeue
);
157 if (ring
== xhci
->event_ring
)
158 xhci_dbg(xhci
, "Event ring deq = 0x%llx (DMA)\n", addr
);
159 else if (ring
== xhci
->cmd_ring
)
160 xhci_dbg(xhci
, "Command ring deq = 0x%llx (DMA)\n", addr
);
162 xhci_dbg(xhci
, "Ring deq = 0x%llx (DMA)\n", addr
);
166 * See Cycle bit rules. SW is the consumer for the event ring only.
167 * Don't make a ring full of link TRBs. That would be dumb and this would loop.
169 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
170 * chain bit is set), then set the chain bit in all the following link TRBs.
171 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
172 * have their chain bit cleared (so that each Link TRB is a separate TD).
174 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
175 * set, but other sections talk about dealing with the chain bit set. This was
176 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
177 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
179 static void inc_enq(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
, bool consumer
)
182 union xhci_trb
*next
;
183 unsigned long long addr
;
185 chain
= ring
->enqueue
->generic
.field
[3] & TRB_CHAIN
;
186 next
= ++(ring
->enqueue
);
189 /* Update the dequeue pointer further if that was a link TRB or we're at
190 * the end of an event ring segment (which doesn't have link TRBS)
192 while (last_trb(xhci
, ring
, ring
->enq_seg
, next
)) {
194 if (ring
!= xhci
->event_ring
) {
195 /* If we're not dealing with 0.95 hardware,
196 * carry over the chain bit of the previous TRB
197 * (which may mean the chain bit is cleared).
199 if (!xhci_link_trb_quirk(xhci
)) {
200 next
->link
.control
&= ~TRB_CHAIN
;
201 next
->link
.control
|= chain
;
203 /* Give this link TRB to the hardware */
205 if (next
->link
.control
& TRB_CYCLE
)
206 next
->link
.control
&= (u32
) ~TRB_CYCLE
;
208 next
->link
.control
|= (u32
) TRB_CYCLE
;
210 /* Toggle the cycle bit after the last ring segment. */
211 if (last_trb_on_last_seg(xhci
, ring
, ring
->enq_seg
, next
)) {
212 ring
->cycle_state
= (ring
->cycle_state
? 0 : 1);
214 xhci_dbg(xhci
, "Toggle cycle state for ring %p = %i\n",
216 (unsigned int) ring
->cycle_state
);
219 ring
->enq_seg
= ring
->enq_seg
->next
;
220 ring
->enqueue
= ring
->enq_seg
->trbs
;
221 next
= ring
->enqueue
;
223 addr
= (unsigned long long) xhci_trb_virt_to_dma(ring
->enq_seg
, ring
->enqueue
);
224 if (ring
== xhci
->event_ring
)
225 xhci_dbg(xhci
, "Event ring enq = 0x%llx (DMA)\n", addr
);
226 else if (ring
== xhci
->cmd_ring
)
227 xhci_dbg(xhci
, "Command ring enq = 0x%llx (DMA)\n", addr
);
229 xhci_dbg(xhci
, "Ring enq = 0x%llx (DMA)\n", addr
);
233 * Check to see if there's room to enqueue num_trbs on the ring. See rules
235 * FIXME: this would be simpler and faster if we just kept track of the number
236 * of free TRBs in a ring.
238 static int room_on_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
239 unsigned int num_trbs
)
242 union xhci_trb
*enq
= ring
->enqueue
;
243 struct xhci_segment
*enq_seg
= ring
->enq_seg
;
245 /* Check if ring is empty */
246 if (enq
== ring
->dequeue
)
248 /* Make sure there's an extra empty TRB available */
249 for (i
= 0; i
<= num_trbs
; ++i
) {
250 if (enq
== ring
->dequeue
)
253 while (last_trb(xhci
, ring
, enq_seg
, enq
)) {
254 enq_seg
= enq_seg
->next
;
261 void xhci_set_hc_event_deq(struct xhci_hcd
*xhci
)
266 deq
= xhci_trb_virt_to_dma(xhci
->event_ring
->deq_seg
,
267 xhci
->event_ring
->dequeue
);
268 if (deq
== 0 && !in_interrupt())
269 xhci_warn(xhci
, "WARN something wrong with SW event ring "
271 /* Update HC event ring dequeue pointer */
272 temp
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_dequeue
);
273 temp
&= ERST_PTR_MASK
;
274 /* Don't clear the EHB bit (which is RW1C) because
275 * there might be more events to service.
278 xhci_dbg(xhci
, "// Write event ring dequeue pointer, preserving EHB bit\n");
279 xhci_write_64(xhci
, ((u64
) deq
& (u64
) ~ERST_PTR_MASK
) | temp
,
280 &xhci
->ir_set
->erst_dequeue
);
283 /* Ring the host controller doorbell after placing a command on the ring */
284 void xhci_ring_cmd_db(struct xhci_hcd
*xhci
)
288 xhci_dbg(xhci
, "// Ding dong!\n");
289 temp
= xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]) & DB_MASK
;
290 xhci_writel(xhci
, temp
| DB_TARGET_HOST
, &xhci
->dba
->doorbell
[0]);
291 /* Flush PCI posted writes */
292 xhci_readl(xhci
, &xhci
->dba
->doorbell
[0]);
295 static void ring_ep_doorbell(struct xhci_hcd
*xhci
,
296 unsigned int slot_id
,
297 unsigned int ep_index
)
299 struct xhci_ring
*ep_ring
;
301 __u32 __iomem
*db_addr
= &xhci
->dba
->doorbell
[slot_id
];
303 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
304 /* Don't ring the doorbell for this endpoint if there are pending
305 * cancellations because the we don't want to interrupt processing.
307 if (!ep_ring
->cancels_pending
&& !(ep_ring
->state
& SET_DEQ_PENDING
)
308 && !(ep_ring
->state
& EP_HALTED
)) {
309 field
= xhci_readl(xhci
, db_addr
) & DB_MASK
;
310 xhci_writel(xhci
, field
| EPI_TO_DB(ep_index
), db_addr
);
311 /* Flush PCI posted writes - FIXME Matthew Wilcox says this
312 * isn't time-critical and we shouldn't make the CPU wait for
315 xhci_readl(xhci
, db_addr
);
320 * Find the segment that trb is in. Start searching in start_seg.
321 * If we must move past a segment that has a link TRB with a toggle cycle state
322 * bit set, then we will toggle the value pointed at by cycle_state.
324 static struct xhci_segment
*find_trb_seg(
325 struct xhci_segment
*start_seg
,
326 union xhci_trb
*trb
, int *cycle_state
)
328 struct xhci_segment
*cur_seg
= start_seg
;
329 struct xhci_generic_trb
*generic_trb
;
331 while (cur_seg
->trbs
> trb
||
332 &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1] < trb
) {
333 generic_trb
= &cur_seg
->trbs
[TRBS_PER_SEGMENT
- 1].generic
;
334 if (TRB_TYPE(generic_trb
->field
[3]) == TRB_LINK
&&
335 (generic_trb
->field
[3] & LINK_TOGGLE
))
336 *cycle_state
= ~(*cycle_state
) & 0x1;
337 cur_seg
= cur_seg
->next
;
338 if (cur_seg
== start_seg
)
339 /* Looped over the entire list. Oops! */
346 * Move the xHC's endpoint ring dequeue pointer past cur_td.
347 * Record the new state of the xHC's endpoint ring dequeue segment,
348 * dequeue pointer, and new consumer cycle state in state.
349 * Update our internal representation of the ring's dequeue pointer.
351 * We do this in three jumps:
352 * - First we update our new ring state to be the same as when the xHC stopped.
353 * - Then we traverse the ring to find the segment that contains
354 * the last TRB in the TD. We toggle the xHC's new cycle state when we pass
355 * any link TRBs with the toggle cycle bit set.
356 * - Finally we move the dequeue state one TRB further, toggling the cycle bit
357 * if we've moved it past a link TRB with the toggle cycle bit set.
359 void xhci_find_new_dequeue_state(struct xhci_hcd
*xhci
,
360 unsigned int slot_id
, unsigned int ep_index
,
361 struct xhci_td
*cur_td
, struct xhci_dequeue_state
*state
)
363 struct xhci_virt_device
*dev
= xhci
->devs
[slot_id
];
364 struct xhci_ring
*ep_ring
= dev
->ep_rings
[ep_index
];
365 struct xhci_generic_trb
*trb
;
366 struct xhci_ep_ctx
*ep_ctx
;
369 state
->new_cycle_state
= 0;
370 xhci_dbg(xhci
, "Finding segment containing stopped TRB.\n");
371 state
->new_deq_seg
= find_trb_seg(cur_td
->start_seg
,
372 ep_ring
->stopped_trb
,
373 &state
->new_cycle_state
);
374 if (!state
->new_deq_seg
)
376 /* Dig out the cycle state saved by the xHC during the stop ep cmd */
377 xhci_dbg(xhci
, "Finding endpoint context\n");
378 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
379 state
->new_cycle_state
= 0x1 & ep_ctx
->deq
;
381 state
->new_deq_ptr
= cur_td
->last_trb
;
382 xhci_dbg(xhci
, "Finding segment containing last TRB in TD.\n");
383 state
->new_deq_seg
= find_trb_seg(state
->new_deq_seg
,
385 &state
->new_cycle_state
);
386 if (!state
->new_deq_seg
)
389 trb
= &state
->new_deq_ptr
->generic
;
390 if (TRB_TYPE(trb
->field
[3]) == TRB_LINK
&&
391 (trb
->field
[3] & LINK_TOGGLE
))
392 state
->new_cycle_state
= ~(state
->new_cycle_state
) & 0x1;
393 next_trb(xhci
, ep_ring
, &state
->new_deq_seg
, &state
->new_deq_ptr
);
395 /* Don't update the ring cycle state for the producer (us). */
396 xhci_dbg(xhci
, "New dequeue segment = %p (virtual)\n",
398 addr
= xhci_trb_virt_to_dma(state
->new_deq_seg
, state
->new_deq_ptr
);
399 xhci_dbg(xhci
, "New dequeue pointer = 0x%llx (DMA)\n",
400 (unsigned long long) addr
);
401 xhci_dbg(xhci
, "Setting dequeue pointer in internal ring state.\n");
402 ep_ring
->dequeue
= state
->new_deq_ptr
;
403 ep_ring
->deq_seg
= state
->new_deq_seg
;
406 static void td_to_noop(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
407 struct xhci_td
*cur_td
)
409 struct xhci_segment
*cur_seg
;
410 union xhci_trb
*cur_trb
;
412 for (cur_seg
= cur_td
->start_seg
, cur_trb
= cur_td
->first_trb
;
414 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
415 if ((cur_trb
->generic
.field
[3] & TRB_TYPE_BITMASK
) ==
416 TRB_TYPE(TRB_LINK
)) {
417 /* Unchain any chained Link TRBs, but
418 * leave the pointers intact.
420 cur_trb
->generic
.field
[3] &= ~TRB_CHAIN
;
421 xhci_dbg(xhci
, "Cancel (unchain) link TRB\n");
422 xhci_dbg(xhci
, "Address = %p (0x%llx dma); "
423 "in seg %p (0x%llx dma)\n",
425 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
427 (unsigned long long)cur_seg
->dma
);
429 cur_trb
->generic
.field
[0] = 0;
430 cur_trb
->generic
.field
[1] = 0;
431 cur_trb
->generic
.field
[2] = 0;
432 /* Preserve only the cycle bit of this TRB */
433 cur_trb
->generic
.field
[3] &= TRB_CYCLE
;
434 cur_trb
->generic
.field
[3] |= TRB_TYPE(TRB_TR_NOOP
);
435 xhci_dbg(xhci
, "Cancel TRB %p (0x%llx dma) "
436 "in seg %p (0x%llx dma)\n",
438 (unsigned long long)xhci_trb_virt_to_dma(cur_seg
, cur_trb
),
440 (unsigned long long)cur_seg
->dma
);
442 if (cur_trb
== cur_td
->last_trb
)
447 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
448 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
449 union xhci_trb
*deq_ptr
, u32 cycle_state
);
451 void xhci_queue_new_dequeue_state(struct xhci_hcd
*xhci
,
452 struct xhci_ring
*ep_ring
, unsigned int slot_id
,
453 unsigned int ep_index
, struct xhci_dequeue_state
*deq_state
)
455 xhci_dbg(xhci
, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
456 "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
457 deq_state
->new_deq_seg
,
458 (unsigned long long)deq_state
->new_deq_seg
->dma
,
459 deq_state
->new_deq_ptr
,
460 (unsigned long long)xhci_trb_virt_to_dma(deq_state
->new_deq_seg
, deq_state
->new_deq_ptr
),
461 deq_state
->new_cycle_state
);
462 queue_set_tr_deq(xhci
, slot_id
, ep_index
,
463 deq_state
->new_deq_seg
,
464 deq_state
->new_deq_ptr
,
465 (u32
) deq_state
->new_cycle_state
);
466 /* Stop the TD queueing code from ringing the doorbell until
467 * this command completes. The HC won't set the dequeue pointer
468 * if the ring is running, and ringing the doorbell starts the
471 ep_ring
->state
|= SET_DEQ_PENDING
;
472 xhci_ring_cmd_db(xhci
);
476 * When we get a command completion for a Stop Endpoint Command, we need to
477 * unlink any cancelled TDs from the ring. There are two ways to do that:
479 * 1. If the HW was in the middle of processing the TD that needs to be
480 * cancelled, then we must move the ring's dequeue pointer past the last TRB
481 * in the TD with a Set Dequeue Pointer Command.
482 * 2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
483 * bit cleared) so that the HW will skip over them.
485 static void handle_stopped_endpoint(struct xhci_hcd
*xhci
,
488 unsigned int slot_id
;
489 unsigned int ep_index
;
490 struct xhci_ring
*ep_ring
;
491 struct list_head
*entry
;
492 struct xhci_td
*cur_td
= 0;
493 struct xhci_td
*last_unlinked_td
;
495 struct xhci_dequeue_state deq_state
;
496 #ifdef CONFIG_USB_HCD_STAT
497 ktime_t stop_time
= ktime_get();
500 memset(&deq_state
, 0, sizeof(deq_state
));
501 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
502 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
503 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
505 if (list_empty(&ep_ring
->cancelled_td_list
))
508 /* Fix up the ep ring first, so HW stops executing cancelled TDs.
509 * We have the xHCI lock, so nothing can modify this list until we drop
510 * it. We're also in the event handler, so we can't get re-interrupted
511 * if another Stop Endpoint command completes
513 list_for_each(entry
, &ep_ring
->cancelled_td_list
) {
514 cur_td
= list_entry(entry
, struct xhci_td
, cancelled_td_list
);
515 xhci_dbg(xhci
, "Cancelling TD starting at %p, 0x%llx (dma).\n",
517 (unsigned long long)xhci_trb_virt_to_dma(cur_td
->start_seg
, cur_td
->first_trb
));
519 * If we stopped on the TD we need to cancel, then we have to
520 * move the xHC endpoint ring dequeue pointer past this TD.
522 if (cur_td
== ep_ring
->stopped_td
)
523 xhci_find_new_dequeue_state(xhci
, slot_id
, ep_index
, cur_td
,
526 td_to_noop(xhci
, ep_ring
, cur_td
);
528 * The event handler won't see a completion for this TD anymore,
529 * so remove it from the endpoint ring's TD list. Keep it in
530 * the cancelled TD list for URB completion later.
532 list_del(&cur_td
->td_list
);
533 ep_ring
->cancels_pending
--;
535 last_unlinked_td
= cur_td
;
537 /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
538 if (deq_state
.new_deq_ptr
&& deq_state
.new_deq_seg
) {
539 xhci_queue_new_dequeue_state(xhci
, ep_ring
,
540 slot_id
, ep_index
, &deq_state
);
542 /* Otherwise just ring the doorbell to restart the ring */
543 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
547 * Drop the lock and complete the URBs in the cancelled TD list.
548 * New TDs to be cancelled might be added to the end of the list before
549 * we can complete all the URBs for the TDs we already unlinked.
550 * So stop when we've completed the URB for the last TD we unlinked.
553 cur_td
= list_entry(ep_ring
->cancelled_td_list
.next
,
554 struct xhci_td
, cancelled_td_list
);
555 list_del(&cur_td
->cancelled_td_list
);
557 /* Clean up the cancelled URB */
558 #ifdef CONFIG_USB_HCD_STAT
559 hcd_stat_update(xhci
->tp_stat
, cur_td
->urb
->actual_length
,
560 ktime_sub(stop_time
, cur_td
->start_time
));
562 cur_td
->urb
->hcpriv
= NULL
;
563 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), cur_td
->urb
);
565 xhci_dbg(xhci
, "Giveback cancelled URB %p\n", cur_td
->urb
);
566 spin_unlock(&xhci
->lock
);
567 /* Doesn't matter what we pass for status, since the core will
568 * just overwrite it (because the URB has been unlinked).
570 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), cur_td
->urb
, 0);
573 spin_lock(&xhci
->lock
);
574 } while (cur_td
!= last_unlinked_td
);
576 /* Return to the event handler with xhci->lock re-acquired */
580 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
581 * we need to clear the set deq pending flag in the endpoint ring state, so that
582 * the TD queueing code can ring the doorbell again. We also need to ring the
583 * endpoint doorbell to restart the ring, but only if there aren't more
584 * cancellations pending.
586 static void handle_set_deq_completion(struct xhci_hcd
*xhci
,
587 struct xhci_event_cmd
*event
,
590 unsigned int slot_id
;
591 unsigned int ep_index
;
592 struct xhci_ring
*ep_ring
;
593 struct xhci_virt_device
*dev
;
594 struct xhci_ep_ctx
*ep_ctx
;
595 struct xhci_slot_ctx
*slot_ctx
;
597 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
598 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
599 dev
= xhci
->devs
[slot_id
];
600 ep_ring
= dev
->ep_rings
[ep_index
];
601 ep_ctx
= xhci_get_ep_ctx(xhci
, dev
->out_ctx
, ep_index
);
602 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->out_ctx
);
604 if (GET_COMP_CODE(event
->status
) != COMP_SUCCESS
) {
605 unsigned int ep_state
;
606 unsigned int slot_state
;
608 switch (GET_COMP_CODE(event
->status
)) {
610 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd invalid because "
611 "of stream ID configuration\n");
614 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed due "
615 "to incorrect slot or ep state.\n");
616 ep_state
= ep_ctx
->ep_info
;
617 ep_state
&= EP_STATE_MASK
;
618 slot_state
= slot_ctx
->dev_state
;
619 slot_state
= GET_SLOT_STATE(slot_state
);
620 xhci_dbg(xhci
, "Slot state = %u, EP state = %u\n",
621 slot_state
, ep_state
);
624 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd failed because "
625 "slot %u was not enabled.\n", slot_id
);
628 xhci_warn(xhci
, "WARN Set TR Deq Ptr cmd with unknown "
629 "completion code of %u.\n",
630 GET_COMP_CODE(event
->status
));
633 /* OK what do we do now? The endpoint state is hosed, and we
634 * should never get to this point if the synchronization between
635 * queueing, and endpoint state are correct. This might happen
636 * if the device gets disconnected after we've finished
637 * cancelling URBs, which might not be an error...
640 xhci_dbg(xhci
, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
644 ep_ring
->state
&= ~SET_DEQ_PENDING
;
645 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
648 static void handle_reset_ep_completion(struct xhci_hcd
*xhci
,
649 struct xhci_event_cmd
*event
,
653 unsigned int ep_index
;
655 slot_id
= TRB_TO_SLOT_ID(trb
->generic
.field
[3]);
656 ep_index
= TRB_TO_EP_INDEX(trb
->generic
.field
[3]);
657 /* This command will only fail if the endpoint wasn't halted,
660 xhci_dbg(xhci
, "Ignoring reset ep completion code of %u\n",
661 (unsigned int) GET_COMP_CODE(event
->status
));
663 /* Clear our internal halted state and restart the ring */
664 xhci
->devs
[slot_id
]->ep_rings
[ep_index
]->state
&= ~EP_HALTED
;
665 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
668 static void handle_cmd_completion(struct xhci_hcd
*xhci
,
669 struct xhci_event_cmd
*event
)
671 int slot_id
= TRB_TO_SLOT_ID(event
->flags
);
673 dma_addr_t cmd_dequeue_dma
;
675 cmd_dma
= event
->cmd_trb
;
676 cmd_dequeue_dma
= xhci_trb_virt_to_dma(xhci
->cmd_ring
->deq_seg
,
677 xhci
->cmd_ring
->dequeue
);
678 /* Is the command ring deq ptr out of sync with the deq seg ptr? */
679 if (cmd_dequeue_dma
== 0) {
680 xhci
->error_bitmask
|= 1 << 4;
683 /* Does the DMA address match our internal dequeue pointer address? */
684 if (cmd_dma
!= (u64
) cmd_dequeue_dma
) {
685 xhci
->error_bitmask
|= 1 << 5;
688 switch (xhci
->cmd_ring
->dequeue
->generic
.field
[3] & TRB_TYPE_BITMASK
) {
689 case TRB_TYPE(TRB_ENABLE_SLOT
):
690 if (GET_COMP_CODE(event
->status
) == COMP_SUCCESS
)
691 xhci
->slot_id
= slot_id
;
694 complete(&xhci
->addr_dev
);
696 case TRB_TYPE(TRB_DISABLE_SLOT
):
697 if (xhci
->devs
[slot_id
])
698 xhci_free_virt_device(xhci
, slot_id
);
700 case TRB_TYPE(TRB_CONFIG_EP
):
701 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
702 complete(&xhci
->devs
[slot_id
]->cmd_completion
);
704 case TRB_TYPE(TRB_ADDR_DEV
):
705 xhci
->devs
[slot_id
]->cmd_status
= GET_COMP_CODE(event
->status
);
706 complete(&xhci
->addr_dev
);
708 case TRB_TYPE(TRB_STOP_RING
):
709 handle_stopped_endpoint(xhci
, xhci
->cmd_ring
->dequeue
);
711 case TRB_TYPE(TRB_SET_DEQ
):
712 handle_set_deq_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
714 case TRB_TYPE(TRB_CMD_NOOP
):
715 ++xhci
->noops_handled
;
717 case TRB_TYPE(TRB_RESET_EP
):
718 handle_reset_ep_completion(xhci
, event
, xhci
->cmd_ring
->dequeue
);
721 /* Skip over unknown commands on the event ring */
722 xhci
->error_bitmask
|= 1 << 6;
725 inc_deq(xhci
, xhci
->cmd_ring
, false);
728 static void handle_port_status(struct xhci_hcd
*xhci
,
729 union xhci_trb
*event
)
733 /* Port status change events always have a successful completion code */
734 if (GET_COMP_CODE(event
->generic
.field
[2]) != COMP_SUCCESS
) {
735 xhci_warn(xhci
, "WARN: xHC returned failed port status event\n");
736 xhci
->error_bitmask
|= 1 << 8;
738 /* FIXME: core doesn't care about all port link state changes yet */
739 port_id
= GET_PORT_ID(event
->generic
.field
[0]);
740 xhci_dbg(xhci
, "Port Status Change Event for port %d\n", port_id
);
742 /* Update event ring dequeue pointer before dropping the lock */
743 inc_deq(xhci
, xhci
->event_ring
, true);
744 xhci_set_hc_event_deq(xhci
);
746 spin_unlock(&xhci
->lock
);
747 /* Pass this up to the core */
748 usb_hcd_poll_rh_status(xhci_to_hcd(xhci
));
749 spin_lock(&xhci
->lock
);
753 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
754 * at end_trb, which may be in another segment. If the suspect DMA address is a
755 * TRB in this TD, this function returns that TRB's segment. Otherwise it
758 static struct xhci_segment
*trb_in_td(
759 struct xhci_segment
*start_seg
,
760 union xhci_trb
*start_trb
,
761 union xhci_trb
*end_trb
,
762 dma_addr_t suspect_dma
)
764 dma_addr_t start_dma
;
765 dma_addr_t end_seg_dma
;
766 dma_addr_t end_trb_dma
;
767 struct xhci_segment
*cur_seg
;
769 start_dma
= xhci_trb_virt_to_dma(start_seg
, start_trb
);
773 /* We may get an event for a Link TRB in the middle of a TD */
774 end_seg_dma
= xhci_trb_virt_to_dma(cur_seg
,
775 &start_seg
->trbs
[TRBS_PER_SEGMENT
- 1]);
776 /* If the end TRB isn't in this segment, this is set to 0 */
777 end_trb_dma
= xhci_trb_virt_to_dma(cur_seg
, end_trb
);
779 if (end_trb_dma
> 0) {
780 /* The end TRB is in this segment, so suspect should be here */
781 if (start_dma
<= end_trb_dma
) {
782 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_trb_dma
)
785 /* Case for one segment with
786 * a TD wrapped around to the top
788 if ((suspect_dma
>= start_dma
&&
789 suspect_dma
<= end_seg_dma
) ||
790 (suspect_dma
>= cur_seg
->dma
&&
791 suspect_dma
<= end_trb_dma
))
796 /* Might still be somewhere in this segment */
797 if (suspect_dma
>= start_dma
&& suspect_dma
<= end_seg_dma
)
800 cur_seg
= cur_seg
->next
;
801 start_dma
= xhci_trb_virt_to_dma(cur_seg
, &cur_seg
->trbs
[0]);
807 * If this function returns an error condition, it means it got a Transfer
808 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
809 * At this point, the host controller is probably hosed and should be reset.
811 static int handle_tx_event(struct xhci_hcd
*xhci
,
812 struct xhci_transfer_event
*event
)
814 struct xhci_virt_device
*xdev
;
815 struct xhci_ring
*ep_ring
;
817 struct xhci_td
*td
= 0;
818 dma_addr_t event_dma
;
819 struct xhci_segment
*event_seg
;
820 union xhci_trb
*event_trb
;
822 int status
= -EINPROGRESS
;
823 struct xhci_ep_ctx
*ep_ctx
;
825 xhci_dbg(xhci
, "In %s\n", __func__
);
826 xdev
= xhci
->devs
[TRB_TO_SLOT_ID(event
->flags
)];
828 xhci_err(xhci
, "ERROR Transfer event pointed to bad slot\n");
832 /* Endpoint ID is 1 based, our index is zero based */
833 ep_index
= TRB_TO_EP_ID(event
->flags
) - 1;
834 xhci_dbg(xhci
, "%s - ep index = %d\n", __func__
, ep_index
);
835 ep_ring
= xdev
->ep_rings
[ep_index
];
836 ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
837 if (!ep_ring
|| (ep_ctx
->ep_info
& EP_STATE_MASK
) == EP_STATE_DISABLED
) {
838 xhci_err(xhci
, "ERROR Transfer event pointed to disabled endpoint\n");
842 event_dma
= event
->buffer
;
843 /* This TRB should be in the TD at the head of this ring's TD list */
844 xhci_dbg(xhci
, "%s - checking for list empty\n", __func__
);
845 if (list_empty(&ep_ring
->td_list
)) {
846 xhci_warn(xhci
, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
847 TRB_TO_SLOT_ID(event
->flags
), ep_index
);
848 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
849 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
850 xhci_print_trb_offsets(xhci
, (union xhci_trb
*) event
);
854 xhci_dbg(xhci
, "%s - getting list entry\n", __func__
);
855 td
= list_entry(ep_ring
->td_list
.next
, struct xhci_td
, td_list
);
857 /* Is this a TRB in the currently executing TD? */
858 xhci_dbg(xhci
, "%s - looking for TD\n", __func__
);
859 event_seg
= trb_in_td(ep_ring
->deq_seg
, ep_ring
->dequeue
,
860 td
->last_trb
, event_dma
);
861 xhci_dbg(xhci
, "%s - found event_seg = %p\n", __func__
, event_seg
);
863 /* HC is busted, give up! */
864 xhci_err(xhci
, "ERROR Transfer event TRB DMA ptr not part of current TD\n");
867 event_trb
= &event_seg
->trbs
[(event_dma
- event_seg
->dma
) / sizeof(*event_trb
)];
868 xhci_dbg(xhci
, "Event TRB with TRB type ID %u\n",
869 (unsigned int) (event
->flags
& TRB_TYPE_BITMASK
)>>10);
870 xhci_dbg(xhci
, "Offset 0x00 (buffer lo) = 0x%x\n",
871 lower_32_bits(event
->buffer
));
872 xhci_dbg(xhci
, "Offset 0x04 (buffer hi) = 0x%x\n",
873 upper_32_bits(event
->buffer
));
874 xhci_dbg(xhci
, "Offset 0x08 (transfer length) = 0x%x\n",
875 (unsigned int) event
->transfer_len
);
876 xhci_dbg(xhci
, "Offset 0x0C (flags) = 0x%x\n",
877 (unsigned int) event
->flags
);
879 /* Look for common error cases */
880 switch (GET_COMP_CODE(event
->transfer_len
)) {
881 /* Skip codes that require special handling depending on
888 xhci_dbg(xhci
, "Stopped on Transfer TRB\n");
890 case COMP_STOP_INVAL
:
891 xhci_dbg(xhci
, "Stopped on No-op or Link TRB\n");
894 xhci_warn(xhci
, "WARN: Stalled endpoint\n");
895 ep_ring
->state
|= EP_HALTED
;
899 xhci_warn(xhci
, "WARN: TRB error on endpoint\n");
903 xhci_warn(xhci
, "WARN: transfer error on endpoint\n");
907 xhci_warn(xhci
, "WARN: babble error on endpoint\n");
911 xhci_warn(xhci
, "WARN: HC couldn't access mem fast enough\n");
915 xhci_warn(xhci
, "ERROR Unknown event condition, HC probably busted\n");
919 /* Now update the urb's actual_length and give back to the core */
920 /* Was this a control transfer? */
921 if (usb_endpoint_xfer_control(&td
->urb
->ep
->desc
)) {
922 xhci_debug_trb(xhci
, xhci
->event_ring
->dequeue
);
923 switch (GET_COMP_CODE(event
->transfer_len
)) {
925 if (event_trb
== ep_ring
->dequeue
) {
926 xhci_warn(xhci
, "WARN: Success on ctrl setup TRB without IOC set??\n");
928 } else if (event_trb
!= td
->last_trb
) {
929 xhci_warn(xhci
, "WARN: Success on ctrl data TRB without IOC set??\n");
932 xhci_dbg(xhci
, "Successful control transfer!\n");
937 xhci_warn(xhci
, "WARN: short transfer on control ep\n");
941 /* Others already handled above */
945 * Did we transfer any data, despite the errors that might have
946 * happened? I.e. did we get past the setup stage?
948 if (event_trb
!= ep_ring
->dequeue
) {
949 /* The event was for the status stage */
950 if (event_trb
== td
->last_trb
) {
951 if (td
->urb
->actual_length
!= 0) {
952 /* Don't overwrite a previously set error code */
953 if (status
== -EINPROGRESS
|| status
== 0)
954 /* Did we already see a short data stage? */
957 td
->urb
->actual_length
=
958 td
->urb
->transfer_buffer_length
;
961 /* Maybe the event was for the data stage? */
962 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
) {
963 /* We didn't stop on a link TRB in the middle */
964 td
->urb
->actual_length
=
965 td
->urb
->transfer_buffer_length
-
966 TRB_LEN(event
->transfer_len
);
967 xhci_dbg(xhci
, "Waiting for status stage event\n");
974 switch (GET_COMP_CODE(event
->transfer_len
)) {
976 /* Double check that the HW transferred everything. */
977 if (event_trb
!= td
->last_trb
) {
978 xhci_warn(xhci
, "WARN Successful completion "
980 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
985 xhci_dbg(xhci
, "Successful bulk transfer!\n");
990 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
996 /* Others already handled above */
999 dev_dbg(&td
->urb
->dev
->dev
,
1000 "ep %#x - asked for %d bytes, "
1001 "%d bytes untransferred\n",
1002 td
->urb
->ep
->desc
.bEndpointAddress
,
1003 td
->urb
->transfer_buffer_length
,
1004 TRB_LEN(event
->transfer_len
));
1005 /* Fast path - was this the last TRB in the TD for this URB? */
1006 if (event_trb
== td
->last_trb
) {
1007 if (TRB_LEN(event
->transfer_len
) != 0) {
1008 td
->urb
->actual_length
=
1009 td
->urb
->transfer_buffer_length
-
1010 TRB_LEN(event
->transfer_len
);
1011 if (td
->urb
->actual_length
< 0) {
1012 xhci_warn(xhci
, "HC gave bad length "
1013 "of %d bytes left\n",
1014 TRB_LEN(event
->transfer_len
));
1015 td
->urb
->actual_length
= 0;
1017 /* Don't overwrite a previously set error code */
1018 if (status
== -EINPROGRESS
) {
1019 if (td
->urb
->transfer_flags
& URB_SHORT_NOT_OK
)
1020 status
= -EREMOTEIO
;
1025 td
->urb
->actual_length
= td
->urb
->transfer_buffer_length
;
1026 /* Ignore a short packet completion if the
1027 * untransferred length was zero.
1029 if (status
== -EREMOTEIO
)
1033 /* Slow path - walk the list, starting from the dequeue
1034 * pointer, to get the actual length transferred.
1036 union xhci_trb
*cur_trb
;
1037 struct xhci_segment
*cur_seg
;
1039 td
->urb
->actual_length
= 0;
1040 for (cur_trb
= ep_ring
->dequeue
, cur_seg
= ep_ring
->deq_seg
;
1041 cur_trb
!= event_trb
;
1042 next_trb(xhci
, ep_ring
, &cur_seg
, &cur_trb
)) {
1043 if (TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_TR_NOOP
&&
1044 TRB_TYPE(cur_trb
->generic
.field
[3]) != TRB_LINK
)
1045 td
->urb
->actual_length
+=
1046 TRB_LEN(cur_trb
->generic
.field
[2]);
1048 /* If the ring didn't stop on a Link or No-op TRB, add
1049 * in the actual bytes transferred from the Normal TRB
1051 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STOP_INVAL
)
1052 td
->urb
->actual_length
+=
1053 TRB_LEN(cur_trb
->generic
.field
[2]) -
1054 TRB_LEN(event
->transfer_len
);
1057 if (GET_COMP_CODE(event
->transfer_len
) == COMP_STOP_INVAL
||
1058 GET_COMP_CODE(event
->transfer_len
) == COMP_STOP
) {
1059 /* The Endpoint Stop Command completion will take care of any
1060 * stopped TDs. A stopped TD may be restarted, so don't update
1061 * the ring dequeue pointer or take this TD off any lists yet.
1063 ep_ring
->stopped_td
= td
;
1064 ep_ring
->stopped_trb
= event_trb
;
1066 if (GET_COMP_CODE(event
->transfer_len
) == COMP_STALL
) {
1067 /* The transfer is completed from the driver's
1068 * perspective, but we need to issue a set dequeue
1069 * command for this stalled endpoint to move the dequeue
1070 * pointer past the TD. We can't do that here because
1071 * the halt condition must be cleared first.
1073 ep_ring
->stopped_td
= td
;
1074 ep_ring
->stopped_trb
= event_trb
;
1076 /* Update ring dequeue pointer */
1077 while (ep_ring
->dequeue
!= td
->last_trb
)
1078 inc_deq(xhci
, ep_ring
, false);
1079 inc_deq(xhci
, ep_ring
, false);
1082 /* Clean up the endpoint's TD list */
1084 list_del(&td
->td_list
);
1085 /* Was this TD slated to be cancelled but completed anyway? */
1086 if (!list_empty(&td
->cancelled_td_list
)) {
1087 list_del(&td
->cancelled_td_list
);
1088 ep_ring
->cancels_pending
--;
1090 /* Leave the TD around for the reset endpoint function to use */
1091 if (GET_COMP_CODE(event
->transfer_len
) != COMP_STALL
) {
1097 inc_deq(xhci
, xhci
->event_ring
, true);
1098 xhci_set_hc_event_deq(xhci
);
1100 /* FIXME for multi-TD URBs (who have buffers bigger than 64MB) */
1102 usb_hcd_unlink_urb_from_ep(xhci_to_hcd(xhci
), urb
);
1103 xhci_dbg(xhci
, "Giveback URB %p, len = %d, status = %d\n",
1104 urb
, td
->urb
->actual_length
, status
);
1105 spin_unlock(&xhci
->lock
);
1106 usb_hcd_giveback_urb(xhci_to_hcd(xhci
), urb
, status
);
1107 spin_lock(&xhci
->lock
);
1113 * This function handles all OS-owned events on the event ring. It may drop
1114 * xhci->lock between event processing (e.g. to pass up port status changes).
1116 void xhci_handle_event(struct xhci_hcd
*xhci
)
1118 union xhci_trb
*event
;
1119 int update_ptrs
= 1;
1122 xhci_dbg(xhci
, "In %s\n", __func__
);
1123 if (!xhci
->event_ring
|| !xhci
->event_ring
->dequeue
) {
1124 xhci
->error_bitmask
|= 1 << 1;
1128 event
= xhci
->event_ring
->dequeue
;
1129 /* Does the HC or OS own the TRB? */
1130 if ((event
->event_cmd
.flags
& TRB_CYCLE
) !=
1131 xhci
->event_ring
->cycle_state
) {
1132 xhci
->error_bitmask
|= 1 << 2;
1135 xhci_dbg(xhci
, "%s - OS owns TRB\n", __func__
);
1137 /* FIXME: Handle more event types. */
1138 switch ((event
->event_cmd
.flags
& TRB_TYPE_BITMASK
)) {
1139 case TRB_TYPE(TRB_COMPLETION
):
1140 xhci_dbg(xhci
, "%s - calling handle_cmd_completion\n", __func__
);
1141 handle_cmd_completion(xhci
, &event
->event_cmd
);
1142 xhci_dbg(xhci
, "%s - returned from handle_cmd_completion\n", __func__
);
1144 case TRB_TYPE(TRB_PORT_STATUS
):
1145 xhci_dbg(xhci
, "%s - calling handle_port_status\n", __func__
);
1146 handle_port_status(xhci
, event
);
1147 xhci_dbg(xhci
, "%s - returned from handle_port_status\n", __func__
);
1150 case TRB_TYPE(TRB_TRANSFER
):
1151 xhci_dbg(xhci
, "%s - calling handle_tx_event\n", __func__
);
1152 ret
= handle_tx_event(xhci
, &event
->trans_event
);
1153 xhci_dbg(xhci
, "%s - returned from handle_tx_event\n", __func__
);
1155 xhci
->error_bitmask
|= 1 << 9;
1160 xhci
->error_bitmask
|= 1 << 3;
1164 /* Update SW and HC event ring dequeue pointer */
1165 inc_deq(xhci
, xhci
->event_ring
, true);
1166 xhci_set_hc_event_deq(xhci
);
1168 /* Are there more items on the event ring? */
1169 xhci_handle_event(xhci
);
1172 /**** Endpoint Ring Operations ****/
1175 * Generic function for queueing a TRB on a ring.
1176 * The caller must have checked to make sure there's room on the ring.
1178 static void queue_trb(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
,
1180 u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1182 struct xhci_generic_trb
*trb
;
1184 trb
= &ring
->enqueue
->generic
;
1185 trb
->field
[0] = field1
;
1186 trb
->field
[1] = field2
;
1187 trb
->field
[2] = field3
;
1188 trb
->field
[3] = field4
;
1189 inc_enq(xhci
, ring
, consumer
);
1193 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
1194 * FIXME allocate segments if the ring is full.
1196 static int prepare_ring(struct xhci_hcd
*xhci
, struct xhci_ring
*ep_ring
,
1197 u32 ep_state
, unsigned int num_trbs
, gfp_t mem_flags
)
1199 /* Make sure the endpoint has been added to xHC schedule */
1200 xhci_dbg(xhci
, "Endpoint state = 0x%x\n", ep_state
);
1202 case EP_STATE_DISABLED
:
1204 * USB core changed config/interfaces without notifying us,
1205 * or hardware is reporting the wrong state.
1207 xhci_warn(xhci
, "WARN urb submitted to disabled ep\n");
1209 case EP_STATE_ERROR
:
1210 xhci_warn(xhci
, "WARN waiting for error on ep to be cleared\n");
1211 /* FIXME event handling code for error needs to clear it */
1212 /* XXX not sure if this should be -ENOENT or not */
1214 case EP_STATE_HALTED
:
1215 xhci_dbg(xhci
, "WARN halted endpoint, queueing URB anyway.\n");
1216 case EP_STATE_STOPPED
:
1217 case EP_STATE_RUNNING
:
1220 xhci_err(xhci
, "ERROR unknown endpoint state for ep\n");
1222 * FIXME issue Configure Endpoint command to try to get the HC
1223 * back into a known state.
1227 if (!room_on_ring(xhci
, ep_ring
, num_trbs
)) {
1228 /* FIXME allocate more room */
1229 xhci_err(xhci
, "ERROR no room on ep ring\n");
1235 static int prepare_transfer(struct xhci_hcd
*xhci
,
1236 struct xhci_virt_device
*xdev
,
1237 unsigned int ep_index
,
1238 unsigned int num_trbs
,
1240 struct xhci_td
**td
,
1244 struct xhci_ep_ctx
*ep_ctx
= xhci_get_ep_ctx(xhci
, xdev
->out_ctx
, ep_index
);
1245 ret
= prepare_ring(xhci
, xdev
->ep_rings
[ep_index
],
1246 ep_ctx
->ep_info
& EP_STATE_MASK
,
1247 num_trbs
, mem_flags
);
1250 *td
= kzalloc(sizeof(struct xhci_td
), mem_flags
);
1253 INIT_LIST_HEAD(&(*td
)->td_list
);
1254 INIT_LIST_HEAD(&(*td
)->cancelled_td_list
);
1256 ret
= usb_hcd_link_urb_to_ep(xhci_to_hcd(xhci
), urb
);
1257 if (unlikely(ret
)) {
1263 urb
->hcpriv
= (void *) (*td
);
1264 /* Add this TD to the tail of the endpoint ring's TD list */
1265 list_add_tail(&(*td
)->td_list
, &xdev
->ep_rings
[ep_index
]->td_list
);
1266 (*td
)->start_seg
= xdev
->ep_rings
[ep_index
]->enq_seg
;
1267 (*td
)->first_trb
= xdev
->ep_rings
[ep_index
]->enqueue
;
1272 static unsigned int count_sg_trbs_needed(struct xhci_hcd
*xhci
, struct urb
*urb
)
1274 int num_sgs
, num_trbs
, running_total
, temp
, i
;
1275 struct scatterlist
*sg
;
1278 num_sgs
= urb
->num_sgs
;
1279 temp
= urb
->transfer_buffer_length
;
1281 xhci_dbg(xhci
, "count sg list trbs: \n");
1283 for_each_sg(urb
->sg
->sg
, sg
, num_sgs
, i
) {
1284 unsigned int previous_total_trbs
= num_trbs
;
1285 unsigned int len
= sg_dma_len(sg
);
1287 /* Scatter gather list entries may cross 64KB boundaries */
1288 running_total
= TRB_MAX_BUFF_SIZE
-
1289 (sg_dma_address(sg
) & ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1290 if (running_total
!= 0)
1293 /* How many more 64KB chunks to transfer, how many more TRBs? */
1294 while (running_total
< sg_dma_len(sg
)) {
1296 running_total
+= TRB_MAX_BUFF_SIZE
;
1298 xhci_dbg(xhci
, " sg #%d: dma = %#llx, len = %#x (%d), num_trbs = %d\n",
1299 i
, (unsigned long long)sg_dma_address(sg
),
1300 len
, len
, num_trbs
- previous_total_trbs
);
1302 len
= min_t(int, len
, temp
);
1307 xhci_dbg(xhci
, "\n");
1308 if (!in_interrupt())
1309 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %d, sglist used, num_trbs = %d\n",
1310 urb
->ep
->desc
.bEndpointAddress
,
1311 urb
->transfer_buffer_length
,
1316 static void check_trb_math(struct urb
*urb
, int num_trbs
, int running_total
)
1319 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated number of "
1320 "TRBs, %d left\n", __func__
,
1321 urb
->ep
->desc
.bEndpointAddress
, num_trbs
);
1322 if (running_total
!= urb
->transfer_buffer_length
)
1323 dev_dbg(&urb
->dev
->dev
, "%s - ep %#x - Miscalculated tx length, "
1324 "queued %#x (%d), asked for %#x (%d)\n",
1326 urb
->ep
->desc
.bEndpointAddress
,
1327 running_total
, running_total
,
1328 urb
->transfer_buffer_length
,
1329 urb
->transfer_buffer_length
);
1332 static void giveback_first_trb(struct xhci_hcd
*xhci
, int slot_id
,
1333 unsigned int ep_index
, int start_cycle
,
1334 struct xhci_generic_trb
*start_trb
, struct xhci_td
*td
)
1337 * Pass all the TRBs to the hardware at once and make sure this write
1341 start_trb
->field
[3] |= start_cycle
;
1342 ring_ep_doorbell(xhci
, slot_id
, ep_index
);
1345 static int queue_bulk_sg_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1346 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1348 struct xhci_ring
*ep_ring
;
1349 unsigned int num_trbs
;
1351 struct scatterlist
*sg
;
1353 int trb_buff_len
, this_sg_len
, running_total
;
1357 struct xhci_generic_trb
*start_trb
;
1360 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1361 num_trbs
= count_sg_trbs_needed(xhci
, urb
);
1362 num_sgs
= urb
->num_sgs
;
1364 trb_buff_len
= prepare_transfer(xhci
, xhci
->devs
[slot_id
],
1365 ep_index
, num_trbs
, urb
, &td
, mem_flags
);
1366 if (trb_buff_len
< 0)
1367 return trb_buff_len
;
1369 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1370 * until we've finished creating all the other TRBs. The ring's cycle
1371 * state may change as we enqueue the other TRBs, so save it too.
1373 start_trb
= &ep_ring
->enqueue
->generic
;
1374 start_cycle
= ep_ring
->cycle_state
;
1378 * How much data is in the first TRB?
1380 * There are three forces at work for TRB buffer pointers and lengths:
1381 * 1. We don't want to walk off the end of this sg-list entry buffer.
1382 * 2. The transfer length that the driver requested may be smaller than
1383 * the amount of memory allocated for this scatter-gather list.
1384 * 3. TRBs buffers can't cross 64KB boundaries.
1387 addr
= (u64
) sg_dma_address(sg
);
1388 this_sg_len
= sg_dma_len(sg
);
1389 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1390 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1391 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1392 if (trb_buff_len
> urb
->transfer_buffer_length
)
1393 trb_buff_len
= urb
->transfer_buffer_length
;
1394 xhci_dbg(xhci
, "First length to xfer from 1st sglist entry = %u\n",
1398 /* Queue the first TRB, even if it's zero-length */
1401 u32 length_field
= 0;
1403 /* Don't change the cycle bit of the first TRB until later */
1407 field
|= ep_ring
->cycle_state
;
1409 /* Chain all the TRBs together; clear the chain bit in the last
1410 * TRB to indicate it's the last TRB in the chain.
1415 /* FIXME - add check for ZERO_PACKET flag before this */
1416 td
->last_trb
= ep_ring
->enqueue
;
1419 xhci_dbg(xhci
, " sg entry: dma = %#x, len = %#x (%d), "
1420 "64KB boundary at %#x, end dma = %#x\n",
1421 (unsigned int) addr
, trb_buff_len
, trb_buff_len
,
1422 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1423 (unsigned int) addr
+ trb_buff_len
);
1424 if (TRB_MAX_BUFF_SIZE
-
1425 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1)) < trb_buff_len
) {
1426 xhci_warn(xhci
, "WARN: sg dma xfer crosses 64KB boundaries!\n");
1427 xhci_dbg(xhci
, "Next boundary at %#x, end dma = %#x\n",
1428 (unsigned int) (addr
+ TRB_MAX_BUFF_SIZE
) & ~(TRB_MAX_BUFF_SIZE
- 1),
1429 (unsigned int) addr
+ trb_buff_len
);
1431 length_field
= TRB_LEN(trb_buff_len
) |
1432 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1434 queue_trb(xhci
, ep_ring
, false,
1435 lower_32_bits(addr
),
1436 upper_32_bits(addr
),
1438 /* We always want to know if the TRB was short,
1439 * or we won't get an event when it completes.
1440 * (Unless we use event data TRBs, which are a
1441 * waste of space and HC resources.)
1443 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1445 running_total
+= trb_buff_len
;
1447 /* Calculate length for next transfer --
1448 * Are we done queueing all the TRBs for this sg entry?
1450 this_sg_len
-= trb_buff_len
;
1451 if (this_sg_len
== 0) {
1456 addr
= (u64
) sg_dma_address(sg
);
1457 this_sg_len
= sg_dma_len(sg
);
1459 addr
+= trb_buff_len
;
1462 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1463 (addr
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1464 trb_buff_len
= min_t(int, trb_buff_len
, this_sg_len
);
1465 if (running_total
+ trb_buff_len
> urb
->transfer_buffer_length
)
1467 urb
->transfer_buffer_length
- running_total
;
1468 } while (running_total
< urb
->transfer_buffer_length
);
1470 check_trb_math(urb
, num_trbs
, running_total
);
1471 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1475 /* This is very similar to what ehci-q.c qtd_fill() does */
1476 int xhci_queue_bulk_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1477 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1479 struct xhci_ring
*ep_ring
;
1482 struct xhci_generic_trb
*start_trb
;
1485 u32 field
, length_field
;
1487 int running_total
, trb_buff_len
, ret
;
1491 return queue_bulk_sg_tx(xhci
, mem_flags
, urb
, slot_id
, ep_index
);
1493 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1496 /* How much data is (potentially) left before the 64KB boundary? */
1497 running_total
= TRB_MAX_BUFF_SIZE
-
1498 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1500 /* If there's some data on this 64KB chunk, or we have to send a
1501 * zero-length transfer, we need at least one TRB
1503 if (running_total
!= 0 || urb
->transfer_buffer_length
== 0)
1505 /* How many more 64KB chunks to transfer, how many more TRBs? */
1506 while (running_total
< urb
->transfer_buffer_length
) {
1508 running_total
+= TRB_MAX_BUFF_SIZE
;
1510 /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
1512 if (!in_interrupt())
1513 dev_dbg(&urb
->dev
->dev
, "ep %#x - urb len = %#x (%d), addr = %#llx, num_trbs = %d\n",
1514 urb
->ep
->desc
.bEndpointAddress
,
1515 urb
->transfer_buffer_length
,
1516 urb
->transfer_buffer_length
,
1517 (unsigned long long)urb
->transfer_dma
,
1520 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
,
1521 num_trbs
, urb
, &td
, mem_flags
);
1526 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1527 * until we've finished creating all the other TRBs. The ring's cycle
1528 * state may change as we enqueue the other TRBs, so save it too.
1530 start_trb
= &ep_ring
->enqueue
->generic
;
1531 start_cycle
= ep_ring
->cycle_state
;
1534 /* How much data is in the first TRB? */
1535 addr
= (u64
) urb
->transfer_dma
;
1536 trb_buff_len
= TRB_MAX_BUFF_SIZE
-
1537 (urb
->transfer_dma
& ((1 << TRB_MAX_BUFF_SHIFT
) - 1));
1538 if (urb
->transfer_buffer_length
< trb_buff_len
)
1539 trb_buff_len
= urb
->transfer_buffer_length
;
1543 /* Queue the first TRB, even if it's zero-length */
1547 /* Don't change the cycle bit of the first TRB until later */
1551 field
|= ep_ring
->cycle_state
;
1553 /* Chain all the TRBs together; clear the chain bit in the last
1554 * TRB to indicate it's the last TRB in the chain.
1559 /* FIXME - add check for ZERO_PACKET flag before this */
1560 td
->last_trb
= ep_ring
->enqueue
;
1563 length_field
= TRB_LEN(trb_buff_len
) |
1564 TD_REMAINDER(urb
->transfer_buffer_length
- running_total
) |
1566 queue_trb(xhci
, ep_ring
, false,
1567 lower_32_bits(addr
),
1568 upper_32_bits(addr
),
1570 /* We always want to know if the TRB was short,
1571 * or we won't get an event when it completes.
1572 * (Unless we use event data TRBs, which are a
1573 * waste of space and HC resources.)
1575 field
| TRB_ISP
| TRB_TYPE(TRB_NORMAL
));
1577 running_total
+= trb_buff_len
;
1579 /* Calculate length for next transfer */
1580 addr
+= trb_buff_len
;
1581 trb_buff_len
= urb
->transfer_buffer_length
- running_total
;
1582 if (trb_buff_len
> TRB_MAX_BUFF_SIZE
)
1583 trb_buff_len
= TRB_MAX_BUFF_SIZE
;
1584 } while (running_total
< urb
->transfer_buffer_length
);
1586 check_trb_math(urb
, num_trbs
, running_total
);
1587 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1591 /* Caller must have locked xhci->lock */
1592 int xhci_queue_ctrl_tx(struct xhci_hcd
*xhci
, gfp_t mem_flags
,
1593 struct urb
*urb
, int slot_id
, unsigned int ep_index
)
1595 struct xhci_ring
*ep_ring
;
1598 struct usb_ctrlrequest
*setup
;
1599 struct xhci_generic_trb
*start_trb
;
1601 u32 field
, length_field
;
1604 ep_ring
= xhci
->devs
[slot_id
]->ep_rings
[ep_index
];
1607 * Need to copy setup packet into setup TRB, so we can't use the setup
1610 if (!urb
->setup_packet
)
1613 if (!in_interrupt())
1614 xhci_dbg(xhci
, "Queueing ctrl tx for slot id %d, ep %d\n",
1616 /* 1 TRB for setup, 1 for status */
1619 * Don't need to check if we need additional event data and normal TRBs,
1620 * since data in control transfers will never get bigger than 16MB
1621 * XXX: can we get a buffer that crosses 64KB boundaries?
1623 if (urb
->transfer_buffer_length
> 0)
1625 ret
= prepare_transfer(xhci
, xhci
->devs
[slot_id
], ep_index
, num_trbs
,
1626 urb
, &td
, mem_flags
);
1631 * Don't give the first TRB to the hardware (by toggling the cycle bit)
1632 * until we've finished creating all the other TRBs. The ring's cycle
1633 * state may change as we enqueue the other TRBs, so save it too.
1635 start_trb
= &ep_ring
->enqueue
->generic
;
1636 start_cycle
= ep_ring
->cycle_state
;
1638 /* Queue setup TRB - see section 6.4.1.2.1 */
1639 /* FIXME better way to translate setup_packet into two u32 fields? */
1640 setup
= (struct usb_ctrlrequest
*) urb
->setup_packet
;
1641 queue_trb(xhci
, ep_ring
, false,
1642 /* FIXME endianness is probably going to bite my ass here. */
1643 setup
->bRequestType
| setup
->bRequest
<< 8 | setup
->wValue
<< 16,
1644 setup
->wIndex
| setup
->wLength
<< 16,
1645 TRB_LEN(8) | TRB_INTR_TARGET(0),
1646 /* Immediate data in pointer */
1647 TRB_IDT
| TRB_TYPE(TRB_SETUP
));
1649 /* If there's data, queue data TRBs */
1651 length_field
= TRB_LEN(urb
->transfer_buffer_length
) |
1652 TD_REMAINDER(urb
->transfer_buffer_length
) |
1654 if (urb
->transfer_buffer_length
> 0) {
1655 if (setup
->bRequestType
& USB_DIR_IN
)
1656 field
|= TRB_DIR_IN
;
1657 queue_trb(xhci
, ep_ring
, false,
1658 lower_32_bits(urb
->transfer_dma
),
1659 upper_32_bits(urb
->transfer_dma
),
1661 /* Event on short tx */
1662 field
| TRB_ISP
| TRB_TYPE(TRB_DATA
) | ep_ring
->cycle_state
);
1665 /* Save the DMA address of the last TRB in the TD */
1666 td
->last_trb
= ep_ring
->enqueue
;
1668 /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
1669 /* If the device sent data, the status stage is an OUT transfer */
1670 if (urb
->transfer_buffer_length
> 0 && setup
->bRequestType
& USB_DIR_IN
)
1674 queue_trb(xhci
, ep_ring
, false,
1678 /* Event on completion */
1679 field
| TRB_IOC
| TRB_TYPE(TRB_STATUS
) | ep_ring
->cycle_state
);
1681 giveback_first_trb(xhci
, slot_id
, ep_index
, start_cycle
, start_trb
, td
);
1685 /**** Command Ring Operations ****/
1687 /* Generic function for queueing a command TRB on the command ring */
1688 static int queue_command(struct xhci_hcd
*xhci
, u32 field1
, u32 field2
, u32 field3
, u32 field4
)
1690 if (!room_on_ring(xhci
, xhci
->cmd_ring
, 1)) {
1691 if (!in_interrupt())
1692 xhci_err(xhci
, "ERR: No room for command on command ring\n");
1695 queue_trb(xhci
, xhci
->cmd_ring
, false, field1
, field2
, field3
,
1696 field4
| xhci
->cmd_ring
->cycle_state
);
1700 /* Queue a no-op command on the command ring */
1701 static int queue_cmd_noop(struct xhci_hcd
*xhci
)
1703 return queue_command(xhci
, 0, 0, 0, TRB_TYPE(TRB_CMD_NOOP
));
1707 * Place a no-op command on the command ring to test the command and
1710 void *xhci_setup_one_noop(struct xhci_hcd
*xhci
)
1712 if (queue_cmd_noop(xhci
) < 0)
1714 xhci
->noops_submitted
++;
1715 return xhci_ring_cmd_db
;
1718 /* Queue a slot enable or disable request on the command ring */
1719 int xhci_queue_slot_control(struct xhci_hcd
*xhci
, u32 trb_type
, u32 slot_id
)
1721 return queue_command(xhci
, 0, 0, 0,
1722 TRB_TYPE(trb_type
) | SLOT_ID_FOR_TRB(slot_id
));
1725 /* Queue an address device command TRB */
1726 int xhci_queue_address_device(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1729 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1730 upper_32_bits(in_ctx_ptr
), 0,
1731 TRB_TYPE(TRB_ADDR_DEV
) | SLOT_ID_FOR_TRB(slot_id
));
1734 /* Queue a configure endpoint command TRB */
1735 int xhci_queue_configure_endpoint(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1738 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1739 upper_32_bits(in_ctx_ptr
), 0,
1740 TRB_TYPE(TRB_CONFIG_EP
) | SLOT_ID_FOR_TRB(slot_id
));
1743 /* Queue an evaluate context command TRB */
1744 int xhci_queue_evaluate_context(struct xhci_hcd
*xhci
, dma_addr_t in_ctx_ptr
,
1747 return queue_command(xhci
, lower_32_bits(in_ctx_ptr
),
1748 upper_32_bits(in_ctx_ptr
), 0,
1749 TRB_TYPE(TRB_EVAL_CONTEXT
) | SLOT_ID_FOR_TRB(slot_id
));
1752 int xhci_queue_stop_endpoint(struct xhci_hcd
*xhci
, int slot_id
,
1753 unsigned int ep_index
)
1755 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1756 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1757 u32 type
= TRB_TYPE(TRB_STOP_RING
);
1759 return queue_command(xhci
, 0, 0, 0,
1760 trb_slot_id
| trb_ep_index
| type
);
1763 /* Set Transfer Ring Dequeue Pointer command.
1764 * This should not be used for endpoints that have streams enabled.
1766 static int queue_set_tr_deq(struct xhci_hcd
*xhci
, int slot_id
,
1767 unsigned int ep_index
, struct xhci_segment
*deq_seg
,
1768 union xhci_trb
*deq_ptr
, u32 cycle_state
)
1771 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1772 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1773 u32 type
= TRB_TYPE(TRB_SET_DEQ
);
1775 addr
= xhci_trb_virt_to_dma(deq_seg
, deq_ptr
);
1777 xhci_warn(xhci
, "WARN Cannot submit Set TR Deq Ptr\n");
1778 xhci_warn(xhci
, "WARN deq seg = %p, deq pt = %p\n",
1782 return queue_command(xhci
, lower_32_bits(addr
) | cycle_state
,
1783 upper_32_bits(addr
), 0,
1784 trb_slot_id
| trb_ep_index
| type
);
1787 int xhci_queue_reset_ep(struct xhci_hcd
*xhci
, int slot_id
,
1788 unsigned int ep_index
)
1790 u32 trb_slot_id
= SLOT_ID_FOR_TRB(slot_id
);
1791 u32 trb_ep_index
= EP_ID_FOR_TRB(ep_index
);
1792 u32 type
= TRB_TYPE(TRB_RESET_EP
);
1794 return queue_command(xhci
, 0, 0, 0, trb_slot_id
| trb_ep_index
| type
);