2 * xHCI host controller driver
4 * Copyright (C) 2008 Intel Corp.
7 * Some code borrowed from the Linux EHCI driver.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software Foundation,
20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 #include <linux/usb.h>
24 #include <linux/pci.h>
25 #include <linux/dmapool.h>
30 * Allocates a generic ring segment from the ring pool, sets the dma address,
31 * initializes the segment to zero, and sets the private next pointer to NULL.
34 * "All components of all Command and Transfer TRBs shall be initialized to '0'"
36 static struct xhci_segment
*xhci_segment_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
38 struct xhci_segment
*seg
;
41 seg
= kzalloc(sizeof *seg
, flags
);
44 xhci_dbg(xhci
, "Allocating priv segment structure at %p\n", seg
);
46 seg
->trbs
= dma_pool_alloc(xhci
->segment_pool
, flags
, &dma
);
51 xhci_dbg(xhci
, "// Allocating segment at %p (virtual) 0x%llx (DMA)\n",
52 seg
->trbs
, (unsigned long long)dma
);
54 memset(seg
->trbs
, 0, SEGMENT_SIZE
);
61 static void xhci_segment_free(struct xhci_hcd
*xhci
, struct xhci_segment
*seg
)
66 xhci_dbg(xhci
, "Freeing DMA segment at %p (virtual) 0x%llx (DMA)\n",
67 seg
->trbs
, (unsigned long long)seg
->dma
);
68 dma_pool_free(xhci
->segment_pool
, seg
->trbs
, seg
->dma
);
71 xhci_dbg(xhci
, "Freeing priv segment structure at %p\n", seg
);
76 * Make the prev segment point to the next segment.
78 * Change the last TRB in the prev segment to be a Link TRB which points to the
79 * DMA address of the next segment. The caller needs to set any Link TRB
80 * related flags, such as End TRB, Toggle Cycle, and no snoop.
82 static void xhci_link_segments(struct xhci_hcd
*xhci
, struct xhci_segment
*prev
,
83 struct xhci_segment
*next
, bool link_trbs
)
91 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.segment_ptr
= next
->dma
;
93 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
94 val
= prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
;
95 val
&= ~TRB_TYPE_BITMASK
;
96 val
|= TRB_TYPE(TRB_LINK
);
97 /* Always set the chain bit with 0.95 hardware */
98 if (xhci_link_trb_quirk(xhci
))
100 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
= val
;
102 xhci_dbg(xhci
, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
103 (unsigned long long)prev
->dma
,
104 (unsigned long long)next
->dma
);
107 /* XXX: Do we need the hcd structure in all these functions? */
108 void xhci_ring_free(struct xhci_hcd
*xhci
, struct xhci_ring
*ring
)
110 struct xhci_segment
*seg
;
111 struct xhci_segment
*first_seg
;
113 if (!ring
|| !ring
->first_seg
)
115 first_seg
= ring
->first_seg
;
116 seg
= first_seg
->next
;
117 xhci_dbg(xhci
, "Freeing ring at %p\n", ring
);
118 while (seg
!= first_seg
) {
119 struct xhci_segment
*next
= seg
->next
;
120 xhci_segment_free(xhci
, seg
);
123 xhci_segment_free(xhci
, first_seg
);
124 ring
->first_seg
= NULL
;
129 * Create a new ring with zero or more segments.
131 * Link each segment together into a ring.
132 * Set the end flag and the cycle toggle bit on the last segment.
133 * See section 4.9.1 and figures 15 and 16.
135 static struct xhci_ring
*xhci_ring_alloc(struct xhci_hcd
*xhci
,
136 unsigned int num_segs
, bool link_trbs
, gfp_t flags
)
138 struct xhci_ring
*ring
;
139 struct xhci_segment
*prev
;
141 ring
= kzalloc(sizeof *(ring
), flags
);
142 xhci_dbg(xhci
, "Allocating ring at %p\n", ring
);
146 INIT_LIST_HEAD(&ring
->td_list
);
147 INIT_LIST_HEAD(&ring
->cancelled_td_list
);
151 ring
->first_seg
= xhci_segment_alloc(xhci
, flags
);
152 if (!ring
->first_seg
)
156 prev
= ring
->first_seg
;
157 while (num_segs
> 0) {
158 struct xhci_segment
*next
;
160 next
= xhci_segment_alloc(xhci
, flags
);
163 xhci_link_segments(xhci
, prev
, next
, link_trbs
);
168 xhci_link_segments(xhci
, prev
, ring
->first_seg
, link_trbs
);
171 /* See section 4.9.2.1 and 6.4.4.1 */
172 prev
->trbs
[TRBS_PER_SEGMENT
-1].link
.control
|= (LINK_TOGGLE
);
173 xhci_dbg(xhci
, "Wrote link toggle flag to"
174 " segment %p (virtual), 0x%llx (DMA)\n",
175 prev
, (unsigned long long)prev
->dma
);
177 /* The ring is empty, so the enqueue pointer == dequeue pointer */
178 ring
->enqueue
= ring
->first_seg
->trbs
;
179 ring
->enq_seg
= ring
->first_seg
;
180 ring
->dequeue
= ring
->enqueue
;
181 ring
->deq_seg
= ring
->first_seg
;
182 /* The ring is initialized to 0. The producer must write 1 to the cycle
183 * bit to handover ownership of the TRB, so PCS = 1. The consumer must
184 * compare CCS to the cycle bit to check ownership, so CCS = 1.
186 ring
->cycle_state
= 1;
191 xhci_ring_free(xhci
, ring
);
195 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
197 struct xhci_container_ctx
*xhci_alloc_container_ctx(struct xhci_hcd
*xhci
,
198 int type
, gfp_t flags
)
200 struct xhci_container_ctx
*ctx
= kzalloc(sizeof(*ctx
), flags
);
204 BUG_ON((type
!= XHCI_CTX_TYPE_DEVICE
) && (type
!= XHCI_CTX_TYPE_INPUT
));
206 ctx
->size
= HCC_64BYTE_CONTEXT(xhci
->hcc_params
) ? 2048 : 1024;
207 if (type
== XHCI_CTX_TYPE_INPUT
)
208 ctx
->size
+= CTX_SIZE(xhci
->hcc_params
);
210 ctx
->bytes
= dma_pool_alloc(xhci
->device_pool
, flags
, &ctx
->dma
);
211 memset(ctx
->bytes
, 0, ctx
->size
);
215 void xhci_free_container_ctx(struct xhci_hcd
*xhci
,
216 struct xhci_container_ctx
*ctx
)
218 dma_pool_free(xhci
->device_pool
, ctx
->bytes
, ctx
->dma
);
222 struct xhci_input_control_ctx
*xhci_get_input_control_ctx(struct xhci_hcd
*xhci
,
223 struct xhci_container_ctx
*ctx
)
225 BUG_ON(ctx
->type
!= XHCI_CTX_TYPE_INPUT
);
226 return (struct xhci_input_control_ctx
*)ctx
->bytes
;
229 struct xhci_slot_ctx
*xhci_get_slot_ctx(struct xhci_hcd
*xhci
,
230 struct xhci_container_ctx
*ctx
)
232 if (ctx
->type
== XHCI_CTX_TYPE_DEVICE
)
233 return (struct xhci_slot_ctx
*)ctx
->bytes
;
235 return (struct xhci_slot_ctx
*)
236 (ctx
->bytes
+ CTX_SIZE(xhci
->hcc_params
));
239 struct xhci_ep_ctx
*xhci_get_ep_ctx(struct xhci_hcd
*xhci
,
240 struct xhci_container_ctx
*ctx
,
241 unsigned int ep_index
)
243 /* increment ep index by offset of start of ep ctx array */
245 if (ctx
->type
== XHCI_CTX_TYPE_INPUT
)
248 return (struct xhci_ep_ctx
*)
249 (ctx
->bytes
+ (ep_index
* CTX_SIZE(xhci
->hcc_params
)));
252 /* All the xhci_tds in the ring's TD list should be freed at this point */
253 void xhci_free_virt_device(struct xhci_hcd
*xhci
, int slot_id
)
255 struct xhci_virt_device
*dev
;
258 /* Slot ID 0 is reserved */
259 if (slot_id
== 0 || !xhci
->devs
[slot_id
])
262 dev
= xhci
->devs
[slot_id
];
263 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = 0;
267 for (i
= 0; i
< 31; ++i
)
268 if (dev
->ep_rings
[i
])
269 xhci_ring_free(xhci
, dev
->ep_rings
[i
]);
272 xhci_free_container_ctx(xhci
, dev
->in_ctx
);
274 xhci_free_container_ctx(xhci
, dev
->out_ctx
);
276 kfree(xhci
->devs
[slot_id
]);
277 xhci
->devs
[slot_id
] = 0;
280 int xhci_alloc_virt_device(struct xhci_hcd
*xhci
, int slot_id
,
281 struct usb_device
*udev
, gfp_t flags
)
283 struct xhci_virt_device
*dev
;
285 /* Slot ID 0 is reserved */
286 if (slot_id
== 0 || xhci
->devs
[slot_id
]) {
287 xhci_warn(xhci
, "Bad Slot ID %d\n", slot_id
);
291 xhci
->devs
[slot_id
] = kzalloc(sizeof(*xhci
->devs
[slot_id
]), flags
);
292 if (!xhci
->devs
[slot_id
])
294 dev
= xhci
->devs
[slot_id
];
296 /* Allocate the (output) device context that will be used in the HC. */
297 dev
->out_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_DEVICE
, flags
);
301 xhci_dbg(xhci
, "Slot %d output ctx = 0x%llx (dma)\n", slot_id
,
302 (unsigned long long)dev
->out_ctx
->dma
);
304 /* Allocate the (input) device context for address device command */
305 dev
->in_ctx
= xhci_alloc_container_ctx(xhci
, XHCI_CTX_TYPE_INPUT
, flags
);
309 xhci_dbg(xhci
, "Slot %d input ctx = 0x%llx (dma)\n", slot_id
,
310 (unsigned long long)dev
->in_ctx
->dma
);
312 /* Allocate endpoint 0 ring */
313 dev
->ep_rings
[0] = xhci_ring_alloc(xhci
, 1, true, flags
);
314 if (!dev
->ep_rings
[0])
317 init_completion(&dev
->cmd_completion
);
319 /* Point to output device context in dcbaa. */
320 xhci
->dcbaa
->dev_context_ptrs
[slot_id
] = dev
->out_ctx
->dma
;
321 xhci_dbg(xhci
, "Set slot id %d dcbaa entry %p to 0x%llx\n",
323 &xhci
->dcbaa
->dev_context_ptrs
[slot_id
],
324 (unsigned long long) xhci
->dcbaa
->dev_context_ptrs
[slot_id
]);
328 xhci_free_virt_device(xhci
, slot_id
);
332 /* Setup an xHCI virtual device for a Set Address command */
333 int xhci_setup_addressable_virt_dev(struct xhci_hcd
*xhci
, struct usb_device
*udev
)
335 struct xhci_virt_device
*dev
;
336 struct xhci_ep_ctx
*ep0_ctx
;
337 struct usb_device
*top_dev
;
338 struct xhci_slot_ctx
*slot_ctx
;
339 struct xhci_input_control_ctx
*ctrl_ctx
;
341 dev
= xhci
->devs
[udev
->slot_id
];
342 /* Slot ID 0 is reserved */
343 if (udev
->slot_id
== 0 || !dev
) {
344 xhci_warn(xhci
, "Slot ID %d is not assigned to this device\n",
348 ep0_ctx
= xhci_get_ep_ctx(xhci
, dev
->in_ctx
, 0);
349 ctrl_ctx
= xhci_get_input_control_ctx(xhci
, dev
->in_ctx
);
350 slot_ctx
= xhci_get_slot_ctx(xhci
, dev
->in_ctx
);
352 /* 2) New slot context and endpoint 0 context are valid*/
353 ctrl_ctx
->add_flags
= SLOT_FLAG
| EP0_FLAG
;
355 /* 3) Only the control endpoint is valid - one endpoint context */
356 slot_ctx
->dev_info
|= LAST_CTX(1);
358 switch (udev
->speed
) {
359 case USB_SPEED_SUPER
:
360 slot_ctx
->dev_info
|= (u32
) udev
->route
;
361 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_SS
;
364 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_HS
;
367 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_FS
;
370 slot_ctx
->dev_info
|= (u32
) SLOT_SPEED_LS
;
372 case USB_SPEED_VARIABLE
:
373 xhci_dbg(xhci
, "FIXME xHCI doesn't support wireless speeds\n");
377 /* Speed was set earlier, this shouldn't happen. */
380 /* Find the root hub port this device is under */
381 for (top_dev
= udev
; top_dev
->parent
&& top_dev
->parent
->parent
;
382 top_dev
= top_dev
->parent
)
383 /* Found device below root hub */;
384 slot_ctx
->dev_info2
|= (u32
) ROOT_HUB_PORT(top_dev
->portnum
);
385 xhci_dbg(xhci
, "Set root hub portnum to %d\n", top_dev
->portnum
);
387 /* Is this a LS/FS device under a HS hub? */
389 * FIXME: I don't think this is right, where does the TT info for the
390 * roothub or parent hub come from?
392 if ((udev
->speed
== USB_SPEED_LOW
|| udev
->speed
== USB_SPEED_FULL
) &&
394 slot_ctx
->tt_info
= udev
->tt
->hub
->slot_id
;
395 slot_ctx
->tt_info
|= udev
->ttport
<< 8;
397 xhci_dbg(xhci
, "udev->tt = %p\n", udev
->tt
);
398 xhci_dbg(xhci
, "udev->ttport = 0x%x\n", udev
->ttport
);
400 /* Step 4 - ring already allocated */
402 ep0_ctx
->ep_info2
= EP_TYPE(CTRL_EP
);
404 * See section 4.3 bullet 6:
405 * The default Max Packet size for ep0 is "8 bytes for a USB2
406 * LS/FS/HS device or 512 bytes for a USB3 SS device"
407 * XXX: Not sure about wireless USB devices.
409 if (udev
->speed
== USB_SPEED_SUPER
)
410 ep0_ctx
->ep_info2
|= MAX_PACKET(512);
412 ep0_ctx
->ep_info2
|= MAX_PACKET(8);
413 /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
414 ep0_ctx
->ep_info2
|= MAX_BURST(0);
415 ep0_ctx
->ep_info2
|= ERROR_COUNT(3);
418 dev
->ep_rings
[0]->first_seg
->dma
;
419 ep0_ctx
->deq
|= dev
->ep_rings
[0]->cycle_state
;
421 /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
426 /* Return the polling or NAK interval.
428 * The polling interval is expressed in "microframes". If xHCI's Interval field
429 * is set to N, it will service the endpoint every 2^(Interval)*125us.
431 * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
434 static inline unsigned int xhci_get_endpoint_interval(struct usb_device
*udev
,
435 struct usb_host_endpoint
*ep
)
437 unsigned int interval
= 0;
439 switch (udev
->speed
) {
442 if (usb_endpoint_xfer_control(&ep
->desc
) ||
443 usb_endpoint_xfer_bulk(&ep
->desc
))
444 interval
= ep
->desc
.bInterval
;
445 /* Fall through - SS and HS isoc/int have same decoding */
446 case USB_SPEED_SUPER
:
447 if (usb_endpoint_xfer_int(&ep
->desc
) ||
448 usb_endpoint_xfer_isoc(&ep
->desc
)) {
449 if (ep
->desc
.bInterval
== 0)
452 interval
= ep
->desc
.bInterval
- 1;
455 if (interval
!= ep
->desc
.bInterval
+ 1)
456 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
457 ep
->desc
.bEndpointAddress
, 1 << interval
);
460 /* Convert bInterval (in 1-255 frames) to microframes and round down to
461 * nearest power of 2.
465 if (usb_endpoint_xfer_int(&ep
->desc
) ||
466 usb_endpoint_xfer_isoc(&ep
->desc
)) {
467 interval
= fls(8*ep
->desc
.bInterval
) - 1;
472 if ((1 << interval
) != 8*ep
->desc
.bInterval
)
473 dev_warn(&udev
->dev
, "ep %#x - rounding interval to %d microframes\n",
474 ep
->desc
.bEndpointAddress
, 1 << interval
);
480 return EP_INTERVAL(interval
);
483 static inline u32
xhci_get_endpoint_type(struct usb_device
*udev
,
484 struct usb_host_endpoint
*ep
)
489 in
= usb_endpoint_dir_in(&ep
->desc
);
490 if (usb_endpoint_xfer_control(&ep
->desc
)) {
491 type
= EP_TYPE(CTRL_EP
);
492 } else if (usb_endpoint_xfer_bulk(&ep
->desc
)) {
494 type
= EP_TYPE(BULK_IN_EP
);
496 type
= EP_TYPE(BULK_OUT_EP
);
497 } else if (usb_endpoint_xfer_isoc(&ep
->desc
)) {
499 type
= EP_TYPE(ISOC_IN_EP
);
501 type
= EP_TYPE(ISOC_OUT_EP
);
502 } else if (usb_endpoint_xfer_int(&ep
->desc
)) {
504 type
= EP_TYPE(INT_IN_EP
);
506 type
= EP_TYPE(INT_OUT_EP
);
513 int xhci_endpoint_init(struct xhci_hcd
*xhci
,
514 struct xhci_virt_device
*virt_dev
,
515 struct usb_device
*udev
,
516 struct usb_host_endpoint
*ep
,
519 unsigned int ep_index
;
520 struct xhci_ep_ctx
*ep_ctx
;
521 struct xhci_ring
*ep_ring
;
522 unsigned int max_packet
;
523 unsigned int max_burst
;
525 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
526 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
528 /* Set up the endpoint ring */
529 virt_dev
->new_ep_rings
[ep_index
] = xhci_ring_alloc(xhci
, 1, true, mem_flags
);
530 if (!virt_dev
->new_ep_rings
[ep_index
])
532 ep_ring
= virt_dev
->new_ep_rings
[ep_index
];
533 ep_ctx
->deq
= ep_ring
->first_seg
->dma
| ep_ring
->cycle_state
;
535 ep_ctx
->ep_info
= xhci_get_endpoint_interval(udev
, ep
);
537 /* FIXME dig Mult and streams info out of ep companion desc */
539 /* Allow 3 retries for everything but isoc;
540 * error count = 0 means infinite retries.
542 if (!usb_endpoint_xfer_isoc(&ep
->desc
))
543 ep_ctx
->ep_info2
= ERROR_COUNT(3);
545 ep_ctx
->ep_info2
= ERROR_COUNT(1);
547 ep_ctx
->ep_info2
|= xhci_get_endpoint_type(udev
, ep
);
549 /* Set the max packet size and max burst */
550 switch (udev
->speed
) {
551 case USB_SPEED_SUPER
:
552 max_packet
= ep
->desc
.wMaxPacketSize
;
553 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
554 /* dig out max burst from ep companion desc */
555 if (!ep
->ss_ep_comp
) {
556 xhci_warn(xhci
, "WARN no SS endpoint companion descriptor.\n");
559 max_packet
= ep
->ss_ep_comp
->desc
.bMaxBurst
;
561 ep_ctx
->ep_info2
|= MAX_BURST(max_packet
);
564 /* bits 11:12 specify the number of additional transaction
565 * opportunities per microframe (USB 2.0, section 9.6.6)
567 if (usb_endpoint_xfer_isoc(&ep
->desc
) ||
568 usb_endpoint_xfer_int(&ep
->desc
)) {
569 max_burst
= (ep
->desc
.wMaxPacketSize
& 0x1800) >> 11;
570 ep_ctx
->ep_info2
|= MAX_BURST(max_burst
);
575 max_packet
= ep
->desc
.wMaxPacketSize
& 0x3ff;
576 ep_ctx
->ep_info2
|= MAX_PACKET(max_packet
);
581 /* FIXME Debug endpoint context */
585 void xhci_endpoint_zero(struct xhci_hcd
*xhci
,
586 struct xhci_virt_device
*virt_dev
,
587 struct usb_host_endpoint
*ep
)
589 unsigned int ep_index
;
590 struct xhci_ep_ctx
*ep_ctx
;
592 ep_index
= xhci_get_endpoint_index(&ep
->desc
);
593 ep_ctx
= xhci_get_ep_ctx(xhci
, virt_dev
->in_ctx
, ep_index
);
596 ep_ctx
->ep_info2
= 0;
599 /* Don't free the endpoint ring until the set interface or configuration
604 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
605 * Useful when you want to change one particular aspect of the endpoint and then
606 * issue a configure endpoint command.
608 void xhci_endpoint_copy(struct xhci_hcd
*xhci
,
609 struct xhci_virt_device
*vdev
, unsigned int ep_index
)
611 struct xhci_ep_ctx
*out_ep_ctx
;
612 struct xhci_ep_ctx
*in_ep_ctx
;
614 out_ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->out_ctx
, ep_index
);
615 in_ep_ctx
= xhci_get_ep_ctx(xhci
, vdev
->in_ctx
, ep_index
);
617 in_ep_ctx
->ep_info
= out_ep_ctx
->ep_info
;
618 in_ep_ctx
->ep_info2
= out_ep_ctx
->ep_info2
;
619 in_ep_ctx
->deq
= out_ep_ctx
->deq
;
620 in_ep_ctx
->tx_info
= out_ep_ctx
->tx_info
;
623 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
624 * Useful when you want to change one particular aspect of the endpoint and then
625 * issue a configure endpoint command. Only the context entries field matters,
626 * but we'll copy the whole thing anyway.
628 void xhci_slot_copy(struct xhci_hcd
*xhci
, struct xhci_virt_device
*vdev
)
630 struct xhci_slot_ctx
*in_slot_ctx
;
631 struct xhci_slot_ctx
*out_slot_ctx
;
633 in_slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->in_ctx
);
634 out_slot_ctx
= xhci_get_slot_ctx(xhci
, vdev
->out_ctx
);
636 in_slot_ctx
->dev_info
= out_slot_ctx
->dev_info
;
637 in_slot_ctx
->dev_info2
= out_slot_ctx
->dev_info2
;
638 in_slot_ctx
->tt_info
= out_slot_ctx
->tt_info
;
639 in_slot_ctx
->dev_state
= out_slot_ctx
->dev_state
;
642 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
643 static int scratchpad_alloc(struct xhci_hcd
*xhci
, gfp_t flags
)
646 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
647 int num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
649 xhci_dbg(xhci
, "Allocating %d scratchpad buffers\n", num_sp
);
654 xhci
->scratchpad
= kzalloc(sizeof(*xhci
->scratchpad
), flags
);
655 if (!xhci
->scratchpad
)
658 xhci
->scratchpad
->sp_array
=
659 pci_alloc_consistent(to_pci_dev(dev
),
660 num_sp
* sizeof(u64
),
661 &xhci
->scratchpad
->sp_dma
);
662 if (!xhci
->scratchpad
->sp_array
)
665 xhci
->scratchpad
->sp_buffers
= kzalloc(sizeof(void *) * num_sp
, flags
);
666 if (!xhci
->scratchpad
->sp_buffers
)
669 xhci
->scratchpad
->sp_dma_buffers
=
670 kzalloc(sizeof(dma_addr_t
) * num_sp
, flags
);
672 if (!xhci
->scratchpad
->sp_dma_buffers
)
675 xhci
->dcbaa
->dev_context_ptrs
[0] = xhci
->scratchpad
->sp_dma
;
676 for (i
= 0; i
< num_sp
; i
++) {
678 void *buf
= pci_alloc_consistent(to_pci_dev(dev
),
679 xhci
->page_size
, &dma
);
683 xhci
->scratchpad
->sp_array
[i
] = dma
;
684 xhci
->scratchpad
->sp_buffers
[i
] = buf
;
685 xhci
->scratchpad
->sp_dma_buffers
[i
] = dma
;
691 for (i
= i
- 1; i
>= 0; i
--) {
692 pci_free_consistent(to_pci_dev(dev
), xhci
->page_size
,
693 xhci
->scratchpad
->sp_buffers
[i
],
694 xhci
->scratchpad
->sp_dma_buffers
[i
]);
696 kfree(xhci
->scratchpad
->sp_dma_buffers
);
699 kfree(xhci
->scratchpad
->sp_buffers
);
702 pci_free_consistent(to_pci_dev(dev
), num_sp
* sizeof(u64
),
703 xhci
->scratchpad
->sp_array
,
704 xhci
->scratchpad
->sp_dma
);
707 kfree(xhci
->scratchpad
);
708 xhci
->scratchpad
= NULL
;
714 static void scratchpad_free(struct xhci_hcd
*xhci
)
718 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
720 if (!xhci
->scratchpad
)
723 num_sp
= HCS_MAX_SCRATCHPAD(xhci
->hcs_params2
);
725 for (i
= 0; i
< num_sp
; i
++) {
726 pci_free_consistent(pdev
, xhci
->page_size
,
727 xhci
->scratchpad
->sp_buffers
[i
],
728 xhci
->scratchpad
->sp_dma_buffers
[i
]);
730 kfree(xhci
->scratchpad
->sp_dma_buffers
);
731 kfree(xhci
->scratchpad
->sp_buffers
);
732 pci_free_consistent(pdev
, num_sp
* sizeof(u64
),
733 xhci
->scratchpad
->sp_array
,
734 xhci
->scratchpad
->sp_dma
);
735 kfree(xhci
->scratchpad
);
736 xhci
->scratchpad
= NULL
;
739 void xhci_mem_cleanup(struct xhci_hcd
*xhci
)
741 struct pci_dev
*pdev
= to_pci_dev(xhci_to_hcd(xhci
)->self
.controller
);
745 /* Free the Event Ring Segment Table and the actual Event Ring */
746 xhci_writel(xhci
, 0, &xhci
->ir_set
->erst_size
);
747 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_base
);
748 xhci_write_64(xhci
, 0, &xhci
->ir_set
->erst_dequeue
);
749 size
= sizeof(struct xhci_erst_entry
)*(xhci
->erst
.num_entries
);
750 if (xhci
->erst
.entries
)
751 pci_free_consistent(pdev
, size
,
752 xhci
->erst
.entries
, xhci
->erst
.erst_dma_addr
);
753 xhci
->erst
.entries
= NULL
;
754 xhci_dbg(xhci
, "Freed ERST\n");
755 if (xhci
->event_ring
)
756 xhci_ring_free(xhci
, xhci
->event_ring
);
757 xhci
->event_ring
= NULL
;
758 xhci_dbg(xhci
, "Freed event ring\n");
760 xhci_write_64(xhci
, 0, &xhci
->op_regs
->cmd_ring
);
762 xhci_ring_free(xhci
, xhci
->cmd_ring
);
763 xhci
->cmd_ring
= NULL
;
764 xhci_dbg(xhci
, "Freed command ring\n");
766 for (i
= 1; i
< MAX_HC_SLOTS
; ++i
)
767 xhci_free_virt_device(xhci
, i
);
769 if (xhci
->segment_pool
)
770 dma_pool_destroy(xhci
->segment_pool
);
771 xhci
->segment_pool
= NULL
;
772 xhci_dbg(xhci
, "Freed segment pool\n");
774 if (xhci
->device_pool
)
775 dma_pool_destroy(xhci
->device_pool
);
776 xhci
->device_pool
= NULL
;
777 xhci_dbg(xhci
, "Freed device context pool\n");
779 xhci_write_64(xhci
, 0, &xhci
->op_regs
->dcbaa_ptr
);
781 pci_free_consistent(pdev
, sizeof(*xhci
->dcbaa
),
782 xhci
->dcbaa
, xhci
->dcbaa
->dma
);
786 xhci
->page_shift
= 0;
787 scratchpad_free(xhci
);
790 int xhci_mem_init(struct xhci_hcd
*xhci
, gfp_t flags
)
793 struct device
*dev
= xhci_to_hcd(xhci
)->self
.controller
;
794 unsigned int val
, val2
;
796 struct xhci_segment
*seg
;
800 page_size
= xhci_readl(xhci
, &xhci
->op_regs
->page_size
);
801 xhci_dbg(xhci
, "Supported page size register = 0x%x\n", page_size
);
802 for (i
= 0; i
< 16; i
++) {
803 if ((0x1 & page_size
) != 0)
805 page_size
= page_size
>> 1;
808 xhci_dbg(xhci
, "Supported page size of %iK\n", (1 << (i
+12)) / 1024);
810 xhci_warn(xhci
, "WARN: no supported page size\n");
811 /* Use 4K pages, since that's common and the minimum the HC supports */
812 xhci
->page_shift
= 12;
813 xhci
->page_size
= 1 << xhci
->page_shift
;
814 xhci_dbg(xhci
, "HCD page size set to %iK\n", xhci
->page_size
/ 1024);
817 * Program the Number of Device Slots Enabled field in the CONFIG
818 * register with the max value of slots the HC can handle.
820 val
= HCS_MAX_SLOTS(xhci_readl(xhci
, &xhci
->cap_regs
->hcs_params1
));
821 xhci_dbg(xhci
, "// xHC can handle at most %d device slots.\n",
823 val2
= xhci_readl(xhci
, &xhci
->op_regs
->config_reg
);
824 val
|= (val2
& ~HCS_SLOTS_MASK
);
825 xhci_dbg(xhci
, "// Setting Max device slots reg = 0x%x.\n",
827 xhci_writel(xhci
, val
, &xhci
->op_regs
->config_reg
);
830 * Section 5.4.8 - doorbell array must be
831 * "physically contiguous and 64-byte (cache line) aligned".
833 xhci
->dcbaa
= pci_alloc_consistent(to_pci_dev(dev
),
834 sizeof(*xhci
->dcbaa
), &dma
);
837 memset(xhci
->dcbaa
, 0, sizeof *(xhci
->dcbaa
));
838 xhci
->dcbaa
->dma
= dma
;
839 xhci_dbg(xhci
, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
840 (unsigned long long)xhci
->dcbaa
->dma
, xhci
->dcbaa
);
841 xhci_write_64(xhci
, dma
, &xhci
->op_regs
->dcbaa_ptr
);
844 * Initialize the ring segment pool. The ring must be a contiguous
845 * structure comprised of TRBs. The TRBs must be 16 byte aligned,
846 * however, the command ring segment needs 64-byte aligned segments,
847 * so we pick the greater alignment need.
849 xhci
->segment_pool
= dma_pool_create("xHCI ring segments", dev
,
850 SEGMENT_SIZE
, 64, xhci
->page_size
);
852 /* See Table 46 and Note on Figure 55 */
853 xhci
->device_pool
= dma_pool_create("xHCI input/output contexts", dev
,
854 2112, 64, xhci
->page_size
);
855 if (!xhci
->segment_pool
|| !xhci
->device_pool
)
858 /* Set up the command ring to have one segments for now. */
859 xhci
->cmd_ring
= xhci_ring_alloc(xhci
, 1, true, flags
);
862 xhci_dbg(xhci
, "Allocated command ring at %p\n", xhci
->cmd_ring
);
863 xhci_dbg(xhci
, "First segment DMA is 0x%llx\n",
864 (unsigned long long)xhci
->cmd_ring
->first_seg
->dma
);
866 /* Set the address in the Command Ring Control register */
867 val_64
= xhci_read_64(xhci
, &xhci
->op_regs
->cmd_ring
);
868 val_64
= (val_64
& (u64
) CMD_RING_RSVD_BITS
) |
869 (xhci
->cmd_ring
->first_seg
->dma
& (u64
) ~CMD_RING_RSVD_BITS
) |
870 xhci
->cmd_ring
->cycle_state
;
871 xhci_dbg(xhci
, "// Setting command ring address to 0x%x\n", val
);
872 xhci_write_64(xhci
, val_64
, &xhci
->op_regs
->cmd_ring
);
873 xhci_dbg_cmd_ptrs(xhci
);
875 val
= xhci_readl(xhci
, &xhci
->cap_regs
->db_off
);
877 xhci_dbg(xhci
, "// Doorbell array is located at offset 0x%x"
878 " from cap regs base addr\n", val
);
879 xhci
->dba
= (void *) xhci
->cap_regs
+ val
;
881 xhci_print_run_regs(xhci
);
882 /* Set ir_set to interrupt register set 0 */
883 xhci
->ir_set
= (void *) xhci
->run_regs
->ir_set
;
886 * Event ring setup: Allocate a normal ring, but also setup
887 * the event ring segment table (ERST). Section 4.9.3.
889 xhci_dbg(xhci
, "// Allocating event ring\n");
890 xhci
->event_ring
= xhci_ring_alloc(xhci
, ERST_NUM_SEGS
, false, flags
);
891 if (!xhci
->event_ring
)
894 xhci
->erst
.entries
= pci_alloc_consistent(to_pci_dev(dev
),
895 sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
, &dma
);
896 if (!xhci
->erst
.entries
)
898 xhci_dbg(xhci
, "// Allocated event ring segment table at 0x%llx\n",
899 (unsigned long long)dma
);
901 memset(xhci
->erst
.entries
, 0, sizeof(struct xhci_erst_entry
)*ERST_NUM_SEGS
);
902 xhci
->erst
.num_entries
= ERST_NUM_SEGS
;
903 xhci
->erst
.erst_dma_addr
= dma
;
904 xhci_dbg(xhci
, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
905 xhci
->erst
.num_entries
,
907 (unsigned long long)xhci
->erst
.erst_dma_addr
);
909 /* set ring base address and size for each segment table entry */
910 for (val
= 0, seg
= xhci
->event_ring
->first_seg
; val
< ERST_NUM_SEGS
; val
++) {
911 struct xhci_erst_entry
*entry
= &xhci
->erst
.entries
[val
];
912 entry
->seg_addr
= seg
->dma
;
913 entry
->seg_size
= TRBS_PER_SEGMENT
;
918 /* set ERST count with the number of entries in the segment table */
919 val
= xhci_readl(xhci
, &xhci
->ir_set
->erst_size
);
920 val
&= ERST_SIZE_MASK
;
921 val
|= ERST_NUM_SEGS
;
922 xhci_dbg(xhci
, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
924 xhci_writel(xhci
, val
, &xhci
->ir_set
->erst_size
);
926 xhci_dbg(xhci
, "// Set ERST entries to point to event ring.\n");
927 /* set the segment table base address */
928 xhci_dbg(xhci
, "// Set ERST base address for ir_set 0 = 0x%llx\n",
929 (unsigned long long)xhci
->erst
.erst_dma_addr
);
930 val_64
= xhci_read_64(xhci
, &xhci
->ir_set
->erst_base
);
931 val_64
&= ERST_PTR_MASK
;
932 val_64
|= (xhci
->erst
.erst_dma_addr
& (u64
) ~ERST_PTR_MASK
);
933 xhci_write_64(xhci
, val_64
, &xhci
->ir_set
->erst_base
);
935 /* Set the event ring dequeue address */
936 xhci_set_hc_event_deq(xhci
);
937 xhci_dbg(xhci
, "Wrote ERST address to ir_set 0.\n");
938 xhci_print_ir_set(xhci
, xhci
->ir_set
, 0);
941 * XXX: Might need to set the Interrupter Moderation Register to
942 * something other than the default (~1ms minimum between interrupts).
943 * See section 5.5.1.2.
945 init_completion(&xhci
->addr_dev
);
946 for (i
= 0; i
< MAX_HC_SLOTS
; ++i
)
949 if (scratchpad_alloc(xhci
, flags
))
955 xhci_warn(xhci
, "Couldn't initialize memory\n");
956 xhci_mem_cleanup(xhci
);